/* Generated automatically by the program 'build/genpreds'
   from the machine description file '../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md'.  */

#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "backend.h"
#include "predict.h"
#include "tree.h"
#include "rtl.h"
#include "alias.h"
#include "varasm.h"
#include "stor-layout.h"
#include "calls.h"
#include "memmodel.h"
#include "tm_p.h"
#include "insn-config.h"
#include "recog.h"
#include "output.h"
#include "flags.h"
#include "df.h"
#include "resource.h"
#include "diagnostic-core.h"
#include "reload.h"
#include "regs.h"
#include "emit-rtl.h"
#include "tm-constrs.h"
#include "target.h"

bool
const_arith_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 24 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(SMALL_OPERAND (INTVAL (op))));
}

bool
arith_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (const_arith_operand (op, mode)) || (register_operand (op, mode));
}

bool
lui_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 32 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(LUI_OPERAND (INTVAL (op))));
}

bool
sfb_alu_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (arith_operand (op, mode)) || (lui_operand (op, mode));
}

bool
const_csr_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 40 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(IN_RANGE (INTVAL (op), 0, 31)));
}

bool
csr_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (const_csr_operand (op, mode)) || (register_operand (op, mode));
}

bool
sle_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 48 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(SMALL_OPERAND (INTVAL (op) + 1)));
}

bool
sleu_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (sle_operand (op, mode)) && (
#line 52 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(INTVAL (op) + 1 != 0));
}

bool
const_0_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case CONST_INT:
    case CONST_WIDE_INT:
    case CONST_VECTOR:
      break;
    default:
      return false;
    }
  return (
#line 56 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(op == CONST0_RTX (GET_MODE (op)))) && (
(mode == VOIDmode || GET_MODE (op) == mode || GET_MODE (op) == VOIDmode));
}

bool
reg_or_0_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (const_0_operand (op, mode)) || (register_operand (op, mode));
}

bool
branch_on_bit_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 65 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(INTVAL (op) >= IMM_BITS - 1));
}

static inline bool
splittable_const_int_operand_1 (rtx op ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED)
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
{
  /* Don't handle multi-word moves this way; we don't want to introduce
     the individual word-mode moves until after reload.  */
  if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD)
    return false;

  /* Check whether the constant can be loaded in a single
     instruction with zbs extensions.  */
  if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (INTVAL (op)))
    return false;

  /* Otherwise check whether the constant can be loaded in a single
     instruction.  */
  return !LUI_OPERAND (INTVAL (op)) && !SMALL_OPERAND (INTVAL (op));
}

bool
splittable_const_int_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
(splittable_const_int_operand_1 (op, mode)));
}

static inline bool
p2m1_shift_operand_1 (rtx op ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED)
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
{
  int val = exact_log2 (INTVAL (op) + 1);
  if (val < 12)
    return false;
  return true;
 }

bool
p2m1_shift_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
(p2m1_shift_operand_1 (op, mode)));
}

static inline bool
high_mask_shift_operand_1 (rtx op ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED)
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
{
  int val1 = clz_hwi (~ INTVAL (op));
  int val0 = ctz_hwi (INTVAL (op));
  if ((val0 + val1 == BITS_PER_WORD)
      && val0 > 31 && val0 < 64)
    return true;
  return false;
}

bool
high_mask_shift_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
(high_mask_shift_operand_1 (op, mode)));
}

static inline bool
move_operand_1 (rtx op ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED)
#line 109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
{
  enum riscv_symbol_type symbol_type;

  /* The thinking here is as follows:

     (1) The move expanders should split complex load sequences into
	 individual instructions.  Those individual instructions can
	 then be optimized by all rtl passes.

     (2) The target of pre-reload load sequences should not be used
	 to store temporary results.  If the target register is only
	 assigned one value, reload can rematerialize that value
	 on demand, rather than spill it to the stack.

     (3) If we allowed pre-reload passes like combine and cse to recreate
	 complex load sequences, we would want to be able to split the
	 sequences before reload as well, so that the pre-reload scheduler
	 can see the individual instructions.  This falls foul of (2);
	 the splitter would be forced to reuse the target register for
	 intermediate results.

     (4) We want to define complex load splitters for combine.  These
	 splitters can request a temporary scratch register, which avoids
	 the problem in (2).  They allow things like:

	      (set (reg T1) (high SYM))
	      (set (reg T2) (low (reg T1) SYM))
	      (set (reg X) (plus (reg T2) (const_int OFFSET)))

	 to be combined into:

	      (set (reg T3) (high SYM+OFFSET))
	      (set (reg X) (lo_sum (reg T3) SYM+OFFSET))

	 if T2 is only used this once.  */
  switch (GET_CODE (op))
    {
    case CONST_INT:
      return !splittable_const_int_operand (op, mode);

    case CONST_POLY_INT:
      return known_eq (rtx_to_poly_int64 (op), BYTES_PER_RISCV_VECTOR);

    case CONST:
    case SYMBOL_REF:
    case LABEL_REF:
      return riscv_symbolic_constant_p (op, &symbol_type)
	      && !riscv_split_symbol_type (symbol_type);

    case HIGH:
      op = XEXP (op, 0);
      return riscv_symbolic_constant_p (op, &symbol_type)
	      && riscv_split_symbol_type (symbol_type)
	      && symbol_type != SYMBOL_PCREL;

    default:
      return true;
    }
}

bool
move_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (general_operand (op, mode)) && (
(move_operand_1 (op, mode)));
}

static inline bool
symbolic_operand_1 (rtx op ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED)
#line 171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
{
  enum riscv_symbol_type type;
  return riscv_symbolic_constant_p (op, &type);
}

bool
symbolic_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case CONST:
    case SYMBOL_REF:
    case LABEL_REF:
      break;
    default:
      return false;
    }
  return (
(symbolic_operand_1 (op, mode))) && (
(mode == VOIDmode || GET_MODE (op) == mode || GET_MODE (op) == VOIDmode));
}

static inline bool
absolute_symbolic_operand_1 (rtx op ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED)
#line 178 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
{
  enum riscv_symbol_type type;
  return (riscv_symbolic_constant_p (op, &type)
	  && (type == SYMBOL_ABSOLUTE || type == SYMBOL_PCREL));
}

bool
absolute_symbolic_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case CONST:
    case SYMBOL_REF:
    case LABEL_REF:
      break;
    default:
      return false;
    }
  return (
(absolute_symbolic_operand_1 (op, mode))) && (
(mode == VOIDmode || GET_MODE (op) == mode || GET_MODE (op) == VOIDmode));
}

static inline bool
plt_symbolic_operand_1 (rtx op ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED)
#line 186 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
{
  enum riscv_symbol_type type;
  return (riscv_symbolic_constant_p (op, &type)
	  && type == SYMBOL_GOT_DISP && !SYMBOL_REF_WEAK (op) && TARGET_PLT);
}

bool
plt_symbolic_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case CONST:
    case SYMBOL_REF:
    case LABEL_REF:
      break;
    default:
      return false;
    }
  return (
(plt_symbolic_operand_1 (op, mode))) && (
(mode == VOIDmode || GET_MODE (op) == mode || GET_MODE (op) == VOIDmode));
}

bool
call_insn_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (absolute_symbolic_operand (op, mode)) || ((plt_symbolic_operand (op, mode)) || (register_operand (op, mode)));
}

bool
modular_operator (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case PLUS:
    case MINUS:
    case MULT:
    case ASHIFT:
      break;
    default:
      return false;
    }
  return 
(mode == VOIDmode || GET_MODE (op) == mode);
}

bool
equality_operator (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case EQ:
    case NE:
      break;
    default:
      return false;
    }
  return 
(mode == VOIDmode || GET_MODE (op) == mode);
}

bool
order_operator (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case EQ:
    case NE:
    case LT:
    case LTU:
    case LE:
    case LEU:
    case GE:
    case GEU:
    case GT:
    case GTU:
      break;
    default:
      return false;
    }
  return 
(mode == VOIDmode || GET_MODE (op) == mode);
}

bool
signed_order_operator (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case EQ:
    case NE:
    case LT:
    case LE:
    case GE:
    case GT:
      break;
    default:
      return false;
    }
  return 
(mode == VOIDmode || GET_MODE (op) == mode);
}

bool
subreg_lowpart_operator (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return ((GET_CODE (op) == TRUNCATE) || ((GET_CODE (op) == SUBREG) && (
#line 212 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(subreg_lowpart_p (op))))) && (
(mode == VOIDmode || GET_MODE (op) == mode));
}

bool
fp_native_comparison (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case EQ:
    case LT:
    case LE:
    case GT:
    case GE:
      break;
    default:
      return false;
    }
  return 
(mode == VOIDmode || GET_MODE (op) == mode);
}

bool
fp_scc_comparison (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case UNORDERED:
    case ORDERED:
    case UNLT:
    case UNGE:
    case UNLE:
    case UNGT:
    case LTGT:
    case NE:
    case EQ:
    case LT:
    case LE:
    case GT:
    case GE:
      break;
    default:
      return false;
    }
  return 
(mode == VOIDmode || GET_MODE (op) == mode);
}

bool
fp_branch_comparison (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case UNORDERED:
    case ORDERED:
    case UNLT:
    case UNGE:
    case UNLE:
    case UNGT:
    case UNEQ:
    case LTGT:
    case NE:
    case EQ:
    case LT:
    case LE:
    case GT:
    case GE:
      break;
    default:
      return false;
    }
  return 
(mode == VOIDmode || GET_MODE (op) == mode);
}

static inline bool
gpr_save_operation_1 (rtx op ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED)
#line 225 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
{
  return riscv_gpr_save_operation_p (op);
}

bool
gpr_save_operation (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == PARALLEL) && (
(gpr_save_operation_1 (op, mode)));
}

bool
single_bit_mask_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(SINGLE_BIT_MASK_OPERAND (UINTVAL (op))));
}

bool
not_single_bit_mask_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(SINGLE_BIT_MASK_OPERAND (~UINTVAL (op))));
}

bool
const31_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 240 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(INTVAL (op) == 31));
}

bool
const63_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 244 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(INTVAL (op) == 63));
}

bool
imm5_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 248 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(INTVAL (op) < 5));
}

bool
imm123_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 253 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(IN_RANGE (INTVAL (op), 1, 3)));
}

static inline bool
consecutive_bits_operand_1 (rtx op ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED)
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
{
	unsigned HOST_WIDE_INT val = UINTVAL (op);
	if (exact_log2 ((val >> ctz_hwi (val)) + 1) < 0)
	        return false;

	return true;
}

bool
consecutive_bits_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
(consecutive_bits_operand_1 (op, mode)));
}

bool
vector_length_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (pmode_register_operand (op, mode)) || (const_csr_operand (op, mode));
}

bool
reg_or_mem_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (register_operand (op, mode)) || (memory_operand (op, mode));
}

bool
reg_or_int_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (register_operand (op, mode)) || (const_int_operand (op, mode));
}

bool
vector_move_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (nonimmediate_operand (op, mode)) || (((GET_CODE (op) == CONST_VECTOR) && (
#line 282 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(reload_completed
		|| satisfies_constraint_vi (op)
		|| satisfies_constraint_Wc0 (op)))) && (
(mode == VOIDmode || GET_MODE (op) == mode)));
}

bool
vector_all_trues_mask_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return ((GET_CODE (op) == CONST_VECTOR) && (
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(op == CONSTM1_RTX (GET_MODE (op))))) && (
(mode == VOIDmode || GET_MODE (op) == mode));
}

bool
vector_least_significant_set_mask_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return ((GET_CODE (op) == CONST_VECTOR) && (
#line 292 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(rtx_equal_p (op, riscv_vector::gen_scalar_move_mask (GET_MODE (op)))))) && (
(mode == VOIDmode || GET_MODE (op) == mode));
}

bool
vector_mask_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (register_operand (op, mode)) || (vector_all_trues_mask_operand (op, mode));
}

bool
vector_broadcast_mask_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (vector_least_significant_set_mask_operand (op, mode)) || ((register_operand (op, mode)) || (vector_all_trues_mask_operand (op, mode)));
}

bool
vector_undef_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (
#line 304 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(rtx_equal_p (op, RVV_VUNDEF (GET_MODE (op))))) && (
(mode == VOIDmode || GET_MODE (op) == mode || GET_MODE (op) == VOIDmode));
}

bool
vector_merge_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (register_operand (op, mode)) || (vector_undef_operand (op, mode));
}

bool
vector_arith_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (register_operand (op, mode)) || (((GET_CODE (op) == CONST_VECTOR) && (
#line 313 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(riscv_vector::const_vec_all_same_in_range_p (op, -16, 15)))) && (
(mode == VOIDmode || GET_MODE (op) == mode)));
}

bool
vector_neg_arith_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (register_operand (op, mode)) || (((GET_CODE (op) == CONST_VECTOR) && (
#line 318 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(riscv_vector::const_vec_all_same_in_range_p (op, -15, 16)))) && (
(mode == VOIDmode || GET_MODE (op) == mode)));
}

bool
vector_shift_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (register_operand (op, mode)) || (((GET_CODE (op) == CONST_VECTOR) && (
#line 323 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(riscv_vector::const_vec_all_same_in_range_p (op, 0, 31)))) && (
(mode == VOIDmode || GET_MODE (op) == mode)));
}

bool
ltge_operator (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case LT:
    case LTU:
    case GE:
    case GEU:
      break;
    default:
      return false;
    }
  return 
(mode == VOIDmode || GET_MODE (op) == mode);
}

bool
comparison_except_ltge_operator (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case EQ:
    case NE:
    case LE:
    case LEU:
    case GT:
    case GTU:
      break;
    default:
      return false;
    }
  return 
(mode == VOIDmode || GET_MODE (op) == mode);
}

bool
comparison_except_eqge_operator (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case LE:
    case LEU:
    case GT:
    case GTU:
    case LT:
    case LTU:
      break;
    default:
      return false;
    }
  return 
(mode == VOIDmode || GET_MODE (op) == mode);
}

bool
ge_operator (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  switch (GET_CODE (op))
    {
    case GE:
    case GEU:
      break;
    default:
      return false;
    }
  return 
(mode == VOIDmode || GET_MODE (op) == mode);
}

bool
pmode_reg_or_uimm5_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return vector_length_operand (op, mode);
}

bool
pmode_reg_or_0_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (const_0_operand (op, mode)) || (pmode_register_operand (op, mode));
}

bool
vector_any_register_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return GET_CODE (op) == REG;
}

bool
direct_broadcast_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return ((
#line 355 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(!(reload_completed && !FLOAT_MODE_P (GET_MODE (op))
		&& (register_operand (op, GET_MODE (op)) || CONST_INT_P (op)
		|| rtx_equal_p (op, CONST0_RTX (GET_MODE (op))))
		&& maybe_gt (GET_MODE_BITSIZE (GET_MODE (op)), GET_MODE_BITSIZE (Pmode))))) && ((
#line 359 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(rtx_equal_p (op, CONST0_RTX (GET_MODE (op))))) || ((const_int_operand (op, mode)) || ((register_operand (op, mode)) || (
#line 362 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(satisfies_constraint_Wdm (op))))))) && (
(mode == VOIDmode || GET_MODE (op) == mode || GET_MODE (op) == VOIDmode));
}

bool
const_nottwobits_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 367 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(popcount_hwi (~UINTVAL (op)) == 2));
}

bool
consecutive_bits32_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (consecutive_bits_operand (op, mode)) && (
#line 373 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(popcount_hwi (UINTVAL (op)) == 32));
}

bool
shifted_const_arith_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && ((
#line 380 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(ctz_hwi (INTVAL (op)) > 0)) && (
#line 381 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(SMALL_OPERAND (INTVAL (op) >> ctz_hwi (INTVAL (op))))));
}

bool
const_twobits_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 386 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(popcount_hwi (UINTVAL (op)) == 2));
}

bool
const_twobits_not_arith_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && ((!(arith_operand (op, mode))) && (const_twobits_operand (op, mode)));
}

bool
uimm_extra_bit_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 397 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(UIMM_EXTRA_BIT_OPERAND (UINTVAL (op))));
}

bool
uimm_extra_bit_or_twobits (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && ((uimm_extra_bit_operand (op, mode)) || (const_twobits_not_arith_operand (op, mode)));
}

bool
not_uimm_extra_bit_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && (
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/predicates.md"
(UIMM_EXTRA_BIT_OPERAND (~UINTVAL (op))));
}

bool
not_uimm_extra_bit_or_nottwobits (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
  return (GET_CODE (op) == CONST_INT) && ((not_uimm_extra_bit_operand (op, mode)) || (const_nottwobits_operand (op, mode)));
}

enum constraint_num
lookup_constraint_1 (const char *str)
{
  switch (str[0])
    {
    case '<':
      return CONSTRAINT__l;
    case '>':
      return CONSTRAINT__g;
    case 'A':
      return CONSTRAINT_A;
    case 'D':
      if (!strncmp (str + 1, "sS", 2))
        return CONSTRAINT_DsS;
      if (!strncmp (str + 1, "sD", 2))
        return CONSTRAINT_DsD;
      if (!strncmp (str + 1, "bS", 2))
        return CONSTRAINT_DbS;
      if (!strncmp (str + 1, "nS", 2))
        return CONSTRAINT_DnS;
      if (!strncmp (str + 1, "03", 2))
        return CONSTRAINT_D03;
      if (!strncmp (str + 1, "sA", 2))
        return CONSTRAINT_DsA;
      if (!strncmp (str + 1, "s3", 2))
        return CONSTRAINT_Ds3;
      break;
    case 'E':
      return CONSTRAINT_E;
    case 'F':
      return CONSTRAINT_F;
    case 'G':
      return CONSTRAINT_G;
    case 'I':
      return CONSTRAINT_I;
    case 'J':
      return CONSTRAINT_J;
    case 'K':
      return CONSTRAINT_K;
    case 'L':
      return CONSTRAINT_L;
    case 'S':
      return CONSTRAINT_S;
    case 'T':
      return CONSTRAINT_T;
    case 'U':
      return CONSTRAINT_U;
    case 'V':
      return CONSTRAINT_V;
    case 'W':
      if (!strncmp (str + 1, "c1", 2))
        return CONSTRAINT_Wc1;
      if (!strncmp (str + 1, "b1", 2))
        return CONSTRAINT_Wb1;
      if (!strncmp (str + 1, "dm", 2))
        return CONSTRAINT_Wdm;
      if (!strncmp (str + 1, "c0", 2))
        return CONSTRAINT_Wc0;
      break;
    case 'X':
      return CONSTRAINT_X;
    case 'f':
      return CONSTRAINT_f;
    case 'i':
      return CONSTRAINT_i;
    case 'j':
      return CONSTRAINT_j;
    case 'l':
      return CONSTRAINT_l;
    case 'm':
      return CONSTRAINT_m;
    case 'n':
      return CONSTRAINT_n;
    case 'o':
      return CONSTRAINT_o;
    case 'p':
      return CONSTRAINT_p;
    case 'r':
      return CONSTRAINT_r;
    case 's':
      return CONSTRAINT_s;
    case 't':
      if (!strncmp (str + 1, "h_r_fmv", 7))
        return CONSTRAINT_th__r__fmv;
      if (!strncmp (str + 1, "h_f_fmv", 7))
        return CONSTRAINT_th__f__fmv;
      break;
    case 'v':
      if (str[1] == 'd')
        return CONSTRAINT_vd;
      if (str[1] == 'm')
        return CONSTRAINT_vm;
      if (str[1] == 'p')
        return CONSTRAINT_vp;
      if (str[1] == 'u')
        return CONSTRAINT_vu;
      if (str[1] == 'i')
        return CONSTRAINT_vi;
      if (str[1] == 'j')
        return CONSTRAINT_vj;
      if (str[1] == 'k')
        return CONSTRAINT_vk;
      if (str[1] == 'r')
        return CONSTRAINT_vr;
      break;
    default: break;
    }
  return CONSTRAINT__UNKNOWN;
}

const unsigned char lookup_constraint_array[] = {
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  MIN ((int) CONSTRAINT__l, (int) UCHAR_MAX),
  CONSTRAINT__UNKNOWN,
  MIN ((int) CONSTRAINT__g, (int) UCHAR_MAX),
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  MIN ((int) CONSTRAINT_A, (int) UCHAR_MAX),
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  UCHAR_MAX,
  MIN ((int) CONSTRAINT_E, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_F, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_G, (int) UCHAR_MAX),
  CONSTRAINT__UNKNOWN,
  MIN ((int) CONSTRAINT_I, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_J, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_K, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_L, (int) UCHAR_MAX),
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  MIN ((int) CONSTRAINT_S, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_T, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_U, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_V, (int) UCHAR_MAX),
  UCHAR_MAX,
  MIN ((int) CONSTRAINT_X, (int) UCHAR_MAX),
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  MIN ((int) CONSTRAINT_f, (int) UCHAR_MAX),
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  MIN ((int) CONSTRAINT_i, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_j, (int) UCHAR_MAX),
  CONSTRAINT__UNKNOWN,
  MIN ((int) CONSTRAINT_l, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_m, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_n, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_o, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_p, (int) UCHAR_MAX),
  CONSTRAINT__UNKNOWN,
  MIN ((int) CONSTRAINT_r, (int) UCHAR_MAX),
  MIN ((int) CONSTRAINT_s, (int) UCHAR_MAX),
  UCHAR_MAX,
  CONSTRAINT__UNKNOWN,
  UCHAR_MAX,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN,
  CONSTRAINT__UNKNOWN
};

enum reg_class
reg_class_for_constraint_1 (enum constraint_num c)
{
  switch (c)
    {
    case CONSTRAINT_r: return GENERAL_REGS;
    case CONSTRAINT_f: return TARGET_HARD_FLOAT ? FP_REGS :
  (TARGET_ZFINX ? GR_REGS : NO_REGS);
    case CONSTRAINT_j: return SIBCALL_REGS;
    case CONSTRAINT_l: return JALR_REGS;
    case CONSTRAINT_vr: return TARGET_VECTOR ? V_REGS : NO_REGS;
    case CONSTRAINT_vd: return TARGET_VECTOR ? VD_REGS : NO_REGS;
    case CONSTRAINT_vm: return TARGET_VECTOR ? VM_REGS : NO_REGS;
    case CONSTRAINT_th__f__fmv: return TARGET_XTHEADFMV ? FP_REGS : NO_REGS;
    case CONSTRAINT_th__r__fmv: return TARGET_XTHEADFMV ? GR_REGS : NO_REGS;
    default: break;
    }
  return NO_REGS;
}

bool (*constraint_satisfied_p_array[]) (rtx) = {
  satisfies_constraint_I,
  satisfies_constraint_J,
  satisfies_constraint_K,
  satisfies_constraint_L,
  satisfies_constraint_m,
  satisfies_constraint_o,
  satisfies_constraint_A,
  satisfies_constraint_Wdm,
  satisfies_constraint_p,
  satisfies_constraint_Ds3,
  satisfies_constraint_DsS,
  satisfies_constraint_DsD,
  satisfies_constraint_DbS,
  satisfies_constraint_DnS,
  satisfies_constraint_G,
  satisfies_constraint_S,
  satisfies_constraint_U,
  satisfies_constraint_vp,
  satisfies_constraint_vu,
  satisfies_constraint_vi,
  satisfies_constraint_vj,
  satisfies_constraint_vk,
  satisfies_constraint_Wc0,
  satisfies_constraint_Wc1,
  satisfies_constraint_Wb1,
  satisfies_constraint_V,
  satisfies_constraint__l,
  satisfies_constraint__g,
  satisfies_constraint_i,
  satisfies_constraint_s,
  satisfies_constraint_n,
  satisfies_constraint_E,
  satisfies_constraint_F,
  satisfies_constraint_X,
  satisfies_constraint_D03,
  satisfies_constraint_DsA,
  satisfies_constraint_T
};

bool
insn_const_int_ok_for_constraint (HOST_WIDE_INT ival, enum constraint_num c)
{
  switch (c)
    {
    case CONSTRAINT_I:
      return 
#line 41 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/constraints.md"
(SMALL_OPERAND (ival));

    case CONSTRAINT_J:
      return 
#line 46 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/constraints.md"
(ival == 0);

    case CONSTRAINT_K:
      return 
#line 51 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/constraints.md"
(IN_RANGE (ival, 0, 31));

    case CONSTRAINT_L:
      return 
#line 56 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/constraints.md"
(LUI_OPERAND (ival));

    default: break;
    }
  return false;
}

