/* Generated automatically by the program `genrecog' from the target
   machine description file.  */

#define IN_TARGET_CODE 1

#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "backend.h"
#include "predict.h"
#include "rtl.h"
#include "memmodel.h"
#include "tm_p.h"
#include "emit-rtl.h"
#include "insn-config.h"
#include "recog.h"
#include "output.h"
#include "flags.h"
#include "df.h"
#include "resource.h"
#include "diagnostic-core.h"
#include "reload.h"
#include "regs.h"
#include "tm-constrs.h"



/* `recog' contains a decision tree that recognizes whether the rtx
   X0 is a valid instruction.

   recog returns -1 if the rtx is not valid.  If the rtx is valid, recog
   returns a nonnegative number which is the insn code number for the
   pattern that matched.  This is the same as the order in the machine
   description of the entry that matched.  This number can be used as an
   index into `insn_data' and other tables.

   The third parameter to recog is an optional pointer to an int.  If
   present, recog will accept a pattern if it matches except for missing
   CLOBBER expressions at the end.  In that case, the value pointed to by
   the optional pointer will be set to the number of CLOBBERs that need
   to be added (it should be initialized to zero by the caller).  If it
   is set nonzero, the caller should allocate a PARALLEL of the
   appropriate size, copy the initial entries, and call add_clobbers
   (found in insn-emit.cc) to fill in the CLOBBERs.


   The function split_insns returns 0 if the rtl could not
   be split or the split rtl as an INSN list if it can be.

   The function peephole2_insns returns 0 if the rtl could not
   be matched. If there was a match, the new rtl is returned in an INSN list,
   and LAST_INSN will point to the last recognized insn in the old sequence.
*/


extern rtx_insn *gen_split_1 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_2 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_3 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_4 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_5 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_6 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_7 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_8 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_9 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_10 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_11 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_12 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_13 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_14 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_15 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_16 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_17 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_18 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_19 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_20 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_21 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_22 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_23 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_24 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_25 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_26 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_27 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_28 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_29 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_30 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_31 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_32 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_33 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_34 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_35 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_36 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_37 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_38 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_39 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_40 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_41 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_42 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_43 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_44 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_45 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_46 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_47 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_48 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_49 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_50 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_51 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_52 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_53 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_54 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_55 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_56 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_57 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_58 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_59 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_60 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_61 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_62 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_63 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_64 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_65 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_66 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_67 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_68 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_69 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_70 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_71 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_72 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_73 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_74 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_75 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_76 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_77 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_78 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_79 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_80 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_81 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_82 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_83 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_84 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_85 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_86 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_87 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_88 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_89 (rtx_insn *, rtx *);
extern rtx_insn *gen_peephole2_1 (rtx_insn *, rtx *);
extern rtx_insn *gen_peephole2_2 (rtx_insn *, rtx *);
extern rtx_insn *gen_peephole2_3 (rtx_insn *, rtx *);
extern rtx_insn *gen_peephole2_4 (rtx_insn *, rtx *);
extern rtx_insn *gen_peephole2_5 (rtx_insn *, rtx *);
extern rtx_insn *gen_peephole2_6 (rtx_insn *, rtx *);
extern rtx_insn *gen_peephole2_7 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_90 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_91 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_92 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_93 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_94 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_95 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_96 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_97 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_98 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_99 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_100 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_101 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_102 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_103 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_104 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_105 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_106 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_107 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_108 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_109 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_110 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_111 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_112 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_113 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_114 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_115 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_116 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_117 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_118 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_119 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_120 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_121 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_122 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_123 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_124 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_125 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_126 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_127 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_128 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_129 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_130 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_131 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_132 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_133 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_134 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_135 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_136 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_137 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_138 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_139 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_140 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_141 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_142 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_143 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_144 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_145 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_146 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_147 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_148 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_149 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_150 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_151 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_152 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_153 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_154 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_155 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_156 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_157 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_158 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_159 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_160 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_161 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_162 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_163 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_164 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_165 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_166 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_167 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_168 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_169 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_170 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_171 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_172 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_173 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_174 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_175 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_176 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_177 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_178 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_179 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_180 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_181 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_182 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_183 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_184 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_185 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_186 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_187 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_188 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_189 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_190 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_191 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_192 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_193 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_194 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_195 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_196 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_197 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_198 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_199 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_200 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_201 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_202 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_203 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_204 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_205 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_206 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_207 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_208 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_209 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_210 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_211 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_212 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_213 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_214 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_215 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_216 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_217 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_218 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_219 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_220 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_221 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_222 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_223 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_224 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_225 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_226 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_227 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_228 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_229 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_230 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_231 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_232 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_233 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_234 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_235 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_236 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_237 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_238 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_239 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_240 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_241 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_242 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_243 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_244 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_245 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_246 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_247 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_248 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_249 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_250 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_251 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_252 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_253 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_254 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_255 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_256 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_257 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_258 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_259 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_260 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_261 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_262 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_263 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_264 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_265 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_266 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_267 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_268 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_269 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_270 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_271 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_272 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_273 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_274 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_275 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_276 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_277 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_278 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_279 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_280 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_281 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_282 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_283 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_284 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_285 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_286 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_287 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_288 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_289 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_290 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_291 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_292 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_293 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_294 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_295 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_296 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_297 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_298 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_299 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_300 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_301 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_302 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_303 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_304 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_305 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_306 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_307 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_308 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_309 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_310 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_311 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_312 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_313 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_314 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_315 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_316 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_317 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_318 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_319 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_320 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_321 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_322 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_323 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_324 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_325 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_326 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_327 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_328 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_329 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_330 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_331 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_332 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_333 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_334 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_335 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_336 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_337 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_338 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_339 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_340 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_341 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_342 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_343 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_344 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_345 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_346 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_347 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_348 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_349 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_350 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_351 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_352 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_353 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_354 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_355 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_356 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_357 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_358 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_359 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_360 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_361 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_362 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_363 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_364 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_365 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_366 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_367 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_368 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_369 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_370 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_371 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_372 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_373 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_374 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_375 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_376 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_377 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_378 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_379 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_380 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_381 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_382 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_383 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_384 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_385 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_386 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_387 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_388 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_389 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_390 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_391 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_392 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_393 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_394 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_395 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_396 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_397 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_398 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_399 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_400 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_401 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_402 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_403 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_404 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_405 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_406 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_407 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_408 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_409 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_410 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_411 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_412 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_413 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_414 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_415 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_416 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_417 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_418 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_419 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_420 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_421 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_422 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_423 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_424 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_425 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_426 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_427 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_428 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_429 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_430 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_431 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_432 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_433 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_434 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_435 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_436 (rtx_insn *, rtx *);
extern rtx_insn *gen_split_437 (rtx_insn *, rtx *);




static int
pattern0 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern1 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  operands[1] = x4;
  x5 = XEXP (x3, 1);
  operands[2] = x5;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      return pattern0 (x3, E_SImode); /* [-1, 0] */

    case E_DImode:
      if (pattern0 (x3, E_DImode) != 0)
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern2 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  operands[1] = x4;
  switch (GET_MODE (operands[0]))
    {
    case E_SFmode:
      if (!register_operand (operands[0], E_SFmode)
          || GET_MODE (x3) != E_SFmode
          || !register_operand (operands[1], E_SFmode))
        return -1;
      return 0;

    case E_DFmode:
      if (!register_operand (operands[0], E_DFmode)
          || GET_MODE (x3) != E_DFmode
          || !register_operand (operands[1], E_DFmode))
        return -1;
      return 1;

    case E_HFmode:
      if (!register_operand (operands[0], E_HFmode)
          || GET_MODE (x3) != E_HFmode
          || !register_operand (operands[1], E_HFmode))
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern3 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1)
      || !reg_or_0_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern4 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  operands[1] = x4;
  x5 = XEXP (x3, 1);
  operands[2] = x5;
  switch (GET_MODE (operands[0]))
    {
    case E_SFmode:
      return pattern0 (x3, E_SFmode); /* [-1, 0] */

    case E_DFmode:
      if (pattern0 (x3, E_DFmode) != 0)
        return -1;
      return 1;

    case E_HFmode:
      if (pattern0 (x3, E_HFmode) != 0)
        return -1;
      return 2;

    case E_SImode:
      if (pattern3 (x3, E_SImode) != 0)
        return -1;
      return 3;

    case E_DImode:
      if (pattern3 (x3, E_DImode) != 0)
        return -1;
      return 4;

    default:
      return -1;
    }
}

static int
pattern5 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  switch (GET_MODE (operands[1]))
    {
    case E_SFmode:
      if (!register_operand (operands[1], E_SFmode))
        return -1;
      return 0;

    case E_DFmode:
      if (!register_operand (operands[1], E_DFmode))
        return -1;
      return 1;

    case E_HFmode:
      if (!register_operand (operands[1], E_HFmode))
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern6 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  operands[1] = x4;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      return pattern5 (x3, E_SImode); /* [-1, 2] */

    case E_DImode:
      res = pattern5 (x3, E_DImode);
      if (res >= 0)
        return res + 3; /* [3, 5] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern7 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  operands[1] = x4;
  switch (GET_MODE (operands[0]))
    {
    case E_SFmode:
      if (!register_operand (operands[0], E_SFmode)
          || GET_MODE (x3) != E_SFmode)
        return -1;
      return 0;

    case E_DFmode:
      if (!register_operand (operands[0], E_DFmode)
          || GET_MODE (x3) != E_DFmode)
        return -1;
      return 1;

    case E_HFmode:
      if (!register_operand (operands[0], E_HFmode)
          || GET_MODE (x3) != E_HFmode)
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern8 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (!register_operand (operands[0], E_SImode)
          || GET_MODE (x1) != E_SImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_SImode:
          if (!register_operand (operands[1], E_SImode))
            return -1;
          return 0;

        case E_DImode:
          if (!register_operand (operands[1], E_DImode))
            return -1;
          return 1;

        default:
          return -1;
        }

    case E_DImode:
      if (!register_operand (operands[0], E_DImode)
          || GET_MODE (x1) != E_DImode
          || !register_operand (operands[1], E_DImode))
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern9 (rtx x1, int i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  if (x3 != const_int_rtx[MAX_SAVED_CONST_INT + i1])
    return -1;
  x4 = XEXP (x1, 0);
  operands[0] = x4;
  x5 = XEXP (x2, 0);
  operands[1] = x5;
  return pattern8 (x2); /* [-1, 2] */
}

static int
pattern10 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  operands[1] = x4;
  x5 = XEXP (x3, 1);
  operands[2] = x5;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      return pattern3 (x3, E_SImode); /* [-1, 0] */

    case E_DImode:
      if (pattern3 (x3, E_DImode) != 0)
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern11 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_CODE (x2) != SET)
    return -1;
  x3 = XVECEXP (x1, 0, 1);
  if (GET_CODE (x3) != SET)
    return -1;
  x4 = XEXP (x3, 1);
  if (GET_CODE (x4) != UNSPEC_VOLATILE
      || XVECLEN (x4, 0) != 2)
    return -1;
  return 0;
}

static int
pattern12 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (!register_operand (operands[0], E_SImode)
          || GET_MODE (x1) != E_SImode
          || !register_operand (operands[1], E_SImode))
        return -1;
      return 0;

    case E_DImode:
      if (!register_operand (operands[0], E_DImode)
          || GET_MODE (x1) != E_DImode
          || !register_operand (operands[1], E_DImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern13 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[1] = x2;
  x3 = XEXP (x1, 1);
  operands[2] = x3;
  return pattern12 (x1); /* [-1, 1] */
}

static int
pattern14 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1))
    return -1;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  switch (GET_MODE (x3))
    {
    case E_SImode:
      if (!register_operand (operands[2], E_SImode))
        return -1;
      return 0;

    case E_DImode:
      if (!register_operand (operands[2], E_DImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern15 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 0);
  operands[2] = x4;
  x5 = XEXP (x3, 1);
  operands[3] = x5;
  if (!const_int_operand (operands[3], E_VOIDmode))
    return -1;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      return pattern14 (x1, E_SImode); /* [-1, 1] */

    case E_DImode:
      res = pattern14 (x1, E_DImode);
      if (res >= 0)
        return res + 2; /* [2, 3] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern16 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (!subreg_lowpart_operator (x2, E_VOIDmode))
    return -1;
  operands[4] = x2;
  x3 = XEXP (x2, 0);
  if (GET_CODE (x3) != AND)
    return -1;
  x4 = XEXP (x1, 0);
  operands[1] = x4;
  return pattern15 (x1); /* [-1, 3] */
}

static int
pattern17 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1)
      || !uimm_extra_bit_or_twobits (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern18 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[1] = x2;
  x3 = XEXP (x1, 1);
  operands[2] = x3;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      return pattern17 (x1, E_SImode); /* [-1, 0] */

    case E_DImode:
      if (pattern17 (x1, E_DImode) != 0)
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern19 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[0], E_DImode)
      || GET_MODE (x1) != E_DImode)
    return -1;
  x3 = XEXP (x2, 0);
  operands[1] = x3;
  if (!register_operand (operands[1], E_SImode))
    return -1;
  return 0;
}

static int
pattern20 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != E_SImode
      || !register_operand (operands[0], E_DImode)
      || GET_MODE (x1) != E_DImode)
    return -1;
  x3 = XEXP (x2, 0);
  operands[1] = x3;
  if (!register_operand (operands[1], E_SImode))
    return -1;
  x4 = XEXP (x2, 1);
  operands[2] = x4;
  if (!register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern21 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern22 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  if (GET_CODE (x3) != USE)
    return -1;
  x4 = XVECEXP (x2, 0, 1);
  if (GET_CODE (x4) != USE)
    return -1;
  x5 = XEXP (x1, 0);
  operands[0] = x5;
  x6 = XEXP (x3, 0);
  operands[1] = x6;
  x7 = XEXP (x4, 0);
  operands[2] = x7;
  switch (GET_MODE (operands[0]))
    {
    case E_SFmode:
      return pattern21 (x2, E_SFmode); /* [-1, 0] */

    case E_DFmode:
      if (pattern21 (x2, E_DFmode) != 0)
        return -1;
      return 1;

    case E_HFmode:
      if (pattern21 (x2, E_HFmode) != 0)
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern23 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (GET_MODE (x2) != i1)
    return -1;
  x3 = XEXP (x1, 0);
  operands[0] = x3;
  if (!register_operand (operands[0], i1))
    return -1;
  x4 = XVECEXP (x2, 0, 0);
  operands[1] = x4;
  if (!register_operand (operands[1], i2))
    return -1;
  x5 = XVECEXP (x2, 0, 1);
  operands[2] = x5;
  if (!register_operand (operands[2], i2))
    return -1;
  return 0;
}

static int
pattern24 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern25 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XVECEXP (x3, 0, 0);
  operands[1] = x4;
  x5 = XVECEXP (x3, 0, 1);
  operands[2] = x5;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      return pattern24 (x3, E_SImode); /* [-1, 0] */

    case E_DImode:
      if (pattern24 (x3, E_DImode) != 0)
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern26 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (GET_MODE (x2) != E_DImode)
    return -1;
  x3 = XEXP (x1, 0);
  operands[0] = x3;
  if (!register_operand (operands[0], E_DImode))
    return -1;
  x4 = XVECEXP (x2, 0, 0);
  operands[1] = x4;
  if (!register_operand (operands[1], E_DImode))
    return -1;
  x5 = XVECEXP (x2, 0, 1);
  operands[2] = x5;
  if (!register_operand (operands[2], E_DImode))
    return -1;
  return 0;
}

static int
pattern27 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_CODE (x2) != VEC_SELECT)
    return -1;
  x3 = XEXP (x2, 1);
  if (GET_CODE (x3) != PARALLEL
      || XVECLEN (x3, 0) != 1)
    return -1;
  x4 = XVECEXP (x3, 0, 0);
  if (x4 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
    return -1;
  x5 = XVECEXP (x1, 0, 1);
  if (GET_CODE (x5) != REG
      || REGNO (x5) != 67
      || GET_MODE (x5) != E_SImode)
    return -1;
  return 0;
}

static int
pattern28 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[3]))
    {
    case E_VNx1QImode:
      if (!register_operand (operands[3], E_VNx1QImode))
        return -1;
      return 0;

    case E_VNx1HImode:
      if (!register_operand (operands[3], E_VNx1HImode))
        return -1;
      return 1;

    case E_VNx1SImode:
      if (!register_operand (operands[3], E_VNx1SImode))
        return -1;
      return 2;

    case E_VNx1DImode:
      if (!register_operand (operands[3], E_VNx1DImode))
        return -1;
      return 3;

    case E_VNx1SFmode:
      if (!register_operand (operands[3], E_VNx1SFmode))
        return -1;
      return 4;

    case E_VNx1DFmode:
      if (!register_operand (operands[3], E_VNx1DFmode))
        return -1;
      return 5;

    default:
      return -1;
    }
}

static int
pattern29 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[3]))
    {
    case E_VNx2QImode:
      if (!register_operand (operands[3], E_VNx2QImode))
        return -1;
      return 0;

    case E_VNx2HImode:
      if (!register_operand (operands[3], E_VNx2HImode))
        return -1;
      return 1;

    case E_VNx2SImode:
      if (!register_operand (operands[3], E_VNx2SImode))
        return -1;
      return 2;

    case E_VNx2DImode:
      if (!register_operand (operands[3], E_VNx2DImode))
        return -1;
      return 3;

    case E_VNx2SFmode:
      if (!register_operand (operands[3], E_VNx2SFmode))
        return -1;
      return 4;

    case E_VNx2DFmode:
      if (!register_operand (operands[3], E_VNx2DFmode))
        return -1;
      return 5;

    default:
      return -1;
    }
}

static int
pattern30 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[3]))
    {
    case E_VNx4QImode:
      if (!register_operand (operands[3], E_VNx4QImode))
        return -1;
      return 0;

    case E_VNx4HImode:
      if (!register_operand (operands[3], E_VNx4HImode))
        return -1;
      return 1;

    case E_VNx4SImode:
      if (!register_operand (operands[3], E_VNx4SImode))
        return -1;
      return 2;

    case E_VNx4DImode:
      if (!register_operand (operands[3], E_VNx4DImode))
        return -1;
      return 3;

    case E_VNx4SFmode:
      if (!register_operand (operands[3], E_VNx4SFmode))
        return -1;
      return 4;

    case E_VNx4DFmode:
      if (!register_operand (operands[3], E_VNx4DFmode))
        return -1;
      return 5;

    default:
      return -1;
    }
}

static int
pattern31 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[3]))
    {
    case E_VNx8QImode:
      if (!register_operand (operands[3], E_VNx8QImode))
        return -1;
      return 0;

    case E_VNx8HImode:
      if (!register_operand (operands[3], E_VNx8HImode))
        return -1;
      return 1;

    case E_VNx8SImode:
      if (!register_operand (operands[3], E_VNx8SImode))
        return -1;
      return 2;

    case E_VNx8DImode:
      if (!register_operand (operands[3], E_VNx8DImode))
        return -1;
      return 3;

    case E_VNx8SFmode:
      if (!register_operand (operands[3], E_VNx8SFmode))
        return -1;
      return 4;

    case E_VNx8DFmode:
      if (!register_operand (operands[3], E_VNx8DFmode))
        return -1;
      return 5;

    default:
      return -1;
    }
}

static int
pattern32 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[3]))
    {
    case E_VNx16QImode:
      if (!register_operand (operands[3], E_VNx16QImode))
        return -1;
      return 0;

    case E_VNx16HImode:
      if (!register_operand (operands[3], E_VNx16HImode))
        return -1;
      return 1;

    case E_VNx16SImode:
      if (!register_operand (operands[3], E_VNx16SImode))
        return -1;
      return 2;

    case E_VNx16SFmode:
      if (!register_operand (operands[3], E_VNx16SFmode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern33 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[3]))
    {
    case E_VNx32QImode:
      if (!register_operand (operands[3], E_VNx32QImode))
        return -1;
      return 0;

    case E_VNx32HImode:
      if (!register_operand (operands[3], E_VNx32HImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern34 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (GET_MODE (x2) != E_BLKmode)
    return -1;
  x3 = XVECEXP (x2, 0, 0);
  if (GET_CODE (x3) != UNSPEC
      || XVECLEN (x3, 0) != 5
      || XINT (x3, 1) != 68)
    return -1;
  x4 = XVECEXP (x3, 0, 3);
  if (GET_CODE (x4) != REG
      || REGNO (x4) != 66
      || GET_MODE (x4) != E_SImode)
    return -1;
  x5 = XVECEXP (x3, 0, 4);
  if (GET_CODE (x5) != REG
      || REGNO (x5) != 67
      || GET_MODE (x5) != E_SImode)
    return -1;
  x6 = XEXP (x1, 0);
  if (GET_CODE (x6) != MEM
      || GET_MODE (x6) != E_BLKmode)
    return -1;
  x7 = XEXP (x6, 0);
  if (GET_CODE (x7) != SCRATCH)
    return -1;
  x8 = XVECEXP (x3, 0, 0);
  operands[0] = x8;
  x9 = XVECEXP (x3, 0, 1);
  operands[4] = x9;
  if (!vector_length_operand (operands[4], E_VOIDmode))
    return -1;
  x10 = XVECEXP (x3, 0, 2);
  operands[5] = x10;
  if (!const_int_operand (operands[5], E_VOIDmode))
    return -1;
  x11 = XVECEXP (x2, 0, 1);
  operands[1] = x11;
  if (!pmode_register_operand (operands[1], E_VOIDmode))
    return -1;
  x12 = XVECEXP (x2, 0, 2);
  operands[2] = x12;
  x13 = XVECEXP (x2, 0, 3);
  operands[3] = x13;
  switch (GET_MODE (x3))
    {
    case E_VNx1BImode:
      if (!vector_mask_operand (operands[0], E_VNx1BImode))
        return -1;
      switch (GET_MODE (operands[2]))
        {
        case E_VNx1QImode:
          return pattern28 (E_VNx1QImode); /* [-1, 5] */

        case E_VNx1HImode:
          res = pattern28 (E_VNx1HImode);
          if (res >= 0)
            return res + 6; /* [6, 11] */
          return -1;

        case E_VNx1SImode:
          res = pattern28 (E_VNx1SImode);
          if (res >= 0)
            return res + 12; /* [12, 17] */
          return -1;

        case E_VNx1DImode:
          res = pattern28 (E_VNx1DImode);
          if (res >= 0)
            return res + 18; /* [18, 23] */
          return -1;

        default:
          return -1;
        }

    case E_VNx2BImode:
      if (!vector_mask_operand (operands[0], E_VNx2BImode))
        return -1;
      switch (GET_MODE (operands[2]))
        {
        case E_VNx2QImode:
          res = pattern29 (E_VNx2QImode);
          if (res >= 0)
            return res + 24; /* [24, 29] */
          return -1;

        case E_VNx2HImode:
          res = pattern29 (E_VNx2HImode);
          if (res >= 0)
            return res + 30; /* [30, 35] */
          return -1;

        case E_VNx2SImode:
          res = pattern29 (E_VNx2SImode);
          if (res >= 0)
            return res + 36; /* [36, 41] */
          return -1;

        case E_VNx2DImode:
          res = pattern29 (E_VNx2DImode);
          if (res >= 0)
            return res + 42; /* [42, 47] */
          return -1;

        default:
          return -1;
        }

    case E_VNx4BImode:
      if (!vector_mask_operand (operands[0], E_VNx4BImode))
        return -1;
      switch (GET_MODE (operands[2]))
        {
        case E_VNx4QImode:
          res = pattern30 (E_VNx4QImode);
          if (res >= 0)
            return res + 48; /* [48, 53] */
          return -1;

        case E_VNx4HImode:
          res = pattern30 (E_VNx4HImode);
          if (res >= 0)
            return res + 54; /* [54, 59] */
          return -1;

        case E_VNx4SImode:
          res = pattern30 (E_VNx4SImode);
          if (res >= 0)
            return res + 60; /* [60, 65] */
          return -1;

        case E_VNx4DImode:
          res = pattern30 (E_VNx4DImode);
          if (res >= 0)
            return res + 66; /* [66, 71] */
          return -1;

        default:
          return -1;
        }

    case E_VNx8BImode:
      if (!vector_mask_operand (operands[0], E_VNx8BImode))
        return -1;
      switch (GET_MODE (operands[2]))
        {
        case E_VNx8QImode:
          res = pattern31 (E_VNx8QImode);
          if (res >= 0)
            return res + 72; /* [72, 77] */
          return -1;

        case E_VNx8HImode:
          res = pattern31 (E_VNx8HImode);
          if (res >= 0)
            return res + 78; /* [78, 83] */
          return -1;

        case E_VNx8SImode:
          res = pattern31 (E_VNx8SImode);
          if (res >= 0)
            return res + 84; /* [84, 89] */
          return -1;

        case E_VNx8DImode:
          res = pattern31 (E_VNx8DImode);
          if (res >= 0)
            return res + 90; /* [90, 95] */
          return -1;

        default:
          return -1;
        }

    case E_VNx16BImode:
      if (!vector_mask_operand (operands[0], E_VNx16BImode))
        return -1;
      switch (GET_MODE (operands[2]))
        {
        case E_VNx16QImode:
          res = pattern32 (E_VNx16QImode);
          if (res >= 0)
            return res + 96; /* [96, 99] */
          return -1;

        case E_VNx16HImode:
          res = pattern32 (E_VNx16HImode);
          if (res >= 0)
            return res + 100; /* [100, 103] */
          return -1;

        case E_VNx16SImode:
          res = pattern32 (E_VNx16SImode);
          if (res >= 0)
            return res + 104; /* [104, 107] */
          return -1;

        default:
          return -1;
        }

    case E_VNx32BImode:
      if (!vector_mask_operand (operands[0], E_VNx32BImode))
        return -1;
      switch (GET_MODE (operands[2]))
        {
        case E_VNx32QImode:
          res = pattern33 (E_VNx32QImode);
          if (res >= 0)
            return res + 108; /* [108, 109] */
          return -1;

        case E_VNx32HImode:
          res = pattern33 (E_VNx32HImode);
          if (res >= 0)
            return res + 110; /* [110, 111] */
          return -1;

        default:
          return -1;
        }

    case E_VNx64BImode:
      if (!vector_mask_operand (operands[0], E_VNx64BImode)
          || !register_operand (operands[2], E_VNx64QImode)
          || !register_operand (operands[3], E_VNx64QImode))
        return -1;
      return 112;

    default:
      return -1;
    }
}

static int
pattern35 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3, machine_mode i4, machine_mode i5)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx1BImode:
      if (!vector_mask_operand (operands[1], E_VNx1BImode)
          || !register_operand (operands[3], i1))
        return -1;
      return 0;

    case E_VNx2BImode:
      if (!vector_mask_operand (operands[1], E_VNx2BImode)
          || !register_operand (operands[3], i2))
        return -1;
      return 1;

    case E_VNx4BImode:
      if (!vector_mask_operand (operands[1], E_VNx4BImode)
          || !register_operand (operands[3], i3))
        return -1;
      return 2;

    case E_VNx8BImode:
      if (!vector_mask_operand (operands[1], E_VNx8BImode)
          || !register_operand (operands[3], i4))
        return -1;
      return 3;

    case E_VNx16BImode:
      if (!vector_mask_operand (operands[1], E_VNx16BImode)
          || !register_operand (operands[3], i5))
        return -1;
      return 4;

    default:
      return -1;
    }
}

static int
pattern36 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  if (GET_CODE (x3) != UNSPEC
      || XVECLEN (x3, 0) != 6
      || XINT (x3, 1) != 68)
    return -1;
  x4 = XVECEXP (x3, 0, 4);
  if (GET_CODE (x4) != REG
      || REGNO (x4) != 66
      || GET_MODE (x4) != E_SImode)
    return -1;
  x5 = XVECEXP (x3, 0, 5);
  if (GET_CODE (x5) != REG
      || REGNO (x5) != 67
      || GET_MODE (x5) != E_SImode)
    return -1;
  x6 = XEXP (x1, 0);
  operands[0] = x6;
  x7 = XVECEXP (x3, 0, 0);
  operands[1] = x7;
  x8 = XVECEXP (x3, 0, 1);
  operands[5] = x8;
  if (!vector_length_operand (operands[5], E_VOIDmode))
    return -1;
  x9 = XVECEXP (x3, 0, 2);
  operands[6] = x9;
  if (!const_int_operand (operands[6], E_VOIDmode))
    return -1;
  x10 = XVECEXP (x3, 0, 3);
  operands[7] = x10;
  if (!const_int_operand (operands[7], E_VOIDmode))
    return -1;
  x11 = XVECEXP (x2, 0, 1);
  operands[3] = x11;
  x12 = XVECEXP (x2, 0, 2);
  operands[4] = x12;
  x13 = XVECEXP (x2, 0, 3);
  operands[2] = x13;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx4HImode:
      if (!register_operand (operands[0], E_VNx4HImode)
          || GET_MODE (x2) != E_VNx4HImode
          || !register_operand (operands[4], E_VNx4HImode)
          || !vector_merge_operand (operands[2], E_VNx4HImode))
        return -1;
      switch (GET_MODE (x3))
        {
        case E_VNx1BImode:
          if (!vector_mask_operand (operands[1], E_VNx1BImode)
              || !register_operand (operands[3], E_VNx1QImode))
            return -1;
          return 0;

        case E_VNx2BImode:
          if (!vector_mask_operand (operands[1], E_VNx2BImode)
              || !register_operand (operands[3], E_VNx2QImode))
            return -1;
          return 1;

        case E_VNx4BImode:
          if (!vector_mask_operand (operands[1], E_VNx4BImode)
              || !register_operand (operands[3], E_VNx4QImode))
            return -1;
          return 2;

        case E_VNx8BImode:
          if (!vector_mask_operand (operands[1], E_VNx8BImode)
              || !register_operand (operands[3], E_VNx8QImode))
            return -1;
          return 3;

        case E_VNx16BImode:
          if (!vector_mask_operand (operands[1], E_VNx16BImode)
              || !register_operand (operands[3], E_VNx16QImode))
            return -1;
          return 4;

        case E_VNx32BImode:
          if (!vector_mask_operand (operands[1], E_VNx32BImode)
              || !register_operand (operands[3], E_VNx32QImode))
            return -1;
          return 5;

        case E_VNx64BImode:
          if (!vector_mask_operand (operands[1], E_VNx64BImode)
              || !register_operand (operands[3], E_VNx64QImode))
            return -1;
          return 6;

        default:
          return -1;
        }

    case E_VNx2SImode:
      if (!register_operand (operands[0], E_VNx2SImode)
          || GET_MODE (x2) != E_VNx2SImode
          || !register_operand (operands[4], E_VNx2SImode)
          || !vector_merge_operand (operands[2], E_VNx2SImode))
        return -1;
      switch (GET_MODE (x3))
        {
        case E_VNx1BImode:
          if (!vector_mask_operand (operands[1], E_VNx1BImode)
              || !register_operand (operands[3], E_VNx1HImode))
            return -1;
          return 7;

        case E_VNx2BImode:
          if (!vector_mask_operand (operands[1], E_VNx2BImode)
              || !register_operand (operands[3], E_VNx2HImode))
            return -1;
          return 8;

        case E_VNx4BImode:
          if (!vector_mask_operand (operands[1], E_VNx4BImode)
              || !register_operand (operands[3], E_VNx4HImode))
            return -1;
          return 9;

        case E_VNx8BImode:
          if (!vector_mask_operand (operands[1], E_VNx8BImode)
              || !register_operand (operands[3], E_VNx8HImode))
            return -1;
          return 10;

        case E_VNx16BImode:
          if (!vector_mask_operand (operands[1], E_VNx16BImode)
              || !register_operand (operands[3], E_VNx16HImode))
            return -1;
          return 11;

        case E_VNx32BImode:
          if (!vector_mask_operand (operands[1], E_VNx32BImode)
              || !register_operand (operands[3], E_VNx32HImode))
            return -1;
          return 12;

        default:
          return -1;
        }

    case E_VNx1DImode:
      if (!register_operand (operands[0], E_VNx1DImode)
          || GET_MODE (x2) != E_VNx1DImode
          || !register_operand (operands[4], E_VNx1DImode)
          || !vector_merge_operand (operands[2], E_VNx1DImode))
        return -1;
      res = pattern35 (x3, E_VNx1SImode, E_VNx2SImode, E_VNx4SImode, E_VNx8SImode, E_VNx16SImode);
      if (res >= 0)
        return res + 13; /* [13, 17] */
      return -1;

    case E_VNx2HImode:
      if (!register_operand (operands[0], E_VNx2HImode)
          || GET_MODE (x2) != E_VNx2HImode
          || !register_operand (operands[4], E_VNx2HImode)
          || !vector_merge_operand (operands[2], E_VNx2HImode))
        return -1;
      switch (GET_MODE (x3))
        {
        case E_VNx1BImode:
          if (!vector_mask_operand (operands[1], E_VNx1BImode)
              || !register_operand (operands[3], E_VNx1QImode))
            return -1;
          return 18;

        case E_VNx2BImode:
          if (!vector_mask_operand (operands[1], E_VNx2BImode)
              || !register_operand (operands[3], E_VNx2QImode))
            return -1;
          return 19;

        case E_VNx4BImode:
          if (!vector_mask_operand (operands[1], E_VNx4BImode)
              || !register_operand (operands[3], E_VNx4QImode))
            return -1;
          return 20;

        case E_VNx8BImode:
          if (!vector_mask_operand (operands[1], E_VNx8BImode)
              || !register_operand (operands[3], E_VNx8QImode))
            return -1;
          return 21;

        case E_VNx16BImode:
          if (!vector_mask_operand (operands[1], E_VNx16BImode)
              || !register_operand (operands[3], E_VNx16QImode))
            return -1;
          return 22;

        case E_VNx32BImode:
          if (!vector_mask_operand (operands[1], E_VNx32BImode)
              || !register_operand (operands[3], E_VNx32QImode))
            return -1;
          return 23;

        default:
          return -1;
        }

    case E_VNx1SImode:
      if (!register_operand (operands[0], E_VNx1SImode)
          || GET_MODE (x2) != E_VNx1SImode
          || !register_operand (operands[4], E_VNx1SImode)
          || !vector_merge_operand (operands[2], E_VNx1SImode))
        return -1;
      res = pattern35 (x3, E_VNx1HImode, E_VNx2HImode, E_VNx4HImode, E_VNx8HImode, E_VNx16HImode);
      if (res >= 0)
        return res + 24; /* [24, 28] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern37 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2)
      || !vector_merge_operand (operands[2], i1)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern38 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  if (GET_CODE (x3) != UNSPEC
      || XVECLEN (x3, 0) != 7
      || XINT (x3, 1) != 68)
    return -1;
  x4 = XVECEXP (x3, 0, 5);
  if (GET_CODE (x4) != REG
      || REGNO (x4) != 66
      || GET_MODE (x4) != E_SImode)
    return -1;
  x5 = XVECEXP (x3, 0, 6);
  if (GET_CODE (x5) != REG
      || REGNO (x5) != 67
      || GET_MODE (x5) != E_SImode)
    return -1;
  x6 = XEXP (x1, 0);
  operands[0] = x6;
  x7 = XVECEXP (x3, 0, 0);
  operands[1] = x7;
  x8 = XVECEXP (x3, 0, 1);
  operands[5] = x8;
  if (!vector_length_operand (operands[5], E_VOIDmode))
    return -1;
  x9 = XVECEXP (x3, 0, 2);
  operands[6] = x9;
  if (!const_int_operand (operands[6], E_VOIDmode))
    return -1;
  x10 = XVECEXP (x3, 0, 3);
  operands[7] = x10;
  if (!const_int_operand (operands[7], E_VOIDmode))
    return -1;
  x11 = XVECEXP (x3, 0, 4);
  operands[8] = x11;
  if (!const_int_operand (operands[8], E_VOIDmode))
    return -1;
  x12 = XVECEXP (x2, 0, 1);
  operands[2] = x12;
  x13 = XVECEXP (x2, 0, 2);
  operands[3] = x13;
  x14 = XVECEXP (x2, 0, 3);
  operands[4] = x14;
  if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode))
    return -1;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      return pattern37 (x2, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2QImode:
      if (pattern37 (x2, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4QImode:
      if (pattern37 (x2, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8QImode:
      if (pattern37 (x2, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16QImode:
      if (pattern37 (x2, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32QImode:
      if (pattern37 (x2, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx64QImode:
      if (pattern37 (x2, E_VNx64QImode, E_VNx64BImode) != 0)
        return -1;
      return 6;

    case E_VNx1HImode:
      if (pattern37 (x2, E_VNx1HImode, E_VNx1BImode) != 0)
        return -1;
      return 7;

    case E_VNx2HImode:
      if (pattern37 (x2, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      return 8;

    case E_VNx4HImode:
      if (pattern37 (x2, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      return 9;

    case E_VNx8HImode:
      if (pattern37 (x2, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      return 10;

    case E_VNx16HImode:
      if (pattern37 (x2, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      return 11;

    case E_VNx32HImode:
      if (pattern37 (x2, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      return 12;

    case E_VNx1SImode:
      if (pattern37 (x2, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      return 13;

    case E_VNx2SImode:
      if (pattern37 (x2, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      return 14;

    case E_VNx4SImode:
      if (pattern37 (x2, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      return 15;

    case E_VNx8SImode:
      if (pattern37 (x2, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      return 16;

    case E_VNx16SImode:
      if (pattern37 (x2, E_VNx16SImode, E_VNx16BImode) != 0)
        return -1;
      return 17;

    case E_VNx1DImode:
      if (pattern37 (x2, E_VNx1DImode, E_VNx1BImode) != 0)
        return -1;
      return 18;

    case E_VNx2DImode:
      if (pattern37 (x2, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      return 19;

    case E_VNx4DImode:
      if (pattern37 (x2, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      return 20;

    case E_VNx8DImode:
      if (pattern37 (x2, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      return 21;

    case E_VNx1SFmode:
      if (pattern37 (x2, E_VNx1SFmode, E_VNx1BImode) != 0)
        return -1;
      return 22;

    case E_VNx2SFmode:
      if (pattern37 (x2, E_VNx2SFmode, E_VNx2BImode) != 0)
        return -1;
      return 23;

    case E_VNx4SFmode:
      if (pattern37 (x2, E_VNx4SFmode, E_VNx4BImode) != 0)
        return -1;
      return 24;

    case E_VNx8SFmode:
      if (pattern37 (x2, E_VNx8SFmode, E_VNx8BImode) != 0)
        return -1;
      return 25;

    case E_VNx16SFmode:
      if (pattern37 (x2, E_VNx16SFmode, E_VNx16BImode) != 0)
        return -1;
      return 26;

    case E_VNx1DFmode:
      if (pattern37 (x2, E_VNx1DFmode, E_VNx1BImode) != 0)
        return -1;
      return 27;

    case E_VNx2DFmode:
      if (pattern37 (x2, E_VNx2DFmode, E_VNx2BImode) != 0)
        return -1;
      return 28;

    case E_VNx4DFmode:
      if (pattern37 (x2, E_VNx4DFmode, E_VNx4BImode) != 0)
        return -1;
      return 29;

    case E_VNx8DFmode:
      if (pattern37 (x2, E_VNx8DFmode, E_VNx8BImode) != 0)
        return -1;
      return 30;

    default:
      return -1;
    }
}

static int
pattern39 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2)
      || !vector_merge_operand (operands[2], i1)
      || !register_operand (operands[3], i1)
      || !reg_or_0_operand (operands[4], i3))
    return -1;
  return 0;
}

static int
pattern40 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  if (GET_CODE (x3) != UNSPEC
      || XVECLEN (x3, 0) != 7
      || XINT (x3, 1) != 68)
    return -1;
  x4 = XVECEXP (x3, 0, 5);
  if (GET_CODE (x4) != REG
      || REGNO (x4) != 66
      || GET_MODE (x4) != E_SImode)
    return -1;
  x5 = XVECEXP (x3, 0, 6);
  if (GET_CODE (x5) != REG
      || REGNO (x5) != 67
      || GET_MODE (x5) != E_SImode)
    return -1;
  x6 = XEXP (x1, 0);
  operands[0] = x6;
  x7 = XVECEXP (x3, 0, 0);
  operands[1] = x7;
  x8 = XVECEXP (x3, 0, 1);
  operands[5] = x8;
  if (!vector_length_operand (operands[5], E_VOIDmode))
    return -1;
  x9 = XVECEXP (x3, 0, 2);
  operands[6] = x9;
  if (!const_int_operand (operands[6], E_VOIDmode))
    return -1;
  x10 = XVECEXP (x3, 0, 3);
  operands[7] = x10;
  if (!const_int_operand (operands[7], E_VOIDmode))
    return -1;
  x11 = XVECEXP (x3, 0, 4);
  operands[8] = x11;
  if (!const_int_operand (operands[8], E_VOIDmode))
    return -1;
  x12 = XVECEXP (x2, 0, 1);
  operands[2] = x12;
  x13 = XVECEXP (x2, 0, 2);
  operands[3] = x13;
  x14 = XVECEXP (x2, 0, 3);
  switch (GET_CODE (x14))
    {
    case CONST_INT:
    case CONST_WIDE_INT:
    case CONST_VECTOR:
    case REG:
    case SUBREG:
      operands[4] = x14;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          return pattern39 (x2, E_VNx1QImode, E_VNx1BImode, E_QImode); /* [-1, 0] */

        case E_VNx2QImode:
          if (pattern39 (x2, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
            return -1;
          return 1;

        case E_VNx4QImode:
          if (pattern39 (x2, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
            return -1;
          return 2;

        case E_VNx8QImode:
          if (pattern39 (x2, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
            return -1;
          return 3;

        case E_VNx16QImode:
          if (pattern39 (x2, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
            return -1;
          return 4;

        case E_VNx32QImode:
          if (pattern39 (x2, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
            return -1;
          return 5;

        case E_VNx64QImode:
          if (pattern39 (x2, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0)
            return -1;
          return 6;

        case E_VNx1HImode:
          if (pattern39 (x2, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
            return -1;
          return 7;

        case E_VNx2HImode:
          if (pattern39 (x2, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
            return -1;
          return 8;

        case E_VNx4HImode:
          if (pattern39 (x2, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
            return -1;
          return 9;

        case E_VNx8HImode:
          if (pattern39 (x2, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
            return -1;
          return 10;

        case E_VNx16HImode:
          if (pattern39 (x2, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
            return -1;
          return 11;

        case E_VNx32HImode:
          if (pattern39 (x2, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0)
            return -1;
          return 12;

        case E_VNx1SImode:
          if (pattern39 (x2, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
            return -1;
          return 13;

        case E_VNx2SImode:
          if (pattern39 (x2, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
            return -1;
          return 14;

        case E_VNx4SImode:
          if (pattern39 (x2, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
            return -1;
          return 15;

        case E_VNx8SImode:
          if (pattern39 (x2, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
            return -1;
          return 16;

        case E_VNx16SImode:
          if (pattern39 (x2, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0)
            return -1;
          return 17;

        case E_VNx1DImode:
          if (pattern39 (x2, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0)
            return -1;
          return 18;

        case E_VNx2DImode:
          if (pattern39 (x2, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0)
            return -1;
          return 19;

        case E_VNx4DImode:
          if (pattern39 (x2, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0)
            return -1;
          return 20;

        case E_VNx8DImode:
          if (pattern39 (x2, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0)
            return -1;
          return 21;

        default:
          return -1;
        }

    case SIGN_EXTEND:
      if (GET_MODE (x14) != E_DImode)
        return -1;
      x15 = XEXP (x14, 0);
      operands[4] = x15;
      if (!reg_or_0_operand (operands[4], E_SImode))
        return -1;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1DImode:
          if (pattern37 (x2, E_VNx1DImode, E_VNx1BImode) != 0)
            return -1;
          return 22;

        case E_VNx2DImode:
          if (pattern37 (x2, E_VNx2DImode, E_VNx2BImode) != 0)
            return -1;
          return 23;

        case E_VNx4DImode:
          if (pattern37 (x2, E_VNx4DImode, E_VNx4BImode) != 0)
            return -1;
          return 24;

        case E_VNx8DImode:
          if (pattern37 (x2, E_VNx8DImode, E_VNx8BImode) != 0)
            return -1;
          return 25;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern41 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2)
      || !vector_merge_operand (operands[2], i1)
      || !register_operand (operands[3], i1)
      || !register_operand (operands[4], i3))
    return -1;
  return 0;
}

static int
pattern42 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  if (GET_CODE (x3) != UNSPEC
      || XVECLEN (x3, 0) != 7
      || XINT (x3, 1) != 68)
    return -1;
  x4 = XVECEXP (x3, 0, 5);
  if (GET_CODE (x4) != REG
      || REGNO (x4) != 66
      || GET_MODE (x4) != E_SImode)
    return -1;
  x5 = XVECEXP (x3, 0, 6);
  if (GET_CODE (x5) != REG
      || REGNO (x5) != 67
      || GET_MODE (x5) != E_SImode)
    return -1;
  x6 = XEXP (x1, 0);
  operands[0] = x6;
  x7 = XVECEXP (x3, 0, 0);
  operands[1] = x7;
  x8 = XVECEXP (x3, 0, 1);
  operands[5] = x8;
  if (!vector_length_operand (operands[5], E_VOIDmode))
    return -1;
  x9 = XVECEXP (x3, 0, 2);
  operands[6] = x9;
  if (!const_int_operand (operands[6], E_VOIDmode))
    return -1;
  x10 = XVECEXP (x3, 0, 3);
  operands[7] = x10;
  if (!const_int_operand (operands[7], E_VOIDmode))
    return -1;
  x11 = XVECEXP (x3, 0, 4);
  operands[8] = x11;
  if (!const_int_operand (operands[8], E_VOIDmode))
    return -1;
  x12 = XVECEXP (x2, 0, 1);
  operands[2] = x12;
  x13 = XVECEXP (x2, 0, 2);
  operands[3] = x13;
  x14 = XVECEXP (x2, 0, 3);
  operands[4] = x14;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1SFmode:
      return pattern41 (x2, E_VNx1SFmode, E_VNx1BImode, E_SFmode); /* [-1, 0] */

    case E_VNx2SFmode:
      if (pattern41 (x2, E_VNx2SFmode, E_VNx2BImode, E_SFmode) != 0)
        return -1;
      return 1;

    case E_VNx4SFmode:
      if (pattern41 (x2, E_VNx4SFmode, E_VNx4BImode, E_SFmode) != 0)
        return -1;
      return 2;

    case E_VNx8SFmode:
      if (pattern41 (x2, E_VNx8SFmode, E_VNx8BImode, E_SFmode) != 0)
        return -1;
      return 3;

    case E_VNx16SFmode:
      if (pattern41 (x2, E_VNx16SFmode, E_VNx16BImode, E_SFmode) != 0)
        return -1;
      return 4;

    case E_VNx1DFmode:
      if (pattern41 (x2, E_VNx1DFmode, E_VNx1BImode, E_DFmode) != 0)
        return -1;
      return 5;

    case E_VNx2DFmode:
      if (pattern41 (x2, E_VNx2DFmode, E_VNx2BImode, E_DFmode) != 0)
        return -1;
      return 6;

    case E_VNx4DFmode:
      if (pattern41 (x2, E_VNx4DFmode, E_VNx4BImode, E_DFmode) != 0)
        return -1;
      return 7;

    case E_VNx8DFmode:
      if (pattern41 (x2, E_VNx8DFmode, E_VNx8BImode, E_DFmode) != 0)
        return -1;
      return 8;

    default:
      return -1;
    }
}

static int
pattern43 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[0], E_DImode)
      || GET_MODE (x1) != E_DImode)
    return -1;
  x3 = XEXP (x2, 0);
  operands[1] = x3;
  if (!register_operand (operands[1], i1))
    return -1;
  x4 = XEXP (x2, 1);
  operands[2] = x4;
  return 0;
}

static int
pattern44 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern45 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XEXP (x2, 0);
  operands[1] = x3;
  x4 = XEXP (x1, 1);
  operands[2] = x4;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      return pattern44 (x1, E_SImode); /* [-1, 0] */

    case E_DImode:
      if (pattern44 (x1, E_DImode) != 0)
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern46 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern47 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[2], E_QImode))
    return -1;
  x2 = XEXP (x1, 1);
  operands[1] = x2;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      return pattern46 (x1, E_SImode); /* [-1, 0] */

    case E_DImode:
      if (pattern46 (x1, E_DImode) != 0)
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern48 (rtx x1, int i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XEXP (x2, 0);
  if (x3 != const_int_rtx[MAX_SAVED_CONST_INT + i1])
    return -1;
  x4 = XEXP (x2, 1);
  operands[2] = x4;
  return pattern47 (x1); /* [-1, 1] */
}

static int
pattern49 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  operands[2] = x2;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (!register_operand (operands[0], E_SImode)
          || GET_MODE (x1) != E_SImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_SImode:
          if (!register_operand (operands[1], E_SImode)
              || !reg_or_0_operand (operands[2], E_SImode))
            return -1;
          return 0;

        case E_DImode:
          if (!register_operand (operands[1], E_DImode)
              || !reg_or_0_operand (operands[2], E_DImode))
            return -1;
          return 1;

        default:
          return -1;
        }

    case E_DImode:
      if (pattern3 (x1, E_DImode) != 0)
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern50 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  operands[2] = x2;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (!register_operand (operands[0], E_SImode)
          || GET_MODE (x1) != E_SImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_SImode:
          if (!register_operand (operands[1], E_SImode)
              || !sle_operand (operands[2], E_SImode))
            return -1;
          return 0;

        case E_DImode:
          if (!register_operand (operands[1], E_DImode)
              || !sle_operand (operands[2], E_DImode))
            return -1;
          return 1;

        default:
          return -1;
        }

    case E_DImode:
      if (!register_operand (operands[0], E_DImode)
          || GET_MODE (x1) != E_DImode
          || !register_operand (operands[1], E_DImode)
          || !sle_operand (operands[2], E_DImode))
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern51 (rtx x1, machine_mode i1, rtx_code i2, rtx_code i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (GET_MODE (x1) != E_DImode)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_CODE (x2) != i3
      || GET_MODE (x2) != i1)
    return -1;
  x3 = XEXP (x2, 0);
  if (GET_CODE (x3) != i2
      || GET_MODE (x3) != i1)
    return -1;
  return 0;
}

static int
pattern52 (rtx x1, rtx_code i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  x3 = XEXP (x2, 1);
  if (GET_MODE (x3) != E_DImode)
    return -1;
  x4 = XVECEXP (x1, 0, 1);
  if (GET_CODE (x4) != SET)
    return -1;
  x5 = XEXP (x4, 1);
  if (GET_CODE (x5) != i1
      || GET_MODE (x5) != E_DImode)
    return -1;
  x6 = XEXP (x2, 0);
  operands[0] = x6;
  if (!register_operand (operands[0], E_DImode))
    return -1;
  x7 = XEXP (x3, 0);
  operands[1] = x7;
  if (!memory_operand (operands[1], E_SImode))
    return -1;
  x8 = XEXP (x4, 0);
  operands[2] = x8;
  if (!register_operand (operands[2], E_DImode))
    return -1;
  x9 = XEXP (x5, 0);
  operands[3] = x9;
  if (!memory_operand (operands[3], E_SImode))
    return -1;
  return 0;
}

static int
pattern53 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (GET_MODE (x1) != E_DImode)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_CODE (x2) != SUBREG
      || maybe_ne (SUBREG_BYTE (x2), 0)
      || GET_MODE (x2) != E_SImode)
    return -1;
  return 0;
}

static int
pattern54 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  if (!equality_operator (x3, E_VOIDmode))
    return -1;
  operands[1] = x3;
  x4 = XEXP (x3, 0);
  if (GET_CODE (x4) != AND)
    return -1;
  x5 = XEXP (x2, 1);
  if (GET_CODE (x5) != LABEL_REF)
    return -1;
  x6 = XEXP (x2, 2);
  if (GET_CODE (x6) != PC)
    return -1;
  x7 = XEXP (x1, 0);
  if (GET_CODE (x7) != PC)
    return -1;
  return 0;
}

static int
pattern55 (rtx x1, int i1, int i2, rtx_code i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (GET_CODE (x1) != SET)
    return -1;
  x2 = XEXP (x1, 1);
  if (GET_CODE (x2) != i3
      || XVECLEN (x2, 0) != i2
      || XINT (x2, 1) != i1
      || GET_MODE (x2) != E_SImode)
    return -1;
  return 0;
}

static int
pattern56 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[2] = x2;
  x3 = XEXP (x1, 1);
  operands[3] = x3;
  if (!const_int_operand (operands[3], E_VOIDmode))
    return -1;
  switch (GET_MODE (x1))
    {
    case E_SImode:
      if (!register_operand (operands[2], E_SImode))
        return -1;
      return 0;

    case E_DImode:
      if (!register_operand (operands[2], E_DImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern57 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != E_SImode)
    return -1;
  x3 = XEXP (x2, 1);
  if (!subreg_lowpart_operator (x3, E_VOIDmode))
    return -1;
  operands[4] = x3;
  x4 = XEXP (x3, 0);
  if (GET_CODE (x4) != AND
      || !register_operand (operands[0], E_DImode)
      || GET_MODE (x1) != E_DImode)
    return -1;
  x5 = XEXP (x2, 0);
  operands[1] = x5;
  if (!register_operand (operands[1], E_SImode))
    return -1;
  return pattern56 (x4); /* [-1, 1] */
}

static int
pattern58 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (maybe_ne (SUBREG_BYTE (x1), 0))
    return -1;
  x2 = XEXP (x1, 0);
  operands[1] = x2;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx2QImode:
      if (!register_operand (operands[0], E_VNx2QImode)
          || GET_MODE (x1) != E_VNx2QImode
          || !register_operand (operands[1], E_VNx1QImode))
        return -1;
      return 0;

    case E_VNx4QImode:
      if (!register_operand (operands[0], E_VNx4QImode)
          || GET_MODE (x1) != E_VNx4QImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx2QImode:
          if (!register_operand (operands[1], E_VNx2QImode))
            return -1;
          return 1;

        case E_VNx1QImode:
          if (!register_operand (operands[1], E_VNx1QImode))
            return -1;
          return 2;

        default:
          return -1;
        }

    case E_VNx8QImode:
      if (!register_operand (operands[0], E_VNx8QImode)
          || GET_MODE (x1) != E_VNx8QImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx4QImode:
          if (!register_operand (operands[1], E_VNx4QImode))
            return -1;
          return 3;

        case E_VNx2QImode:
          if (!register_operand (operands[1], E_VNx2QImode))
            return -1;
          return 4;

        case E_VNx1QImode:
          if (!register_operand (operands[1], E_VNx1QImode))
            return -1;
          return 5;

        default:
          return -1;
        }

    case E_VNx16QImode:
      if (!register_operand (operands[0], E_VNx16QImode)
          || GET_MODE (x1) != E_VNx16QImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx8QImode:
          if (!register_operand (operands[1], E_VNx8QImode))
            return -1;
          return 6;

        case E_VNx4QImode:
          if (!register_operand (operands[1], E_VNx4QImode))
            return -1;
          return 7;

        case E_VNx2QImode:
          if (!register_operand (operands[1], E_VNx2QImode))
            return -1;
          return 8;

        case E_VNx1QImode:
          if (!register_operand (operands[1], E_VNx1QImode))
            return -1;
          return 9;

        default:
          return -1;
        }

    case E_VNx32QImode:
      if (!register_operand (operands[0], E_VNx32QImode)
          || GET_MODE (x1) != E_VNx32QImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx16QImode:
          if (!register_operand (operands[1], E_VNx16QImode))
            return -1;
          return 10;

        case E_VNx8QImode:
          if (!register_operand (operands[1], E_VNx8QImode))
            return -1;
          return 11;

        case E_VNx4QImode:
          if (!register_operand (operands[1], E_VNx4QImode))
            return -1;
          return 12;

        case E_VNx2QImode:
          if (!register_operand (operands[1], E_VNx2QImode))
            return -1;
          return 13;

        case E_VNx1QImode:
          if (!register_operand (operands[1], E_VNx1QImode))
            return -1;
          return 14;

        default:
          return -1;
        }

    case E_VNx64QImode:
      if (!register_operand (operands[0], E_VNx64QImode)
          || GET_MODE (x1) != E_VNx64QImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx32QImode:
          if (!register_operand (operands[1], E_VNx32QImode))
            return -1;
          return 15;

        case E_VNx16QImode:
          if (!register_operand (operands[1], E_VNx16QImode))
            return -1;
          return 16;

        case E_VNx8QImode:
          if (!register_operand (operands[1], E_VNx8QImode))
            return -1;
          return 17;

        case E_VNx4QImode:
          if (!register_operand (operands[1], E_VNx4QImode))
            return -1;
          return 18;

        case E_VNx2QImode:
          if (!register_operand (operands[1], E_VNx2QImode))
            return -1;
          return 19;

        case E_VNx1QImode:
          if (!register_operand (operands[1], E_VNx1QImode))
            return -1;
          return 20;

        default:
          return -1;
        }

    case E_VNx2HImode:
      if (!register_operand (operands[0], E_VNx2HImode)
          || GET_MODE (x1) != E_VNx2HImode
          || !register_operand (operands[1], E_VNx1HImode))
        return -1;
      return 21;

    case E_VNx4HImode:
      if (!register_operand (operands[0], E_VNx4HImode)
          || GET_MODE (x1) != E_VNx4HImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx2HImode:
          if (!register_operand (operands[1], E_VNx2HImode))
            return -1;
          return 22;

        case E_VNx1HImode:
          if (!register_operand (operands[1], E_VNx1HImode))
            return -1;
          return 23;

        default:
          return -1;
        }

    case E_VNx8HImode:
      if (!register_operand (operands[0], E_VNx8HImode)
          || GET_MODE (x1) != E_VNx8HImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx4HImode:
          if (!register_operand (operands[1], E_VNx4HImode))
            return -1;
          return 24;

        case E_VNx2HImode:
          if (!register_operand (operands[1], E_VNx2HImode))
            return -1;
          return 25;

        case E_VNx1HImode:
          if (!register_operand (operands[1], E_VNx1HImode))
            return -1;
          return 26;

        default:
          return -1;
        }

    case E_VNx16HImode:
      if (!register_operand (operands[0], E_VNx16HImode)
          || GET_MODE (x1) != E_VNx16HImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx8HImode:
          if (!register_operand (operands[1], E_VNx8HImode))
            return -1;
          return 27;

        case E_VNx4HImode:
          if (!register_operand (operands[1], E_VNx4HImode))
            return -1;
          return 28;

        case E_VNx2HImode:
          if (!register_operand (operands[1], E_VNx2HImode))
            return -1;
          return 29;

        case E_VNx1HImode:
          if (!register_operand (operands[1], E_VNx1HImode))
            return -1;
          return 30;

        default:
          return -1;
        }

    case E_VNx32HImode:
      if (!register_operand (operands[0], E_VNx32HImode)
          || GET_MODE (x1) != E_VNx32HImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx16HImode:
          if (!register_operand (operands[1], E_VNx16HImode))
            return -1;
          return 31;

        case E_VNx8HImode:
          if (!register_operand (operands[1], E_VNx8HImode))
            return -1;
          return 32;

        case E_VNx4HImode:
          if (!register_operand (operands[1], E_VNx4HImode))
            return -1;
          return 33;

        case E_VNx2HImode:
          if (!register_operand (operands[1], E_VNx2HImode))
            return -1;
          return 34;

        case E_VNx1HImode:
          if (!register_operand (operands[1], E_VNx1HImode))
            return -1;
          return 35;

        default:
          return -1;
        }

    case E_VNx2SImode:
      if (!register_operand (operands[0], E_VNx2SImode)
          || GET_MODE (x1) != E_VNx2SImode
          || !register_operand (operands[1], E_VNx1SImode))
        return -1;
      return 36;

    case E_VNx4SImode:
      if (!register_operand (operands[0], E_VNx4SImode)
          || GET_MODE (x1) != E_VNx4SImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx2SImode:
          if (!register_operand (operands[1], E_VNx2SImode))
            return -1;
          return 37;

        case E_VNx1SImode:
          if (!register_operand (operands[1], E_VNx1SImode))
            return -1;
          return 38;

        default:
          return -1;
        }

    case E_VNx8SImode:
      if (!register_operand (operands[0], E_VNx8SImode)
          || GET_MODE (x1) != E_VNx8SImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx4SImode:
          if (!register_operand (operands[1], E_VNx4SImode))
            return -1;
          return 39;

        case E_VNx2SImode:
          if (!register_operand (operands[1], E_VNx2SImode))
            return -1;
          return 40;

        case E_VNx1SImode:
          if (!register_operand (operands[1], E_VNx1SImode))
            return -1;
          return 41;

        default:
          return -1;
        }

    case E_VNx16SImode:
      if (!register_operand (operands[0], E_VNx16SImode)
          || GET_MODE (x1) != E_VNx16SImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx8SImode:
          if (!register_operand (operands[1], E_VNx8SImode))
            return -1;
          return 42;

        case E_VNx4SImode:
          if (!register_operand (operands[1], E_VNx4SImode))
            return -1;
          return 43;

        case E_VNx2SImode:
          if (!register_operand (operands[1], E_VNx2SImode))
            return -1;
          return 44;

        case E_VNx1SImode:
          if (!register_operand (operands[1], E_VNx1SImode))
            return -1;
          return 45;

        default:
          return -1;
        }

    case E_VNx2DImode:
      if (!register_operand (operands[0], E_VNx2DImode)
          || GET_MODE (x1) != E_VNx2DImode
          || !register_operand (operands[1], E_VNx1DImode))
        return -1;
      return 46;

    case E_VNx4DImode:
      if (!register_operand (operands[0], E_VNx4DImode)
          || GET_MODE (x1) != E_VNx4DImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx2DImode:
          if (!register_operand (operands[1], E_VNx2DImode))
            return -1;
          return 47;

        case E_VNx1DImode:
          if (!register_operand (operands[1], E_VNx1DImode))
            return -1;
          return 48;

        default:
          return -1;
        }

    case E_VNx8DImode:
      if (!register_operand (operands[0], E_VNx8DImode)
          || GET_MODE (x1) != E_VNx8DImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx4DImode:
          if (!register_operand (operands[1], E_VNx4DImode))
            return -1;
          return 49;

        case E_VNx2DImode:
          if (!register_operand (operands[1], E_VNx2DImode))
            return -1;
          return 50;

        case E_VNx1DImode:
          if (!register_operand (operands[1], E_VNx1DImode))
            return -1;
          return 51;

        default:
          return -1;
        }

    case E_VNx2SFmode:
      if (!register_operand (operands[0], E_VNx2SFmode)
          || GET_MODE (x1) != E_VNx2SFmode
          || !register_operand (operands[1], E_VNx1SFmode))
        return -1;
      return 52;

    case E_VNx4SFmode:
      if (!register_operand (operands[0], E_VNx4SFmode)
          || GET_MODE (x1) != E_VNx4SFmode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx2SFmode:
          if (!register_operand (operands[1], E_VNx2SFmode))
            return -1;
          return 53;

        case E_VNx1SFmode:
          if (!register_operand (operands[1], E_VNx1SFmode))
            return -1;
          return 54;

        default:
          return -1;
        }

    case E_VNx8SFmode:
      if (!register_operand (operands[0], E_VNx8SFmode)
          || GET_MODE (x1) != E_VNx8SFmode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx4SFmode:
          if (!register_operand (operands[1], E_VNx4SFmode))
            return -1;
          return 55;

        case E_VNx2SFmode:
          if (!register_operand (operands[1], E_VNx2SFmode))
            return -1;
          return 56;

        case E_VNx1SFmode:
          if (!register_operand (operands[1], E_VNx1SFmode))
            return -1;
          return 57;

        default:
          return -1;
        }

    case E_VNx16SFmode:
      if (!register_operand (operands[0], E_VNx16SFmode)
          || GET_MODE (x1) != E_VNx16SFmode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx8SFmode:
          if (!register_operand (operands[1], E_VNx8SFmode))
            return -1;
          return 58;

        case E_VNx4SFmode:
          if (!register_operand (operands[1], E_VNx4SFmode))
            return -1;
          return 59;

        case E_VNx2SFmode:
          if (!register_operand (operands[1], E_VNx2SFmode))
            return -1;
          return 60;

        case E_VNx1SFmode:
          if (!register_operand (operands[1], E_VNx1SFmode))
            return -1;
          return 61;

        default:
          return -1;
        }

    case E_VNx2DFmode:
      if (!register_operand (operands[0], E_VNx2DFmode)
          || GET_MODE (x1) != E_VNx2DFmode
          || !register_operand (operands[1], E_VNx1DFmode))
        return -1;
      return 62;

    case E_VNx4DFmode:
      if (!register_operand (operands[0], E_VNx4DFmode)
          || GET_MODE (x1) != E_VNx4DFmode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx2DFmode:
          if (!register_operand (operands[1], E_VNx2DFmode))
            return -1;
          return 63;

        case E_VNx1DFmode:
          if (!register_operand (operands[1], E_VNx1DFmode))
            return -1;
          return 64;

        default:
          return -1;
        }

    case E_VNx8DFmode:
      if (!register_operand (operands[0], E_VNx8DFmode)
          || GET_MODE (x1) != E_VNx8DFmode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx4DFmode:
          if (!register_operand (operands[1], E_VNx4DFmode))
            return -1;
          return 65;

        case E_VNx2DFmode:
          if (!register_operand (operands[1], E_VNx2DFmode))
            return -1;
          return 66;

        case E_VNx1DFmode:
          if (!register_operand (operands[1], E_VNx1DFmode))
            return -1;
          return 67;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern59 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  switch (GET_MODE (operands[1]))
    {
    case E_SFmode:
      if (!register_operand (operands[1], E_SFmode))
        return -1;
      return 0;

    case E_DFmode:
      if (!register_operand (operands[1], E_DFmode))
        return -1;
      return 1;

    case E_HFmode:
      if (!register_operand (operands[1], E_HFmode))
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern60 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  operands[1] = x2;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      return pattern59 (x1, E_SImode); /* [-1, 2] */

    case E_DImode:
      res = pattern59 (x1, E_DImode);
      if (res >= 0)
        return res + 3; /* [3, 5] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern61 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  operands[1] = x2;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (!register_operand (operands[0], E_SImode)
          || GET_MODE (x1) != E_SImode
          || !symbolic_operand (operands[1], E_SImode))
        return -1;
      return 0;

    case E_DImode:
      if (!register_operand (operands[0], E_DImode)
          || GET_MODE (x1) != E_DImode
          || !symbolic_operand (operands[1], E_DImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern62 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  operands[1] = x2;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (!register_operand (operands[0], E_SImode)
          || GET_MODE (x1) != E_SImode
          || !register_operand (operands[1], E_SImode))
        return -1;
      return 0;

    case E_DImode:
      if (!register_operand (operands[0], E_DImode)
          || GET_MODE (x1) != E_DImode
          || !register_operand (operands[1], E_DImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern63 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (GET_MODE (x1) != E_SImode
      || !register_operand (operands[0], E_SImode))
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  operands[1] = x2;
  switch (GET_MODE (operands[1]))
    {
    case E_SImode:
      if (!register_operand (operands[1], E_SImode))
        return -1;
      return 0;

    case E_DFmode:
      if (!register_operand (operands[1], E_DFmode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern64 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!vector_mask_operand (operands[1], i2)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern65 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15, x16, x17;
  rtx x18;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_CODE (x2) != UNSPEC)
    return -1;
  switch (XVECLEN (x2, 0))
    {
    case 3:
      if (XINT (x2, 1) != 103)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      if (GET_CODE (x3) != UNSPEC
          || XVECLEN (x3, 0) != 6
          || XINT (x3, 1) != 68)
        return -1;
      x4 = XVECEXP (x3, 0, 4);
      if (GET_CODE (x4) != REG
          || REGNO (x4) != 66
          || GET_MODE (x4) != E_SImode)
        return -1;
      x5 = XVECEXP (x3, 0, 5);
      if (GET_CODE (x5) != REG
          || REGNO (x5) != 67
          || GET_MODE (x5) != E_SImode)
        return -1;
      x6 = XVECEXP (x2, 0, 1);
      if (GET_CODE (x6) != PLUS)
        return -1;
      x7 = XEXP (x6, 0);
      if (GET_CODE (x7) != VEC_DUPLICATE)
        return -1;
      x8 = XEXP (x7, 0);
      if (GET_CODE (x8) != VEC_SELECT)
        return -1;
      x9 = XEXP (x8, 1);
      if (GET_CODE (x9) != PARALLEL
          || XVECLEN (x9, 0) != 1)
        return -1;
      x10 = XVECEXP (x9, 0, 0);
      if (x10 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
        return -1;
      x11 = XVECEXP (x3, 0, 0);
      operands[1] = x11;
      x12 = XVECEXP (x3, 0, 1);
      operands[5] = x12;
      if (!vector_length_operand (operands[5], E_VOIDmode))
        return -1;
      x13 = XVECEXP (x3, 0, 2);
      operands[6] = x13;
      if (!const_int_operand (operands[6], E_VOIDmode))
        return -1;
      x14 = XVECEXP (x3, 0, 3);
      operands[7] = x14;
      if (!const_int_operand (operands[7], E_VOIDmode))
        return -1;
      x15 = XEXP (x8, 0);
      operands[4] = x15;
      x16 = XEXP (x6, 1);
      operands[3] = x16;
      x17 = XVECEXP (x2, 0, 2);
      operands[2] = x17;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx2SFmode:
          if (!register_operand (operands[0], E_VNx2SFmode)
              || GET_MODE (x1) != E_VNx2SFmode
              || GET_MODE (x2) != E_VNx2SFmode
              || GET_MODE (x8) != E_SFmode
              || !register_operand (operands[4], E_VNx2SFmode)
              || !vector_merge_operand (operands[2], E_VNx2SFmode))
            return -1;
          switch (GET_MODE (x3))
            {
            case E_VNx1BImode:
              return pattern64 (x6, E_VNx1SFmode, E_VNx1BImode); /* [-1, 0] */

            case E_VNx2BImode:
              if (pattern64 (x6, E_VNx2SFmode, E_VNx2BImode) != 0)
                return -1;
              return 1;

            case E_VNx4BImode:
              if (pattern64 (x6, E_VNx4SFmode, E_VNx4BImode) != 0)
                return -1;
              return 2;

            case E_VNx8BImode:
              if (pattern64 (x6, E_VNx8SFmode, E_VNx8BImode) != 0)
                return -1;
              return 3;

            case E_VNx16BImode:
              if (pattern64 (x6, E_VNx16SFmode, E_VNx16BImode) != 0)
                return -1;
              return 4;

            default:
              return -1;
            }

        case E_VNx1DFmode:
          if (!register_operand (operands[0], E_VNx1DFmode)
              || GET_MODE (x1) != E_VNx1DFmode
              || GET_MODE (x2) != E_VNx1DFmode
              || GET_MODE (x8) != E_DFmode
              || !register_operand (operands[4], E_VNx1DFmode)
              || !vector_merge_operand (operands[2], E_VNx1DFmode))
            return -1;
          switch (GET_MODE (x3))
            {
            case E_VNx1BImode:
              if (pattern64 (x6, E_VNx1DFmode, E_VNx1BImode) != 0)
                return -1;
              return 5;

            case E_VNx2BImode:
              if (pattern64 (x6, E_VNx2DFmode, E_VNx2BImode) != 0)
                return -1;
              return 6;

            case E_VNx4BImode:
              if (pattern64 (x6, E_VNx4DFmode, E_VNx4BImode) != 0)
                return -1;
              return 7;

            case E_VNx8BImode:
              if (pattern64 (x6, E_VNx8DFmode, E_VNx8BImode) != 0)
                return -1;
              return 8;

            default:
              return -1;
            }

        default:
          return -1;
        }

    case 4:
      if (XINT (x2, 1) != 104
          || GET_MODE (x2) != E_VNx1DFmode)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      if (GET_CODE (x3) != UNSPEC
          || XVECLEN (x3, 0) != 6
          || XINT (x3, 1) != 68)
        return -1;
      x4 = XVECEXP (x3, 0, 4);
      if (GET_CODE (x4) != REG
          || REGNO (x4) != 66
          || GET_MODE (x4) != E_SImode)
        return -1;
      x5 = XVECEXP (x3, 0, 5);
      if (GET_CODE (x5) != REG
          || REGNO (x5) != 67
          || GET_MODE (x5) != E_SImode
          || !register_operand (operands[0], E_VNx1DFmode)
          || GET_MODE (x1) != E_VNx1DFmode)
        return -1;
      x11 = XVECEXP (x3, 0, 0);
      operands[1] = x11;
      x12 = XVECEXP (x3, 0, 1);
      operands[5] = x12;
      if (!vector_length_operand (operands[5], E_VOIDmode))
        return -1;
      x13 = XVECEXP (x3, 0, 2);
      operands[6] = x13;
      if (!const_int_operand (operands[6], E_VOIDmode))
        return -1;
      x14 = XVECEXP (x3, 0, 3);
      operands[7] = x14;
      if (!const_int_operand (operands[7], E_VOIDmode))
        return -1;
      x6 = XVECEXP (x2, 0, 1);
      operands[3] = x6;
      x17 = XVECEXP (x2, 0, 2);
      operands[4] = x17;
      if (!register_operand (operands[4], E_VNx1DFmode))
        return -1;
      x18 = XVECEXP (x2, 0, 3);
      operands[2] = x18;
      if (!vector_merge_operand (operands[2], E_VNx1DFmode))
        return -1;
      switch (GET_MODE (x3))
        {
        case E_VNx1BImode:
          if (!vector_mask_operand (operands[1], E_VNx1BImode)
              || !register_operand (operands[3], E_VNx1SFmode))
            return -1;
          return 9;

        case E_VNx2BImode:
          if (!vector_mask_operand (operands[1], E_VNx2BImode)
              || !register_operand (operands[3], E_VNx2SFmode))
            return -1;
          return 10;

        case E_VNx4BImode:
          if (!vector_mask_operand (operands[1], E_VNx4BImode)
              || !register_operand (operands[3], E_VNx4SFmode))
            return -1;
          return 11;

        case E_VNx8BImode:
          if (!vector_mask_operand (operands[1], E_VNx8BImode)
              || !register_operand (operands[3], E_VNx8SFmode))
            return -1;
          return 12;

        case E_VNx16BImode:
          if (!vector_mask_operand (operands[1], E_VNx16BImode)
              || !register_operand (operands[3], E_VNx16SFmode))
            return -1;
          return 13;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern66 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (GET_MODE (x1) != E_SImode
      || !register_operand (operands[0], E_SImode))
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  operands[1] = x2;
  if (!register_operand (operands[1], E_SImode))
    return -1;
  x3 = XVECEXP (x1, 0, 1);
  operands[2] = x3;
  if (!register_operand (operands[2], E_SImode))
    return -1;
  x4 = XVECEXP (x1, 0, 2);
  operands[3] = x4;
  if (!register_operand (operands[3], E_SImode))
    return -1;
  return 0;
}

static int
pattern67 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  operands[1] = x2;
  x3 = XVECEXP (x1, 0, 1);
  operands[2] = x3;
  x4 = XVECEXP (x1, 0, 2);
  operands[3] = x4;
  if (!register_operand (operands[3], E_SImode))
    return -1;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      return pattern24 (x1, E_SImode); /* [-1, 0] */

    case E_DImode:
      if (pattern24 (x1, E_DImode) != 0)
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern68 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x2, 0);
  if (GET_MODE (x3) != i2
      || !register_operand (operands[1], i2)
      || !register_operand (operands[3], i1))
    return -1;
  x4 = XVECEXP (x1, 0, 2);
  if (GET_MODE (x4) != i1)
    return -1;
  return 0;
}

static int
pattern69 (rtx x1, rtx_code i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_CODE (x2) != i1)
    return -1;
  x3 = XVECEXP (x1, 0, 2);
  if (GET_CODE (x3) != UNSPEC
      || XVECLEN (x3, 0) != 4
      || XINT (x3, 1) != 68)
    return -1;
  x4 = XVECEXP (x3, 0, 2);
  if (GET_CODE (x4) != REG
      || REGNO (x4) != 66
      || GET_MODE (x4) != E_SImode)
    return -1;
  x5 = XVECEXP (x3, 0, 3);
  if (GET_CODE (x5) != REG
      || REGNO (x5) != 67
      || GET_MODE (x5) != E_SImode)
    return -1;
  x6 = XVECEXP (x1, 0, 1);
  operands[3] = x6;
  x7 = XVECEXP (x3, 0, 0);
  operands[4] = x7;
  if (!vector_length_operand (operands[4], E_VOIDmode))
    return -1;
  x8 = XVECEXP (x3, 0, 1);
  operands[5] = x8;
  if (!const_int_operand (operands[5], E_VOIDmode))
    return -1;
  x9 = XEXP (x2, 0);
  switch (GET_CODE (x9))
    {
    case REG:
    case SUBREG:
      operands[1] = x9;
      x10 = XEXP (x2, 1);
      operands[2] = x10;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1BImode:
          return 0;

        case E_VNx2BImode:
          return 1;

        case E_VNx4BImode:
          return 2;

        case E_VNx8BImode:
          return 3;

        case E_VNx16BImode:
          return 4;

        case E_VNx32BImode:
          return 5;

        case E_VNx64BImode:
          return 6;

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x10 = XEXP (x2, 1);
      operands[1] = x10;
      x11 = XEXP (x9, 0);
      switch (GET_CODE (x11))
        {
        case CONST_INT:
        case CONST_WIDE_INT:
        case CONST_VECTOR:
        case REG:
        case SUBREG:
          operands[2] = x11;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1BImode:
              return 7;

            case E_VNx2BImode:
              return 8;

            case E_VNx4BImode:
              return 9;

            case E_VNx8BImode:
              return 10;

            case E_VNx16BImode:
              return 11;

            case E_VNx32BImode:
              return 12;

            case E_VNx64BImode:
              return 13;

            default:
              return -1;
            }

        case SIGN_EXTEND:
          if (GET_MODE (x11) != E_DImode)
            return -1;
          x12 = XEXP (x11, 0);
          operands[2] = x12;
          if (!reg_or_0_operand (operands[2], E_SImode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1BImode:
              if (pattern68 (x1, E_VNx1BImode, E_VNx1DImode) != 0)
                return -1;
              return 14;

            case E_VNx2BImode:
              if (pattern68 (x1, E_VNx2BImode, E_VNx2DImode) != 0)
                return -1;
              return 15;

            case E_VNx4BImode:
              if (pattern68 (x1, E_VNx4BImode, E_VNx4DImode) != 0)
                return -1;
              return 16;

            case E_VNx8BImode:
              if (pattern68 (x1, E_VNx8BImode, E_VNx8DImode) != 0)
                return -1;
              return 17;

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern70 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (GET_CODE (x1) != UNSPEC
      || XVECLEN (x1, 0) != 6
      || XINT (x1, 1) != 68)
    return -1;
  x2 = XVECEXP (x1, 0, 4);
  if (GET_CODE (x2) != REG
      || REGNO (x2) != 66
      || GET_MODE (x2) != E_SImode)
    return -1;
  x3 = XVECEXP (x1, 0, 5);
  if (GET_CODE (x3) != REG
      || REGNO (x3) != 67
      || GET_MODE (x3) != E_SImode)
    return -1;
  return 0;
}

static int
pattern71 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  operands[1] = x2;
  x3 = XVECEXP (x1, 0, 1);
  operands[2] = x3;
  if (!const_int_operand (operands[2], E_VOIDmode))
    return -1;
  x4 = XVECEXP (x1, 0, 2);
  operands[3] = x4;
  if (!const_int_operand (operands[3], E_VOIDmode))
    return -1;
  x5 = XVECEXP (x1, 0, 3);
  operands[4] = x5;
  if (!const_int_operand (operands[4], E_VOIDmode))
    return -1;
  x6 = XVECEXP (x1, 0, 4);
  operands[5] = x6;
  if (!const_int_operand (operands[5], E_VOIDmode))
    return -1;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (!register_operand (operands[0], E_SImode)
          || GET_MODE (x1) != E_SImode
          || !csr_operand (operands[1], E_SImode))
        return -1;
      return 0;

    case E_DImode:
      if (!register_operand (operands[0], E_DImode)
          || GET_MODE (x1) != E_DImode
          || !csr_operand (operands[1], E_DImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern72 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  operands[4] = x2;
  x3 = XEXP (x2, 0);
  if (GET_CODE (x3) != AND)
    return -1;
  return pattern15 (x1); /* [-1, 3] */
}

static int
pattern73 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1)
      || !arith_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern74 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (!register_operand (operands[0], E_SImode)
          || GET_MODE (x1) != E_SImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_SImode:
          if (!register_operand (operands[1], E_SImode)
              || !arith_operand (operands[2], E_SImode))
            return -1;
          return 0;

        case E_DImode:
          if (!register_operand (operands[1], E_DImode)
              || !arith_operand (operands[2], E_DImode))
            return -1;
          return 1;

        default:
          return -1;
        }

    case E_DImode:
      if (pattern73 (x1, E_DImode) != 0)
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern75 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!const_int_operand (operands[2], E_VOIDmode))
    return -1;
  x2 = XEXP (x1, 2);
  operands[3] = x2;
  if (!const_int_operand (operands[3], E_VOIDmode))
    return -1;
  return pattern12 (x1); /* [-1, 1] */
}

static int
pattern76 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  if (!equality_operator (x3, E_VOIDmode))
    return -1;
  x4 = XEXP (x3, 1);
  if (x4 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
    return -1;
  x5 = XEXP (x2, 1);
  if (GET_CODE (x5) != LABEL_REF)
    return -1;
  x6 = XEXP (x2, 2);
  if (GET_CODE (x6) != PC)
    return -1;
  x7 = XEXP (x1, 0);
  if (GET_CODE (x7) != PC)
    return -1;
  return 0;
}

static int
pattern77 (rtx x1, rtx_code i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  if (GET_MODE (x1) != E_DImode
      || !register_operand (operands[0], E_DImode))
    return -1;
  x2 = XEXP (x1, 0);
  operands[1] = x2;
  if (!memory_operand (operands[1], E_SImode))
    return -1;
  x3 = PATTERN (peep2_next_insn (1));
  x4 = XEXP (x3, 1);
  if (GET_CODE (x4) != i1
      || GET_MODE (x4) != E_DImode)
    return -1;
  x5 = XEXP (x3, 0);
  operands[2] = x5;
  if (!register_operand (operands[2], E_DImode))
    return -1;
  x6 = XEXP (x4, 0);
  operands[3] = x6;
  if (!memory_operand (operands[3], E_SImode))
    return -1;
  return 0;
}

static int
pattern78 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  switch (GET_MODE (operands[1]))
    {
    case E_QImode:
      if (!nonimmediate_operand (operands[1], E_QImode))
        return -1;
      return 0;

    case E_HImode:
      if (!nonimmediate_operand (operands[1], E_HImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern79 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1)
      || !symbolic_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern80 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 5);
  if (GET_CODE (x2) != REG
      || REGNO (x2) != 66
      || GET_MODE (x2) != E_SImode)
    return -1;
  x3 = XVECEXP (x1, 0, 6);
  if (GET_CODE (x3) != REG
      || REGNO (x3) != 67
      || GET_MODE (x3) != E_SImode)
    return -1;
  x4 = XVECEXP (x1, 0, 0);
  operands[1] = x4;
  x5 = XVECEXP (x1, 0, 1);
  if (!vector_length_operand (x5, E_VOIDmode))
    return -1;
  x6 = XVECEXP (x1, 0, 2);
  if (!const_int_operand (x6, E_VOIDmode))
    return -1;
  x7 = XVECEXP (x1, 0, 3);
  if (!const_int_operand (x7, E_VOIDmode))
    return -1;
  x8 = XVECEXP (x1, 0, 4);
  if (!const_int_operand (x8, E_VOIDmode))
    return -1;
  return 0;
}

static int
pattern81 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 3);
  if (GET_CODE (x2) != REG
      || REGNO (x2) != 66
      || GET_MODE (x2) != E_SImode)
    return -1;
  x3 = XVECEXP (x1, 0, 4);
  if (GET_CODE (x3) != REG
      || REGNO (x3) != 67
      || GET_MODE (x3) != E_SImode)
    return -1;
  return 0;
}

static int
pattern82 (rtx x1, unsigned int i1, int i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (GET_CODE (x1) != SET)
    return -1;
  x2 = XEXP (x1, 1);
  if (GET_CODE (x2) != UNSPEC
      || XVECLEN (x2, 0) != i2
      || XINT (x2, 1) != 66
      || GET_MODE (x2) != E_SImode)
    return -1;
  x3 = XEXP (x1, 0);
  if (GET_CODE (x3) != REG
      || REGNO (x3) != i1
      || GET_MODE (x3) != E_SImode)
    return -1;
  return 0;
}

static int
pattern83 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], E_HImode)
      || GET_MODE (x1) != E_HImode)
    return -1;
  switch (GET_MODE (operands[1]))
    {
    case E_HImode:
      if (!register_operand (operands[1], E_HImode)
          || !arith_operand (operands[2], E_HImode))
        return -1;
      return 0;

    case E_SImode:
      if (!register_operand (operands[1], E_SImode)
          || !arith_operand (operands[2], E_SImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern84 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !reg_or_0_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern85 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern86 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (!register_operand (operands[0], E_SImode)
          || GET_MODE (x1) != E_SImode)
        return -1;
      return 0;

    case E_DImode:
      if (!register_operand (operands[0], E_DImode)
          || GET_MODE (x1) != E_DImode)
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern87 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || !fp_native_comparison (operands[1], i1))
    return -1;
  switch (GET_MODE (operands[2]))
    {
    case E_SFmode:
      if (!register_operand (operands[2], E_SFmode)
          || !register_operand (operands[3], E_SFmode))
        return -1;
      return 0;

    case E_DFmode:
      if (!register_operand (operands[2], E_DFmode)
          || !register_operand (operands[3], E_DFmode))
        return -1;
      return 1;

    case E_HFmode:
      if (!register_operand (operands[2], E_HFmode)
          || !register_operand (operands[3], E_HFmode))
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern88 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern89 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  switch (GET_MODE (operands[1]))
    {
    case E_HImode:
      if (!register_operand (operands[1], E_HImode)
          || !register_operand (operands[2], E_HImode))
        return -1;
      return 0;

    case E_SImode:
      if (!register_operand (operands[1], E_SImode)
          || !register_operand (operands[2], E_SImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern90 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !reg_or_0_operand (operands[2], i1)
      || !reg_or_0_operand (operands[3], i1))
    return -1;
  switch (GET_MODE (operands[1]))
    {
    case E_SImode:
      if (!register_operand (operands[1], E_SImode))
        return -1;
      return 0;

    case E_DImode:
      if (!register_operand (operands[1], E_DImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern91 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!memory_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != i1
      || !reg_or_0_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern92 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  x3 = XEXP (x2, 1);
  operands[1] = x3;
  x4 = XEXP (x2, 0);
  if (!rtx_equal_p (x4, operands[0]))
    return -1;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      return pattern91 (x1, E_SImode); /* [-1, 0] */

    case E_DImode:
      if (pattern91 (x1, E_DImode) != 0)
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern93 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!reg_or_mem_operand (operands[0], i1)
      || !reg_or_mem_operand (operands[1], i1))
    return -1;
  switch (GET_MODE (operands[2]))
    {
    case E_SImode:
      if (!scratch_operand (operands[2], E_SImode))
        return -1;
      return 0;

    case E_DImode:
      if (!scratch_operand (operands[2], E_DImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern94 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern95 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[3], i1))
    return -1;
  x2 = XEXP (x1, 1);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern96 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x2, 0);
  if (GET_MODE (x3) != i2)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i2
      || !register_operand (operands[1], i1))
    return -1;
  x5 = XEXP (x3, 1);
  if (GET_MODE (x5) != i2
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern97 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 1);
  x5 = XEXP (x4, 0);
  operands[2] = x5;
  x6 = XEXP (x2, 1);
  switch (XWINT (x6, 0))
    {
    case 64L:
      return pattern96 (x1, E_DImode, E_TImode); /* [-1, 0] */

    case 32L:
      if (pattern96 (x1, E_SImode, E_DImode) != 0)
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern98 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern99 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  x2 = XEXP (x1, 2);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern100 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  x3 = XEXP (x1, 2);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern101 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern102 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !memory_operand (operands[1], i1)
      || !memory_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern103 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1)
      || !symbolic_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern104 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !symbolic_operand (operands[1], i1)
      || !const_int_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern105 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern106 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  operands[4] = x1;
  x2 = XEXP (x1, 0);
  if (GET_CODE (x2) != AND)
    return -1;
  return pattern56 (x2); /* [-1, 1] */
}

static int
pattern107 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1)
    return -1;
  x3 = XEXP (x2, 0);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  x4 = XEXP (x2, 2);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern108 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1)
    return -1;
  x3 = XEXP (x2, 0);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern109 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern110 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  x3 = XEXP (x2, 2);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern111 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[1], i1))
    return -1;
  x2 = XEXP (x1, 2);
  if (GET_MODE (x2) != i1)
    return -1;
  return 0;
}

static int
pattern112 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  x5 = XEXP (x4, 0);
  operands[1] = x5;
  if (!register_operand (operands[1], E_DImode))
    return -1;
  x6 = XEXP (x4, 1);
  operands[2] = x6;
  if (!immediate_operand (operands[2], E_QImode))
    return -1;
  x7 = XEXP (x3, 1);
  operands[3] = x7;
  if (!immediate_operand (operands[3], E_VOIDmode))
    return -1;
  x8 = XVECEXP (x1, 0, 1);
  x9 = XEXP (x8, 0);
  operands[4] = x9;
  if (!scratch_operand (operands[4], E_DImode))
    return -1;
  return 0;
}

static int
pattern113 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  if (GET_CODE (x2) != ZERO_EXTEND
      || GET_MODE (x2) != E_DImode)
    return -1;
  x3 = XEXP (x2, 0);
  operands[1] = x3;
  if (!register_operand (operands[1], E_SImode))
    return -1;
  x4 = XEXP (x1, 1);
  operands[2] = x4;
  if (!immediate_operand (operands[2], E_DImode))
    return -1;
  return 0;
}

static int
pattern114 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  x3 = XEXP (x2, 0);
  operands[0] = x3;
  if (!register_operand (operands[0], E_DImode))
    return -1;
  x4 = XEXP (x2, 1);
  x5 = XEXP (x4, 0);
  x6 = XEXP (x5, 0);
  if (GET_MODE (x6) != E_DImode)
    return -1;
  x7 = XVECEXP (x1, 0, 1);
  x8 = XEXP (x7, 0);
  operands[3] = x8;
  if (!scratch_operand (operands[3], E_DImode))
    return -1;
  x9 = XVECEXP (x1, 0, 2);
  x10 = XEXP (x9, 0);
  operands[4] = x10;
  if (!scratch_operand (operands[4], E_DImode))
    return -1;
  switch (GET_CODE (x6))
    {
    case SMIN:
      return pattern113 (x6); /* [-1, 0] */

    case UMIN:
      if (pattern113 (x6) != 0)
        return -1;
      return 1;

    case SMAX:
      if (pattern113 (x6) != 0)
        return -1;
      return 2;

    case UMAX:
      if (pattern113 (x6) != 0)
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern115 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1)
    return -1;
  x3 = XEXP (x2, 0);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern116 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 1);
  x3 = XEXP (x2, 0);
  operands[4] = x3;
  x4 = XVECEXP (x1, 0, 0);
  x5 = XEXP (x4, 1);
  x6 = XEXP (x5, 0);
  x7 = XEXP (x6, 0);
  switch (GET_CODE (x7))
    {
    case AND:
      operands[1] = x6;
      x8 = XEXP (x7, 0);
      operands[2] = x8;
      x9 = XEXP (x7, 1);
      operands[3] = x9;
      x10 = XEXP (x5, 1);
      x11 = XEXP (x10, 0);
      operands[0] = x11;
      switch (GET_MODE (x7))
        {
        case E_QImode:
          if (!register_operand (operands[2], E_QImode))
            return -1;
          return 0;

        case E_HImode:
          if (!register_operand (operands[2], E_HImode))
            return -1;
          return 1;

        case E_SImode:
          if (!register_operand (operands[2], E_SImode))
            return -1;
          return 2;

        case E_DImode:
          if (!register_operand (operands[2], E_DImode))
            return -1;
          return 3;

        default:
          return -1;
        }

    case ZERO_EXTRACT:
      x9 = XEXP (x7, 1);
      if (GET_CODE (x9) != CONST_INT)
        return -1;
      operands[0] = x6;
      x8 = XEXP (x7, 0);
      operands[2] = x8;
      x10 = XEXP (x5, 1);
      x11 = XEXP (x10, 0);
      operands[1] = x11;
      return 4;

    default:
      return -1;
    }
}

static int
pattern117 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!memory_operand (operands[0], i1)
      || !register_operand (operands[1], i1)
      || !memory_operand (operands[2], i1)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern118 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  switch (GET_MODE (operands[2]))
    {
    case E_SImode:
      if (!scratch_operand (operands[2], E_SImode))
        return -1;
      return 0;

    case E_DImode:
      if (!scratch_operand (operands[2], E_DImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern119 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  if (GET_CODE (x2) != ZERO_EXTEND
      || GET_MODE (x2) != E_DImode)
    return -1;
  x3 = XEXP (x2, 0);
  operands[1] = x3;
  if (!register_operand (operands[1], E_SImode))
    return -1;
  x4 = XEXP (x1, 1);
  operands[2] = x4;
  if (!immediate_operand (operands[2], E_DImode))
    return -1;
  return 0;
}

static int
pattern120 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern121 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!reg_or_0_operand (operands[1], i1))
    return -1;
  switch (GET_MODE (operands[2]))
    {
    case E_SImode:
      if (!scratch_operand (operands[2], E_SImode))
        return -1;
      return 0;

    case E_DImode:
      if (!scratch_operand (operands[2], E_DImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern122 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[1], i1))
    return -1;
  switch (GET_MODE (operands[2]))
    {
    case E_SImode:
      if (!scratch_operand (operands[2], E_SImode))
        return -1;
      return 0;

    case E_DImode:
      if (!scratch_operand (operands[2], E_DImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern123 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!memory_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !memory_operand (operands[1], i1)
      || !scratch_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern124 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !memory_operand (operands[1], i1)
      || !memory_operand (operands[2], i1)
      || !scratch_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern125 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[2], i1)
      || !const_twobits_not_arith_operand (operands[3], i1)
      || !single_bit_mask_operand (operands[4], i1)
      || !scratch_operand (operands[5], i1)
      || !scratch_operand (operands[6], i1))
    return -1;
  return 0;
}

static int
pattern126 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  x5 = XEXP (x4, 0);
  x6 = XEXP (x5, 0);
  operands[2] = x6;
  x7 = XEXP (x5, 1);
  operands[3] = x7;
  x8 = XEXP (x4, 1);
  operands[4] = x8;
  x9 = XEXP (x3, 1);
  x10 = XEXP (x9, 0);
  operands[0] = x10;
  x11 = XVECEXP (x1, 0, 1);
  x12 = XEXP (x11, 0);
  operands[5] = x12;
  x13 = XVECEXP (x1, 0, 2);
  x14 = XEXP (x13, 0);
  operands[6] = x14;
  switch (GET_MODE (x5))
    {
    case E_SImode:
      return pattern125 (E_SImode); /* [-1, 0] */

    case E_DImode:
      if (pattern125 (E_DImode) != 0)
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern127 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1)
    return -1;
  x3 = XEXP (x2, 0);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern128 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1)
    return -1;
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern129 (machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || !memory_operand (operands[1], i1)
      || !register_operand (operands[2], i1)
      || !memory_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern130 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], E_QImode)
      || GET_MODE (x1) != E_QImode)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != E_QImode)
    return -1;
  switch (GET_MODE (operands[1]))
    {
    case E_VNx1QImode:
      if (!register_operand (operands[1], E_VNx1QImode))
        return -1;
      return 0;

    case E_VNx2QImode:
      if (!register_operand (operands[1], E_VNx2QImode))
        return -1;
      return 1;

    case E_VNx4QImode:
      if (!register_operand (operands[1], E_VNx4QImode))
        return -1;
      return 2;

    case E_VNx8QImode:
      if (!register_operand (operands[1], E_VNx8QImode))
        return -1;
      return 3;

    case E_VNx16QImode:
      if (!register_operand (operands[1], E_VNx16QImode))
        return -1;
      return 4;

    case E_VNx32QImode:
      if (!register_operand (operands[1], E_VNx32QImode))
        return -1;
      return 5;

    case E_VNx64QImode:
      if (!register_operand (operands[1], E_VNx64QImode))
        return -1;
      return 6;

    default:
      return -1;
    }
}

static int
pattern131 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], E_HImode)
      || GET_MODE (x1) != E_HImode)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != E_HImode)
    return -1;
  switch (GET_MODE (operands[1]))
    {
    case E_VNx1HImode:
      if (!register_operand (operands[1], E_VNx1HImode))
        return -1;
      return 0;

    case E_VNx2HImode:
      if (!register_operand (operands[1], E_VNx2HImode))
        return -1;
      return 1;

    case E_VNx4HImode:
      if (!register_operand (operands[1], E_VNx4HImode))
        return -1;
      return 2;

    case E_VNx8HImode:
      if (!register_operand (operands[1], E_VNx8HImode))
        return -1;
      return 3;

    case E_VNx16HImode:
      if (!register_operand (operands[1], E_VNx16HImode))
        return -1;
      return 4;

    case E_VNx32HImode:
      if (!register_operand (operands[1], E_VNx32HImode))
        return -1;
      return 5;

    default:
      return -1;
    }
}

static int
pattern132 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], E_SImode)
      || GET_MODE (x1) != E_SImode)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != E_SImode)
    return -1;
  switch (GET_MODE (operands[1]))
    {
    case E_VNx1SImode:
      if (!register_operand (operands[1], E_VNx1SImode))
        return -1;
      return 0;

    case E_VNx2SImode:
      if (!register_operand (operands[1], E_VNx2SImode))
        return -1;
      return 1;

    case E_VNx4SImode:
      if (!register_operand (operands[1], E_VNx4SImode))
        return -1;
      return 2;

    case E_VNx8SImode:
      if (!register_operand (operands[1], E_VNx8SImode))
        return -1;
      return 3;

    case E_VNx16SImode:
      if (!register_operand (operands[1], E_VNx16SImode))
        return -1;
      return 4;

    default:
      return -1;
    }
}

static int
pattern133 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], E_DImode)
      || GET_MODE (x1) != E_DImode)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != E_DImode)
    return -1;
  switch (GET_MODE (operands[1]))
    {
    case E_VNx1DImode:
      if (!register_operand (operands[1], E_VNx1DImode))
        return -1;
      return 0;

    case E_VNx2DImode:
      if (!register_operand (operands[1], E_VNx2DImode))
        return -1;
      return 1;

    case E_VNx4DImode:
      if (!register_operand (operands[1], E_VNx4DImode))
        return -1;
      return 2;

    case E_VNx8DImode:
      if (!register_operand (operands[1], E_VNx8DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern134 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !memory_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern135 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[1], i1)
      || !register_operand (operands[3], i1)
      || !register_operand (operands[4], i1))
    return -1;
  return 0;
}

static int
pattern136 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || !memory_operand (operands[1], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != i1
      || !reg_or_0_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern137 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  x3 = XEXP (x2, 1);
  operands[2] = x3;
  x4 = XEXP (x2, 0);
  if (!rtx_equal_p (x4, operands[1]))
    return -1;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      return pattern136 (x1, E_SImode); /* [-1, 0] */

    case E_DImode:
      if (pattern136 (x1, E_DImode) != 0)
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern138 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_SImode:
      if (!register_operand (operands[2], E_SImode)
          || !scratch_operand (operands[4], E_SImode))
        return -1;
      return 0;

    case E_DImode:
      if (!register_operand (operands[2], E_DImode)
          || !scratch_operand (operands[4], E_DImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern139 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 2);
  operands[3] = x2;
  if (!branch_on_bit_operand (operands[3], E_VOIDmode))
    return -1;
  return pattern138 (x1); /* [-1, 1] */
}

static int
pattern140 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  operands[3] = x2;
  if (!branch_on_bit_operand (operands[3], E_VOIDmode))
    return -1;
  return pattern138 (x1); /* [-1, 1] */
}

static int
pattern141 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!nonimmediate_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2)
      || !vector_move_operand (operands[3], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern142 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  operands[3] = x2;
  x3 = XEXP (x1, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[4] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[5] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[6] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[7] = x7;
  x8 = XEXP (x1, 2);
  operands[2] = x8;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      return pattern141 (x1, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2QImode:
      if (pattern141 (x1, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4QImode:
      if (pattern141 (x1, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8QImode:
      if (pattern141 (x1, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16QImode:
      if (pattern141 (x1, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32QImode:
      if (pattern141 (x1, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx64QImode:
      if (pattern141 (x1, E_VNx64QImode, E_VNx64BImode) != 0)
        return -1;
      return 6;

    case E_VNx1HImode:
      if (pattern141 (x1, E_VNx1HImode, E_VNx1BImode) != 0)
        return -1;
      return 7;

    case E_VNx2HImode:
      if (pattern141 (x1, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      return 8;

    case E_VNx4HImode:
      if (pattern141 (x1, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      return 9;

    case E_VNx8HImode:
      if (pattern141 (x1, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      return 10;

    case E_VNx16HImode:
      if (pattern141 (x1, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      return 11;

    case E_VNx32HImode:
      if (pattern141 (x1, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      return 12;

    case E_VNx1SImode:
      if (pattern141 (x1, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      return 13;

    case E_VNx2SImode:
      if (pattern141 (x1, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      return 14;

    case E_VNx4SImode:
      if (pattern141 (x1, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      return 15;

    case E_VNx8SImode:
      if (pattern141 (x1, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      return 16;

    case E_VNx16SImode:
      if (pattern141 (x1, E_VNx16SImode, E_VNx16BImode) != 0)
        return -1;
      return 17;

    case E_VNx1DImode:
      if (pattern141 (x1, E_VNx1DImode, E_VNx1BImode) != 0)
        return -1;
      return 18;

    case E_VNx2DImode:
      if (pattern141 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      return 19;

    case E_VNx4DImode:
      if (pattern141 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      return 20;

    case E_VNx8DImode:
      if (pattern141 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      return 21;

    case E_VNx1SFmode:
      if (pattern141 (x1, E_VNx1SFmode, E_VNx1BImode) != 0)
        return -1;
      return 22;

    case E_VNx2SFmode:
      if (pattern141 (x1, E_VNx2SFmode, E_VNx2BImode) != 0)
        return -1;
      return 23;

    case E_VNx4SFmode:
      if (pattern141 (x1, E_VNx4SFmode, E_VNx4BImode) != 0)
        return -1;
      return 24;

    case E_VNx8SFmode:
      if (pattern141 (x1, E_VNx8SFmode, E_VNx8BImode) != 0)
        return -1;
      return 25;

    case E_VNx16SFmode:
      if (pattern141 (x1, E_VNx16SFmode, E_VNx16BImode) != 0)
        return -1;
      return 26;

    case E_VNx1DFmode:
      if (pattern141 (x1, E_VNx1DFmode, E_VNx1BImode) != 0)
        return -1;
      return 27;

    case E_VNx2DFmode:
      if (pattern141 (x1, E_VNx2DFmode, E_VNx2BImode) != 0)
        return -1;
      return 28;

    case E_VNx4DFmode:
      if (pattern141 (x1, E_VNx4DFmode, E_VNx4BImode) != 0)
        return -1;
      return 29;

    case E_VNx8DFmode:
      if (pattern141 (x1, E_VNx8DFmode, E_VNx8BImode) != 0)
        return -1;
      return 30;

    default:
      return -1;
    }
}

static int
pattern143 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1)
      || !vector_arith_operand (operands[4], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern144 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  operands[3] = x3;
  x4 = XEXP (x2, 1);
  operands[4] = x4;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      return pattern143 (x1, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2QImode:
      if (pattern143 (x1, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4QImode:
      if (pattern143 (x1, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8QImode:
      if (pattern143 (x1, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16QImode:
      if (pattern143 (x1, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32QImode:
      if (pattern143 (x1, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx64QImode:
      if (pattern143 (x1, E_VNx64QImode, E_VNx64BImode) != 0)
        return -1;
      return 6;

    case E_VNx1HImode:
      if (pattern143 (x1, E_VNx1HImode, E_VNx1BImode) != 0)
        return -1;
      return 7;

    case E_VNx2HImode:
      if (pattern143 (x1, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      return 8;

    case E_VNx4HImode:
      if (pattern143 (x1, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      return 9;

    case E_VNx8HImode:
      if (pattern143 (x1, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      return 10;

    case E_VNx16HImode:
      if (pattern143 (x1, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      return 11;

    case E_VNx32HImode:
      if (pattern143 (x1, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      return 12;

    case E_VNx1SImode:
      if (pattern143 (x1, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      return 13;

    case E_VNx2SImode:
      if (pattern143 (x1, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      return 14;

    case E_VNx4SImode:
      if (pattern143 (x1, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      return 15;

    case E_VNx8SImode:
      if (pattern143 (x1, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      return 16;

    case E_VNx16SImode:
      if (pattern143 (x1, E_VNx16SImode, E_VNx16BImode) != 0)
        return -1;
      return 17;

    case E_VNx1DImode:
      if (pattern143 (x1, E_VNx1DImode, E_VNx1BImode) != 0)
        return -1;
      return 18;

    case E_VNx2DImode:
      if (pattern143 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      return 19;

    case E_VNx4DImode:
      if (pattern143 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      return 20;

    case E_VNx8DImode:
      if (pattern143 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      return 21;

    default:
      return -1;
    }
}

static int
pattern145 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !reg_or_0_operand (operands[4], i3)
      || !register_operand (operands[3], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern146 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[3], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern147 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != E_DImode)
    return -1;
  x5 = XEXP (x4, 0);
  operands[4] = x5;
  if (!reg_or_0_operand (operands[4], E_SImode))
    return -1;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1DImode:
      return pattern146 (x1, E_VNx1DImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2DImode:
      if (pattern146 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4DImode:
      if (pattern146 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8DImode:
      if (pattern146 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern148 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  operands[3] = x3;
  x4 = XEXP (x2, 0);
  x5 = XEXP (x4, 0);
  switch (GET_CODE (x5))
    {
    case CONST_INT:
    case CONST_WIDE_INT:
    case CONST_VECTOR:
    case REG:
    case SUBREG:
      operands[4] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          return pattern145 (x1, E_VNx1QImode, E_VNx1BImode, E_QImode); /* [-1, 0] */

        case E_VNx2QImode:
          if (pattern145 (x1, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
            return -1;
          return 1;

        case E_VNx4QImode:
          if (pattern145 (x1, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
            return -1;
          return 2;

        case E_VNx8QImode:
          if (pattern145 (x1, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
            return -1;
          return 3;

        case E_VNx16QImode:
          if (pattern145 (x1, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
            return -1;
          return 4;

        case E_VNx32QImode:
          if (pattern145 (x1, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
            return -1;
          return 5;

        case E_VNx64QImode:
          if (pattern145 (x1, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0)
            return -1;
          return 6;

        case E_VNx1HImode:
          if (pattern145 (x1, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
            return -1;
          return 7;

        case E_VNx2HImode:
          if (pattern145 (x1, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
            return -1;
          return 8;

        case E_VNx4HImode:
          if (pattern145 (x1, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
            return -1;
          return 9;

        case E_VNx8HImode:
          if (pattern145 (x1, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
            return -1;
          return 10;

        case E_VNx16HImode:
          if (pattern145 (x1, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
            return -1;
          return 11;

        case E_VNx32HImode:
          if (pattern145 (x1, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0)
            return -1;
          return 12;

        case E_VNx1SImode:
          if (pattern145 (x1, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
            return -1;
          return 13;

        case E_VNx2SImode:
          if (pattern145 (x1, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
            return -1;
          return 14;

        case E_VNx4SImode:
          if (pattern145 (x1, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
            return -1;
          return 15;

        case E_VNx8SImode:
          if (pattern145 (x1, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
            return -1;
          return 16;

        case E_VNx16SImode:
          if (pattern145 (x1, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0)
            return -1;
          return 17;

        case E_VNx1DImode:
          if (pattern145 (x1, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0)
            return -1;
          return 18;

        case E_VNx2DImode:
          if (pattern145 (x1, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0)
            return -1;
          return 19;

        case E_VNx4DImode:
          if (pattern145 (x1, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0)
            return -1;
          return 20;

        case E_VNx8DImode:
          if (pattern145 (x1, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0)
            return -1;
          return 21;

        default:
          return -1;
        }

    case SIGN_EXTEND:
      res = pattern147 (x1);
      if (res >= 0)
        return res + 22; /* [22, 25] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern149 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[5] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[6] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[7] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[8] = x6;
  x7 = XEXP (x1, 2);
  operands[2] = x7;
  x8 = XEXP (x1, 1);
  x9 = XEXP (x8, 0);
  switch (GET_CODE (x9))
    {
    case REG:
    case SUBREG:
      return pattern144 (x1); /* [-1, 21] */

    case VEC_DUPLICATE:
      res = pattern148 (x1);
      if (res >= 0)
        return res + 22; /* [22, 47] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern150 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern151 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 2);
  operands[2] = x2;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      return pattern150 (x1, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2QImode:
      if (pattern150 (x1, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4QImode:
      if (pattern150 (x1, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8QImode:
      if (pattern150 (x1, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16QImode:
      if (pattern150 (x1, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32QImode:
      if (pattern150 (x1, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx64QImode:
      if (pattern150 (x1, E_VNx64QImode, E_VNx64BImode) != 0)
        return -1;
      return 6;

    case E_VNx1HImode:
      if (pattern150 (x1, E_VNx1HImode, E_VNx1BImode) != 0)
        return -1;
      return 7;

    case E_VNx2HImode:
      if (pattern150 (x1, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      return 8;

    case E_VNx4HImode:
      if (pattern150 (x1, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      return 9;

    case E_VNx8HImode:
      if (pattern150 (x1, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      return 10;

    case E_VNx16HImode:
      if (pattern150 (x1, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      return 11;

    case E_VNx32HImode:
      if (pattern150 (x1, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      return 12;

    case E_VNx1SImode:
      if (pattern150 (x1, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      return 13;

    case E_VNx2SImode:
      if (pattern150 (x1, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      return 14;

    case E_VNx4SImode:
      if (pattern150 (x1, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      return 15;

    case E_VNx8SImode:
      if (pattern150 (x1, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      return 16;

    case E_VNx16SImode:
      if (pattern150 (x1, E_VNx16SImode, E_VNx16BImode) != 0)
        return -1;
      return 17;

    case E_VNx1DImode:
      if (pattern150 (x1, E_VNx1DImode, E_VNx1BImode) != 0)
        return -1;
      return 18;

    case E_VNx2DImode:
      if (pattern150 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      return 19;

    case E_VNx4DImode:
      if (pattern150 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      return 20;

    case E_VNx8DImode:
      if (pattern150 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      return 21;

    default:
      return -1;
    }
}

static int
pattern152 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[5] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[6] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[7] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[8] = x6;
  x7 = XEXP (x1, 1);
  x8 = XEXP (x7, 0);
  operands[3] = x8;
  x9 = XEXP (x7, 1);
  operands[4] = x9;
  return pattern151 (x1); /* [-1, 21] */
}

static int
pattern153 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1)
      || !register_operand (operands[4], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern154 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  operands[4] = x3;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      return pattern153 (x1, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2QImode:
      if (pattern153 (x1, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4QImode:
      if (pattern153 (x1, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8QImode:
      if (pattern153 (x1, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16QImode:
      if (pattern153 (x1, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32QImode:
      if (pattern153 (x1, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx64QImode:
      if (pattern153 (x1, E_VNx64QImode, E_VNx64BImode) != 0)
        return -1;
      return 6;

    case E_VNx1HImode:
      if (pattern153 (x1, E_VNx1HImode, E_VNx1BImode) != 0)
        return -1;
      return 7;

    case E_VNx2HImode:
      if (pattern153 (x1, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      return 8;

    case E_VNx4HImode:
      if (pattern153 (x1, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      return 9;

    case E_VNx8HImode:
      if (pattern153 (x1, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      return 10;

    case E_VNx16HImode:
      if (pattern153 (x1, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      return 11;

    case E_VNx32HImode:
      if (pattern153 (x1, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      return 12;

    case E_VNx1SImode:
      if (pattern153 (x1, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      return 13;

    case E_VNx2SImode:
      if (pattern153 (x1, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      return 14;

    case E_VNx4SImode:
      if (pattern153 (x1, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      return 15;

    case E_VNx8SImode:
      if (pattern153 (x1, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      return 16;

    case E_VNx16SImode:
      if (pattern153 (x1, E_VNx16SImode, E_VNx16BImode) != 0)
        return -1;
      return 17;

    case E_VNx1DImode:
      if (pattern153 (x1, E_VNx1DImode, E_VNx1BImode) != 0)
        return -1;
      return 18;

    case E_VNx2DImode:
      if (pattern153 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      return 19;

    case E_VNx4DImode:
      if (pattern153 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      return 20;

    case E_VNx8DImode:
      if (pattern153 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      return 21;

    case E_VNx1SFmode:
      if (pattern153 (x1, E_VNx1SFmode, E_VNx1BImode) != 0)
        return -1;
      return 22;

    case E_VNx2SFmode:
      if (pattern153 (x1, E_VNx2SFmode, E_VNx2BImode) != 0)
        return -1;
      return 23;

    case E_VNx4SFmode:
      if (pattern153 (x1, E_VNx4SFmode, E_VNx4BImode) != 0)
        return -1;
      return 24;

    case E_VNx8SFmode:
      if (pattern153 (x1, E_VNx8SFmode, E_VNx8BImode) != 0)
        return -1;
      return 25;

    case E_VNx16SFmode:
      if (pattern153 (x1, E_VNx16SFmode, E_VNx16BImode) != 0)
        return -1;
      return 26;

    case E_VNx1DFmode:
      if (pattern153 (x1, E_VNx1DFmode, E_VNx1BImode) != 0)
        return -1;
      return 27;

    case E_VNx2DFmode:
      if (pattern153 (x1, E_VNx2DFmode, E_VNx2BImode) != 0)
        return -1;
      return 28;

    case E_VNx4DFmode:
      if (pattern153 (x1, E_VNx4DFmode, E_VNx4BImode) != 0)
        return -1;
      return 29;

    case E_VNx8DFmode:
      if (pattern153 (x1, E_VNx8DFmode, E_VNx8BImode) != 0)
        return -1;
      return 30;

    default:
      return -1;
    }
}

static int
pattern155 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[4], i3)
      || !register_operand (operands[3], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern156 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case CONST_INT:
    case CONST_WIDE_INT:
    case CONST_VECTOR:
    case REG:
    case SUBREG:
      operands[4] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          return pattern145 (x1, E_VNx1QImode, E_VNx1BImode, E_QImode); /* [-1, 0] */

        case E_VNx2QImode:
          if (pattern145 (x1, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
            return -1;
          return 1;

        case E_VNx4QImode:
          if (pattern145 (x1, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
            return -1;
          return 2;

        case E_VNx8QImode:
          if (pattern145 (x1, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
            return -1;
          return 3;

        case E_VNx16QImode:
          if (pattern145 (x1, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
            return -1;
          return 4;

        case E_VNx32QImode:
          if (pattern145 (x1, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
            return -1;
          return 5;

        case E_VNx64QImode:
          if (pattern145 (x1, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0)
            return -1;
          return 6;

        case E_VNx1HImode:
          if (pattern145 (x1, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
            return -1;
          return 7;

        case E_VNx2HImode:
          if (pattern145 (x1, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
            return -1;
          return 8;

        case E_VNx4HImode:
          if (pattern145 (x1, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
            return -1;
          return 9;

        case E_VNx8HImode:
          if (pattern145 (x1, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
            return -1;
          return 10;

        case E_VNx16HImode:
          if (pattern145 (x1, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
            return -1;
          return 11;

        case E_VNx32HImode:
          if (pattern145 (x1, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0)
            return -1;
          return 12;

        case E_VNx1SImode:
          if (pattern145 (x1, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
            return -1;
          return 13;

        case E_VNx2SImode:
          if (pattern145 (x1, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
            return -1;
          return 14;

        case E_VNx4SImode:
          if (pattern145 (x1, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
            return -1;
          return 15;

        case E_VNx8SImode:
          if (pattern145 (x1, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
            return -1;
          return 16;

        case E_VNx16SImode:
          if (pattern145 (x1, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0)
            return -1;
          return 17;

        case E_VNx1DImode:
          if (pattern145 (x1, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0)
            return -1;
          return 18;

        case E_VNx2DImode:
          if (pattern145 (x1, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0)
            return -1;
          return 19;

        case E_VNx4DImode:
          if (pattern145 (x1, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0)
            return -1;
          return 20;

        case E_VNx8DImode:
          if (pattern145 (x1, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0)
            return -1;
          return 21;

        case E_VNx1SFmode:
          if (pattern155 (x1, E_VNx1SFmode, E_VNx1BImode, E_SFmode) != 0)
            return -1;
          return 22;

        case E_VNx2SFmode:
          if (pattern155 (x1, E_VNx2SFmode, E_VNx2BImode, E_SFmode) != 0)
            return -1;
          return 23;

        case E_VNx4SFmode:
          if (pattern155 (x1, E_VNx4SFmode, E_VNx4BImode, E_SFmode) != 0)
            return -1;
          return 24;

        case E_VNx8SFmode:
          if (pattern155 (x1, E_VNx8SFmode, E_VNx8BImode, E_SFmode) != 0)
            return -1;
          return 25;

        case E_VNx16SFmode:
          if (pattern155 (x1, E_VNx16SFmode, E_VNx16BImode, E_SFmode) != 0)
            return -1;
          return 26;

        case E_VNx1DFmode:
          if (pattern155 (x1, E_VNx1DFmode, E_VNx1BImode, E_DFmode) != 0)
            return -1;
          return 27;

        case E_VNx2DFmode:
          if (pattern155 (x1, E_VNx2DFmode, E_VNx2BImode, E_DFmode) != 0)
            return -1;
          return 28;

        case E_VNx4DFmode:
          if (pattern155 (x1, E_VNx4DFmode, E_VNx4BImode, E_DFmode) != 0)
            return -1;
          return 29;

        case E_VNx8DFmode:
          if (pattern155 (x1, E_VNx8DFmode, E_VNx8BImode, E_DFmode) != 0)
            return -1;
          return 30;

        default:
          return -1;
        }

    case SIGN_EXTEND:
      res = pattern147 (x1);
      if (res >= 0)
        return res + 31; /* [31, 34] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern157 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[5] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[6] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[7] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[8] = x6;
  x7 = XEXP (x1, 2);
  operands[2] = x7;
  x8 = XEXP (x1, 1);
  x9 = XEXP (x8, 0);
  switch (GET_CODE (x9))
    {
    case REG:
    case SUBREG:
      operands[3] = x9;
      return pattern154 (x1); /* [-1, 30] */

    case VEC_DUPLICATE:
      x10 = XEXP (x8, 1);
      operands[3] = x10;
      res = pattern156 (x1);
      if (res >= 0)
        return res + 31; /* [31, 65] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern158 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  operands[4] = x3;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      return pattern153 (x1, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2QImode:
      if (pattern153 (x1, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4QImode:
      if (pattern153 (x1, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8QImode:
      if (pattern153 (x1, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16QImode:
      if (pattern153 (x1, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32QImode:
      if (pattern153 (x1, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx64QImode:
      if (pattern153 (x1, E_VNx64QImode, E_VNx64BImode) != 0)
        return -1;
      return 6;

    case E_VNx1HImode:
      if (pattern153 (x1, E_VNx1HImode, E_VNx1BImode) != 0)
        return -1;
      return 7;

    case E_VNx2HImode:
      if (pattern153 (x1, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      return 8;

    case E_VNx4HImode:
      if (pattern153 (x1, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      return 9;

    case E_VNx8HImode:
      if (pattern153 (x1, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      return 10;

    case E_VNx16HImode:
      if (pattern153 (x1, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      return 11;

    case E_VNx32HImode:
      if (pattern153 (x1, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      return 12;

    case E_VNx1SImode:
      if (pattern153 (x1, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      return 13;

    case E_VNx2SImode:
      if (pattern153 (x1, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      return 14;

    case E_VNx4SImode:
      if (pattern153 (x1, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      return 15;

    case E_VNx8SImode:
      if (pattern153 (x1, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      return 16;

    case E_VNx16SImode:
      if (pattern153 (x1, E_VNx16SImode, E_VNx16BImode) != 0)
        return -1;
      return 17;

    case E_VNx1DImode:
      if (pattern153 (x1, E_VNx1DImode, E_VNx1BImode) != 0)
        return -1;
      return 18;

    case E_VNx2DImode:
      if (pattern153 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      return 19;

    case E_VNx4DImode:
      if (pattern153 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      return 20;

    case E_VNx8DImode:
      if (pattern153 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      return 21;

    default:
      return -1;
    }
}

static int
pattern159 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[5] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[6] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[7] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[8] = x6;
  x7 = XEXP (x1, 2);
  operands[2] = x7;
  x8 = XEXP (x1, 1);
  x9 = XEXP (x8, 0);
  switch (GET_CODE (x9))
    {
    case REG:
    case SUBREG:
      operands[3] = x9;
      return pattern158 (x1); /* [-1, 21] */

    case VEC_DUPLICATE:
      res = pattern148 (x1);
      if (res >= 0)
        return res + 22; /* [22, 47] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern160 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1))
    return -1;
  x4 = XEXP (x3, 1);
  if (GET_MODE (x4) != i1
      || !reg_or_0_operand (operands[4], i3)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern161 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1))
    return -1;
  x4 = XEXP (x3, 1);
  if (GET_MODE (x4) != i1
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern162 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != E_DImode)
    return -1;
  x5 = XEXP (x4, 0);
  operands[4] = x5;
  if (!reg_or_0_operand (operands[4], E_SImode))
    return -1;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1DImode:
      return pattern161 (x1, E_VNx1DImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2DImode:
      if (pattern161 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4DImode:
      if (pattern161 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8DImode:
      if (pattern161 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern163 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[5] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[6] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[7] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[8] = x6;
  x7 = XEXP (x1, 1);
  x8 = XEXP (x7, 0);
  operands[3] = x8;
  x9 = XEXP (x1, 2);
  operands[2] = x9;
  x10 = XEXP (x7, 1);
  switch (GET_CODE (x10))
    {
    case REG:
    case SUBREG:
      return pattern158 (x1); /* [-1, 21] */

    case VEC_DUPLICATE:
      x11 = XEXP (x10, 0);
      switch (GET_CODE (x11))
        {
        case CONST_INT:
        case CONST_WIDE_INT:
        case CONST_VECTOR:
        case REG:
        case SUBREG:
          operands[4] = x11;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1QImode:
              if (pattern160 (x1, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0)
                return -1;
              return 22;

            case E_VNx2QImode:
              if (pattern160 (x1, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
                return -1;
              return 23;

            case E_VNx4QImode:
              if (pattern160 (x1, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
                return -1;
              return 24;

            case E_VNx8QImode:
              if (pattern160 (x1, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
                return -1;
              return 25;

            case E_VNx16QImode:
              if (pattern160 (x1, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
                return -1;
              return 26;

            case E_VNx32QImode:
              if (pattern160 (x1, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
                return -1;
              return 27;

            case E_VNx64QImode:
              if (pattern160 (x1, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0)
                return -1;
              return 28;

            case E_VNx1HImode:
              if (pattern160 (x1, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
                return -1;
              return 29;

            case E_VNx2HImode:
              if (pattern160 (x1, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
                return -1;
              return 30;

            case E_VNx4HImode:
              if (pattern160 (x1, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
                return -1;
              return 31;

            case E_VNx8HImode:
              if (pattern160 (x1, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
                return -1;
              return 32;

            case E_VNx16HImode:
              if (pattern160 (x1, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
                return -1;
              return 33;

            case E_VNx32HImode:
              if (pattern160 (x1, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0)
                return -1;
              return 34;

            case E_VNx1SImode:
              if (pattern160 (x1, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
                return -1;
              return 35;

            case E_VNx2SImode:
              if (pattern160 (x1, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
                return -1;
              return 36;

            case E_VNx4SImode:
              if (pattern160 (x1, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
                return -1;
              return 37;

            case E_VNx8SImode:
              if (pattern160 (x1, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
                return -1;
              return 38;

            case E_VNx16SImode:
              if (pattern160 (x1, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0)
                return -1;
              return 39;

            case E_VNx1DImode:
              if (pattern160 (x1, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0)
                return -1;
              return 40;

            case E_VNx2DImode:
              if (pattern160 (x1, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0)
                return -1;
              return 41;

            case E_VNx4DImode:
              if (pattern160 (x1, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0)
                return -1;
              return 42;

            case E_VNx8DImode:
              if (pattern160 (x1, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0)
                return -1;
              return 43;

            default:
              return -1;
            }

        case SIGN_EXTEND:
          res = pattern162 (x1);
          if (res >= 0)
            return res + 44; /* [44, 47] */
          return -1;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern164 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i2)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern165 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[4] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[5] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[6] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[7] = x6;
  x7 = XEXP (x1, 1);
  x8 = XEXP (x7, 0);
  operands[3] = x8;
  x9 = XEXP (x1, 2);
  operands[2] = x9;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1HImode:
      return pattern164 (x1, E_VNx1HImode, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2HImode:
      if (pattern164 (x1, E_VNx2HImode, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4HImode:
      if (pattern164 (x1, E_VNx4HImode, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8HImode:
      if (pattern164 (x1, E_VNx8HImode, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16HImode:
      if (pattern164 (x1, E_VNx16HImode, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32HImode:
      if (pattern164 (x1, E_VNx32HImode, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx1SImode:
      if (!register_operand (operands[0], E_VNx1SImode)
          || GET_MODE (x1) != E_VNx1SImode
          || GET_MODE (x2) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode)
          || GET_MODE (x7) != E_VNx1SImode
          || !vector_merge_operand (operands[2], E_VNx1SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx1HImode:
          if (!register_operand (operands[3], E_VNx1HImode))
            return -1;
          return 6;

        case E_VNx1QImode:
          if (!register_operand (operands[3], E_VNx1QImode))
            return -1;
          return 7;

        default:
          return -1;
        }

    case E_VNx2SImode:
      if (!register_operand (operands[0], E_VNx2SImode)
          || GET_MODE (x1) != E_VNx2SImode
          || GET_MODE (x2) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode)
          || GET_MODE (x7) != E_VNx2SImode
          || !vector_merge_operand (operands[2], E_VNx2SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx2HImode:
          if (!register_operand (operands[3], E_VNx2HImode))
            return -1;
          return 8;

        case E_VNx2QImode:
          if (!register_operand (operands[3], E_VNx2QImode))
            return -1;
          return 9;

        default:
          return -1;
        }

    case E_VNx4SImode:
      if (!register_operand (operands[0], E_VNx4SImode)
          || GET_MODE (x1) != E_VNx4SImode
          || GET_MODE (x2) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode)
          || GET_MODE (x7) != E_VNx4SImode
          || !vector_merge_operand (operands[2], E_VNx4SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx4HImode:
          if (!register_operand (operands[3], E_VNx4HImode))
            return -1;
          return 10;

        case E_VNx4QImode:
          if (!register_operand (operands[3], E_VNx4QImode))
            return -1;
          return 11;

        default:
          return -1;
        }

    case E_VNx8SImode:
      if (!register_operand (operands[0], E_VNx8SImode)
          || GET_MODE (x1) != E_VNx8SImode
          || GET_MODE (x2) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode)
          || GET_MODE (x7) != E_VNx8SImode
          || !vector_merge_operand (operands[2], E_VNx8SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx8HImode:
          if (!register_operand (operands[3], E_VNx8HImode))
            return -1;
          return 12;

        case E_VNx8QImode:
          if (!register_operand (operands[3], E_VNx8QImode))
            return -1;
          return 13;

        default:
          return -1;
        }

    case E_VNx16SImode:
      if (!register_operand (operands[0], E_VNx16SImode)
          || GET_MODE (x1) != E_VNx16SImode
          || GET_MODE (x2) != E_VNx16BImode
          || !vector_mask_operand (operands[1], E_VNx16BImode)
          || GET_MODE (x7) != E_VNx16SImode
          || !vector_merge_operand (operands[2], E_VNx16SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx16HImode:
          if (!register_operand (operands[3], E_VNx16HImode))
            return -1;
          return 14;

        case E_VNx16QImode:
          if (!register_operand (operands[3], E_VNx16QImode))
            return -1;
          return 15;

        default:
          return -1;
        }

    case E_VNx1DImode:
      if (!register_operand (operands[0], E_VNx1DImode)
          || GET_MODE (x1) != E_VNx1DImode
          || GET_MODE (x2) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode)
          || GET_MODE (x7) != E_VNx1DImode
          || !vector_merge_operand (operands[2], E_VNx1DImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx1SImode:
          if (!register_operand (operands[3], E_VNx1SImode))
            return -1;
          return 16;

        case E_VNx1HImode:
          if (!register_operand (operands[3], E_VNx1HImode))
            return -1;
          return 17;

        case E_VNx1QImode:
          if (!register_operand (operands[3], E_VNx1QImode))
            return -1;
          return 18;

        default:
          return -1;
        }

    case E_VNx2DImode:
      if (!register_operand (operands[0], E_VNx2DImode)
          || GET_MODE (x1) != E_VNx2DImode
          || GET_MODE (x2) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode)
          || GET_MODE (x7) != E_VNx2DImode
          || !vector_merge_operand (operands[2], E_VNx2DImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx2SImode:
          if (!register_operand (operands[3], E_VNx2SImode))
            return -1;
          return 19;

        case E_VNx2HImode:
          if (!register_operand (operands[3], E_VNx2HImode))
            return -1;
          return 20;

        case E_VNx2QImode:
          if (!register_operand (operands[3], E_VNx2QImode))
            return -1;
          return 21;

        default:
          return -1;
        }

    case E_VNx4DImode:
      if (!register_operand (operands[0], E_VNx4DImode)
          || GET_MODE (x1) != E_VNx4DImode
          || GET_MODE (x2) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode)
          || GET_MODE (x7) != E_VNx4DImode
          || !vector_merge_operand (operands[2], E_VNx4DImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx4SImode:
          if (!register_operand (operands[3], E_VNx4SImode))
            return -1;
          return 22;

        case E_VNx4HImode:
          if (!register_operand (operands[3], E_VNx4HImode))
            return -1;
          return 23;

        case E_VNx4QImode:
          if (!register_operand (operands[3], E_VNx4QImode))
            return -1;
          return 24;

        default:
          return -1;
        }

    case E_VNx8DImode:
      if (!register_operand (operands[0], E_VNx8DImode)
          || GET_MODE (x1) != E_VNx8DImode
          || GET_MODE (x2) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode)
          || GET_MODE (x7) != E_VNx8DImode
          || !vector_merge_operand (operands[2], E_VNx8DImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx8SImode:
          if (!register_operand (operands[3], E_VNx8SImode))
            return -1;
          return 25;

        case E_VNx8HImode:
          if (!register_operand (operands[3], E_VNx8HImode))
            return -1;
          return 26;

        case E_VNx8QImode:
          if (!register_operand (operands[3], E_VNx8QImode))
            return -1;
          return 27;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern166 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[5] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[6] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[7] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[8] = x6;
  x7 = XEXP (x1, 2);
  operands[2] = x7;
  x8 = XEXP (x1, 1);
  x9 = XEXP (x8, 0);
  switch (GET_CODE (x9))
    {
    case REG:
    case SUBREG:
      return pattern144 (x1); /* [-1, 21] */

    case VEC_DUPLICATE:
      x10 = XEXP (x8, 1);
      operands[3] = x10;
      x11 = XEXP (x9, 0);
      switch (GET_CODE (x11))
        {
        case REG:
        case SUBREG:
          operands[4] = x11;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1QImode:
              if (pattern155 (x1, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0)
                return -1;
              return 22;

            case E_VNx2QImode:
              if (pattern155 (x1, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
                return -1;
              return 23;

            case E_VNx4QImode:
              if (pattern155 (x1, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
                return -1;
              return 24;

            case E_VNx8QImode:
              if (pattern155 (x1, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
                return -1;
              return 25;

            case E_VNx16QImode:
              if (pattern155 (x1, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
                return -1;
              return 26;

            case E_VNx32QImode:
              if (pattern155 (x1, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
                return -1;
              return 27;

            case E_VNx64QImode:
              if (pattern155 (x1, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0)
                return -1;
              return 28;

            case E_VNx1HImode:
              if (pattern155 (x1, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
                return -1;
              return 29;

            case E_VNx2HImode:
              if (pattern155 (x1, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
                return -1;
              return 30;

            case E_VNx4HImode:
              if (pattern155 (x1, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
                return -1;
              return 31;

            case E_VNx8HImode:
              if (pattern155 (x1, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
                return -1;
              return 32;

            case E_VNx16HImode:
              if (pattern155 (x1, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
                return -1;
              return 33;

            case E_VNx32HImode:
              if (pattern155 (x1, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0)
                return -1;
              return 34;

            case E_VNx1SImode:
              if (pattern155 (x1, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
                return -1;
              return 35;

            case E_VNx2SImode:
              if (pattern155 (x1, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
                return -1;
              return 36;

            case E_VNx4SImode:
              if (pattern155 (x1, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
                return -1;
              return 37;

            case E_VNx8SImode:
              if (pattern155 (x1, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
                return -1;
              return 38;

            case E_VNx16SImode:
              if (pattern155 (x1, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0)
                return -1;
              return 39;

            case E_VNx1DImode:
              if (pattern155 (x1, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0)
                return -1;
              return 40;

            case E_VNx2DImode:
              if (pattern155 (x1, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0)
                return -1;
              return 41;

            case E_VNx4DImode:
              if (pattern155 (x1, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0)
                return -1;
              return 42;

            case E_VNx8DImode:
              if (pattern155 (x1, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0)
                return -1;
              return 43;

            default:
              return -1;
            }

        case SIGN_EXTEND:
          if (GET_MODE (x11) != E_DImode)
            return -1;
          x12 = XEXP (x11, 0);
          operands[4] = x12;
          if (!register_operand (operands[4], E_SImode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1DImode:
              if (pattern146 (x1, E_VNx1DImode, E_VNx1BImode) != 0)
                return -1;
              return 44;

            case E_VNx2DImode:
              if (pattern146 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
                return -1;
              return 45;

            case E_VNx4DImode:
              if (pattern146 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
                return -1;
              return 46;

            case E_VNx8DImode:
              if (pattern146 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
                return -1;
              return 47;

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern167 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[4] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[5] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[6] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[7] = x6;
  x7 = XEXP (x1, 1);
  x8 = XEXP (x7, 0);
  operands[3] = x8;
  x9 = XEXP (x1, 2);
  operands[2] = x9;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1SFmode:
      return pattern150 (x1, E_VNx1SFmode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2SFmode:
      if (pattern150 (x1, E_VNx2SFmode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4SFmode:
      if (pattern150 (x1, E_VNx4SFmode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8SFmode:
      if (pattern150 (x1, E_VNx8SFmode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16SFmode:
      if (pattern150 (x1, E_VNx16SFmode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx1DFmode:
      if (pattern150 (x1, E_VNx1DFmode, E_VNx1BImode) != 0)
        return -1;
      return 5;

    case E_VNx2DFmode:
      if (pattern150 (x1, E_VNx2DFmode, E_VNx2BImode) != 0)
        return -1;
      return 6;

    case E_VNx4DFmode:
      if (pattern150 (x1, E_VNx4DFmode, E_VNx4BImode) != 0)
        return -1;
      return 7;

    case E_VNx8DFmode:
      if (pattern150 (x1, E_VNx8DFmode, E_VNx8BImode) != 0)
        return -1;
      return 8;

    default:
      return -1;
    }
}

static int
pattern168 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[4] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[5] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[6] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[7] = x6;
  x7 = XEXP (x1, 1);
  x8 = XEXP (x7, 0);
  operands[3] = x8;
  x9 = XEXP (x1, 2);
  operands[2] = x9;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1SImode:
      if (!register_operand (operands[0], E_VNx1SImode)
          || GET_MODE (x1) != E_VNx1SImode
          || GET_MODE (x2) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode)
          || GET_MODE (x7) != E_VNx1SImode
          || !vector_merge_operand (operands[2], E_VNx1SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx1SFmode:
          if (!register_operand (operands[3], E_VNx1SFmode))
            return -1;
          return 0;

        case E_VNx1DFmode:
          if (!register_operand (operands[3], E_VNx1DFmode))
            return -1;
          return 1;

        default:
          return -1;
        }

    case E_VNx2SImode:
      if (!register_operand (operands[0], E_VNx2SImode)
          || GET_MODE (x1) != E_VNx2SImode
          || GET_MODE (x2) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode)
          || GET_MODE (x7) != E_VNx2SImode
          || !vector_merge_operand (operands[2], E_VNx2SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx2SFmode:
          if (!register_operand (operands[3], E_VNx2SFmode))
            return -1;
          return 2;

        case E_VNx2DFmode:
          if (!register_operand (operands[3], E_VNx2DFmode))
            return -1;
          return 3;

        default:
          return -1;
        }

    case E_VNx4SImode:
      if (!register_operand (operands[0], E_VNx4SImode)
          || GET_MODE (x1) != E_VNx4SImode
          || GET_MODE (x2) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode)
          || GET_MODE (x7) != E_VNx4SImode
          || !vector_merge_operand (operands[2], E_VNx4SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx4SFmode:
          if (!register_operand (operands[3], E_VNx4SFmode))
            return -1;
          return 4;

        case E_VNx4DFmode:
          if (!register_operand (operands[3], E_VNx4DFmode))
            return -1;
          return 5;

        default:
          return -1;
        }

    case E_VNx8SImode:
      if (!register_operand (operands[0], E_VNx8SImode)
          || GET_MODE (x1) != E_VNx8SImode
          || GET_MODE (x2) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode)
          || GET_MODE (x7) != E_VNx8SImode
          || !vector_merge_operand (operands[2], E_VNx8SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx8SFmode:
          if (!register_operand (operands[3], E_VNx8SFmode))
            return -1;
          return 6;

        case E_VNx8DFmode:
          if (!register_operand (operands[3], E_VNx8DFmode))
            return -1;
          return 7;

        default:
          return -1;
        }

    case E_VNx16SImode:
      if (pattern164 (x1, E_VNx16SImode, E_VNx16SFmode, E_VNx16BImode) != 0)
        return -1;
      return 8;

    case E_VNx1DImode:
      if (!register_operand (operands[0], E_VNx1DImode)
          || GET_MODE (x1) != E_VNx1DImode
          || GET_MODE (x2) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode)
          || GET_MODE (x7) != E_VNx1DImode
          || !vector_merge_operand (operands[2], E_VNx1DImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx1DFmode:
          if (!register_operand (operands[3], E_VNx1DFmode))
            return -1;
          return 9;

        case E_VNx1SFmode:
          if (!register_operand (operands[3], E_VNx1SFmode))
            return -1;
          return 10;

        default:
          return -1;
        }

    case E_VNx2DImode:
      if (!register_operand (operands[0], E_VNx2DImode)
          || GET_MODE (x1) != E_VNx2DImode
          || GET_MODE (x2) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode)
          || GET_MODE (x7) != E_VNx2DImode
          || !vector_merge_operand (operands[2], E_VNx2DImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx2DFmode:
          if (!register_operand (operands[3], E_VNx2DFmode))
            return -1;
          return 11;

        case E_VNx2SFmode:
          if (!register_operand (operands[3], E_VNx2SFmode))
            return -1;
          return 12;

        default:
          return -1;
        }

    case E_VNx4DImode:
      if (!register_operand (operands[0], E_VNx4DImode)
          || GET_MODE (x1) != E_VNx4DImode
          || GET_MODE (x2) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode)
          || GET_MODE (x7) != E_VNx4DImode
          || !vector_merge_operand (operands[2], E_VNx4DImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx4DFmode:
          if (!register_operand (operands[3], E_VNx4DFmode))
            return -1;
          return 13;

        case E_VNx4SFmode:
          if (!register_operand (operands[3], E_VNx4SFmode))
            return -1;
          return 14;

        default:
          return -1;
        }

    case E_VNx8DImode:
      if (!register_operand (operands[0], E_VNx8DImode)
          || GET_MODE (x1) != E_VNx8DImode
          || GET_MODE (x2) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode)
          || GET_MODE (x7) != E_VNx8DImode
          || !vector_merge_operand (operands[2], E_VNx8DImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx8DFmode:
          if (!register_operand (operands[3], E_VNx8DFmode))
            return -1;
          return 15;

        case E_VNx8SFmode:
          if (!register_operand (operands[3], E_VNx8SFmode))
            return -1;
          return 16;

        default:
          return -1;
        }

    case E_VNx1HImode:
      if (pattern164 (x1, E_VNx1HImode, E_VNx1SFmode, E_VNx1BImode) != 0)
        return -1;
      return 17;

    case E_VNx2HImode:
      if (pattern164 (x1, E_VNx2HImode, E_VNx2SFmode, E_VNx2BImode) != 0)
        return -1;
      return 18;

    case E_VNx4HImode:
      if (pattern164 (x1, E_VNx4HImode, E_VNx4SFmode, E_VNx4BImode) != 0)
        return -1;
      return 19;

    case E_VNx8HImode:
      if (pattern164 (x1, E_VNx8HImode, E_VNx8SFmode, E_VNx8BImode) != 0)
        return -1;
      return 20;

    case E_VNx16HImode:
      if (pattern164 (x1, E_VNx16HImode, E_VNx16SFmode, E_VNx16BImode) != 0)
        return -1;
      return 21;

    default:
      return -1;
    }
}

static int
pattern169 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[4] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[5] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[6] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[7] = x6;
  x7 = XEXP (x1, 1);
  x8 = XEXP (x7, 0);
  operands[3] = x8;
  x9 = XEXP (x1, 2);
  operands[2] = x9;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1SFmode:
      if (!register_operand (operands[0], E_VNx1SFmode)
          || GET_MODE (x1) != E_VNx1SFmode
          || GET_MODE (x2) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode)
          || GET_MODE (x7) != E_VNx1SFmode
          || !vector_merge_operand (operands[2], E_VNx1SFmode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx1SImode:
          if (!register_operand (operands[3], E_VNx1SImode))
            return -1;
          return 0;

        case E_VNx1HImode:
          if (!register_operand (operands[3], E_VNx1HImode))
            return -1;
          return 1;

        case E_VNx1DImode:
          if (!register_operand (operands[3], E_VNx1DImode))
            return -1;
          return 2;

        default:
          return -1;
        }

    case E_VNx2SFmode:
      if (!register_operand (operands[0], E_VNx2SFmode)
          || GET_MODE (x1) != E_VNx2SFmode
          || GET_MODE (x2) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode)
          || GET_MODE (x7) != E_VNx2SFmode
          || !vector_merge_operand (operands[2], E_VNx2SFmode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx2SImode:
          if (!register_operand (operands[3], E_VNx2SImode))
            return -1;
          return 3;

        case E_VNx2HImode:
          if (!register_operand (operands[3], E_VNx2HImode))
            return -1;
          return 4;

        case E_VNx2DImode:
          if (!register_operand (operands[3], E_VNx2DImode))
            return -1;
          return 5;

        default:
          return -1;
        }

    case E_VNx4SFmode:
      if (!register_operand (operands[0], E_VNx4SFmode)
          || GET_MODE (x1) != E_VNx4SFmode
          || GET_MODE (x2) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode)
          || GET_MODE (x7) != E_VNx4SFmode
          || !vector_merge_operand (operands[2], E_VNx4SFmode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx4SImode:
          if (!register_operand (operands[3], E_VNx4SImode))
            return -1;
          return 6;

        case E_VNx4HImode:
          if (!register_operand (operands[3], E_VNx4HImode))
            return -1;
          return 7;

        case E_VNx4DImode:
          if (!register_operand (operands[3], E_VNx4DImode))
            return -1;
          return 8;

        default:
          return -1;
        }

    case E_VNx8SFmode:
      if (!register_operand (operands[0], E_VNx8SFmode)
          || GET_MODE (x1) != E_VNx8SFmode
          || GET_MODE (x2) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode)
          || GET_MODE (x7) != E_VNx8SFmode
          || !vector_merge_operand (operands[2], E_VNx8SFmode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx8SImode:
          if (!register_operand (operands[3], E_VNx8SImode))
            return -1;
          return 9;

        case E_VNx8HImode:
          if (!register_operand (operands[3], E_VNx8HImode))
            return -1;
          return 10;

        case E_VNx8DImode:
          if (!register_operand (operands[3], E_VNx8DImode))
            return -1;
          return 11;

        default:
          return -1;
        }

    case E_VNx16SFmode:
      if (!register_operand (operands[0], E_VNx16SFmode)
          || GET_MODE (x1) != E_VNx16SFmode
          || GET_MODE (x2) != E_VNx16BImode
          || !vector_mask_operand (operands[1], E_VNx16BImode)
          || GET_MODE (x7) != E_VNx16SFmode
          || !vector_merge_operand (operands[2], E_VNx16SFmode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx16SImode:
          if (!register_operand (operands[3], E_VNx16SImode))
            return -1;
          return 12;

        case E_VNx16HImode:
          if (!register_operand (operands[3], E_VNx16HImode))
            return -1;
          return 13;

        default:
          return -1;
        }

    case E_VNx1DFmode:
      if (!register_operand (operands[0], E_VNx1DFmode)
          || GET_MODE (x1) != E_VNx1DFmode
          || GET_MODE (x2) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode)
          || GET_MODE (x7) != E_VNx1DFmode
          || !vector_merge_operand (operands[2], E_VNx1DFmode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx1DImode:
          if (!register_operand (operands[3], E_VNx1DImode))
            return -1;
          return 14;

        case E_VNx1SImode:
          if (!register_operand (operands[3], E_VNx1SImode))
            return -1;
          return 15;

        default:
          return -1;
        }

    case E_VNx2DFmode:
      if (!register_operand (operands[0], E_VNx2DFmode)
          || GET_MODE (x1) != E_VNx2DFmode
          || GET_MODE (x2) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode)
          || GET_MODE (x7) != E_VNx2DFmode
          || !vector_merge_operand (operands[2], E_VNx2DFmode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx2DImode:
          if (!register_operand (operands[3], E_VNx2DImode))
            return -1;
          return 16;

        case E_VNx2SImode:
          if (!register_operand (operands[3], E_VNx2SImode))
            return -1;
          return 17;

        default:
          return -1;
        }

    case E_VNx4DFmode:
      if (!register_operand (operands[0], E_VNx4DFmode)
          || GET_MODE (x1) != E_VNx4DFmode
          || GET_MODE (x2) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode)
          || GET_MODE (x7) != E_VNx4DFmode
          || !vector_merge_operand (operands[2], E_VNx4DFmode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx4DImode:
          if (!register_operand (operands[3], E_VNx4DImode))
            return -1;
          return 18;

        case E_VNx4SImode:
          if (!register_operand (operands[3], E_VNx4SImode))
            return -1;
          return 19;

        default:
          return -1;
        }

    case E_VNx8DFmode:
      if (!register_operand (operands[0], E_VNx8DFmode)
          || GET_MODE (x1) != E_VNx8DFmode
          || GET_MODE (x2) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode)
          || GET_MODE (x7) != E_VNx8DFmode
          || !vector_merge_operand (operands[2], E_VNx8DFmode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx8DImode:
          if (!register_operand (operands[3], E_VNx8DImode))
            return -1;
          return 20;

        case E_VNx8SImode:
          if (!register_operand (operands[3], E_VNx8SImode))
            return -1;
          return 21;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern170 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_all_trues_mask_operand (operands[1], i1))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1)
      || !register_operand (operands[4], i1)
      || !vector_undef_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern171 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  operands[4] = x3;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1BImode:
      return pattern170 (x1, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2BImode:
      if (pattern170 (x1, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4BImode:
      if (pattern170 (x1, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8BImode:
      if (pattern170 (x1, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16BImode:
      if (pattern170 (x1, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32BImode:
      if (pattern170 (x1, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx64BImode:
      if (pattern170 (x1, E_VNx64BImode) != 0)
        return -1;
      return 6;

    default:
      return -1;
    }
}

static int
pattern172 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_all_trues_mask_operand (operands[1], i1))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1))
    return -1;
  x4 = XEXP (x3, 1);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[4], i1)
      || !vector_undef_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern173 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[5] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[6] = x4;
  x5 = XEXP (x1, 1);
  x6 = XEXP (x5, 0);
  operands[3] = x6;
  x7 = XEXP (x5, 1);
  switch (GET_CODE (x7))
    {
    case REG:
    case SUBREG:
      return pattern171 (x1); /* [-1, 6] */

    case NOT:
      x8 = XEXP (x7, 0);
      operands[4] = x8;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1BImode:
          if (pattern172 (x1, E_VNx1BImode) != 0)
            return -1;
          return 7;

        case E_VNx2BImode:
          if (pattern172 (x1, E_VNx2BImode) != 0)
            return -1;
          return 8;

        case E_VNx4BImode:
          if (pattern172 (x1, E_VNx4BImode) != 0)
            return -1;
          return 9;

        case E_VNx8BImode:
          if (pattern172 (x1, E_VNx8BImode) != 0)
            return -1;
          return 10;

        case E_VNx16BImode:
          if (pattern172 (x1, E_VNx16BImode) != 0)
            return -1;
          return 11;

        case E_VNx32BImode:
          if (pattern172 (x1, E_VNx32BImode) != 0)
            return -1;
          return 12;

        case E_VNx64BImode:
          if (pattern172 (x1, E_VNx64BImode) != 0)
            return -1;
          return 13;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern174 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx1QImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx1QImode
          || !reg_or_0_operand (operands[2], E_QImode)
          || !register_operand (operands[1], E_VNx1QImode))
        return -1;
      return 0;

    case E_VNx1HImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx1HImode
          || !reg_or_0_operand (operands[2], E_HImode)
          || !register_operand (operands[1], E_VNx1HImode))
        return -1;
      return 1;

    case E_VNx1SImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx1SImode
          || !reg_or_0_operand (operands[2], E_SImode)
          || !register_operand (operands[1], E_VNx1SImode))
        return -1;
      return 2;

    case E_VNx1DImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx1DImode
          || !reg_or_0_operand (operands[2], E_DImode)
          || !register_operand (operands[1], E_VNx1DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern175 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx2QImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx2QImode
          || !reg_or_0_operand (operands[2], E_QImode)
          || !register_operand (operands[1], E_VNx2QImode))
        return -1;
      return 0;

    case E_VNx2HImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx2HImode
          || !reg_or_0_operand (operands[2], E_HImode)
          || !register_operand (operands[1], E_VNx2HImode))
        return -1;
      return 1;

    case E_VNx2SImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx2SImode
          || !reg_or_0_operand (operands[2], E_SImode)
          || !register_operand (operands[1], E_VNx2SImode))
        return -1;
      return 2;

    case E_VNx2DImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx2DImode
          || !reg_or_0_operand (operands[2], E_DImode)
          || !register_operand (operands[1], E_VNx2DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern176 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx4QImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx4QImode
          || !reg_or_0_operand (operands[2], E_QImode)
          || !register_operand (operands[1], E_VNx4QImode))
        return -1;
      return 0;

    case E_VNx4HImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx4HImode
          || !reg_or_0_operand (operands[2], E_HImode)
          || !register_operand (operands[1], E_VNx4HImode))
        return -1;
      return 1;

    case E_VNx4SImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx4SImode
          || !reg_or_0_operand (operands[2], E_SImode)
          || !register_operand (operands[1], E_VNx4SImode))
        return -1;
      return 2;

    case E_VNx4DImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx4DImode
          || !reg_or_0_operand (operands[2], E_DImode)
          || !register_operand (operands[1], E_VNx4DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern177 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx8QImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx8QImode
          || !reg_or_0_operand (operands[2], E_QImode)
          || !register_operand (operands[1], E_VNx8QImode))
        return -1;
      return 0;

    case E_VNx8HImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx8HImode
          || !reg_or_0_operand (operands[2], E_HImode)
          || !register_operand (operands[1], E_VNx8HImode))
        return -1;
      return 1;

    case E_VNx8SImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx8SImode
          || !reg_or_0_operand (operands[2], E_SImode)
          || !register_operand (operands[1], E_VNx8SImode))
        return -1;
      return 2;

    case E_VNx8DImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx8DImode
          || !reg_or_0_operand (operands[2], E_DImode)
          || !register_operand (operands[1], E_VNx8DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern178 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx16QImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx16QImode
          || !reg_or_0_operand (operands[2], E_QImode)
          || !register_operand (operands[1], E_VNx16QImode))
        return -1;
      return 0;

    case E_VNx16HImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx16HImode
          || !reg_or_0_operand (operands[2], E_HImode)
          || !register_operand (operands[1], E_VNx16HImode))
        return -1;
      return 1;

    case E_VNx16SImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx16SImode
          || !reg_or_0_operand (operands[2], E_SImode)
          || !register_operand (operands[1], E_VNx16SImode))
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern179 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx32QImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx32QImode
          || !reg_or_0_operand (operands[2], E_QImode)
          || !register_operand (operands[1], E_VNx32QImode))
        return -1;
      return 0;

    case E_VNx32HImode:
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx32HImode
          || !reg_or_0_operand (operands[2], E_HImode)
          || !register_operand (operands[1], E_VNx32HImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern180 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x2, 0);
  if (GET_MODE (x3) != i2
      || !register_operand (operands[1], i2))
    return -1;
  x4 = XVECEXP (x1, 0, 1);
  if (GET_MODE (x4) != i1)
    return -1;
  return 0;
}

static int
pattern181 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  x3 = XEXP (x2, 0);
  switch (GET_CODE (x3))
    {
    case REG:
    case SUBREG:
      operands[1] = x3;
      x4 = XEXP (x2, 1);
      operands[2] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1BImode:
          return 0;

        case E_VNx2BImode:
          return 1;

        case E_VNx4BImode:
          return 2;

        case E_VNx8BImode:
          return 3;

        case E_VNx16BImode:
          return 4;

        case E_VNx32BImode:
          return 5;

        case E_VNx64BImode:
          return 6;

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x4 = XEXP (x2, 1);
      operands[1] = x4;
      x5 = XEXP (x3, 0);
      switch (GET_CODE (x5))
        {
        case CONST_INT:
        case CONST_WIDE_INT:
        case CONST_VECTOR:
        case REG:
        case SUBREG:
          operands[2] = x5;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1BImode:
              if (!register_operand (operands[0], E_VNx1BImode)
                  || GET_MODE (x1) != E_VNx1BImode)
                return -1;
              x6 = XVECEXP (x1, 0, 1);
              if (GET_MODE (x6) != E_VNx1BImode)
                return -1;
              res = pattern174 (x2);
              if (res >= 0)
                return res + 7; /* [7, 10] */
              return -1;

            case E_VNx2BImode:
              if (!register_operand (operands[0], E_VNx2BImode)
                  || GET_MODE (x1) != E_VNx2BImode)
                return -1;
              x6 = XVECEXP (x1, 0, 1);
              if (GET_MODE (x6) != E_VNx2BImode)
                return -1;
              res = pattern175 (x2);
              if (res >= 0)
                return res + 11; /* [11, 14] */
              return -1;

            case E_VNx4BImode:
              if (!register_operand (operands[0], E_VNx4BImode)
                  || GET_MODE (x1) != E_VNx4BImode)
                return -1;
              x6 = XVECEXP (x1, 0, 1);
              if (GET_MODE (x6) != E_VNx4BImode)
                return -1;
              res = pattern176 (x2);
              if (res >= 0)
                return res + 15; /* [15, 18] */
              return -1;

            case E_VNx8BImode:
              if (!register_operand (operands[0], E_VNx8BImode)
                  || GET_MODE (x1) != E_VNx8BImode)
                return -1;
              x6 = XVECEXP (x1, 0, 1);
              if (GET_MODE (x6) != E_VNx8BImode)
                return -1;
              res = pattern177 (x2);
              if (res >= 0)
                return res + 19; /* [19, 22] */
              return -1;

            case E_VNx16BImode:
              if (!register_operand (operands[0], E_VNx16BImode)
                  || GET_MODE (x1) != E_VNx16BImode)
                return -1;
              x6 = XVECEXP (x1, 0, 1);
              if (GET_MODE (x6) != E_VNx16BImode)
                return -1;
              res = pattern178 (x2);
              if (res >= 0)
                return res + 23; /* [23, 25] */
              return -1;

            case E_VNx32BImode:
              if (!register_operand (operands[0], E_VNx32BImode)
                  || GET_MODE (x1) != E_VNx32BImode)
                return -1;
              x6 = XVECEXP (x1, 0, 1);
              if (GET_MODE (x6) != E_VNx32BImode)
                return -1;
              res = pattern179 (x2);
              if (res >= 0)
                return res + 26; /* [26, 27] */
              return -1;

            case E_VNx64BImode:
              if (!register_operand (operands[0], E_VNx64BImode)
                  || GET_MODE (x1) != E_VNx64BImode
                  || GET_MODE (x2) != E_VNx64QImode
                  || GET_MODE (x3) != E_VNx64QImode
                  || !reg_or_0_operand (operands[2], E_QImode)
                  || !register_operand (operands[1], E_VNx64QImode))
                return -1;
              x6 = XVECEXP (x1, 0, 1);
              if (GET_MODE (x6) != E_VNx64BImode)
                return -1;
              return 28;

            default:
              return -1;
            }

        case SIGN_EXTEND:
          if (GET_MODE (x5) != E_DImode)
            return -1;
          x7 = XEXP (x5, 0);
          operands[2] = x7;
          if (!reg_or_0_operand (operands[2], E_SImode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1BImode:
              if (pattern180 (x1, E_VNx1BImode, E_VNx1DImode) != 0)
                return -1;
              return 29;

            case E_VNx2BImode:
              if (pattern180 (x1, E_VNx2BImode, E_VNx2DImode) != 0)
                return -1;
              return 30;

            case E_VNx4BImode:
              if (pattern180 (x1, E_VNx4BImode, E_VNx4DImode) != 0)
                return -1;
              return 31;

            case E_VNx8BImode:
              if (pattern180 (x1, E_VNx8BImode, E_VNx8DImode) != 0)
                return -1;
              return 32;

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern182 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[5] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[6] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[7] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[8] = x6;
  x7 = XEXP (x1, 1);
  x8 = XEXP (x7, 1);
  operands[3] = x8;
  x9 = XEXP (x1, 2);
  operands[2] = x9;
  return pattern156 (x1); /* [-1, 34] */
}

static int
pattern183 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[2], i1)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern184 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1)
    return -1;
  x6 = XEXP (x5, 0);
  if (GET_MODE (x6) != i1
      || !register_operand (operands[2], i3)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern185 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1)
    return -1;
  x6 = XEXP (x5, 0);
  if (GET_MODE (x6) != i1
      || !register_operand (operands[3], i2))
    return -1;
  x7 = XEXP (x5, 1);
  if (GET_MODE (x7) != i1
      || !register_operand (operands[4], i2)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern186 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1)
    return -1;
  x6 = XEXP (x5, 0);
  if (GET_MODE (x6) != i1)
    return -1;
  x7 = XEXP (x6, 0);
  if (GET_MODE (x7) != i2)
    return -1;
  x8 = XEXP (x5, 1);
  if (GET_MODE (x8) != i1
      || !register_operand (operands[4], i2)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern187 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15, x16;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 0);
  if (GET_CODE (x4) != MULT)
    return -1;
  x5 = XEXP (x4, 0);
  switch (GET_CODE (x5))
    {
    case REG:
    case SUBREG:
      operands[2] = x5;
      x6 = XEXP (x4, 1);
      operands[3] = x6;
      x7 = XEXP (x2, 1);
      operands[4] = x7;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1SFmode:
          return pattern183 (x1, E_VNx1SFmode, E_VNx1BImode); /* [-1, 0] */

        case E_VNx2SFmode:
          if (pattern183 (x1, E_VNx2SFmode, E_VNx2BImode) != 0)
            return -1;
          return 1;

        case E_VNx4SFmode:
          if (pattern183 (x1, E_VNx4SFmode, E_VNx4BImode) != 0)
            return -1;
          return 2;

        case E_VNx8SFmode:
          if (pattern183 (x1, E_VNx8SFmode, E_VNx8BImode) != 0)
            return -1;
          return 3;

        case E_VNx16SFmode:
          if (pattern183 (x1, E_VNx16SFmode, E_VNx16BImode) != 0)
            return -1;
          return 4;

        case E_VNx1DFmode:
          if (pattern183 (x1, E_VNx1DFmode, E_VNx1BImode) != 0)
            return -1;
          return 5;

        case E_VNx2DFmode:
          if (pattern183 (x1, E_VNx2DFmode, E_VNx2BImode) != 0)
            return -1;
          return 6;

        case E_VNx4DFmode:
          if (pattern183 (x1, E_VNx4DFmode, E_VNx4BImode) != 0)
            return -1;
          return 7;

        case E_VNx8DFmode:
          if (pattern183 (x1, E_VNx8DFmode, E_VNx8BImode) != 0)
            return -1;
          return 8;

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x8 = XEXP (x5, 0);
      operands[2] = x8;
      x6 = XEXP (x4, 1);
      operands[3] = x6;
      x7 = XEXP (x2, 1);
      operands[4] = x7;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1SFmode:
          if (pattern184 (x1, E_VNx1SFmode, E_VNx1BImode, E_SFmode) != 0)
            return -1;
          return 9;

        case E_VNx2SFmode:
          if (pattern184 (x1, E_VNx2SFmode, E_VNx2BImode, E_SFmode) != 0)
            return -1;
          return 10;

        case E_VNx4SFmode:
          if (pattern184 (x1, E_VNx4SFmode, E_VNx4BImode, E_SFmode) != 0)
            return -1;
          return 11;

        case E_VNx8SFmode:
          if (pattern184 (x1, E_VNx8SFmode, E_VNx8BImode, E_SFmode) != 0)
            return -1;
          return 12;

        case E_VNx16SFmode:
          if (pattern184 (x1, E_VNx16SFmode, E_VNx16BImode, E_SFmode) != 0)
            return -1;
          return 13;

        case E_VNx1DFmode:
          if (pattern184 (x1, E_VNx1DFmode, E_VNx1BImode, E_DFmode) != 0)
            return -1;
          return 14;

        case E_VNx2DFmode:
          if (pattern184 (x1, E_VNx2DFmode, E_VNx2BImode, E_DFmode) != 0)
            return -1;
          return 15;

        case E_VNx4DFmode:
          if (pattern184 (x1, E_VNx4DFmode, E_VNx4BImode, E_DFmode) != 0)
            return -1;
          return 16;

        case E_VNx8DFmode:
          if (pattern184 (x1, E_VNx8DFmode, E_VNx8BImode, E_DFmode) != 0)
            return -1;
          return 17;

        default:
          return -1;
        }

    case FLOAT_EXTEND:
      x6 = XEXP (x4, 1);
      if (GET_CODE (x6) != FLOAT_EXTEND)
        return -1;
      x9 = XEXP (x1, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      x14 = XEXP (x6, 0);
      operands[4] = x14;
      x7 = XEXP (x2, 1);
      operands[2] = x7;
      x15 = XEXP (x1, 2);
      if (!rtx_equal_p (x15, operands[2]))
        return -1;
      x8 = XEXP (x5, 0);
      switch (GET_CODE (x8))
        {
        case REG:
        case SUBREG:
          operands[3] = x8;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1DFmode:
              if (pattern185 (x1, E_VNx1DFmode, E_VNx1SFmode, E_VNx1BImode) != 0)
                return -1;
              return 18;

            case E_VNx2DFmode:
              if (pattern185 (x1, E_VNx2DFmode, E_VNx2SFmode, E_VNx2BImode) != 0)
                return -1;
              return 19;

            case E_VNx4DFmode:
              if (pattern185 (x1, E_VNx4DFmode, E_VNx4SFmode, E_VNx4BImode) != 0)
                return -1;
              return 20;

            case E_VNx8DFmode:
              if (pattern185 (x1, E_VNx8DFmode, E_VNx8SFmode, E_VNx8BImode) != 0)
                return -1;
              return 21;

            default:
              return -1;
            }

        case VEC_DUPLICATE:
          x16 = XEXP (x8, 0);
          operands[3] = x16;
          if (!register_operand (operands[3], E_SFmode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1DFmode:
              if (pattern186 (x1, E_VNx1DFmode, E_VNx1SFmode, E_VNx1BImode) != 0)
                return -1;
              return 22;

            case E_VNx2DFmode:
              if (pattern186 (x1, E_VNx2DFmode, E_VNx2SFmode, E_VNx2BImode) != 0)
                return -1;
              return 23;

            case E_VNx4DFmode:
              if (pattern186 (x1, E_VNx4DFmode, E_VNx4SFmode, E_VNx4BImode) != 0)
                return -1;
              return 24;

            case E_VNx8DFmode:
              if (pattern186 (x1, E_VNx8DFmode, E_VNx8SFmode, E_VNx8BImode) != 0)
                return -1;
              return 25;

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern188 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[3], i2))
    return -1;
  x5 = XEXP (x3, 1);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern189 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[3], i2))
    return -1;
  x5 = XEXP (x3, 1);
  if (GET_MODE (x5) != i1)
    return -1;
  x6 = XEXP (x5, 0);
  if (GET_MODE (x6) != i2
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern190 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      operands[4] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1DFmode:
          return pattern188 (x1, E_VNx1DFmode, E_VNx1SFmode, E_VNx1BImode); /* [-1, 0] */

        case E_VNx2DFmode:
          if (pattern188 (x1, E_VNx2DFmode, E_VNx2SFmode, E_VNx2BImode) != 0)
            return -1;
          return 1;

        case E_VNx4DFmode:
          if (pattern188 (x1, E_VNx4DFmode, E_VNx4SFmode, E_VNx4BImode) != 0)
            return -1;
          return 2;

        case E_VNx8DFmode:
          if (pattern188 (x1, E_VNx8DFmode, E_VNx8SFmode, E_VNx8BImode) != 0)
            return -1;
          return 3;

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x5 = XEXP (x4, 0);
      operands[4] = x5;
      if (!register_operand (operands[4], E_SFmode))
        return -1;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1DFmode:
          if (pattern189 (x1, E_VNx1DFmode, E_VNx1SFmode, E_VNx1BImode) != 0)
            return -1;
          return 4;

        case E_VNx2DFmode:
          if (pattern189 (x1, E_VNx2DFmode, E_VNx2SFmode, E_VNx2BImode) != 0)
            return -1;
          return 5;

        case E_VNx4DFmode:
          if (pattern189 (x1, E_VNx4DFmode, E_VNx4SFmode, E_VNx4BImode) != 0)
            return -1;
          return 6;

        case E_VNx8DFmode:
          if (pattern189 (x1, E_VNx8DFmode, E_VNx8SFmode, E_VNx8BImode) != 0)
            return -1;
          return 7;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern191 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  if (GET_CODE (x3) != FLOAT_EXTEND)
    return -1;
  x4 = XEXP (x1, 0);
  x5 = XVECEXP (x4, 0, 1);
  operands[5] = x5;
  x6 = XVECEXP (x4, 0, 2);
  operands[6] = x6;
  x7 = XVECEXP (x4, 0, 3);
  operands[7] = x7;
  x8 = XVECEXP (x4, 0, 4);
  operands[8] = x8;
  x9 = XEXP (x2, 0);
  x10 = XEXP (x9, 0);
  operands[3] = x10;
  x11 = XEXP (x1, 2);
  operands[2] = x11;
  return pattern190 (x1); /* [-1, 7] */
}

static int
pattern192 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !reg_or_0_operand (operands[4], i3)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern193 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3, machine_mode i4)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[3], i2))
    return -1;
  x5 = XEXP (x3, 1);
  return pattern192 (x5, i1, i2, i4); /* [-1, 0] */
}

static int
pattern194 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      operands[4] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1HImode:
          return pattern188 (x1, E_VNx1HImode, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

        case E_VNx2HImode:
          if (pattern188 (x1, E_VNx2HImode, E_VNx2QImode, E_VNx2BImode) != 0)
            return -1;
          return 1;

        case E_VNx4HImode:
          if (pattern188 (x1, E_VNx4HImode, E_VNx4QImode, E_VNx4BImode) != 0)
            return -1;
          return 2;

        case E_VNx8HImode:
          if (pattern188 (x1, E_VNx8HImode, E_VNx8QImode, E_VNx8BImode) != 0)
            return -1;
          return 3;

        case E_VNx16HImode:
          if (pattern188 (x1, E_VNx16HImode, E_VNx16QImode, E_VNx16BImode) != 0)
            return -1;
          return 4;

        case E_VNx32HImode:
          if (pattern188 (x1, E_VNx32HImode, E_VNx32QImode, E_VNx32BImode) != 0)
            return -1;
          return 5;

        case E_VNx1SImode:
          if (pattern188 (x1, E_VNx1SImode, E_VNx1HImode, E_VNx1BImode) != 0)
            return -1;
          return 6;

        case E_VNx2SImode:
          if (pattern188 (x1, E_VNx2SImode, E_VNx2HImode, E_VNx2BImode) != 0)
            return -1;
          return 7;

        case E_VNx4SImode:
          if (pattern188 (x1, E_VNx4SImode, E_VNx4HImode, E_VNx4BImode) != 0)
            return -1;
          return 8;

        case E_VNx8SImode:
          if (pattern188 (x1, E_VNx8SImode, E_VNx8HImode, E_VNx8BImode) != 0)
            return -1;
          return 9;

        case E_VNx16SImode:
          if (pattern188 (x1, E_VNx16SImode, E_VNx16HImode, E_VNx16BImode) != 0)
            return -1;
          return 10;

        case E_VNx1DImode:
          if (pattern188 (x1, E_VNx1DImode, E_VNx1SImode, E_VNx1BImode) != 0)
            return -1;
          return 11;

        case E_VNx2DImode:
          if (pattern188 (x1, E_VNx2DImode, E_VNx2SImode, E_VNx2BImode) != 0)
            return -1;
          return 12;

        case E_VNx4DImode:
          if (pattern188 (x1, E_VNx4DImode, E_VNx4SImode, E_VNx4BImode) != 0)
            return -1;
          return 13;

        case E_VNx8DImode:
          if (pattern188 (x1, E_VNx8DImode, E_VNx8SImode, E_VNx8BImode) != 0)
            return -1;
          return 14;

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x5 = XEXP (x4, 0);
      operands[4] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1HImode:
          if (pattern193 (x1, E_VNx1HImode, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0)
            return -1;
          return 15;

        case E_VNx2HImode:
          if (pattern193 (x1, E_VNx2HImode, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
            return -1;
          return 16;

        case E_VNx4HImode:
          if (pattern193 (x1, E_VNx4HImode, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
            return -1;
          return 17;

        case E_VNx8HImode:
          if (pattern193 (x1, E_VNx8HImode, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
            return -1;
          return 18;

        case E_VNx16HImode:
          if (pattern193 (x1, E_VNx16HImode, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
            return -1;
          return 19;

        case E_VNx32HImode:
          if (pattern193 (x1, E_VNx32HImode, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
            return -1;
          return 20;

        case E_VNx1SImode:
          if (pattern193 (x1, E_VNx1SImode, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
            return -1;
          return 21;

        case E_VNx2SImode:
          if (pattern193 (x1, E_VNx2SImode, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
            return -1;
          return 22;

        case E_VNx4SImode:
          if (pattern193 (x1, E_VNx4SImode, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
            return -1;
          return 23;

        case E_VNx8SImode:
          if (pattern193 (x1, E_VNx8SImode, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
            return -1;
          return 24;

        case E_VNx16SImode:
          if (pattern193 (x1, E_VNx16SImode, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
            return -1;
          return 25;

        case E_VNx1DImode:
          if (pattern193 (x1, E_VNx1DImode, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
            return -1;
          return 26;

        case E_VNx2DImode:
          if (pattern193 (x1, E_VNx2DImode, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
            return -1;
          return 27;

        case E_VNx4DImode:
          if (pattern193 (x1, E_VNx4DImode, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
            return -1;
          return 28;

        case E_VNx8DImode:
          if (pattern193 (x1, E_VNx8DImode, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
            return -1;
          return 29;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern195 (rtx x1, rtx_code i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  if (GET_CODE (x3) != i1)
    return -1;
  x4 = XEXP (x1, 0);
  x5 = XVECEXP (x4, 0, 1);
  operands[5] = x5;
  x6 = XVECEXP (x4, 0, 2);
  operands[6] = x6;
  x7 = XVECEXP (x4, 0, 3);
  operands[7] = x7;
  x8 = XVECEXP (x4, 0, 4);
  operands[8] = x8;
  x9 = XEXP (x2, 0);
  x10 = XEXP (x9, 0);
  operands[3] = x10;
  x11 = XEXP (x1, 2);
  operands[2] = x11;
  return pattern194 (x1); /* [-1, 29] */
}

static int
pattern196 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!memory_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern197 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!memory_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_all_trues_mask_operand (operands[1], i1)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern198 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_all_trues_mask_operand (operands[1], i1))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[3], i1)
      || !register_operand (operands[4], i1)
      || !vector_undef_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern199 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[5] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[6] = x4;
  x5 = XEXP (x1, 1);
  x6 = XEXP (x5, 0);
  x7 = XEXP (x6, 0);
  operands[3] = x7;
  x8 = XEXP (x6, 1);
  operands[4] = x8;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1BImode:
      return pattern198 (x1, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2BImode:
      if (pattern198 (x1, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4BImode:
      if (pattern198 (x1, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8BImode:
      if (pattern198 (x1, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16BImode:
      if (pattern198 (x1, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32BImode:
      if (pattern198 (x1, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx64BImode:
      if (pattern198 (x1, E_VNx64BImode) != 0)
        return -1;
      return 6;

    default:
      return -1;
    }
}

static int
pattern200 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[3], i2))
    return -1;
  x6 = XEXP (x4, 1);
  if (GET_MODE (x6) != i1
      || !register_operand (operands[4], i2)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern201 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1)
    return -1;
  x6 = XEXP (x5, 0);
  if (GET_MODE (x6) != i2)
    return -1;
  x7 = XEXP (x4, 1);
  if (GET_MODE (x7) != i1
      || !register_operand (operands[4], i2)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern202 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 1);
  if (GET_CODE (x4) != FLOAT_EXTEND)
    return -1;
  x5 = XEXP (x1, 0);
  x6 = XVECEXP (x5, 0, 1);
  operands[5] = x6;
  x7 = XVECEXP (x5, 0, 2);
  operands[6] = x7;
  x8 = XVECEXP (x5, 0, 3);
  operands[7] = x8;
  x9 = XVECEXP (x5, 0, 4);
  operands[8] = x9;
  x10 = XEXP (x4, 0);
  operands[4] = x10;
  x11 = XEXP (x2, 1);
  operands[2] = x11;
  x12 = XEXP (x1, 2);
  if (!rtx_equal_p (x12, operands[2]))
    return -1;
  x13 = XEXP (x3, 0);
  x14 = XEXP (x13, 0);
  switch (GET_CODE (x14))
    {
    case REG:
    case SUBREG:
      operands[3] = x14;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1DFmode:
          return pattern200 (x1, E_VNx1DFmode, E_VNx1SFmode, E_VNx1BImode); /* [-1, 0] */

        case E_VNx2DFmode:
          if (pattern200 (x1, E_VNx2DFmode, E_VNx2SFmode, E_VNx2BImode) != 0)
            return -1;
          return 1;

        case E_VNx4DFmode:
          if (pattern200 (x1, E_VNx4DFmode, E_VNx4SFmode, E_VNx4BImode) != 0)
            return -1;
          return 2;

        case E_VNx8DFmode:
          if (pattern200 (x1, E_VNx8DFmode, E_VNx8SFmode, E_VNx8BImode) != 0)
            return -1;
          return 3;

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x15 = XEXP (x14, 0);
      operands[3] = x15;
      if (!register_operand (operands[3], E_SFmode))
        return -1;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1DFmode:
          if (pattern201 (x1, E_VNx1DFmode, E_VNx1SFmode, E_VNx1BImode) != 0)
            return -1;
          return 4;

        case E_VNx2DFmode:
          if (pattern201 (x1, E_VNx2DFmode, E_VNx2SFmode, E_VNx2BImode) != 0)
            return -1;
          return 5;

        case E_VNx4DFmode:
          if (pattern201 (x1, E_VNx4DFmode, E_VNx4SFmode, E_VNx4BImode) != 0)
            return -1;
          return 6;

        case E_VNx8DFmode:
          if (pattern201 (x1, E_VNx8DFmode, E_VNx8SFmode, E_VNx8BImode) != 0)
            return -1;
          return 7;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern203 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1))
    return -1;
  x4 = XEXP (x3, 1);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[4], i3)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern204 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3, machine_mode i4)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1))
    return -1;
  x4 = XEXP (x3, 1);
  return pattern192 (x4, i1, i2, i4); /* [-1, 0] */
}

static int
pattern205 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      operands[4] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1HImode:
          return pattern203 (x1, E_VNx1HImode, E_VNx1BImode, E_VNx1QImode); /* [-1, 0] */

        case E_VNx2HImode:
          if (pattern203 (x1, E_VNx2HImode, E_VNx2BImode, E_VNx2QImode) != 0)
            return -1;
          return 1;

        case E_VNx4HImode:
          if (pattern203 (x1, E_VNx4HImode, E_VNx4BImode, E_VNx4QImode) != 0)
            return -1;
          return 2;

        case E_VNx8HImode:
          if (pattern203 (x1, E_VNx8HImode, E_VNx8BImode, E_VNx8QImode) != 0)
            return -1;
          return 3;

        case E_VNx16HImode:
          if (pattern203 (x1, E_VNx16HImode, E_VNx16BImode, E_VNx16QImode) != 0)
            return -1;
          return 4;

        case E_VNx32HImode:
          if (pattern203 (x1, E_VNx32HImode, E_VNx32BImode, E_VNx32QImode) != 0)
            return -1;
          return 5;

        case E_VNx1SImode:
          if (pattern203 (x1, E_VNx1SImode, E_VNx1BImode, E_VNx1HImode) != 0)
            return -1;
          return 6;

        case E_VNx2SImode:
          if (pattern203 (x1, E_VNx2SImode, E_VNx2BImode, E_VNx2HImode) != 0)
            return -1;
          return 7;

        case E_VNx4SImode:
          if (pattern203 (x1, E_VNx4SImode, E_VNx4BImode, E_VNx4HImode) != 0)
            return -1;
          return 8;

        case E_VNx8SImode:
          if (pattern203 (x1, E_VNx8SImode, E_VNx8BImode, E_VNx8HImode) != 0)
            return -1;
          return 9;

        case E_VNx16SImode:
          if (pattern203 (x1, E_VNx16SImode, E_VNx16BImode, E_VNx16HImode) != 0)
            return -1;
          return 10;

        case E_VNx1DImode:
          if (pattern203 (x1, E_VNx1DImode, E_VNx1BImode, E_VNx1SImode) != 0)
            return -1;
          return 11;

        case E_VNx2DImode:
          if (pattern203 (x1, E_VNx2DImode, E_VNx2BImode, E_VNx2SImode) != 0)
            return -1;
          return 12;

        case E_VNx4DImode:
          if (pattern203 (x1, E_VNx4DImode, E_VNx4BImode, E_VNx4SImode) != 0)
            return -1;
          return 13;

        case E_VNx8DImode:
          if (pattern203 (x1, E_VNx8DImode, E_VNx8BImode, E_VNx8SImode) != 0)
            return -1;
          return 14;

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x5 = XEXP (x4, 0);
      operands[4] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1HImode:
          if (pattern204 (x1, E_VNx1HImode, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0)
            return -1;
          return 15;

        case E_VNx2HImode:
          if (pattern204 (x1, E_VNx2HImode, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
            return -1;
          return 16;

        case E_VNx4HImode:
          if (pattern204 (x1, E_VNx4HImode, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
            return -1;
          return 17;

        case E_VNx8HImode:
          if (pattern204 (x1, E_VNx8HImode, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
            return -1;
          return 18;

        case E_VNx16HImode:
          if (pattern204 (x1, E_VNx16HImode, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
            return -1;
          return 19;

        case E_VNx32HImode:
          if (pattern204 (x1, E_VNx32HImode, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
            return -1;
          return 20;

        case E_VNx1SImode:
          if (pattern204 (x1, E_VNx1SImode, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
            return -1;
          return 21;

        case E_VNx2SImode:
          if (pattern204 (x1, E_VNx2SImode, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
            return -1;
          return 22;

        case E_VNx4SImode:
          if (pattern204 (x1, E_VNx4SImode, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
            return -1;
          return 23;

        case E_VNx8SImode:
          if (pattern204 (x1, E_VNx8SImode, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
            return -1;
          return 24;

        case E_VNx16SImode:
          if (pattern204 (x1, E_VNx16SImode, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
            return -1;
          return 25;

        case E_VNx1DImode:
          if (pattern204 (x1, E_VNx1DImode, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
            return -1;
          return 26;

        case E_VNx2DImode:
          if (pattern204 (x1, E_VNx2DImode, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
            return -1;
          return 27;

        case E_VNx4DImode:
          if (pattern204 (x1, E_VNx4DImode, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
            return -1;
          return 28;

        case E_VNx8DImode:
          if (pattern204 (x1, E_VNx8DImode, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
            return -1;
          return 29;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern206 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[5] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[6] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[7] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[8] = x6;
  x7 = XEXP (x1, 1);
  x8 = XEXP (x7, 0);
  operands[3] = x8;
  x9 = XEXP (x1, 2);
  operands[2] = x9;
  return pattern205 (x1); /* [-1, 29] */
}

static int
pattern207 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i2
      || !register_operand (operands[3], i2)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern208 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[5] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[6] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[7] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[8] = x6;
  x7 = XEXP (x1, 1);
  x8 = XEXP (x7, 0);
  x9 = XEXP (x8, 0);
  operands[3] = x9;
  x10 = XEXP (x8, 1);
  operands[4] = x10;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      return pattern207 (x1, E_VNx1QImode, E_VNx1HImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2QImode:
      if (pattern207 (x1, E_VNx2QImode, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4QImode:
      if (pattern207 (x1, E_VNx4QImode, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8QImode:
      if (pattern207 (x1, E_VNx8QImode, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16QImode:
      if (pattern207 (x1, E_VNx16QImode, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32QImode:
      if (pattern207 (x1, E_VNx32QImode, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx1HImode:
      if (pattern207 (x1, E_VNx1HImode, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      return 6;

    case E_VNx2HImode:
      if (pattern207 (x1, E_VNx2HImode, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      return 7;

    case E_VNx4HImode:
      if (pattern207 (x1, E_VNx4HImode, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      return 8;

    case E_VNx8HImode:
      if (pattern207 (x1, E_VNx8HImode, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      return 9;

    case E_VNx16HImode:
      if (pattern207 (x1, E_VNx16HImode, E_VNx16SImode, E_VNx16BImode) != 0)
        return -1;
      return 10;

    case E_VNx1SImode:
      if (pattern207 (x1, E_VNx1SImode, E_VNx1DImode, E_VNx1BImode) != 0)
        return -1;
      return 11;

    case E_VNx2SImode:
      if (pattern207 (x1, E_VNx2SImode, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      return 12;

    case E_VNx4SImode:
      if (pattern207 (x1, E_VNx4SImode, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      return 13;

    case E_VNx8SImode:
      if (pattern207 (x1, E_VNx8SImode, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      return 14;

    default:
      return -1;
    }
}

static int
pattern209 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  switch (GET_MODE (x2))
    {
    case E_VNx1BImode:
      x3 = XVECEXP (x2, 0, 0);
      if (GET_MODE (x3) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode)
          || !register_operand (operands[2], E_VNx1BImode))
        return -1;
      return 0;

    case E_VNx2BImode:
      x3 = XVECEXP (x2, 0, 0);
      if (GET_MODE (x3) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode)
          || !register_operand (operands[2], E_VNx2BImode))
        return -1;
      return 1;

    case E_VNx4BImode:
      x3 = XVECEXP (x2, 0, 0);
      if (GET_MODE (x3) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode)
          || !register_operand (operands[2], E_VNx4BImode))
        return -1;
      return 2;

    case E_VNx8BImode:
      x3 = XVECEXP (x2, 0, 0);
      if (GET_MODE (x3) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode)
          || !register_operand (operands[2], E_VNx8BImode))
        return -1;
      return 3;

    case E_VNx16BImode:
      x3 = XVECEXP (x2, 0, 0);
      if (GET_MODE (x3) != E_VNx16BImode
          || !vector_mask_operand (operands[1], E_VNx16BImode)
          || !register_operand (operands[2], E_VNx16BImode))
        return -1;
      return 4;

    case E_VNx32BImode:
      x3 = XVECEXP (x2, 0, 0);
      if (GET_MODE (x3) != E_VNx32BImode
          || !vector_mask_operand (operands[1], E_VNx32BImode)
          || !register_operand (operands[2], E_VNx32BImode))
        return -1;
      return 5;

    case E_VNx64BImode:
      x3 = XVECEXP (x2, 0, 0);
      if (GET_MODE (x3) != E_VNx64BImode
          || !vector_mask_operand (operands[1], E_VNx64BImode)
          || !register_operand (operands[2], E_VNx64BImode))
        return -1;
      return 6;

    default:
      return -1;
    }
}

static int
pattern210 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || !memory_operand (operands[1], i1)
      || GET_MODE (x1) != i1
      || !reg_or_0_operand (operands[2], i1)
      || !reg_or_0_operand (operands[3], i1)
      || !scratch_operand (operands[6], i1))
    return -1;
  return 0;
}

static int
pattern211 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!nonimmediate_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_all_trues_mask_operand (operands[1], i1)
      || !vector_move_operand (operands[3], i1)
      || !vector_undef_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern212 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  operands[3] = x2;
  x3 = XEXP (x1, 0);
  switch (GET_CODE (x3))
    {
    case REG:
    case SUBREG:
      operands[2] = x3;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          return 0;

        case E_VNx2QImode:
          return 1;

        case E_VNx4QImode:
          return 2;

        case E_VNx8QImode:
          return 3;

        case E_VNx16QImode:
          return 4;

        case E_VNx32QImode:
          return 5;

        case E_VNx64QImode:
          return 6;

        case E_VNx1HImode:
          return 7;

        case E_VNx2HImode:
          return 8;

        case E_VNx4HImode:
          return 9;

        case E_VNx8HImode:
          return 10;

        case E_VNx16HImode:
          return 11;

        case E_VNx32HImode:
          return 12;

        case E_VNx1SImode:
          return 13;

        case E_VNx2SImode:
          return 14;

        case E_VNx4SImode:
          return 15;

        case E_VNx8SImode:
          return 16;

        case E_VNx16SImode:
          return 17;

        case E_VNx1DImode:
          return 18;

        case E_VNx2DImode:
          return 19;

        case E_VNx4DImode:
          return 20;

        case E_VNx8DImode:
          return 21;

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x4 = XEXP (x3, 0);
      switch (GET_CODE (x4))
        {
        case REG:
        case SUBREG:
          operands[2] = x4;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1QImode:
              return 22;

            case E_VNx2QImode:
              return 23;

            case E_VNx4QImode:
              return 24;

            case E_VNx8QImode:
              return 25;

            case E_VNx16QImode:
              return 26;

            case E_VNx32QImode:
              return 27;

            case E_VNx64QImode:
              return 28;

            case E_VNx1HImode:
              return 29;

            case E_VNx2HImode:
              return 30;

            case E_VNx4HImode:
              return 31;

            case E_VNx8HImode:
              return 32;

            case E_VNx16HImode:
              return 33;

            case E_VNx32HImode:
              return 34;

            case E_VNx1SImode:
              return 35;

            case E_VNx2SImode:
              return 36;

            case E_VNx4SImode:
              return 37;

            case E_VNx8SImode:
              return 38;

            case E_VNx16SImode:
              return 39;

            case E_VNx1DImode:
              return 40;

            case E_VNx2DImode:
              return 41;

            case E_VNx4DImode:
              return 42;

            case E_VNx8DImode:
              return 43;

            default:
              return -1;
            }

        case SIGN_EXTEND:
          if (GET_MODE (x4) != E_DImode)
            return -1;
          x5 = XEXP (x4, 0);
          operands[2] = x5;
          if (!register_operand (operands[2], E_SImode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1DImode:
              return 44;

            case E_VNx2DImode:
              return 45;

            case E_VNx4DImode:
              return 46;

            case E_VNx8DImode:
              return 47;

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern213 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || !memory_operand (operands[1], i1)
      || GET_MODE (x1) != i1
      || !reg_or_0_operand (operands[2], i1)
      || !reg_or_0_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern214 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  switch (GET_CODE (x1))
    {
    case PLUS:
      x2 = XEXP (x1, 1);
      operands[2] = x2;
      if (!register_operand (operands[2], E_SImode))
        return -1;
      x3 = XEXP (x1, 0);
      if (!rtx_equal_p (x3, operands[1]))
        return -1;
      return 0;

    case IOR:
      x2 = XEXP (x1, 1);
      operands[2] = x2;
      if (!register_operand (operands[2], E_SImode))
        return -1;
      x3 = XEXP (x1, 0);
      if (!rtx_equal_p (x3, operands[1]))
        return -1;
      return 1;

    case XOR:
      x2 = XEXP (x1, 1);
      operands[2] = x2;
      if (!register_operand (operands[2], E_SImode))
        return -1;
      x3 = XEXP (x1, 0);
      if (!rtx_equal_p (x3, operands[1]))
        return -1;
      return 2;

    case AND:
      x2 = XEXP (x1, 1);
      operands[2] = x2;
      if (!register_operand (operands[2], E_SImode))
        return -1;
      x3 = XEXP (x1, 0);
      if (!rtx_equal_p (x3, operands[1]))
        return -1;
      return 3;

    case NOT:
      x3 = XEXP (x1, 0);
      if (GET_CODE (x3) != AND
          || GET_MODE (x3) != E_SImode)
        return -1;
      x4 = XEXP (x3, 1);
      operands[2] = x4;
      if (!register_operand (operands[2], E_SImode))
        return -1;
      x5 = XEXP (x3, 0);
      if (!rtx_equal_p (x5, operands[1]))
        return -1;
      return 4;

    default:
      return -1;
    }
}

static int
pattern215 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1)
    return -1;
  x3 = XEXP (x2, 0);
  switch (GET_MODE (x3))
    {
    case E_VNx1BImode:
      x4 = XVECEXP (x3, 0, 0);
      if (GET_MODE (x4) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode)
          || !register_operand (operands[2], E_VNx1BImode))
        return -1;
      return 0;

    case E_VNx2BImode:
      x4 = XVECEXP (x3, 0, 0);
      if (GET_MODE (x4) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode)
          || !register_operand (operands[2], E_VNx2BImode))
        return -1;
      return 1;

    case E_VNx4BImode:
      x4 = XVECEXP (x3, 0, 0);
      if (GET_MODE (x4) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode)
          || !register_operand (operands[2], E_VNx4BImode))
        return -1;
      return 2;

    case E_VNx8BImode:
      x4 = XVECEXP (x3, 0, 0);
      if (GET_MODE (x4) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode)
          || !register_operand (operands[2], E_VNx8BImode))
        return -1;
      return 3;

    case E_VNx16BImode:
      x4 = XVECEXP (x3, 0, 0);
      if (GET_MODE (x4) != E_VNx16BImode
          || !vector_mask_operand (operands[1], E_VNx16BImode)
          || !register_operand (operands[2], E_VNx16BImode))
        return -1;
      return 4;

    case E_VNx32BImode:
      x4 = XVECEXP (x3, 0, 0);
      if (GET_MODE (x4) != E_VNx32BImode
          || !vector_mask_operand (operands[1], E_VNx32BImode)
          || !register_operand (operands[2], E_VNx32BImode))
        return -1;
      return 5;

    case E_VNx64BImode:
      x4 = XVECEXP (x3, 0, 0);
      if (GET_MODE (x4) != E_VNx64BImode
          || !vector_mask_operand (operands[1], E_VNx64BImode)
          || !register_operand (operands[2], E_VNx64BImode))
        return -1;
      return 6;

    default:
      return -1;
    }
}

static int
pattern216 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  x3 = XVECEXP (x2, 0, 1);
  operands[5] = x3;
  x4 = XVECEXP (x2, 0, 2);
  operands[6] = x4;
  x5 = XVECEXP (x2, 0, 3);
  operands[7] = x5;
  x6 = XVECEXP (x2, 0, 4);
  operands[8] = x6;
  return pattern194 (x1); /* [-1, 29] */
}

static int
pattern217 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3, machine_mode i4)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[3], i2))
    return -1;
  x5 = XEXP (x3, 1);
  if (GET_MODE (x5) != i1)
    return -1;
  x6 = XEXP (x5, 0);
  if (GET_MODE (x6) != i4
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern218 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  if (GET_CODE (x4) != REG
      || REGNO (x4) != 0)
    return -1;
  x5 = XEXP (x1, 0);
  x6 = XVECEXP (x5, 0, 1);
  operands[4] = x6;
  x7 = XVECEXP (x5, 0, 2);
  operands[5] = x7;
  x8 = XVECEXP (x5, 0, 3);
  operands[6] = x8;
  x9 = XVECEXP (x5, 0, 4);
  operands[7] = x9;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1HImode:
      return pattern217 (x1, E_VNx1HImode, E_VNx1QImode, E_VNx1BImode, E_HImode); /* [-1, 0] */

    case E_VNx2HImode:
      if (pattern217 (x1, E_VNx2HImode, E_VNx2QImode, E_VNx2BImode, E_HImode) != 0)
        return -1;
      return 1;

    case E_VNx4HImode:
      if (pattern217 (x1, E_VNx4HImode, E_VNx4QImode, E_VNx4BImode, E_HImode) != 0)
        return -1;
      return 2;

    case E_VNx8HImode:
      if (pattern217 (x1, E_VNx8HImode, E_VNx8QImode, E_VNx8BImode, E_HImode) != 0)
        return -1;
      return 3;

    case E_VNx16HImode:
      if (pattern217 (x1, E_VNx16HImode, E_VNx16QImode, E_VNx16BImode, E_HImode) != 0)
        return -1;
      return 4;

    case E_VNx32HImode:
      if (pattern217 (x1, E_VNx32HImode, E_VNx32QImode, E_VNx32BImode, E_HImode) != 0)
        return -1;
      return 5;

    case E_VNx1SImode:
      if (pattern217 (x1, E_VNx1SImode, E_VNx1HImode, E_VNx1BImode, E_SImode) != 0)
        return -1;
      return 6;

    case E_VNx2SImode:
      if (pattern217 (x1, E_VNx2SImode, E_VNx2HImode, E_VNx2BImode, E_SImode) != 0)
        return -1;
      return 7;

    case E_VNx4SImode:
      if (pattern217 (x1, E_VNx4SImode, E_VNx4HImode, E_VNx4BImode, E_SImode) != 0)
        return -1;
      return 8;

    case E_VNx8SImode:
      if (pattern217 (x1, E_VNx8SImode, E_VNx8HImode, E_VNx8BImode, E_SImode) != 0)
        return -1;
      return 9;

    case E_VNx16SImode:
      if (pattern217 (x1, E_VNx16SImode, E_VNx16HImode, E_VNx16BImode, E_SImode) != 0)
        return -1;
      return 10;

    case E_VNx1DImode:
      if (pattern217 (x1, E_VNx1DImode, E_VNx1SImode, E_VNx1BImode, E_DImode) != 0)
        return -1;
      return 11;

    case E_VNx2DImode:
      if (pattern217 (x1, E_VNx2DImode, E_VNx2SImode, E_VNx2BImode, E_DImode) != 0)
        return -1;
      return 12;

    case E_VNx4DImode:
      if (pattern217 (x1, E_VNx4DImode, E_VNx4SImode, E_VNx4BImode, E_DImode) != 0)
        return -1;
      return 13;

    case E_VNx8DImode:
      if (pattern217 (x1, E_VNx8DImode, E_VNx8SImode, E_VNx8BImode, E_DImode) != 0)
        return -1;
      return 14;

    default:
      return -1;
    }
}

static int
pattern219 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  switch (GET_CODE (x1))
    {
    case REG:
    case SUBREG:
      operands[2] = x1;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          return 0;

        case E_VNx2QImode:
          return 1;

        case E_VNx4QImode:
          return 2;

        case E_VNx8QImode:
          return 3;

        case E_VNx16QImode:
          return 4;

        case E_VNx32QImode:
          return 5;

        case E_VNx64QImode:
          return 6;

        case E_VNx1HImode:
          return 7;

        case E_VNx2HImode:
          return 8;

        case E_VNx4HImode:
          return 9;

        case E_VNx8HImode:
          return 10;

        case E_VNx16HImode:
          return 11;

        case E_VNx32HImode:
          return 12;

        case E_VNx1SImode:
          return 13;

        case E_VNx2SImode:
          return 14;

        case E_VNx4SImode:
          return 15;

        case E_VNx8SImode:
          return 16;

        case E_VNx16SImode:
          return 17;

        case E_VNx1DImode:
          return 18;

        case E_VNx2DImode:
          return 19;

        case E_VNx4DImode:
          return 20;

        case E_VNx8DImode:
          return 21;

        case E_VNx1SFmode:
          return 22;

        case E_VNx2SFmode:
          return 23;

        case E_VNx4SFmode:
          return 24;

        case E_VNx8SFmode:
          return 25;

        case E_VNx16SFmode:
          return 26;

        case E_VNx1DFmode:
          return 27;

        case E_VNx2DFmode:
          return 28;

        case E_VNx4DFmode:
          return 29;

        case E_VNx8DFmode:
          return 30;

        default:
          return -1;
        }

    case SIGN_EXTEND:
      if (GET_MODE (x1) != E_DImode)
        return -1;
      x2 = XEXP (x1, 0);
      operands[2] = x2;
      if (!register_operand (operands[2], E_SImode))
        return -1;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1DImode:
          return 31;

        case E_VNx2DImode:
          return 32;

        case E_VNx4DImode:
          return 33;

        case E_VNx8DImode:
          return 34;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern220 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], E_VNx64BImode)
      || GET_MODE (x1) != E_VNx64BImode)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != E_VNx64QImode
      || !register_operand (operands[1], E_VNx64QImode)
      || !vector_arith_operand (operands[2], E_VNx64QImode))
    return -1;
  return 0;
}

static int
pattern221 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], E_VNx64BImode)
      || GET_MODE (x1) != E_VNx64BImode)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != E_VNx64QImode
      || !register_operand (operands[1], E_VNx64QImode)
      || !register_operand (operands[2], E_VNx64QImode))
    return -1;
  return 0;
}

static int
pattern222 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!vector_mask_operand (operands[1], i2)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern223 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], E_VNx8QImode)
      || GET_MODE (x1) != E_VNx8QImode)
    return -1;
  x2 = XVECEXP (x1, 0, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != E_QImode
      || !register_operand (operands[4], E_VNx8QImode)
      || !vector_merge_operand (operands[2], E_VNx8QImode))
    return -1;
  x5 = XVECEXP (x1, 0, 0);
  switch (GET_MODE (x5))
    {
    case E_VNx1BImode:
      return pattern222 (x2, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2BImode:
      if (pattern222 (x2, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4BImode:
      if (pattern222 (x2, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8BImode:
      if (pattern222 (x2, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16BImode:
      if (pattern222 (x2, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32BImode:
      if (pattern222 (x2, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx64BImode:
      if (pattern222 (x2, E_VNx64QImode, E_VNx64BImode) != 0)
        return -1;
      return 6;

    default:
      return -1;
    }
}

static int
pattern224 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], E_VNx4HImode)
      || GET_MODE (x1) != E_VNx4HImode)
    return -1;
  x2 = XVECEXP (x1, 0, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != E_HImode
      || !register_operand (operands[4], E_VNx4HImode)
      || !vector_merge_operand (operands[2], E_VNx4HImode))
    return -1;
  x5 = XVECEXP (x1, 0, 0);
  switch (GET_MODE (x5))
    {
    case E_VNx1BImode:
      return pattern222 (x2, E_VNx1HImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2BImode:
      if (pattern222 (x2, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4BImode:
      if (pattern222 (x2, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8BImode:
      if (pattern222 (x2, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16BImode:
      if (pattern222 (x2, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32BImode:
      if (pattern222 (x2, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    default:
      return -1;
    }
}

static int
pattern225 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3, machine_mode i4, machine_mode i5)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[4], i2)
      || !vector_merge_operand (operands[2], i2))
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  switch (GET_MODE (x2))
    {
    case E_VNx1BImode:
      x3 = XVECEXP (x1, 0, 1);
      return pattern222 (x3, i1, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2BImode:
      x3 = XVECEXP (x1, 0, 1);
      if (pattern222 (x3, i2, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4BImode:
      x3 = XVECEXP (x1, 0, 1);
      if (pattern222 (x3, i3, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8BImode:
      x3 = XVECEXP (x1, 0, 1);
      if (pattern222 (x3, i4, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16BImode:
      x3 = XVECEXP (x1, 0, 1);
      if (pattern222 (x3, i5, E_VNx16BImode) != 0)
        return -1;
      return 4;

    default:
      return -1;
    }
}

static int
pattern226 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], E_VNx2SImode)
      || GET_MODE (x1) != E_VNx2SImode)
    return -1;
  x2 = XVECEXP (x1, 0, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != E_SImode)
    return -1;
  return pattern225 (x1, E_VNx1SImode, E_VNx2SImode, E_VNx4SImode, E_VNx8SImode, E_VNx16SImode); /* [-1, 4] */
}

static int
pattern227 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3, machine_mode i4, machine_mode i5)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XVECEXP (x1, 0, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i5
      || !register_operand (operands[4], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  x5 = XVECEXP (x1, 0, 0);
  switch (GET_MODE (x5))
    {
    case E_VNx1BImode:
      return pattern222 (x2, i1, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2BImode:
      if (pattern222 (x2, i2, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4BImode:
      if (pattern222 (x2, i3, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8BImode:
      if (pattern222 (x2, i4, E_VNx8BImode) != 0)
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern228 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], E_VNx4QImode)
      || GET_MODE (x1) != E_VNx4QImode)
    return -1;
  x2 = XVECEXP (x1, 0, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != E_QImode
      || !register_operand (operands[4], E_VNx4QImode)
      || !vector_merge_operand (operands[2], E_VNx4QImode))
    return -1;
  x5 = XVECEXP (x1, 0, 0);
  switch (GET_MODE (x5))
    {
    case E_VNx1BImode:
      return pattern222 (x2, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2BImode:
      if (pattern222 (x2, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4BImode:
      if (pattern222 (x2, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8BImode:
      if (pattern222 (x2, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16BImode:
      if (pattern222 (x2, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32BImode:
      if (pattern222 (x2, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    default:
      return -1;
    }
}

static int
pattern229 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], E_VNx2HImode)
      || GET_MODE (x1) != E_VNx2HImode)
    return -1;
  x2 = XVECEXP (x1, 0, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != E_HImode)
    return -1;
  return pattern225 (x1, E_VNx1HImode, E_VNx2HImode, E_VNx4HImode, E_VNx8HImode, E_VNx16HImode); /* [-1, 4] */
}

static int
pattern230 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 1);
  x3 = XEXP (x2, 0);
  if (GET_CODE (x3) != VEC_DUPLICATE)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_CODE (x4) != VEC_SELECT)
    return -1;
  x5 = XEXP (x4, 1);
  if (GET_CODE (x5) != PARALLEL
      || XVECLEN (x5, 0) != 1)
    return -1;
  x6 = XVECEXP (x5, 0, 0);
  if (x6 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
    return -1;
  x7 = XEXP (x4, 0);
  operands[4] = x7;
  x8 = XEXP (x2, 1);
  operands[3] = x8;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx8QImode:
      return pattern223 (x1); /* [-1, 6] */

    case E_VNx4HImode:
      res = pattern224 (x1);
      if (res >= 0)
        return res + 7; /* [7, 12] */
      return -1;

    case E_VNx2SImode:
      res = pattern226 (x1);
      if (res >= 0)
        return res + 13; /* [13, 17] */
      return -1;

    case E_VNx1DImode:
      res = pattern227 (x1, E_VNx1DImode, E_VNx2DImode, E_VNx4DImode, E_VNx8DImode, E_DImode);
      if (res >= 0)
        return res + 18; /* [18, 21] */
      return -1;

    case E_VNx4QImode:
      res = pattern228 (x1);
      if (res >= 0)
        return res + 22; /* [22, 27] */
      return -1;

    case E_VNx2HImode:
      res = pattern229 (x1);
      if (res >= 0)
        return res + 28; /* [28, 32] */
      return -1;

    case E_VNx1SImode:
      res = pattern227 (x1, E_VNx1SImode, E_VNx2SImode, E_VNx4SImode, E_VNx8SImode, E_SImode);
      if (res >= 0)
        return res + 33; /* [33, 36] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern231 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 1);
  x3 = XEXP (x2, 0);
  if (GET_CODE (x3) != VEC_DUPLICATE)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_CODE (x4) != VEC_SELECT)
    return -1;
  x5 = XEXP (x4, 1);
  if (GET_CODE (x5) != PARALLEL
      || XVECLEN (x5, 0) != 1)
    return -1;
  x6 = XVECEXP (x5, 0, 0);
  if (x6 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
    return -1;
  x7 = XEXP (x4, 0);
  operands[4] = x7;
  x8 = XEXP (x2, 1);
  operands[3] = x8;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx8QImode:
      return pattern223 (x1); /* [-1, 6] */

    case E_VNx4HImode:
      res = pattern224 (x1);
      if (res >= 0)
        return res + 7; /* [7, 12] */
      return -1;

    case E_VNx2SImode:
      res = pattern226 (x1);
      if (res >= 0)
        return res + 13; /* [13, 17] */
      return -1;

    case E_VNx1DImode:
      res = pattern227 (x1, E_VNx1DImode, E_VNx2DImode, E_VNx4DImode, E_VNx8DImode, E_DImode);
      if (res >= 0)
        return res + 18; /* [18, 21] */
      return -1;

    case E_VNx4QImode:
      res = pattern228 (x1);
      if (res >= 0)
        return res + 22; /* [22, 27] */
      return -1;

    case E_VNx2HImode:
      res = pattern229 (x1);
      if (res >= 0)
        return res + 28; /* [28, 32] */
      return -1;

    case E_VNx1SImode:
      res = pattern227 (x1, E_VNx1SImode, E_VNx2SImode, E_VNx4SImode, E_VNx8SImode, E_SImode);
      if (res >= 0)
        return res + 33; /* [33, 36] */
      return -1;

    case E_VNx2SFmode:
      if (!register_operand (operands[0], E_VNx2SFmode)
          || GET_MODE (x1) != E_VNx2SFmode
          || GET_MODE (x4) != E_SFmode)
        return -1;
      res = pattern225 (x1, E_VNx1SFmode, E_VNx2SFmode, E_VNx4SFmode, E_VNx8SFmode, E_VNx16SFmode);
      if (res >= 0)
        return res + 37; /* [37, 41] */
      return -1;

    case E_VNx1DFmode:
      res = pattern227 (x1, E_VNx1DFmode, E_VNx2DFmode, E_VNx4DFmode, E_VNx8DFmode, E_DFmode);
      if (res >= 0)
        return res + 42; /* [42, 45] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern232 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!memory_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern233 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_all_trues_mask_operand (operands[1], i1))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1)
      || !vector_undef_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern234 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1
      || !register_operand (operands[3], i1))
    return -1;
  x2 = XVECEXP (x1, 0, 2);
  if (GET_MODE (x2) != i1)
    return -1;
  return 0;
}

static int
pattern235 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_MODE (x2) != i2
      || !register_operand (operands[3], i2)
      || !register_operand (operands[2], i1)
      || !vector_merge_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern236 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[2], i1)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern237 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[2], i3)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern238 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_broadcast_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !direct_broadcast_operand (operands[3], i3)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern239 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1)
      || !register_operand (operands[4], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern240 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XVECEXP (x3, 0, 0);
  if (GET_MODE (x4) != i1
      || !reg_or_0_operand (operands[4], i3)
      || !register_operand (operands[3], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern241 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XVECEXP (x3, 0, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[3], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern242 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  switch (GET_CODE (x3))
    {
    case REG:
    case SUBREG:
      operands[3] = x3;
      x4 = XVECEXP (x2, 0, 1);
      operands[4] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          return pattern239 (x1, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

        case E_VNx2QImode:
          if (pattern239 (x1, E_VNx2QImode, E_VNx2BImode) != 0)
            return -1;
          return 1;

        case E_VNx4QImode:
          if (pattern239 (x1, E_VNx4QImode, E_VNx4BImode) != 0)
            return -1;
          return 2;

        case E_VNx8QImode:
          if (pattern239 (x1, E_VNx8QImode, E_VNx8BImode) != 0)
            return -1;
          return 3;

        case E_VNx16QImode:
          if (pattern239 (x1, E_VNx16QImode, E_VNx16BImode) != 0)
            return -1;
          return 4;

        case E_VNx32QImode:
          if (pattern239 (x1, E_VNx32QImode, E_VNx32BImode) != 0)
            return -1;
          return 5;

        case E_VNx64QImode:
          if (pattern239 (x1, E_VNx64QImode, E_VNx64BImode) != 0)
            return -1;
          return 6;

        case E_VNx1HImode:
          if (pattern239 (x1, E_VNx1HImode, E_VNx1BImode) != 0)
            return -1;
          return 7;

        case E_VNx2HImode:
          if (pattern239 (x1, E_VNx2HImode, E_VNx2BImode) != 0)
            return -1;
          return 8;

        case E_VNx4HImode:
          if (pattern239 (x1, E_VNx4HImode, E_VNx4BImode) != 0)
            return -1;
          return 9;

        case E_VNx8HImode:
          if (pattern239 (x1, E_VNx8HImode, E_VNx8BImode) != 0)
            return -1;
          return 10;

        case E_VNx16HImode:
          if (pattern239 (x1, E_VNx16HImode, E_VNx16BImode) != 0)
            return -1;
          return 11;

        case E_VNx32HImode:
          if (pattern239 (x1, E_VNx32HImode, E_VNx32BImode) != 0)
            return -1;
          return 12;

        case E_VNx1SImode:
          if (pattern239 (x1, E_VNx1SImode, E_VNx1BImode) != 0)
            return -1;
          return 13;

        case E_VNx2SImode:
          if (pattern239 (x1, E_VNx2SImode, E_VNx2BImode) != 0)
            return -1;
          return 14;

        case E_VNx4SImode:
          if (pattern239 (x1, E_VNx4SImode, E_VNx4BImode) != 0)
            return -1;
          return 15;

        case E_VNx8SImode:
          if (pattern239 (x1, E_VNx8SImode, E_VNx8BImode) != 0)
            return -1;
          return 16;

        case E_VNx16SImode:
          if (pattern239 (x1, E_VNx16SImode, E_VNx16BImode) != 0)
            return -1;
          return 17;

        case E_VNx1DImode:
          if (pattern239 (x1, E_VNx1DImode, E_VNx1BImode) != 0)
            return -1;
          return 18;

        case E_VNx2DImode:
          if (pattern239 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
            return -1;
          return 19;

        case E_VNx4DImode:
          if (pattern239 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
            return -1;
          return 20;

        case E_VNx8DImode:
          if (pattern239 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
            return -1;
          return 21;

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x4 = XVECEXP (x2, 0, 1);
      operands[3] = x4;
      x5 = XEXP (x3, 0);
      switch (GET_CODE (x5))
        {
        case CONST_INT:
        case CONST_WIDE_INT:
        case CONST_VECTOR:
        case REG:
        case SUBREG:
          operands[4] = x5;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1QImode:
              if (pattern240 (x1, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0)
                return -1;
              return 22;

            case E_VNx2QImode:
              if (pattern240 (x1, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
                return -1;
              return 23;

            case E_VNx4QImode:
              if (pattern240 (x1, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
                return -1;
              return 24;

            case E_VNx8QImode:
              if (pattern240 (x1, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
                return -1;
              return 25;

            case E_VNx16QImode:
              if (pattern240 (x1, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
                return -1;
              return 26;

            case E_VNx32QImode:
              if (pattern240 (x1, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
                return -1;
              return 27;

            case E_VNx64QImode:
              if (pattern240 (x1, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0)
                return -1;
              return 28;

            case E_VNx1HImode:
              if (pattern240 (x1, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
                return -1;
              return 29;

            case E_VNx2HImode:
              if (pattern240 (x1, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
                return -1;
              return 30;

            case E_VNx4HImode:
              if (pattern240 (x1, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
                return -1;
              return 31;

            case E_VNx8HImode:
              if (pattern240 (x1, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
                return -1;
              return 32;

            case E_VNx16HImode:
              if (pattern240 (x1, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
                return -1;
              return 33;

            case E_VNx32HImode:
              if (pattern240 (x1, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0)
                return -1;
              return 34;

            case E_VNx1SImode:
              if (pattern240 (x1, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
                return -1;
              return 35;

            case E_VNx2SImode:
              if (pattern240 (x1, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
                return -1;
              return 36;

            case E_VNx4SImode:
              if (pattern240 (x1, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
                return -1;
              return 37;

            case E_VNx8SImode:
              if (pattern240 (x1, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
                return -1;
              return 38;

            case E_VNx16SImode:
              if (pattern240 (x1, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0)
                return -1;
              return 39;

            case E_VNx1DImode:
              if (pattern240 (x1, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0)
                return -1;
              return 40;

            case E_VNx2DImode:
              if (pattern240 (x1, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0)
                return -1;
              return 41;

            case E_VNx4DImode:
              if (pattern240 (x1, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0)
                return -1;
              return 42;

            case E_VNx8DImode:
              if (pattern240 (x1, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0)
                return -1;
              return 43;

            default:
              return -1;
            }

        case SIGN_EXTEND:
          if (GET_MODE (x5) != E_DImode)
            return -1;
          x6 = XEXP (x5, 0);
          operands[4] = x6;
          if (!reg_or_0_operand (operands[4], E_SImode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1DImode:
              if (pattern241 (x1, E_VNx1DImode, E_VNx1BImode) != 0)
                return -1;
              return 44;

            case E_VNx2DImode:
              if (pattern241 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
                return -1;
              return 45;

            case E_VNx4DImode:
              if (pattern241 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
                return -1;
              return 46;

            case E_VNx8DImode:
              if (pattern241 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
                return -1;
              return 47;

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern243 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern244 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 1);
  operands[4] = x3;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      return pattern243 (x1, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2QImode:
      if (pattern243 (x1, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4QImode:
      if (pattern243 (x1, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8QImode:
      if (pattern243 (x1, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16QImode:
      if (pattern243 (x1, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32QImode:
      if (pattern243 (x1, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx64QImode:
      if (pattern243 (x1, E_VNx64QImode, E_VNx64BImode) != 0)
        return -1;
      return 6;

    case E_VNx1HImode:
      if (pattern243 (x1, E_VNx1HImode, E_VNx1BImode) != 0)
        return -1;
      return 7;

    case E_VNx2HImode:
      if (pattern243 (x1, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      return 8;

    case E_VNx4HImode:
      if (pattern243 (x1, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      return 9;

    case E_VNx8HImode:
      if (pattern243 (x1, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      return 10;

    case E_VNx16HImode:
      if (pattern243 (x1, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      return 11;

    case E_VNx32HImode:
      if (pattern243 (x1, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      return 12;

    case E_VNx1SImode:
      if (pattern243 (x1, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      return 13;

    case E_VNx2SImode:
      if (pattern243 (x1, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      return 14;

    case E_VNx4SImode:
      if (pattern243 (x1, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      return 15;

    case E_VNx8SImode:
      if (pattern243 (x1, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      return 16;

    case E_VNx16SImode:
      if (pattern243 (x1, E_VNx16SImode, E_VNx16BImode) != 0)
        return -1;
      return 17;

    case E_VNx1DImode:
      if (pattern243 (x1, E_VNx1DImode, E_VNx1BImode) != 0)
        return -1;
      return 18;

    case E_VNx2DImode:
      if (pattern243 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      return 19;

    case E_VNx4DImode:
      if (pattern243 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      return 20;

    case E_VNx8DImode:
      if (pattern243 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      return 21;

    default:
      return -1;
    }
}

static int
pattern245 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  operands[3] = x3;
  x4 = XVECEXP (x2, 0, 1);
  switch (GET_CODE (x4))
    {
    case CONST_INT:
    case CONST_WIDE_INT:
    case CONST_VECTOR:
    case REG:
    case SUBREG:
      return pattern244 (x1); /* [-1, 21] */

    case SIGN_EXTEND:
      if (GET_MODE (x4) != E_DImode)
        return -1;
      x5 = XEXP (x4, 0);
      operands[4] = x5;
      if (!reg_or_0_operand (operands[4], E_SImode))
        return -1;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1DImode:
          if (pattern243 (x1, E_VNx1DImode, E_VNx1BImode) != 0)
            return -1;
          return 22;

        case E_VNx2DImode:
          if (pattern243 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
            return -1;
          return 23;

        case E_VNx4DImode:
          if (pattern243 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
            return -1;
          return 24;

        case E_VNx8DImode:
          if (pattern243 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
            return -1;
          return 25;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern246 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i2)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern247 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  operands[3] = x3;
  x4 = XVECEXP (x2, 0, 1);
  operands[4] = x4;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      return pattern246 (x1, E_VNx1QImode, E_VNx1HImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2QImode:
      if (pattern246 (x1, E_VNx2QImode, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4QImode:
      if (pattern246 (x1, E_VNx4QImode, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8QImode:
      if (pattern246 (x1, E_VNx8QImode, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16QImode:
      if (pattern246 (x1, E_VNx16QImode, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32QImode:
      if (pattern246 (x1, E_VNx32QImode, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx1HImode:
      if (pattern246 (x1, E_VNx1HImode, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      return 6;

    case E_VNx2HImode:
      if (pattern246 (x1, E_VNx2HImode, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      return 7;

    case E_VNx4HImode:
      if (pattern246 (x1, E_VNx4HImode, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      return 8;

    case E_VNx8HImode:
      if (pattern246 (x1, E_VNx8HImode, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      return 9;

    case E_VNx16HImode:
      if (pattern246 (x1, E_VNx16HImode, E_VNx16SImode, E_VNx16BImode) != 0)
        return -1;
      return 10;

    case E_VNx1SImode:
      if (pattern246 (x1, E_VNx1SImode, E_VNx1DImode, E_VNx1BImode) != 0)
        return -1;
      return 11;

    case E_VNx2SImode:
      if (pattern246 (x1, E_VNx2SImode, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      return 12;

    case E_VNx4SImode:
      if (pattern246 (x1, E_VNx4SImode, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      return 13;

    case E_VNx8SImode:
      if (pattern246 (x1, E_VNx8SImode, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      return 14;

    default:
      return -1;
    }
}

static int
pattern248 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1))
    return -1;
  x4 = XVECEXP (x3, 0, 1);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[4], i3)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern249 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  operands[3] = x3;
  x4 = XVECEXP (x2, 0, 1);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      operands[4] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1SFmode:
          return pattern239 (x1, E_VNx1SFmode, E_VNx1BImode); /* [-1, 0] */

        case E_VNx2SFmode:
          if (pattern239 (x1, E_VNx2SFmode, E_VNx2BImode) != 0)
            return -1;
          return 1;

        case E_VNx4SFmode:
          if (pattern239 (x1, E_VNx4SFmode, E_VNx4BImode) != 0)
            return -1;
          return 2;

        case E_VNx8SFmode:
          if (pattern239 (x1, E_VNx8SFmode, E_VNx8BImode) != 0)
            return -1;
          return 3;

        case E_VNx16SFmode:
          if (pattern239 (x1, E_VNx16SFmode, E_VNx16BImode) != 0)
            return -1;
          return 4;

        case E_VNx1DFmode:
          if (pattern239 (x1, E_VNx1DFmode, E_VNx1BImode) != 0)
            return -1;
          return 5;

        case E_VNx2DFmode:
          if (pattern239 (x1, E_VNx2DFmode, E_VNx2BImode) != 0)
            return -1;
          return 6;

        case E_VNx4DFmode:
          if (pattern239 (x1, E_VNx4DFmode, E_VNx4BImode) != 0)
            return -1;
          return 7;

        case E_VNx8DFmode:
          if (pattern239 (x1, E_VNx8DFmode, E_VNx8BImode) != 0)
            return -1;
          return 8;

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x5 = XEXP (x4, 0);
      operands[4] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1SFmode:
          if (pattern248 (x1, E_VNx1SFmode, E_VNx1BImode, E_SFmode) != 0)
            return -1;
          return 9;

        case E_VNx2SFmode:
          if (pattern248 (x1, E_VNx2SFmode, E_VNx2BImode, E_SFmode) != 0)
            return -1;
          return 10;

        case E_VNx4SFmode:
          if (pattern248 (x1, E_VNx4SFmode, E_VNx4BImode, E_SFmode) != 0)
            return -1;
          return 11;

        case E_VNx8SFmode:
          if (pattern248 (x1, E_VNx8SFmode, E_VNx8BImode, E_SFmode) != 0)
            return -1;
          return 12;

        case E_VNx16SFmode:
          if (pattern248 (x1, E_VNx16SFmode, E_VNx16BImode, E_SFmode) != 0)
            return -1;
          return 13;

        case E_VNx1DFmode:
          if (pattern248 (x1, E_VNx1DFmode, E_VNx1BImode, E_DFmode) != 0)
            return -1;
          return 14;

        case E_VNx2DFmode:
          if (pattern248 (x1, E_VNx2DFmode, E_VNx2BImode, E_DFmode) != 0)
            return -1;
          return 15;

        case E_VNx4DFmode:
          if (pattern248 (x1, E_VNx4DFmode, E_VNx4BImode, E_DFmode) != 0)
            return -1;
          return 16;

        case E_VNx8DFmode:
          if (pattern248 (x1, E_VNx8DFmode, E_VNx8BImode, E_DFmode) != 0)
            return -1;
          return 17;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern250 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  operands[3] = x3;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1SFmode:
      return pattern243 (x1, E_VNx1SFmode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2SFmode:
      if (pattern243 (x1, E_VNx2SFmode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4SFmode:
      if (pattern243 (x1, E_VNx4SFmode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8SFmode:
      if (pattern243 (x1, E_VNx8SFmode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16SFmode:
      if (pattern243 (x1, E_VNx16SFmode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx1DFmode:
      if (pattern243 (x1, E_VNx1DFmode, E_VNx1BImode) != 0)
        return -1;
      return 5;

    case E_VNx2DFmode:
      if (pattern243 (x1, E_VNx2DFmode, E_VNx2BImode) != 0)
        return -1;
      return 6;

    case E_VNx4DFmode:
      if (pattern243 (x1, E_VNx4DFmode, E_VNx4BImode) != 0)
        return -1;
      return 7;

    case E_VNx8DFmode:
      if (pattern243 (x1, E_VNx8DFmode, E_VNx8BImode) != 0)
        return -1;
      return 8;

    default:
      return -1;
    }
}

static int
pattern251 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  operands[3] = x3;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1SImode:
      if (!register_operand (operands[0], E_VNx1SImode)
          || GET_MODE (x1) != E_VNx1SImode)
        return -1;
      x4 = XEXP (x1, 0);
      if (GET_MODE (x4) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode)
          || GET_MODE (x2) != E_VNx1SImode
          || !vector_merge_operand (operands[2], E_VNx1SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx1SFmode:
          if (!register_operand (operands[3], E_VNx1SFmode))
            return -1;
          return 0;

        case E_VNx1DFmode:
          if (!register_operand (operands[3], E_VNx1DFmode))
            return -1;
          return 1;

        default:
          return -1;
        }

    case E_VNx2SImode:
      if (!register_operand (operands[0], E_VNx2SImode)
          || GET_MODE (x1) != E_VNx2SImode)
        return -1;
      x4 = XEXP (x1, 0);
      if (GET_MODE (x4) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode)
          || GET_MODE (x2) != E_VNx2SImode
          || !vector_merge_operand (operands[2], E_VNx2SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx2SFmode:
          if (!register_operand (operands[3], E_VNx2SFmode))
            return -1;
          return 2;

        case E_VNx2DFmode:
          if (!register_operand (operands[3], E_VNx2DFmode))
            return -1;
          return 3;

        default:
          return -1;
        }

    case E_VNx4SImode:
      if (!register_operand (operands[0], E_VNx4SImode)
          || GET_MODE (x1) != E_VNx4SImode)
        return -1;
      x4 = XEXP (x1, 0);
      if (GET_MODE (x4) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode)
          || GET_MODE (x2) != E_VNx4SImode
          || !vector_merge_operand (operands[2], E_VNx4SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx4SFmode:
          if (!register_operand (operands[3], E_VNx4SFmode))
            return -1;
          return 4;

        case E_VNx4DFmode:
          if (!register_operand (operands[3], E_VNx4DFmode))
            return -1;
          return 5;

        default:
          return -1;
        }

    case E_VNx8SImode:
      if (!register_operand (operands[0], E_VNx8SImode)
          || GET_MODE (x1) != E_VNx8SImode)
        return -1;
      x4 = XEXP (x1, 0);
      if (GET_MODE (x4) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode)
          || GET_MODE (x2) != E_VNx8SImode
          || !vector_merge_operand (operands[2], E_VNx8SImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx8SFmode:
          if (!register_operand (operands[3], E_VNx8SFmode))
            return -1;
          return 6;

        case E_VNx8DFmode:
          if (!register_operand (operands[3], E_VNx8DFmode))
            return -1;
          return 7;

        default:
          return -1;
        }

    case E_VNx16SImode:
      if (pattern246 (x1, E_VNx16SImode, E_VNx16SFmode, E_VNx16BImode) != 0)
        return -1;
      return 8;

    case E_VNx1DImode:
      if (!register_operand (operands[0], E_VNx1DImode)
          || GET_MODE (x1) != E_VNx1DImode)
        return -1;
      x4 = XEXP (x1, 0);
      if (GET_MODE (x4) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode)
          || GET_MODE (x2) != E_VNx1DImode
          || !vector_merge_operand (operands[2], E_VNx1DImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx1DFmode:
          if (!register_operand (operands[3], E_VNx1DFmode))
            return -1;
          return 9;

        case E_VNx1SFmode:
          if (!register_operand (operands[3], E_VNx1SFmode))
            return -1;
          return 10;

        default:
          return -1;
        }

    case E_VNx2DImode:
      if (!register_operand (operands[0], E_VNx2DImode)
          || GET_MODE (x1) != E_VNx2DImode)
        return -1;
      x4 = XEXP (x1, 0);
      if (GET_MODE (x4) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode)
          || GET_MODE (x2) != E_VNx2DImode
          || !vector_merge_operand (operands[2], E_VNx2DImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx2DFmode:
          if (!register_operand (operands[3], E_VNx2DFmode))
            return -1;
          return 11;

        case E_VNx2SFmode:
          if (!register_operand (operands[3], E_VNx2SFmode))
            return -1;
          return 12;

        default:
          return -1;
        }

    case E_VNx4DImode:
      if (!register_operand (operands[0], E_VNx4DImode)
          || GET_MODE (x1) != E_VNx4DImode)
        return -1;
      x4 = XEXP (x1, 0);
      if (GET_MODE (x4) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode)
          || GET_MODE (x2) != E_VNx4DImode
          || !vector_merge_operand (operands[2], E_VNx4DImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx4DFmode:
          if (!register_operand (operands[3], E_VNx4DFmode))
            return -1;
          return 13;

        case E_VNx4SFmode:
          if (!register_operand (operands[3], E_VNx4SFmode))
            return -1;
          return 14;

        default:
          return -1;
        }

    case E_VNx8DImode:
      if (!register_operand (operands[0], E_VNx8DImode)
          || GET_MODE (x1) != E_VNx8DImode)
        return -1;
      x4 = XEXP (x1, 0);
      if (GET_MODE (x4) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode)
          || GET_MODE (x2) != E_VNx8DImode
          || !vector_merge_operand (operands[2], E_VNx8DImode))
        return -1;
      switch (GET_MODE (operands[3]))
        {
        case E_VNx8DFmode:
          if (!register_operand (operands[3], E_VNx8DFmode))
            return -1;
          return 15;

        case E_VNx8SFmode:
          if (!register_operand (operands[3], E_VNx8SFmode))
            return -1;
          return 16;

        default:
          return -1;
        }

    case E_VNx1HImode:
      if (pattern246 (x1, E_VNx1HImode, E_VNx1SFmode, E_VNx1BImode) != 0)
        return -1;
      return 17;

    case E_VNx2HImode:
      if (pattern246 (x1, E_VNx2HImode, E_VNx2SFmode, E_VNx2BImode) != 0)
        return -1;
      return 18;

    case E_VNx4HImode:
      if (pattern246 (x1, E_VNx4HImode, E_VNx4SFmode, E_VNx4BImode) != 0)
        return -1;
      return 19;

    case E_VNx8HImode:
      if (pattern246 (x1, E_VNx8HImode, E_VNx8SFmode, E_VNx8BImode) != 0)
        return -1;
      return 20;

    case E_VNx16HImode:
      if (pattern246 (x1, E_VNx16HImode, E_VNx16SFmode, E_VNx16BImode) != 0)
        return -1;
      return 21;

    default:
      return -1;
    }
}

static int
pattern252 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 1);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[2], i1)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern253 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      operands[4] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          return pattern203 (x1, E_VNx1QImode, E_VNx1BImode, E_QImode); /* [-1, 0] */

        case E_VNx2QImode:
          if (pattern203 (x1, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
            return -1;
          return 1;

        case E_VNx4QImode:
          if (pattern203 (x1, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
            return -1;
          return 2;

        case E_VNx8QImode:
          if (pattern203 (x1, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
            return -1;
          return 3;

        case E_VNx16QImode:
          if (pattern203 (x1, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
            return -1;
          return 4;

        case E_VNx32QImode:
          if (pattern203 (x1, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
            return -1;
          return 5;

        case E_VNx64QImode:
          if (pattern203 (x1, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0)
            return -1;
          return 6;

        case E_VNx1HImode:
          if (pattern203 (x1, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
            return -1;
          return 7;

        case E_VNx2HImode:
          if (pattern203 (x1, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
            return -1;
          return 8;

        case E_VNx4HImode:
          if (pattern203 (x1, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
            return -1;
          return 9;

        case E_VNx8HImode:
          if (pattern203 (x1, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
            return -1;
          return 10;

        case E_VNx16HImode:
          if (pattern203 (x1, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
            return -1;
          return 11;

        case E_VNx32HImode:
          if (pattern203 (x1, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0)
            return -1;
          return 12;

        case E_VNx1SImode:
          if (pattern203 (x1, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
            return -1;
          return 13;

        case E_VNx2SImode:
          if (pattern203 (x1, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
            return -1;
          return 14;

        case E_VNx4SImode:
          if (pattern203 (x1, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
            return -1;
          return 15;

        case E_VNx8SImode:
          if (pattern203 (x1, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
            return -1;
          return 16;

        case E_VNx16SImode:
          if (pattern203 (x1, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0)
            return -1;
          return 17;

        case E_VNx1DImode:
          if (pattern203 (x1, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0)
            return -1;
          return 18;

        case E_VNx2DImode:
          if (pattern203 (x1, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0)
            return -1;
          return 19;

        case E_VNx4DImode:
          if (pattern203 (x1, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0)
            return -1;
          return 20;

        case E_VNx8DImode:
          if (pattern203 (x1, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0)
            return -1;
          return 21;

        default:
          return -1;
        }

    case SIGN_EXTEND:
      if (GET_MODE (x4) != E_DImode)
        return -1;
      x5 = XEXP (x4, 0);
      operands[4] = x5;
      if (!register_operand (operands[4], E_SImode))
        return -1;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1DImode:
          if (pattern161 (x1, E_VNx1DImode, E_VNx1BImode) != 0)
            return -1;
          return 22;

        case E_VNx2DImode:
          if (pattern161 (x1, E_VNx2DImode, E_VNx2BImode) != 0)
            return -1;
          return 23;

        case E_VNx4DImode:
          if (pattern161 (x1, E_VNx4DImode, E_VNx4BImode) != 0)
            return -1;
          return 24;

        case E_VNx8DImode:
          if (pattern161 (x1, E_VNx8DImode, E_VNx8BImode) != 0)
            return -1;
          return 25;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern254 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_mask_operand (operands[1], i1))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern255 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx1QImode:
      if (!register_operand (operands[1], E_VNx1QImode)
          || !vector_arith_operand (operands[2], E_VNx1QImode))
        return -1;
      return 0;

    case E_VNx1HImode:
      if (!register_operand (operands[1], E_VNx1HImode)
          || !vector_arith_operand (operands[2], E_VNx1HImode))
        return -1;
      return 1;

    case E_VNx1SImode:
      if (!register_operand (operands[1], E_VNx1SImode)
          || !vector_arith_operand (operands[2], E_VNx1SImode))
        return -1;
      return 2;

    case E_VNx1DImode:
      if (!register_operand (operands[1], E_VNx1DImode)
          || !vector_arith_operand (operands[2], E_VNx1DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern256 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx2QImode:
      if (!register_operand (operands[1], E_VNx2QImode)
          || !vector_arith_operand (operands[2], E_VNx2QImode))
        return -1;
      return 0;

    case E_VNx2HImode:
      if (!register_operand (operands[1], E_VNx2HImode)
          || !vector_arith_operand (operands[2], E_VNx2HImode))
        return -1;
      return 1;

    case E_VNx2SImode:
      if (!register_operand (operands[1], E_VNx2SImode)
          || !vector_arith_operand (operands[2], E_VNx2SImode))
        return -1;
      return 2;

    case E_VNx2DImode:
      if (!register_operand (operands[1], E_VNx2DImode)
          || !vector_arith_operand (operands[2], E_VNx2DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern257 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx4QImode:
      if (!register_operand (operands[1], E_VNx4QImode)
          || !vector_arith_operand (operands[2], E_VNx4QImode))
        return -1;
      return 0;

    case E_VNx4HImode:
      if (!register_operand (operands[1], E_VNx4HImode)
          || !vector_arith_operand (operands[2], E_VNx4HImode))
        return -1;
      return 1;

    case E_VNx4SImode:
      if (!register_operand (operands[1], E_VNx4SImode)
          || !vector_arith_operand (operands[2], E_VNx4SImode))
        return -1;
      return 2;

    case E_VNx4DImode:
      if (!register_operand (operands[1], E_VNx4DImode)
          || !vector_arith_operand (operands[2], E_VNx4DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern258 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx8QImode:
      if (!register_operand (operands[1], E_VNx8QImode)
          || !vector_arith_operand (operands[2], E_VNx8QImode))
        return -1;
      return 0;

    case E_VNx8HImode:
      if (!register_operand (operands[1], E_VNx8HImode)
          || !vector_arith_operand (operands[2], E_VNx8HImode))
        return -1;
      return 1;

    case E_VNx8SImode:
      if (!register_operand (operands[1], E_VNx8SImode)
          || !vector_arith_operand (operands[2], E_VNx8SImode))
        return -1;
      return 2;

    case E_VNx8DImode:
      if (!register_operand (operands[1], E_VNx8DImode)
          || !vector_arith_operand (operands[2], E_VNx8DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern259 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx16QImode:
      if (!register_operand (operands[1], E_VNx16QImode)
          || !vector_arith_operand (operands[2], E_VNx16QImode))
        return -1;
      return 0;

    case E_VNx16HImode:
      if (!register_operand (operands[1], E_VNx16HImode)
          || !vector_arith_operand (operands[2], E_VNx16HImode))
        return -1;
      return 1;

    case E_VNx16SImode:
      if (!register_operand (operands[1], E_VNx16SImode)
          || !vector_arith_operand (operands[2], E_VNx16SImode))
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern260 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx32QImode:
      if (!register_operand (operands[1], E_VNx32QImode)
          || !vector_arith_operand (operands[2], E_VNx32QImode))
        return -1;
      return 0;

    case E_VNx32HImode:
      if (!register_operand (operands[1], E_VNx32HImode)
          || !vector_arith_operand (operands[2], E_VNx32HImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern261 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx1QImode:
      if (!register_operand (operands[1], E_VNx1QImode)
          || !register_operand (operands[2], E_VNx1QImode))
        return -1;
      return 0;

    case E_VNx1HImode:
      if (!register_operand (operands[1], E_VNx1HImode)
          || !register_operand (operands[2], E_VNx1HImode))
        return -1;
      return 1;

    case E_VNx1SImode:
      if (!register_operand (operands[1], E_VNx1SImode)
          || !register_operand (operands[2], E_VNx1SImode))
        return -1;
      return 2;

    case E_VNx1DImode:
      if (!register_operand (operands[1], E_VNx1DImode)
          || !register_operand (operands[2], E_VNx1DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern262 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx2QImode:
      if (!register_operand (operands[1], E_VNx2QImode)
          || !register_operand (operands[2], E_VNx2QImode))
        return -1;
      return 0;

    case E_VNx2HImode:
      if (!register_operand (operands[1], E_VNx2HImode)
          || !register_operand (operands[2], E_VNx2HImode))
        return -1;
      return 1;

    case E_VNx2SImode:
      if (!register_operand (operands[1], E_VNx2SImode)
          || !register_operand (operands[2], E_VNx2SImode))
        return -1;
      return 2;

    case E_VNx2DImode:
      if (!register_operand (operands[1], E_VNx2DImode)
          || !register_operand (operands[2], E_VNx2DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern263 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx4QImode:
      if (!register_operand (operands[1], E_VNx4QImode)
          || !register_operand (operands[2], E_VNx4QImode))
        return -1;
      return 0;

    case E_VNx4HImode:
      if (!register_operand (operands[1], E_VNx4HImode)
          || !register_operand (operands[2], E_VNx4HImode))
        return -1;
      return 1;

    case E_VNx4SImode:
      if (!register_operand (operands[1], E_VNx4SImode)
          || !register_operand (operands[2], E_VNx4SImode))
        return -1;
      return 2;

    case E_VNx4DImode:
      if (!register_operand (operands[1], E_VNx4DImode)
          || !register_operand (operands[2], E_VNx4DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern264 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx8QImode:
      if (!register_operand (operands[1], E_VNx8QImode)
          || !register_operand (operands[2], E_VNx8QImode))
        return -1;
      return 0;

    case E_VNx8HImode:
      if (!register_operand (operands[1], E_VNx8HImode)
          || !register_operand (operands[2], E_VNx8HImode))
        return -1;
      return 1;

    case E_VNx8SImode:
      if (!register_operand (operands[1], E_VNx8SImode)
          || !register_operand (operands[2], E_VNx8SImode))
        return -1;
      return 2;

    case E_VNx8DImode:
      if (!register_operand (operands[1], E_VNx8DImode)
          || !register_operand (operands[2], E_VNx8DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern265 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx16QImode:
      if (!register_operand (operands[1], E_VNx16QImode)
          || !register_operand (operands[2], E_VNx16QImode))
        return -1;
      return 0;

    case E_VNx16HImode:
      if (!register_operand (operands[1], E_VNx16HImode)
          || !register_operand (operands[2], E_VNx16HImode))
        return -1;
      return 1;

    case E_VNx16SImode:
      if (!register_operand (operands[1], E_VNx16SImode)
          || !register_operand (operands[2], E_VNx16SImode))
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern266 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (x1))
    {
    case E_VNx32QImode:
      if (!register_operand (operands[1], E_VNx32QImode)
          || !register_operand (operands[2], E_VNx32QImode))
        return -1;
      return 0;

    case E_VNx32HImode:
      if (!register_operand (operands[1], E_VNx32HImode)
          || !register_operand (operands[2], E_VNx32HImode))
        return -1;
      return 1;

    default:
      return -1;
    }
}

static int
pattern267 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1))
    return -1;
  x4 = XEXP (x3, 1);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i2
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern268 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      operands[4] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1DFmode:
          return pattern203 (x1, E_VNx1DFmode, E_VNx1BImode, E_VNx1SFmode); /* [-1, 0] */

        case E_VNx2DFmode:
          if (pattern203 (x1, E_VNx2DFmode, E_VNx2BImode, E_VNx2SFmode) != 0)
            return -1;
          return 1;

        case E_VNx4DFmode:
          if (pattern203 (x1, E_VNx4DFmode, E_VNx4BImode, E_VNx4SFmode) != 0)
            return -1;
          return 2;

        case E_VNx8DFmode:
          if (pattern203 (x1, E_VNx8DFmode, E_VNx8BImode, E_VNx8SFmode) != 0)
            return -1;
          return 3;

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x5 = XEXP (x4, 0);
      operands[4] = x5;
      if (!register_operand (operands[4], E_SFmode))
        return -1;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1DFmode:
          if (pattern267 (x1, E_VNx1DFmode, E_VNx1SFmode, E_VNx1BImode) != 0)
            return -1;
          return 4;

        case E_VNx2DFmode:
          if (pattern267 (x1, E_VNx2DFmode, E_VNx2SFmode, E_VNx2BImode) != 0)
            return -1;
          return 5;

        case E_VNx4DFmode:
          if (pattern267 (x1, E_VNx4DFmode, E_VNx4SFmode, E_VNx4BImode) != 0)
            return -1;
          return 6;

        case E_VNx8DFmode:
          if (pattern267 (x1, E_VNx8DFmode, E_VNx8SFmode, E_VNx8BImode) != 0)
            return -1;
          return 7;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern269 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case CONST_INT:
    case CONST_WIDE_INT:
    case CONST_VECTOR:
    case REG:
    case SUBREG:
      operands[4] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          return pattern160 (x1, E_VNx1QImode, E_VNx1BImode, E_QImode); /* [-1, 0] */

        case E_VNx2QImode:
          if (pattern160 (x1, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
            return -1;
          return 1;

        case E_VNx4QImode:
          if (pattern160 (x1, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
            return -1;
          return 2;

        case E_VNx8QImode:
          if (pattern160 (x1, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
            return -1;
          return 3;

        case E_VNx16QImode:
          if (pattern160 (x1, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
            return -1;
          return 4;

        case E_VNx32QImode:
          if (pattern160 (x1, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
            return -1;
          return 5;

        case E_VNx64QImode:
          if (pattern160 (x1, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0)
            return -1;
          return 6;

        case E_VNx1HImode:
          if (pattern160 (x1, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
            return -1;
          return 7;

        case E_VNx2HImode:
          if (pattern160 (x1, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
            return -1;
          return 8;

        case E_VNx4HImode:
          if (pattern160 (x1, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
            return -1;
          return 9;

        case E_VNx8HImode:
          if (pattern160 (x1, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
            return -1;
          return 10;

        case E_VNx16HImode:
          if (pattern160 (x1, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
            return -1;
          return 11;

        case E_VNx32HImode:
          if (pattern160 (x1, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0)
            return -1;
          return 12;

        case E_VNx1SImode:
          if (pattern160 (x1, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
            return -1;
          return 13;

        case E_VNx2SImode:
          if (pattern160 (x1, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
            return -1;
          return 14;

        case E_VNx4SImode:
          if (pattern160 (x1, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
            return -1;
          return 15;

        case E_VNx8SImode:
          if (pattern160 (x1, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
            return -1;
          return 16;

        case E_VNx16SImode:
          if (pattern160 (x1, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0)
            return -1;
          return 17;

        case E_VNx1DImode:
          if (pattern160 (x1, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0)
            return -1;
          return 18;

        case E_VNx2DImode:
          if (pattern160 (x1, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0)
            return -1;
          return 19;

        case E_VNx4DImode:
          if (pattern160 (x1, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0)
            return -1;
          return 20;

        case E_VNx8DImode:
          if (pattern160 (x1, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0)
            return -1;
          return 21;

        case E_VNx1SFmode:
          if (pattern203 (x1, E_VNx1SFmode, E_VNx1BImode, E_SFmode) != 0)
            return -1;
          return 22;

        case E_VNx2SFmode:
          if (pattern203 (x1, E_VNx2SFmode, E_VNx2BImode, E_SFmode) != 0)
            return -1;
          return 23;

        case E_VNx4SFmode:
          if (pattern203 (x1, E_VNx4SFmode, E_VNx4BImode, E_SFmode) != 0)
            return -1;
          return 24;

        case E_VNx8SFmode:
          if (pattern203 (x1, E_VNx8SFmode, E_VNx8BImode, E_SFmode) != 0)
            return -1;
          return 25;

        case E_VNx16SFmode:
          if (pattern203 (x1, E_VNx16SFmode, E_VNx16BImode, E_SFmode) != 0)
            return -1;
          return 26;

        case E_VNx1DFmode:
          if (pattern203 (x1, E_VNx1DFmode, E_VNx1BImode, E_DFmode) != 0)
            return -1;
          return 27;

        case E_VNx2DFmode:
          if (pattern203 (x1, E_VNx2DFmode, E_VNx2BImode, E_DFmode) != 0)
            return -1;
          return 28;

        case E_VNx4DFmode:
          if (pattern203 (x1, E_VNx4DFmode, E_VNx4BImode, E_DFmode) != 0)
            return -1;
          return 29;

        case E_VNx8DFmode:
          if (pattern203 (x1, E_VNx8DFmode, E_VNx8BImode, E_DFmode) != 0)
            return -1;
          return 30;

        default:
          return -1;
        }

    case SIGN_EXTEND:
      res = pattern162 (x1);
      if (res >= 0)
        return res + 31; /* [31, 34] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern270 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 1);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[2], i3)
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern271 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern272 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_arith_operand (operands[3], i1)
      || !register_operand (operands[2], i1)
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern273 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_mask_operand (operands[1], i1)
      || !comparison_except_ltge_operator (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern274 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_mask_operand (operands[1], i1)
      || !ltge_operator (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern275 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1BImode:
      if (!register_operand (operands[0], E_VNx1BImode)
          || GET_MODE (x1) != E_VNx1BImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode)
          || !signed_order_operator (operands[3], E_VNx1BImode)
          || !vector_merge_operand (operands[2], E_VNx1BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx1SFmode:
          return 0;

        case E_VNx1DFmode:
          return 1;

        default:
          return -1;
        }

    case E_VNx2BImode:
      if (!register_operand (operands[0], E_VNx2BImode)
          || GET_MODE (x1) != E_VNx2BImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode)
          || !signed_order_operator (operands[3], E_VNx2BImode)
          || !vector_merge_operand (operands[2], E_VNx2BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx2SFmode:
          return 2;

        case E_VNx2DFmode:
          return 3;

        default:
          return -1;
        }

    case E_VNx4BImode:
      if (!register_operand (operands[0], E_VNx4BImode)
          || GET_MODE (x1) != E_VNx4BImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode)
          || !signed_order_operator (operands[3], E_VNx4BImode)
          || !vector_merge_operand (operands[2], E_VNx4BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx4SFmode:
          return 4;

        case E_VNx4DFmode:
          return 5;

        default:
          return -1;
        }

    case E_VNx8BImode:
      if (!register_operand (operands[0], E_VNx8BImode)
          || GET_MODE (x1) != E_VNx8BImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode)
          || !signed_order_operator (operands[3], E_VNx8BImode)
          || !vector_merge_operand (operands[2], E_VNx8BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx8SFmode:
          return 6;

        case E_VNx8DFmode:
          return 7;

        default:
          return -1;
        }

    case E_VNx16BImode:
      if (!register_operand (operands[0], E_VNx16BImode)
          || GET_MODE (x1) != E_VNx16BImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx16BImode
          || !vector_mask_operand (operands[1], E_VNx16BImode)
          || !signed_order_operator (operands[3], E_VNx16BImode))
        return -1;
      return 8;

    default:
      return -1;
    }
}

static int
pattern276 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i2)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern277 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern278 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1)
      || !vector_neg_arith_operand (operands[4], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern279 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[3], i3)
      || !register_operand (operands[2], i1)
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern280 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !memory_operand (operands[3], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern281 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[2], i1)
      || !register_operand (operands[3], i1)
      || !vector_arith_operand (operands[4], i1)
      || !register_operand (operands[5], i1))
    return -1;
  return 0;
}

static int
pattern282 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1)
    return -1;
  x6 = XEXP (x5, 0);
  if (GET_MODE (x6) != i1
      || !register_operand (operands[2], i3)
      || !register_operand (operands[3], i1)
      || !vector_arith_operand (operands[4], i1)
      || !register_operand (operands[5], i1))
    return -1;
  return 0;
}

static int
pattern283 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 0);
  x5 = XEXP (x4, 0);
  switch (GET_CODE (x5))
    {
    case REG:
    case SUBREG:
      operands[2] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1SFmode:
          return pattern281 (x1, E_VNx1SFmode, E_VNx1BImode); /* [-1, 0] */

        case E_VNx2SFmode:
          if (pattern281 (x1, E_VNx2SFmode, E_VNx2BImode) != 0)
            return -1;
          return 1;

        case E_VNx4SFmode:
          if (pattern281 (x1, E_VNx4SFmode, E_VNx4BImode) != 0)
            return -1;
          return 2;

        case E_VNx8SFmode:
          if (pattern281 (x1, E_VNx8SFmode, E_VNx8BImode) != 0)
            return -1;
          return 3;

        case E_VNx16SFmode:
          if (pattern281 (x1, E_VNx16SFmode, E_VNx16BImode) != 0)
            return -1;
          return 4;

        case E_VNx1DFmode:
          if (pattern281 (x1, E_VNx1DFmode, E_VNx1BImode) != 0)
            return -1;
          return 5;

        case E_VNx2DFmode:
          if (pattern281 (x1, E_VNx2DFmode, E_VNx2BImode) != 0)
            return -1;
          return 6;

        case E_VNx4DFmode:
          if (pattern281 (x1, E_VNx4DFmode, E_VNx4BImode) != 0)
            return -1;
          return 7;

        case E_VNx8DFmode:
          if (pattern281 (x1, E_VNx8DFmode, E_VNx8BImode) != 0)
            return -1;
          return 8;

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x6 = XEXP (x5, 0);
      operands[2] = x6;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1SFmode:
          if (pattern282 (x1, E_VNx1SFmode, E_VNx1BImode, E_SFmode) != 0)
            return -1;
          return 9;

        case E_VNx2SFmode:
          if (pattern282 (x1, E_VNx2SFmode, E_VNx2BImode, E_SFmode) != 0)
            return -1;
          return 10;

        case E_VNx4SFmode:
          if (pattern282 (x1, E_VNx4SFmode, E_VNx4BImode, E_SFmode) != 0)
            return -1;
          return 11;

        case E_VNx8SFmode:
          if (pattern282 (x1, E_VNx8SFmode, E_VNx8BImode, E_SFmode) != 0)
            return -1;
          return 12;

        case E_VNx16SFmode:
          if (pattern282 (x1, E_VNx16SFmode, E_VNx16BImode, E_SFmode) != 0)
            return -1;
          return 13;

        case E_VNx1DFmode:
          if (pattern282 (x1, E_VNx1DFmode, E_VNx1BImode, E_DFmode) != 0)
            return -1;
          return 14;

        case E_VNx2DFmode:
          if (pattern282 (x1, E_VNx2DFmode, E_VNx2BImode, E_DFmode) != 0)
            return -1;
          return 15;

        case E_VNx4DFmode:
          if (pattern282 (x1, E_VNx4DFmode, E_VNx4BImode, E_DFmode) != 0)
            return -1;
          return 16;

        case E_VNx8DFmode:
          if (pattern282 (x1, E_VNx8DFmode, E_VNx8BImode, E_DFmode) != 0)
            return -1;
          return 17;

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
pattern284 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_broadcast_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern285 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !register_operand (operands[3], i1)
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern286 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XVECEXP (x3, 0, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[3], i2)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern287 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_arith_operand (operands[3], i1)
      || !vector_neg_arith_operand (operands[4], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern288 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 1);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern289 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_mask_operand (operands[1], i1)
      || !comparison_except_eqge_operator (operands[3], i1))
    return -1;
  return 0;
}

static int
pattern290 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 1);
  x5 = XEXP (x4, 0);
  operands[4] = x5;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1HImode:
      return pattern200 (x1, E_VNx1HImode, E_VNx1QImode, E_VNx1BImode); /* [-1, 0] */

    case E_VNx2HImode:
      if (pattern200 (x1, E_VNx2HImode, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      return 1;

    case E_VNx4HImode:
      if (pattern200 (x1, E_VNx4HImode, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      return 2;

    case E_VNx8HImode:
      if (pattern200 (x1, E_VNx8HImode, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      return 3;

    case E_VNx16HImode:
      if (pattern200 (x1, E_VNx16HImode, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      return 4;

    case E_VNx32HImode:
      if (pattern200 (x1, E_VNx32HImode, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      return 5;

    case E_VNx1SImode:
      if (pattern200 (x1, E_VNx1SImode, E_VNx1HImode, E_VNx1BImode) != 0)
        return -1;
      return 6;

    case E_VNx2SImode:
      if (pattern200 (x1, E_VNx2SImode, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      return 7;

    case E_VNx4SImode:
      if (pattern200 (x1, E_VNx4SImode, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      return 8;

    case E_VNx8SImode:
      if (pattern200 (x1, E_VNx8SImode, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      return 9;

    case E_VNx16SImode:
      if (pattern200 (x1, E_VNx16SImode, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      return 10;

    case E_VNx1DImode:
      if (pattern200 (x1, E_VNx1DImode, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      return 11;

    case E_VNx2DImode:
      if (pattern200 (x1, E_VNx2DImode, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      return 12;

    case E_VNx4DImode:
      if (pattern200 (x1, E_VNx4DImode, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      return 13;

    case E_VNx8DImode:
      if (pattern200 (x1, E_VNx8DImode, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      return 14;

    default:
      return -1;
    }
}

static int
pattern291 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3, machine_mode i4)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i3
      || !vector_mask_operand (operands[1], i3))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1)
    return -1;
  x6 = XEXP (x5, 0);
  if (GET_MODE (x6) != i2
      || !register_operand (operands[3], i4))
    return -1;
  x7 = XEXP (x4, 1);
  if (GET_MODE (x7) != i1
      || !register_operand (operands[4], i2)
      || !register_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern292 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 1);
  x5 = XEXP (x4, 0);
  operands[4] = x5;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1HImode:
      return pattern291 (x1, E_VNx1HImode, E_VNx1QImode, E_VNx1BImode, E_QImode); /* [-1, 0] */

    case E_VNx2HImode:
      if (pattern291 (x1, E_VNx2HImode, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
        return -1;
      return 1;

    case E_VNx4HImode:
      if (pattern291 (x1, E_VNx4HImode, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
        return -1;
      return 2;

    case E_VNx8HImode:
      if (pattern291 (x1, E_VNx8HImode, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
        return -1;
      return 3;

    case E_VNx16HImode:
      if (pattern291 (x1, E_VNx16HImode, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
        return -1;
      return 4;

    case E_VNx32HImode:
      if (pattern291 (x1, E_VNx32HImode, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
        return -1;
      return 5;

    case E_VNx1SImode:
      if (pattern291 (x1, E_VNx1SImode, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
        return -1;
      return 6;

    case E_VNx2SImode:
      if (pattern291 (x1, E_VNx2SImode, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
        return -1;
      return 7;

    case E_VNx4SImode:
      if (pattern291 (x1, E_VNx4SImode, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
        return -1;
      return 8;

    case E_VNx8SImode:
      if (pattern291 (x1, E_VNx8SImode, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
        return -1;
      return 9;

    case E_VNx16SImode:
      if (pattern291 (x1, E_VNx16SImode, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
        return -1;
      return 10;

    case E_VNx1DImode:
      if (pattern291 (x1, E_VNx1DImode, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
        return -1;
      return 11;

    case E_VNx2DImode:
      if (pattern291 (x1, E_VNx2DImode, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
        return -1;
      return 12;

    case E_VNx4DImode:
      if (pattern291 (x1, E_VNx4DImode, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
        return -1;
      return 13;

    case E_VNx8DImode:
      if (pattern291 (x1, E_VNx8DImode, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
        return -1;
      return 14;

    default:
      return -1;
    }
}

static int
pattern293 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[2], i1)
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern294 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XVECEXP (x3, 0, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[2], i1)
      || !vector_arith_operand (operands[3], i1)
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern295 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XVECEXP (x3, 0, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[2], i1)
      || !register_operand (operands[3], i1)
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern296 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_mask_operand (operands[1], i1)
      || !equality_operator (operands[3], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern297 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[2], i1)
      || !register_operand (operands[3], i1)
      || !vector_arith_operand (operands[4], i1)
      || !register_operand (operands[5], i1))
    return -1;
  return 0;
}

static int
pattern298 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[2], i3)
      || !register_operand (operands[3], i1)
      || !vector_arith_operand (operands[4], i1)
      || !register_operand (operands[5], i1))
    return -1;
  return 0;
}

static int
pattern299 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XVECEXP (x3, 0, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[3], i3)
      || !register_operand (operands[2], i1)
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern300 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XVECEXP (x3, 0, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !reg_or_0_operand (operands[3], E_DImode)
      || !register_operand (operands[2], i1)
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern301 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XVECEXP (x3, 0, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[2], i1))
    return -1;
  x5 = XEXP (x4, 1);
  if (GET_MODE (x5) != i1
      || !reg_or_0_operand (operands[3], i3)
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern302 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_mask_operand (operands[1], i1)
      || !comparison_except_eqge_operator (operands[3], i1)
      || !register_operand (operands[4], i2))
    return -1;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 1);
  if (GET_MODE (x4) != i2
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern303 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_arith_operand (operands[4], i1))
    return -1;
  x4 = XEXP (x3, 1);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[2], i1)
      || !register_operand (operands[3], i1)
      || !register_operand (operands[5], i1))
    return -1;
  return 0;
}

static int
pattern304 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != E_VNx1BImode
      || !vector_mask_operand (operands[1], E_VNx1BImode))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_merge_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[4]))
    {
    case E_VNx1SImode:
      if (!register_operand (operands[4], E_VNx1SImode))
        return -1;
      return 0;

    case E_VNx1HImode:
      if (!register_operand (operands[4], E_VNx1HImode))
        return -1;
      return 1;

    case E_VNx1QImode:
      if (!register_operand (operands[4], E_VNx1QImode))
        return -1;
      return 2;

    case E_VNx1DImode:
      if (!register_operand (operands[4], E_VNx1DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern305 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != E_VNx2BImode
      || !vector_mask_operand (operands[1], E_VNx2BImode))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_merge_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[4]))
    {
    case E_VNx2SImode:
      if (!register_operand (operands[4], E_VNx2SImode))
        return -1;
      return 0;

    case E_VNx2HImode:
      if (!register_operand (operands[4], E_VNx2HImode))
        return -1;
      return 1;

    case E_VNx2QImode:
      if (!register_operand (operands[4], E_VNx2QImode))
        return -1;
      return 2;

    case E_VNx2DImode:
      if (!register_operand (operands[4], E_VNx2DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern306 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != E_VNx4BImode
      || !vector_mask_operand (operands[1], E_VNx4BImode))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_merge_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[4]))
    {
    case E_VNx4SImode:
      if (!register_operand (operands[4], E_VNx4SImode))
        return -1;
      return 0;

    case E_VNx4HImode:
      if (!register_operand (operands[4], E_VNx4HImode))
        return -1;
      return 1;

    case E_VNx4QImode:
      if (!register_operand (operands[4], E_VNx4QImode))
        return -1;
      return 2;

    case E_VNx4DImode:
      if (!register_operand (operands[4], E_VNx4DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern307 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != E_VNx8BImode
      || !vector_mask_operand (operands[1], E_VNx8BImode))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_merge_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[4]))
    {
    case E_VNx8SImode:
      if (!register_operand (operands[4], E_VNx8SImode))
        return -1;
      return 0;

    case E_VNx8HImode:
      if (!register_operand (operands[4], E_VNx8HImode))
        return -1;
      return 1;

    case E_VNx8QImode:
      if (!register_operand (operands[4], E_VNx8QImode))
        return -1;
      return 2;

    case E_VNx8DImode:
      if (!register_operand (operands[4], E_VNx8DImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern308 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != E_VNx16BImode
      || !vector_mask_operand (operands[1], E_VNx16BImode))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_merge_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[4]))
    {
    case E_VNx16SImode:
      if (!register_operand (operands[4], E_VNx16SImode))
        return -1;
      return 0;

    case E_VNx16HImode:
      if (!register_operand (operands[4], E_VNx16HImode))
        return -1;
      return 1;

    case E_VNx16QImode:
      if (!register_operand (operands[4], E_VNx16QImode))
        return -1;
      return 2;

    default:
      return -1;
    }
}

static int
pattern309 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != E_VNx1BImode
      || !vector_mask_operand (operands[1], E_VNx1BImode))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_merge_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[4]))
    {
    case E_VNx1DImode:
      if (!register_operand (operands[4], E_VNx1DImode))
        return -1;
      return 0;

    case E_VNx1SImode:
      if (!register_operand (operands[4], E_VNx1SImode))
        return -1;
      return 1;

    case E_VNx1HImode:
      if (!register_operand (operands[4], E_VNx1HImode))
        return -1;
      return 2;

    case E_VNx1QImode:
      if (!register_operand (operands[4], E_VNx1QImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern310 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != E_VNx2BImode
      || !vector_mask_operand (operands[1], E_VNx2BImode))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_merge_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[4]))
    {
    case E_VNx2DImode:
      if (!register_operand (operands[4], E_VNx2DImode))
        return -1;
      return 0;

    case E_VNx2SImode:
      if (!register_operand (operands[4], E_VNx2SImode))
        return -1;
      return 1;

    case E_VNx2HImode:
      if (!register_operand (operands[4], E_VNx2HImode))
        return -1;
      return 2;

    case E_VNx2QImode:
      if (!register_operand (operands[4], E_VNx2QImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern311 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != E_VNx4BImode
      || !vector_mask_operand (operands[1], E_VNx4BImode))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_merge_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[4]))
    {
    case E_VNx4DImode:
      if (!register_operand (operands[4], E_VNx4DImode))
        return -1;
      return 0;

    case E_VNx4SImode:
      if (!register_operand (operands[4], E_VNx4SImode))
        return -1;
      return 1;

    case E_VNx4HImode:
      if (!register_operand (operands[4], E_VNx4HImode))
        return -1;
      return 2;

    case E_VNx4QImode:
      if (!register_operand (operands[4], E_VNx4QImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern312 (rtx x1, machine_mode i1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != E_VNx8BImode
      || !vector_mask_operand (operands[1], E_VNx8BImode))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_merge_operand (operands[2], i1))
    return -1;
  switch (GET_MODE (operands[4]))
    {
    case E_VNx8DImode:
      if (!register_operand (operands[4], E_VNx8DImode))
        return -1;
      return 0;

    case E_VNx8SImode:
      if (!register_operand (operands[4], E_VNx8SImode))
        return -1;
      return 1;

    case E_VNx8HImode:
      if (!register_operand (operands[4], E_VNx8HImode))
        return -1;
      return 2;

    case E_VNx8QImode:
      if (!register_operand (operands[4], E_VNx8QImode))
        return -1;
      return 3;

    default:
      return -1;
    }
}

static int
pattern313 (rtx x1)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      if (!register_operand (operands[0], E_VNx1QImode)
          || GET_MODE (x1) != E_VNx1QImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx1QImode
          || !vector_merge_operand (operands[2], E_VNx1QImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx1QImode:
          if (!register_operand (operands[4], E_VNx1QImode))
            return -1;
          return 0;

        case E_VNx1HImode:
          if (!register_operand (operands[4], E_VNx1HImode))
            return -1;
          return 1;

        case E_VNx1SImode:
          if (!register_operand (operands[4], E_VNx1SImode))
            return -1;
          return 2;

        case E_VNx1DImode:
          if (!register_operand (operands[4], E_VNx1DImode))
            return -1;
          return 3;

        default:
          return -1;
        }

    case E_VNx2QImode:
      if (!register_operand (operands[0], E_VNx2QImode)
          || GET_MODE (x1) != E_VNx2QImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx2QImode
          || !vector_merge_operand (operands[2], E_VNx2QImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx2QImode:
          if (!register_operand (operands[4], E_VNx2QImode))
            return -1;
          return 4;

        case E_VNx2HImode:
          if (!register_operand (operands[4], E_VNx2HImode))
            return -1;
          return 5;

        case E_VNx2SImode:
          if (!register_operand (operands[4], E_VNx2SImode))
            return -1;
          return 6;

        case E_VNx2DImode:
          if (!register_operand (operands[4], E_VNx2DImode))
            return -1;
          return 7;

        default:
          return -1;
        }

    case E_VNx4QImode:
      if (!register_operand (operands[0], E_VNx4QImode)
          || GET_MODE (x1) != E_VNx4QImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx4QImode
          || !vector_merge_operand (operands[2], E_VNx4QImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx4QImode:
          if (!register_operand (operands[4], E_VNx4QImode))
            return -1;
          return 8;

        case E_VNx4HImode:
          if (!register_operand (operands[4], E_VNx4HImode))
            return -1;
          return 9;

        case E_VNx4SImode:
          if (!register_operand (operands[4], E_VNx4SImode))
            return -1;
          return 10;

        case E_VNx4DImode:
          if (!register_operand (operands[4], E_VNx4DImode))
            return -1;
          return 11;

        default:
          return -1;
        }

    case E_VNx8QImode:
      if (!register_operand (operands[0], E_VNx8QImode)
          || GET_MODE (x1) != E_VNx8QImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx8QImode
          || !vector_merge_operand (operands[2], E_VNx8QImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx8QImode:
          if (!register_operand (operands[4], E_VNx8QImode))
            return -1;
          return 12;

        case E_VNx8HImode:
          if (!register_operand (operands[4], E_VNx8HImode))
            return -1;
          return 13;

        case E_VNx8SImode:
          if (!register_operand (operands[4], E_VNx8SImode))
            return -1;
          return 14;

        case E_VNx8DImode:
          if (!register_operand (operands[4], E_VNx8DImode))
            return -1;
          return 15;

        default:
          return -1;
        }

    case E_VNx16QImode:
      if (!register_operand (operands[0], E_VNx16QImode)
          || GET_MODE (x1) != E_VNx16QImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx16BImode
          || !vector_mask_operand (operands[1], E_VNx16BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx16QImode
          || !vector_merge_operand (operands[2], E_VNx16QImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx16QImode:
          if (!register_operand (operands[4], E_VNx16QImode))
            return -1;
          return 16;

        case E_VNx16HImode:
          if (!register_operand (operands[4], E_VNx16HImode))
            return -1;
          return 17;

        case E_VNx16SImode:
          if (!register_operand (operands[4], E_VNx16SImode))
            return -1;
          return 18;

        default:
          return -1;
        }

    case E_VNx32QImode:
      if (!register_operand (operands[0], E_VNx32QImode)
          || GET_MODE (x1) != E_VNx32QImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx32BImode
          || !vector_mask_operand (operands[1], E_VNx32BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx32QImode
          || !vector_merge_operand (operands[2], E_VNx32QImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx32QImode:
          if (!register_operand (operands[4], E_VNx32QImode))
            return -1;
          return 19;

        case E_VNx32HImode:
          if (!register_operand (operands[4], E_VNx32HImode))
            return -1;
          return 20;

        default:
          return -1;
        }

    case E_VNx64QImode:
      if (!register_operand (operands[0], E_VNx64QImode)
          || GET_MODE (x1) != E_VNx64QImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx64BImode
          || !vector_mask_operand (operands[1], E_VNx64BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx64QImode
          || !register_operand (operands[4], E_VNx64QImode)
          || !vector_merge_operand (operands[2], E_VNx64QImode))
        return -1;
      return 21;

    case E_VNx1HImode:
      if (!register_operand (operands[0], E_VNx1HImode)
          || GET_MODE (x1) != E_VNx1HImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx1BImode
          || !vector_mask_operand (operands[1], E_VNx1BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx1HImode
          || !vector_merge_operand (operands[2], E_VNx1HImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx1HImode:
          if (!register_operand (operands[4], E_VNx1HImode))
            return -1;
          return 22;

        case E_VNx1QImode:
          if (!register_operand (operands[4], E_VNx1QImode))
            return -1;
          return 23;

        case E_VNx1SImode:
          if (!register_operand (operands[4], E_VNx1SImode))
            return -1;
          return 24;

        case E_VNx1DImode:
          if (!register_operand (operands[4], E_VNx1DImode))
            return -1;
          return 25;

        default:
          return -1;
        }

    case E_VNx2HImode:
      if (!register_operand (operands[0], E_VNx2HImode)
          || GET_MODE (x1) != E_VNx2HImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx2BImode
          || !vector_mask_operand (operands[1], E_VNx2BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx2HImode
          || !vector_merge_operand (operands[2], E_VNx2HImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx2HImode:
          if (!register_operand (operands[4], E_VNx2HImode))
            return -1;
          return 26;

        case E_VNx2QImode:
          if (!register_operand (operands[4], E_VNx2QImode))
            return -1;
          return 27;

        case E_VNx2SImode:
          if (!register_operand (operands[4], E_VNx2SImode))
            return -1;
          return 28;

        case E_VNx2DImode:
          if (!register_operand (operands[4], E_VNx2DImode))
            return -1;
          return 29;

        default:
          return -1;
        }

    case E_VNx4HImode:
      if (!register_operand (operands[0], E_VNx4HImode)
          || GET_MODE (x1) != E_VNx4HImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx4BImode
          || !vector_mask_operand (operands[1], E_VNx4BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx4HImode
          || !vector_merge_operand (operands[2], E_VNx4HImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx4HImode:
          if (!register_operand (operands[4], E_VNx4HImode))
            return -1;
          return 30;

        case E_VNx4QImode:
          if (!register_operand (operands[4], E_VNx4QImode))
            return -1;
          return 31;

        case E_VNx4SImode:
          if (!register_operand (operands[4], E_VNx4SImode))
            return -1;
          return 32;

        case E_VNx4DImode:
          if (!register_operand (operands[4], E_VNx4DImode))
            return -1;
          return 33;

        default:
          return -1;
        }

    case E_VNx8HImode:
      if (!register_operand (operands[0], E_VNx8HImode)
          || GET_MODE (x1) != E_VNx8HImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx8BImode
          || !vector_mask_operand (operands[1], E_VNx8BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx8HImode
          || !vector_merge_operand (operands[2], E_VNx8HImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx8HImode:
          if (!register_operand (operands[4], E_VNx8HImode))
            return -1;
          return 34;

        case E_VNx8QImode:
          if (!register_operand (operands[4], E_VNx8QImode))
            return -1;
          return 35;

        case E_VNx8SImode:
          if (!register_operand (operands[4], E_VNx8SImode))
            return -1;
          return 36;

        case E_VNx8DImode:
          if (!register_operand (operands[4], E_VNx8DImode))
            return -1;
          return 37;

        default:
          return -1;
        }

    case E_VNx16HImode:
      if (!register_operand (operands[0], E_VNx16HImode)
          || GET_MODE (x1) != E_VNx16HImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx16BImode
          || !vector_mask_operand (operands[1], E_VNx16BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx16HImode
          || !vector_merge_operand (operands[2], E_VNx16HImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx16HImode:
          if (!register_operand (operands[4], E_VNx16HImode))
            return -1;
          return 38;

        case E_VNx16QImode:
          if (!register_operand (operands[4], E_VNx16QImode))
            return -1;
          return 39;

        case E_VNx16SImode:
          if (!register_operand (operands[4], E_VNx16SImode))
            return -1;
          return 40;

        default:
          return -1;
        }

    case E_VNx32HImode:
      if (!register_operand (operands[0], E_VNx32HImode)
          || GET_MODE (x1) != E_VNx32HImode)
        return -1;
      x2 = XEXP (x1, 0);
      if (GET_MODE (x2) != E_VNx32BImode
          || !vector_mask_operand (operands[1], E_VNx32BImode))
        return -1;
      x3 = XEXP (x1, 1);
      if (GET_MODE (x3) != E_VNx32HImode
          || !vector_merge_operand (operands[2], E_VNx32HImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx32HImode:
          if (!register_operand (operands[4], E_VNx32HImode))
            return -1;
          return 41;

        case E_VNx32QImode:
          if (!register_operand (operands[4], E_VNx32QImode))
            return -1;
          return 42;

        default:
          return -1;
        }

    case E_VNx1SImode:
      res = pattern304 (x1, E_VNx1SImode);
      if (res >= 0)
        return res + 43; /* [43, 46] */
      return -1;

    case E_VNx2SImode:
      res = pattern305 (x1, E_VNx2SImode);
      if (res >= 0)
        return res + 47; /* [47, 50] */
      return -1;

    case E_VNx4SImode:
      res = pattern306 (x1, E_VNx4SImode);
      if (res >= 0)
        return res + 51; /* [51, 54] */
      return -1;

    case E_VNx8SImode:
      res = pattern307 (x1, E_VNx8SImode);
      if (res >= 0)
        return res + 55; /* [55, 58] */
      return -1;

    case E_VNx16SImode:
      res = pattern308 (x1, E_VNx16SImode);
      if (res >= 0)
        return res + 59; /* [59, 61] */
      return -1;

    case E_VNx1DImode:
      res = pattern309 (x1, E_VNx1DImode);
      if (res >= 0)
        return res + 62; /* [62, 65] */
      return -1;

    case E_VNx2DImode:
      res = pattern310 (x1, E_VNx2DImode);
      if (res >= 0)
        return res + 66; /* [66, 69] */
      return -1;

    case E_VNx4DImode:
      res = pattern311 (x1, E_VNx4DImode);
      if (res >= 0)
        return res + 70; /* [70, 73] */
      return -1;

    case E_VNx8DImode:
      res = pattern312 (x1, E_VNx8DImode);
      if (res >= 0)
        return res + 74; /* [74, 77] */
      return -1;

    case E_VNx1SFmode:
      res = pattern304 (x1, E_VNx1SFmode);
      if (res >= 0)
        return res + 78; /* [78, 81] */
      return -1;

    case E_VNx2SFmode:
      res = pattern305 (x1, E_VNx2SFmode);
      if (res >= 0)
        return res + 82; /* [82, 85] */
      return -1;

    case E_VNx4SFmode:
      res = pattern306 (x1, E_VNx4SFmode);
      if (res >= 0)
        return res + 86; /* [86, 89] */
      return -1;

    case E_VNx8SFmode:
      res = pattern307 (x1, E_VNx8SFmode);
      if (res >= 0)
        return res + 90; /* [90, 93] */
      return -1;

    case E_VNx16SFmode:
      res = pattern308 (x1, E_VNx16SFmode);
      if (res >= 0)
        return res + 94; /* [94, 96] */
      return -1;

    case E_VNx1DFmode:
      res = pattern309 (x1, E_VNx1DFmode);
      if (res >= 0)
        return res + 97; /* [97, 100] */
      return -1;

    case E_VNx2DFmode:
      res = pattern310 (x1, E_VNx2DFmode);
      if (res >= 0)
        return res + 101; /* [101, 104] */
      return -1;

    case E_VNx4DFmode:
      res = pattern311 (x1, E_VNx4DFmode);
      if (res >= 0)
        return res + 105; /* [105, 108] */
      return -1;

    case E_VNx8DFmode:
      res = pattern312 (x1, E_VNx8DFmode);
      if (res >= 0)
        return res + 109; /* [109, 112] */
      return -1;

    default:
      return -1;
    }
}

static int
pattern314 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i1
      || !vector_mask_operand (operands[1], i1)
      || !equality_operator (operands[3], i1))
    return -1;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i2
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern315 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_arith_operand (operands[4], i1))
    return -1;
  x4 = XEXP (x3, 1);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[2], i3)
      || !register_operand (operands[3], i1)
      || !register_operand (operands[5], i1))
    return -1;
  return 0;
}

static int
pattern316 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XVECEXP (x3, 0, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[2], i1)
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern317 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2)
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XVECEXP (x3, 0, 0);
  if (GET_MODE (x4) != i1
      || !register_operand (operands[2], i1))
    return -1;
  x5 = XEXP (x4, 1);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[4], i2)
      || !vector_merge_operand (operands[1], i1))
    return -1;
  return 0;
}

static int
pattern318 (rtx x1, machine_mode i1, machine_mode i2, machine_mode i3)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[4], i3)
      || GET_MODE (x1) != i3
      || !register_operand (operands[5], i2)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
pattern319 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[3], i1)
      || !vector_arith_operand (operands[4], i1)
      || !register_operand (operands[5], i1))
    return -1;
  return 0;
}

static int
pattern320 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !vector_arith_operand (operands[4], i1))
    return -1;
  x4 = XEXP (x3, 1);
  if (GET_MODE (x4) != i1)
    return -1;
  x5 = XEXP (x4, 0);
  if (GET_MODE (x5) != i1
      || !register_operand (operands[3], i1)
      || !register_operand (operands[5], i1))
    return -1;
  return 0;
}

static int
pattern321 (rtx x1, machine_mode i1, machine_mode i2)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  if (!register_operand (operands[0], i1)
      || GET_MODE (x1) != i1)
    return -1;
  x2 = XEXP (x1, 0);
  if (GET_MODE (x2) != i2
      || !vector_mask_operand (operands[1], i2))
    return -1;
  x3 = XEXP (x1, 1);
  if (GET_MODE (x3) != i1
      || !memory_operand (operands[3], i1)
      || !vector_merge_operand (operands[2], i1))
    return -1;
  return 0;
}

static int
recog_1 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  if (!subreg_lowpart_operator (x3, E_SImode)
      || !register_operand (operands[0], E_DImode)
      || GET_MODE (x2) != E_DImode)
    return -1;
  x4 = XEXP (x3, 0);
  if (GET_MODE (x4) != E_DImode)
    return -1;
  switch (GET_CODE (x4))
    {
    case PLUS:
      operands[3] = x3;
      x5 = XEXP (x4, 0);
      operands[1] = x5;
      if (!register_operand (operands[1], E_DImode))
        return -1;
      x6 = XEXP (x4, 1);
      operands[2] = x6;
      if (!arith_operand (operands[2], E_DImode)
          || !
#line 579 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
        return -1;
      return 7; /* *addsi3_extended2 */

    case MINUS:
      operands[3] = x3;
      x5 = XEXP (x4, 0);
      operands[1] = x5;
      if (!reg_or_0_operand (operands[1], E_DImode))
        return -1;
      x6 = XEXP (x4, 1);
      operands[2] = x6;
      if (!register_operand (operands[2], E_DImode)
          || !
#line 714 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
        return -1;
      return 14; /* *subsi3_extended2 */

    case NEG:
      operands[2] = x3;
      x5 = XEXP (x4, 0);
      operands[1] = x5;
      if (!register_operand (operands[1], E_DImode)
          || !
#line 749 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
        return -1;
      return 18; /* *negsi2_extended2 */

    case MULT:
      operands[3] = x3;
      x5 = XEXP (x4, 0);
      operands[1] = x5;
      if (!register_operand (operands[1], E_DImode))
        return -1;
      x6 = XEXP (x4, 1);
      operands[2] = x6;
      if (!register_operand (operands[2], E_DImode)
          || !
#line 896 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT))
        return -1;
      return 25; /* *mulsi3_extended2 */

    default:
      return -1;
    }
}

static int
recog_2 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (operands[0]))
    {
    case E_DImode:
      if (!register_operand (operands[0], E_DImode))
        return -1;
      x2 = XEXP (x1, 1);
      if (GET_MODE (x2) != E_DImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_SImode:
          if (!nonimmediate_operand (operands[1], E_SImode)
              || !
#line 1438 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
            return -1;
          return 116; /* extendsidi2 */

        case E_QImode:
          if (!nonimmediate_operand (operands[1], E_QImode))
            return -1;
          if ((
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return 119; /* *extendqidi2 */
          if (!(
#line 280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 357; /* *extendqidi2_zbb */

        case E_HImode:
          if (!nonimmediate_operand (operands[1], E_HImode))
            return -1;
          if ((
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return 122; /* *extendhidi2 */
          if (!(
#line 280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 360; /* *extendhidi2_zbb */

        default:
          return -1;
        }

    case E_HImode:
      x2 = XEXP (x1, 1);
      switch (pattern78 (x2, E_HImode))
        {
        case 0:
          if (
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB))
            return 117; /* *extendqihi2 */
          if (!
#line 280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB))
            return -1;
          return 355; /* *extendqihi2_zbb */

        case 1:
          if (
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB))
            return 120; /* *extendhihi2 */
          if (!
#line 280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB))
            return -1;
          return 358; /* *extendhihi2_zbb */

        default:
          return -1;
        }

    case E_SImode:
      x2 = XEXP (x1, 1);
      switch (pattern78 (x2, E_SImode))
        {
        case 0:
          if (
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB))
            return 118; /* *extendqisi2 */
          if (!
#line 280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB))
            return -1;
          return 356; /* *extendqisi2_zbb */

        case 1:
          if (
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB))
            return 121; /* *extendhisi2 */
          if (!
#line 280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB))
            return -1;
          return 359; /* *extendhisi2_zbb */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_3 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 1);
  if (GET_CODE (x3) != UNSPEC
      || XVECLEN (x3, 0) != 4
      || XINT (x3, 1) != 68)
    return -1;
  x4 = XVECEXP (x3, 0, 2);
  if (GET_CODE (x4) != REG
      || REGNO (x4) != 66
      || GET_MODE (x4) != E_SImode)
    return -1;
  x5 = XVECEXP (x3, 0, 3);
  if (GET_CODE (x5) != REG
      || REGNO (x5) != 67
      || GET_MODE (x5) != E_SImode)
    return -1;
  x6 = XEXP (x1, 0);
  operands[0] = x6;
  x7 = XVECEXP (x3, 0, 0);
  operands[3] = x7;
  if (!vector_length_operand (operands[3], E_VOIDmode))
    return -1;
  x8 = XVECEXP (x3, 0, 1);
  operands[4] = x8;
  if (!const_int_operand (operands[4], E_VOIDmode))
    return -1;
  x9 = XVECEXP (x2, 0, 0);
  switch (GET_CODE (x9))
    {
    case PLUS:
      switch (pattern181 (x2))
        {
        case 0:
          if (!register_operand (operands[0], E_VNx1BImode)
              || GET_MODE (x2) != E_VNx1BImode
              || GET_MODE (x3) != E_VNx1BImode)
            return -1;
          switch (pattern255 (x9))
            {
            case 0:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2648; /* pred_madcvnx1qi_overflow */

            case 1:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2655; /* pred_madcvnx1hi_overflow */

            case 2:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2661; /* pred_madcvnx1si_overflow */

            case 3:
              if (!(
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2666; /* pred_madcvnx1di_overflow */

            default:
              return -1;
            }

        case 1:
          if (!register_operand (operands[0], E_VNx2BImode)
              || GET_MODE (x2) != E_VNx2BImode
              || GET_MODE (x3) != E_VNx2BImode)
            return -1;
          switch (pattern256 (x9))
            {
            case 0:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2649; /* pred_madcvnx2qi_overflow */

            case 1:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2656; /* pred_madcvnx2hi_overflow */

            case 2:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2662; /* pred_madcvnx2si_overflow */

            case 3:
              if (!(
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2667; /* pred_madcvnx2di_overflow */

            default:
              return -1;
            }

        case 2:
          if (!register_operand (operands[0], E_VNx4BImode)
              || GET_MODE (x2) != E_VNx4BImode
              || GET_MODE (x3) != E_VNx4BImode)
            return -1;
          switch (pattern257 (x9))
            {
            case 0:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2650; /* pred_madcvnx4qi_overflow */

            case 1:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2657; /* pred_madcvnx4hi_overflow */

            case 2:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2663; /* pred_madcvnx4si_overflow */

            case 3:
              if (!(
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2668; /* pred_madcvnx4di_overflow */

            default:
              return -1;
            }

        case 3:
          if (!register_operand (operands[0], E_VNx8BImode)
              || GET_MODE (x2) != E_VNx8BImode
              || GET_MODE (x3) != E_VNx8BImode)
            return -1;
          switch (pattern258 (x9))
            {
            case 0:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2651; /* pred_madcvnx8qi_overflow */

            case 1:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2658; /* pred_madcvnx8hi_overflow */

            case 2:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2664; /* pred_madcvnx8si_overflow */

            case 3:
              if (!(
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2669; /* pred_madcvnx8di_overflow */

            default:
              return -1;
            }

        case 4:
          if (!register_operand (operands[0], E_VNx16BImode)
              || GET_MODE (x2) != E_VNx16BImode
              || GET_MODE (x3) != E_VNx16BImode)
            return -1;
          switch (pattern259 (x9))
            {
            case 0:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2652; /* pred_madcvnx16qi_overflow */

            case 1:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2659; /* pred_madcvnx16hi_overflow */

            case 2:
              if (!(
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2665; /* pred_madcvnx16si_overflow */

            default:
              return -1;
            }

        case 5:
          if (!register_operand (operands[0], E_VNx32BImode)
              || GET_MODE (x2) != E_VNx32BImode
              || GET_MODE (x3) != E_VNx32BImode)
            return -1;
          switch (pattern260 (x9))
            {
            case 0:
              if (!
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2653; /* pred_madcvnx32qi_overflow */

            case 1:
              if (!(
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2660; /* pred_madcvnx32hi_overflow */

            default:
              return -1;
            }

        case 6:
          if (pattern220 (x2) != 0
              || GET_MODE (x3) != E_VNx64BImode
              || !(
#line 2647 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2654; /* pred_madcvnx64qi_overflow */

        case 7:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2692; /* pred_madcvnx1qi_overflow_scalar */

        case 8:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2699; /* pred_madcvnx1hi_overflow_scalar */

        case 9:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2705; /* pred_madcvnx1si_overflow_scalar */

        case 10:
          if (!(
#line 2750 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2728; /* *pred_madcvnx1di_overflow_scalar */

        case 11:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2693; /* pred_madcvnx2qi_overflow_scalar */

        case 12:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2700; /* pred_madcvnx2hi_overflow_scalar */

        case 13:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2706; /* pred_madcvnx2si_overflow_scalar */

        case 14:
          if (!(
#line 2750 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2729; /* *pred_madcvnx2di_overflow_scalar */

        case 15:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2694; /* pred_madcvnx4qi_overflow_scalar */

        case 16:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2701; /* pred_madcvnx4hi_overflow_scalar */

        case 17:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2707; /* pred_madcvnx4si_overflow_scalar */

        case 18:
          if (!(
#line 2750 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2730; /* *pred_madcvnx4di_overflow_scalar */

        case 19:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2695; /* pred_madcvnx8qi_overflow_scalar */

        case 20:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2702; /* pred_madcvnx8hi_overflow_scalar */

        case 21:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2708; /* pred_madcvnx8si_overflow_scalar */

        case 22:
          if (!(
#line 2750 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2731; /* *pred_madcvnx8di_overflow_scalar */

        case 23:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2696; /* pred_madcvnx16qi_overflow_scalar */

        case 24:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2703; /* pred_madcvnx16hi_overflow_scalar */

        case 25:
          if (!(
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2709; /* pred_madcvnx16si_overflow_scalar */

        case 26:
          if (!
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2697; /* pred_madcvnx32qi_overflow_scalar */

        case 27:
          if (!(
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2704; /* pred_madcvnx32hi_overflow_scalar */

        case 28:
          if (!(
#line 2684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2698; /* pred_madcvnx64qi_overflow_scalar */

        case 29:
          if (!(
#line 2770 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2732; /* *pred_madcvnx1di_overflow_extended_scalar */

        case 30:
          if (!(
#line 2770 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2733; /* *pred_madcvnx2di_overflow_extended_scalar */

        case 31:
          if (!(
#line 2770 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2734; /* *pred_madcvnx4di_overflow_extended_scalar */

        case 32:
          if (!(
#line 2770 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2735; /* *pred_madcvnx8di_overflow_extended_scalar */

        default:
          return -1;
        }

    case MINUS:
      switch (pattern181 (x2))
        {
        case 0:
          if (!register_operand (operands[0], E_VNx1BImode)
              || GET_MODE (x2) != E_VNx1BImode
              || GET_MODE (x3) != E_VNx1BImode)
            return -1;
          switch (pattern261 (x9))
            {
            case 0:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2670; /* pred_msbcvnx1qi_overflow */

            case 1:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2677; /* pred_msbcvnx1hi_overflow */

            case 2:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2683; /* pred_msbcvnx1si_overflow */

            case 3:
              if (!(
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2688; /* pred_msbcvnx1di_overflow */

            default:
              return -1;
            }

        case 1:
          if (!register_operand (operands[0], E_VNx2BImode)
              || GET_MODE (x2) != E_VNx2BImode
              || GET_MODE (x3) != E_VNx2BImode)
            return -1;
          switch (pattern262 (x9))
            {
            case 0:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2671; /* pred_msbcvnx2qi_overflow */

            case 1:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2678; /* pred_msbcvnx2hi_overflow */

            case 2:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2684; /* pred_msbcvnx2si_overflow */

            case 3:
              if (!(
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2689; /* pred_msbcvnx2di_overflow */

            default:
              return -1;
            }

        case 2:
          if (!register_operand (operands[0], E_VNx4BImode)
              || GET_MODE (x2) != E_VNx4BImode
              || GET_MODE (x3) != E_VNx4BImode)
            return -1;
          switch (pattern263 (x9))
            {
            case 0:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2672; /* pred_msbcvnx4qi_overflow */

            case 1:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2679; /* pred_msbcvnx4hi_overflow */

            case 2:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2685; /* pred_msbcvnx4si_overflow */

            case 3:
              if (!(
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2690; /* pred_msbcvnx4di_overflow */

            default:
              return -1;
            }

        case 3:
          if (!register_operand (operands[0], E_VNx8BImode)
              || GET_MODE (x2) != E_VNx8BImode
              || GET_MODE (x3) != E_VNx8BImode)
            return -1;
          switch (pattern264 (x9))
            {
            case 0:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2673; /* pred_msbcvnx8qi_overflow */

            case 1:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2680; /* pred_msbcvnx8hi_overflow */

            case 2:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2686; /* pred_msbcvnx8si_overflow */

            case 3:
              if (!(
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2691; /* pred_msbcvnx8di_overflow */

            default:
              return -1;
            }

        case 4:
          if (!register_operand (operands[0], E_VNx16BImode)
              || GET_MODE (x2) != E_VNx16BImode
              || GET_MODE (x3) != E_VNx16BImode)
            return -1;
          switch (pattern265 (x9))
            {
            case 0:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2674; /* pred_msbcvnx16qi_overflow */

            case 1:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2681; /* pred_msbcvnx16hi_overflow */

            case 2:
              if (!(
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2687; /* pred_msbcvnx16si_overflow */

            default:
              return -1;
            }

        case 5:
          if (!register_operand (operands[0], E_VNx32BImode)
              || GET_MODE (x2) != E_VNx32BImode
              || GET_MODE (x3) != E_VNx32BImode)
            return -1;
          switch (pattern266 (x9))
            {
            case 0:
              if (!
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2675; /* pred_msbcvnx32qi_overflow */

            case 1:
              if (!(
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2682; /* pred_msbcvnx32hi_overflow */

            default:
              return -1;
            }

        case 6:
          if (pattern221 (x2) != 0
              || GET_MODE (x3) != E_VNx64BImode
              || !(
#line 2665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2676; /* pred_msbcvnx64qi_overflow */

        case 7:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2710; /* pred_msbcvnx1qi_overflow_scalar */

        case 8:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2717; /* pred_msbcvnx1hi_overflow_scalar */

        case 9:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2723; /* pred_msbcvnx1si_overflow_scalar */

        case 10:
          if (!(
#line 2817 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2736; /* *pred_msbcvnx1di_overflow_scalar */

        case 11:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2711; /* pred_msbcvnx2qi_overflow_scalar */

        case 12:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2718; /* pred_msbcvnx2hi_overflow_scalar */

        case 13:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2724; /* pred_msbcvnx2si_overflow_scalar */

        case 14:
          if (!(
#line 2817 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2737; /* *pred_msbcvnx2di_overflow_scalar */

        case 15:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2712; /* pred_msbcvnx4qi_overflow_scalar */

        case 16:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2719; /* pred_msbcvnx4hi_overflow_scalar */

        case 17:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2725; /* pred_msbcvnx4si_overflow_scalar */

        case 18:
          if (!(
#line 2817 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2738; /* *pred_msbcvnx4di_overflow_scalar */

        case 19:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2713; /* pred_msbcvnx8qi_overflow_scalar */

        case 20:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2720; /* pred_msbcvnx8hi_overflow_scalar */

        case 21:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2726; /* pred_msbcvnx8si_overflow_scalar */

        case 22:
          if (!(
#line 2817 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2739; /* *pred_msbcvnx8di_overflow_scalar */

        case 23:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2714; /* pred_msbcvnx16qi_overflow_scalar */

        case 24:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2721; /* pred_msbcvnx16hi_overflow_scalar */

        case 25:
          if (!(
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2727; /* pred_msbcvnx16si_overflow_scalar */

        case 26:
          if (!
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2715; /* pred_msbcvnx32qi_overflow_scalar */

        case 27:
          if (!(
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2722; /* pred_msbcvnx32hi_overflow_scalar */

        case 28:
          if (!(
#line 2703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2716; /* pred_msbcvnx64qi_overflow_scalar */

        case 29:
          if (!(
#line 2837 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2740; /* *pred_msbcvnx1di_overflow_extended_scalar */

        case 30:
          if (!(
#line 2837 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2741; /* *pred_msbcvnx2di_overflow_extended_scalar */

        case 31:
          if (!(
#line 2837 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2742; /* *pred_msbcvnx4di_overflow_extended_scalar */

        case 32:
          if (!(
#line 2837 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2743; /* *pred_msbcvnx8di_overflow_extended_scalar */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_4 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  if (GET_CODE (x3) != REG
      || REGNO (x3) != 0
      || GET_MODE (x3) != E_SImode)
    return -1;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      if (!register_operand (operands[0], E_VNx1QImode)
          || GET_MODE (x2) != E_VNx1QImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 615; /* vundefinedvnx1qi */

    case E_VNx2QImode:
      if (!register_operand (operands[0], E_VNx2QImode)
          || GET_MODE (x2) != E_VNx2QImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 616; /* vundefinedvnx2qi */

    case E_VNx4QImode:
      if (!register_operand (operands[0], E_VNx4QImode)
          || GET_MODE (x2) != E_VNx4QImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 617; /* vundefinedvnx4qi */

    case E_VNx8QImode:
      if (!register_operand (operands[0], E_VNx8QImode)
          || GET_MODE (x2) != E_VNx8QImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 618; /* vundefinedvnx8qi */

    case E_VNx16QImode:
      if (!register_operand (operands[0], E_VNx16QImode)
          || GET_MODE (x2) != E_VNx16QImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 619; /* vundefinedvnx16qi */

    case E_VNx32QImode:
      if (!register_operand (operands[0], E_VNx32QImode)
          || GET_MODE (x2) != E_VNx32QImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 620; /* vundefinedvnx32qi */

    case E_VNx64QImode:
      if (!register_operand (operands[0], E_VNx64QImode)
          || GET_MODE (x2) != E_VNx64QImode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 621; /* vundefinedvnx64qi */

    case E_VNx1HImode:
      if (!register_operand (operands[0], E_VNx1HImode)
          || GET_MODE (x2) != E_VNx1HImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 622; /* vundefinedvnx1hi */

    case E_VNx2HImode:
      if (!register_operand (operands[0], E_VNx2HImode)
          || GET_MODE (x2) != E_VNx2HImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 623; /* vundefinedvnx2hi */

    case E_VNx4HImode:
      if (!register_operand (operands[0], E_VNx4HImode)
          || GET_MODE (x2) != E_VNx4HImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 624; /* vundefinedvnx4hi */

    case E_VNx8HImode:
      if (!register_operand (operands[0], E_VNx8HImode)
          || GET_MODE (x2) != E_VNx8HImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 625; /* vundefinedvnx8hi */

    case E_VNx16HImode:
      if (!register_operand (operands[0], E_VNx16HImode)
          || GET_MODE (x2) != E_VNx16HImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 626; /* vundefinedvnx16hi */

    case E_VNx32HImode:
      if (!register_operand (operands[0], E_VNx32HImode)
          || GET_MODE (x2) != E_VNx32HImode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 627; /* vundefinedvnx32hi */

    case E_VNx1SImode:
      if (!register_operand (operands[0], E_VNx1SImode)
          || GET_MODE (x2) != E_VNx1SImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 628; /* vundefinedvnx1si */

    case E_VNx2SImode:
      if (!register_operand (operands[0], E_VNx2SImode)
          || GET_MODE (x2) != E_VNx2SImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 629; /* vundefinedvnx2si */

    case E_VNx4SImode:
      if (!register_operand (operands[0], E_VNx4SImode)
          || GET_MODE (x2) != E_VNx4SImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 630; /* vundefinedvnx4si */

    case E_VNx8SImode:
      if (!register_operand (operands[0], E_VNx8SImode)
          || GET_MODE (x2) != E_VNx8SImode
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 631; /* vundefinedvnx8si */

    case E_VNx16SImode:
      if (!register_operand (operands[0], E_VNx16SImode)
          || GET_MODE (x2) != E_VNx16SImode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 632; /* vundefinedvnx16si */

    case E_VNx1DImode:
      if (!register_operand (operands[0], E_VNx1DImode)
          || GET_MODE (x2) != E_VNx1DImode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 633; /* vundefinedvnx1di */

    case E_VNx2DImode:
      if (!register_operand (operands[0], E_VNx2DImode)
          || GET_MODE (x2) != E_VNx2DImode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 634; /* vundefinedvnx2di */

    case E_VNx4DImode:
      if (!register_operand (operands[0], E_VNx4DImode)
          || GET_MODE (x2) != E_VNx4DImode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 635; /* vundefinedvnx4di */

    case E_VNx8DImode:
      if (!register_operand (operands[0], E_VNx8DImode)
          || GET_MODE (x2) != E_VNx8DImode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 636; /* vundefinedvnx8di */

    case E_VNx1SFmode:
      if (!register_operand (operands[0], E_VNx1SFmode)
          || GET_MODE (x2) != E_VNx1SFmode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 637; /* vundefinedvnx1sf */

    case E_VNx2SFmode:
      if (!register_operand (operands[0], E_VNx2SFmode)
          || GET_MODE (x2) != E_VNx2SFmode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 638; /* vundefinedvnx2sf */

    case E_VNx4SFmode:
      if (!register_operand (operands[0], E_VNx4SFmode)
          || GET_MODE (x2) != E_VNx4SFmode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 639; /* vundefinedvnx4sf */

    case E_VNx8SFmode:
      if (!register_operand (operands[0], E_VNx8SFmode)
          || GET_MODE (x2) != E_VNx8SFmode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 640; /* vundefinedvnx8sf */

    case E_VNx16SFmode:
      if (!register_operand (operands[0], E_VNx16SFmode)
          || GET_MODE (x2) != E_VNx16SFmode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 641; /* vundefinedvnx16sf */

    case E_VNx1DFmode:
      if (!register_operand (operands[0], E_VNx1DFmode)
          || GET_MODE (x2) != E_VNx1DFmode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 642; /* vundefinedvnx1df */

    case E_VNx2DFmode:
      if (!register_operand (operands[0], E_VNx2DFmode)
          || GET_MODE (x2) != E_VNx2DFmode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 643; /* vundefinedvnx2df */

    case E_VNx4DFmode:
      if (!register_operand (operands[0], E_VNx4DFmode)
          || GET_MODE (x2) != E_VNx4DFmode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 644; /* vundefinedvnx4df */

    case E_VNx8DFmode:
      if (!register_operand (operands[0], E_VNx8DFmode)
          || GET_MODE (x2) != E_VNx8DFmode
          || !(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 645; /* vundefinedvnx8df */

    case E_VNx1BImode:
      if (!register_operand (operands[0], E_VNx1BImode)
          || GET_MODE (x2) != E_VNx1BImode
          || !
#line 367 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 646; /* vundefinedvnx1bi */

    case E_VNx2BImode:
      if (!register_operand (operands[0], E_VNx2BImode)
          || GET_MODE (x2) != E_VNx2BImode
          || !
#line 367 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 647; /* vundefinedvnx2bi */

    case E_VNx4BImode:
      if (!register_operand (operands[0], E_VNx4BImode)
          || GET_MODE (x2) != E_VNx4BImode
          || !
#line 367 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 648; /* vundefinedvnx4bi */

    case E_VNx8BImode:
      if (!register_operand (operands[0], E_VNx8BImode)
          || GET_MODE (x2) != E_VNx8BImode
          || !
#line 367 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 649; /* vundefinedvnx8bi */

    case E_VNx16BImode:
      if (!register_operand (operands[0], E_VNx16BImode)
          || GET_MODE (x2) != E_VNx16BImode
          || !
#line 367 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 650; /* vundefinedvnx16bi */

    case E_VNx32BImode:
      if (!register_operand (operands[0], E_VNx32BImode)
          || GET_MODE (x2) != E_VNx32BImode
          || !
#line 367 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 651; /* vundefinedvnx32bi */

    case E_VNx64BImode:
      if (!register_operand (operands[0], E_VNx64BImode)
          || GET_MODE (x2) != E_VNx64BImode
          || !(
#line 367 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 652; /* vundefinedvnx64bi */

    default:
      return -1;
    }
}

static int
recog_5 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern231 (x2))
    {
    case 0:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5333; /* pred_reduc_minvnx1qivnx8qi */

    case 1:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5341; /* pred_reduc_minvnx2qivnx8qi */

    case 2:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5349; /* pred_reduc_minvnx4qivnx8qi */

    case 3:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5357; /* pred_reduc_minvnx8qivnx8qi */

    case 4:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5365; /* pred_reduc_minvnx16qivnx8qi */

    case 5:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5373; /* pred_reduc_minvnx32qivnx8qi */

    case 6:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5381; /* pred_reduc_minvnx64qivnx8qi */

    case 7:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5389; /* pred_reduc_minvnx1hivnx4hi */

    case 8:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5397; /* pred_reduc_minvnx2hivnx4hi */

    case 9:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5405; /* pred_reduc_minvnx4hivnx4hi */

    case 10:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5413; /* pred_reduc_minvnx8hivnx4hi */

    case 11:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5421; /* pred_reduc_minvnx16hivnx4hi */

    case 12:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5429; /* pred_reduc_minvnx32hivnx4hi */

    case 13:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5437; /* pred_reduc_minvnx1sivnx2si */

    case 14:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5445; /* pred_reduc_minvnx2sivnx2si */

    case 15:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5453; /* pred_reduc_minvnx4sivnx2si */

    case 16:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5461; /* pred_reduc_minvnx8sivnx2si */

    case 17:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5469; /* pred_reduc_minvnx16sivnx2si */

    case 18:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5477; /* pred_reduc_minvnx1divnx1DI */

    case 19:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5485; /* pred_reduc_minvnx2divnx1DI */

    case 20:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5493; /* pred_reduc_minvnx4divnx1DI */

    case 21:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5501; /* pred_reduc_minvnx8divnx1DI */

    case 22:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5509; /* pred_reduc_minvnx1qivnx4qi */

    case 23:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5517; /* pred_reduc_minvnx2qivnx4qi */

    case 24:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5525; /* pred_reduc_minvnx4qivnx4qi */

    case 25:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5533; /* pred_reduc_minvnx8qivnx4qi */

    case 26:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5541; /* pred_reduc_minvnx16qivnx4qi */

    case 27:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5549; /* pred_reduc_minvnx32qivnx4qi */

    case 28:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5557; /* pred_reduc_minvnx1hivnx2hi */

    case 29:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5565; /* pred_reduc_minvnx2hivnx2hi */

    case 30:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5573; /* pred_reduc_minvnx4hivnx2hi */

    case 31:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5581; /* pred_reduc_minvnx8hivnx2hi */

    case 32:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5589; /* pred_reduc_minvnx16hivnx2hi */

    case 33:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5597; /* pred_reduc_minvnx1sivnx1si */

    case 34:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5605; /* pred_reduc_minvnx2sivnx1si */

    case 35:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5613; /* pred_reduc_minvnx4sivnx1si */

    case 36:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5621; /* pred_reduc_minvnx8sivnx1si */

    case 37:
      if ((
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 5684; /* pred_reduc_minvnx1sfvnx2sf */
      if (!(
#line 6867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 269 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5702; /* pred_reduc_minvnx1sfvnx1sf */

    case 38:
      if ((
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 5686; /* pred_reduc_minvnx2sfvnx2sf */
      if (!(
#line 6867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5704; /* pred_reduc_minvnx2sfvnx1sf */

    case 39:
      if ((
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 5688; /* pred_reduc_minvnx4sfvnx2sf */
      if (!(
#line 6867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 271 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5706; /* pred_reduc_minvnx4sfvnx1sf */

    case 40:
      if ((
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 5690; /* pred_reduc_minvnx8sfvnx2sf */
      if (!(
#line 6867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 272 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5708; /* pred_reduc_minvnx8sfvnx1sf */

    case 41:
      if (!(
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 5692; /* pred_reduc_minvnx16sfvnx2sf */

    case 42:
      if (!(
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5694; /* pred_reduc_minvnx1dfvnx1df */

    case 43:
      if (!(
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5696; /* pred_reduc_minvnx2dfvnx1df */

    case 44:
      if (!(
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5698; /* pred_reduc_minvnx4dfvnx1df */

    case 45:
      if (!(
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5700; /* pred_reduc_minvnx8dfvnx1df */

    default:
      return -1;
    }
}

static int
recog_6 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern231 (x2))
    {
    case 0:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5331; /* pred_reduc_maxvnx1qivnx8qi */

    case 1:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5339; /* pred_reduc_maxvnx2qivnx8qi */

    case 2:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5347; /* pred_reduc_maxvnx4qivnx8qi */

    case 3:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5355; /* pred_reduc_maxvnx8qivnx8qi */

    case 4:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5363; /* pred_reduc_maxvnx16qivnx8qi */

    case 5:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5371; /* pred_reduc_maxvnx32qivnx8qi */

    case 6:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5379; /* pred_reduc_maxvnx64qivnx8qi */

    case 7:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5387; /* pred_reduc_maxvnx1hivnx4hi */

    case 8:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5395; /* pred_reduc_maxvnx2hivnx4hi */

    case 9:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5403; /* pred_reduc_maxvnx4hivnx4hi */

    case 10:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5411; /* pred_reduc_maxvnx8hivnx4hi */

    case 11:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5419; /* pred_reduc_maxvnx16hivnx4hi */

    case 12:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5427; /* pred_reduc_maxvnx32hivnx4hi */

    case 13:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5435; /* pred_reduc_maxvnx1sivnx2si */

    case 14:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5443; /* pred_reduc_maxvnx2sivnx2si */

    case 15:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5451; /* pred_reduc_maxvnx4sivnx2si */

    case 16:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5459; /* pred_reduc_maxvnx8sivnx2si */

    case 17:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5467; /* pred_reduc_maxvnx16sivnx2si */

    case 18:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5475; /* pred_reduc_maxvnx1divnx1DI */

    case 19:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5483; /* pred_reduc_maxvnx2divnx1DI */

    case 20:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5491; /* pred_reduc_maxvnx4divnx1DI */

    case 21:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5499; /* pred_reduc_maxvnx8divnx1DI */

    case 22:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5507; /* pred_reduc_maxvnx1qivnx4qi */

    case 23:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5515; /* pred_reduc_maxvnx2qivnx4qi */

    case 24:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5523; /* pred_reduc_maxvnx4qivnx4qi */

    case 25:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5531; /* pred_reduc_maxvnx8qivnx4qi */

    case 26:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5539; /* pred_reduc_maxvnx16qivnx4qi */

    case 27:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5547; /* pred_reduc_maxvnx32qivnx4qi */

    case 28:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5555; /* pred_reduc_maxvnx1hivnx2hi */

    case 29:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5563; /* pred_reduc_maxvnx2hivnx2hi */

    case 30:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5571; /* pred_reduc_maxvnx4hivnx2hi */

    case 31:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5579; /* pred_reduc_maxvnx8hivnx2hi */

    case 32:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5587; /* pred_reduc_maxvnx16hivnx2hi */

    case 33:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5595; /* pred_reduc_maxvnx1sivnx1si */

    case 34:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5603; /* pred_reduc_maxvnx2sivnx1si */

    case 35:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5611; /* pred_reduc_maxvnx4sivnx1si */

    case 36:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5619; /* pred_reduc_maxvnx8sivnx1si */

    case 37:
      if ((
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 5683; /* pred_reduc_maxvnx1sfvnx2sf */
      if (!(
#line 6867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 269 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5701; /* pred_reduc_maxvnx1sfvnx1sf */

    case 38:
      if ((
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 5685; /* pred_reduc_maxvnx2sfvnx2sf */
      if (!(
#line 6867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5703; /* pred_reduc_maxvnx2sfvnx1sf */

    case 39:
      if ((
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 5687; /* pred_reduc_maxvnx4sfvnx2sf */
      if (!(
#line 6867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 271 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5705; /* pred_reduc_maxvnx4sfvnx1sf */

    case 40:
      if ((
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 5689; /* pred_reduc_maxvnx8sfvnx2sf */
      if (!(
#line 6867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 272 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5707; /* pred_reduc_maxvnx8sfvnx1sf */

    case 41:
      if (!(
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 5691; /* pred_reduc_maxvnx16sfvnx2sf */

    case 42:
      if (!(
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5693; /* pred_reduc_maxvnx1dfvnx1df */

    case 43:
      if (!(
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5695; /* pred_reduc_maxvnx2dfvnx1df */

    case 44:
      if (!(
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5697; /* pred_reduc_maxvnx4dfvnx1df */

    case 45:
      if (!(
#line 6845 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5699; /* pred_reduc_maxvnx8dfvnx1df */

    default:
      return -1;
    }
}

static int
recog_7 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern230 (x2))
    {
    case 0:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5335; /* pred_reduc_orvnx1qivnx8qi */

    case 1:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5343; /* pred_reduc_orvnx2qivnx8qi */

    case 2:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5351; /* pred_reduc_orvnx4qivnx8qi */

    case 3:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5359; /* pred_reduc_orvnx8qivnx8qi */

    case 4:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5367; /* pred_reduc_orvnx16qivnx8qi */

    case 5:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5375; /* pred_reduc_orvnx32qivnx8qi */

    case 6:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5383; /* pred_reduc_orvnx64qivnx8qi */

    case 7:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5391; /* pred_reduc_orvnx1hivnx4hi */

    case 8:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5399; /* pred_reduc_orvnx2hivnx4hi */

    case 9:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5407; /* pred_reduc_orvnx4hivnx4hi */

    case 10:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5415; /* pred_reduc_orvnx8hivnx4hi */

    case 11:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5423; /* pred_reduc_orvnx16hivnx4hi */

    case 12:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5431; /* pred_reduc_orvnx32hivnx4hi */

    case 13:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5439; /* pred_reduc_orvnx1sivnx2si */

    case 14:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5447; /* pred_reduc_orvnx2sivnx2si */

    case 15:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5455; /* pred_reduc_orvnx4sivnx2si */

    case 16:
      if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
        return -1;
      return 5463; /* pred_reduc_orvnx8sivnx2si */

    case 17:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5471; /* pred_reduc_orvnx16sivnx2si */

    case 18:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5479; /* pred_reduc_orvnx1divnx1DI */

    case 19:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5487; /* pred_reduc_orvnx2divnx1DI */

    case 20:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5495; /* pred_reduc_orvnx4divnx1DI */

    case 21:
      if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5503; /* pred_reduc_orvnx8divnx1DI */

    case 22:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5511; /* pred_reduc_orvnx1qivnx4qi */

    case 23:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5519; /* pred_reduc_orvnx2qivnx4qi */

    case 24:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5527; /* pred_reduc_orvnx4qivnx4qi */

    case 25:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5535; /* pred_reduc_orvnx8qivnx4qi */

    case 26:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5543; /* pred_reduc_orvnx16qivnx4qi */

    case 27:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5551; /* pred_reduc_orvnx32qivnx4qi */

    case 28:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5559; /* pred_reduc_orvnx1hivnx2hi */

    case 29:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5567; /* pred_reduc_orvnx2hivnx2hi */

    case 30:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5575; /* pred_reduc_orvnx4hivnx2hi */

    case 31:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5583; /* pred_reduc_orvnx8hivnx2hi */

    case 32:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5591; /* pred_reduc_orvnx16hivnx2hi */

    case 33:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5599; /* pred_reduc_orvnx1sivnx1si */

    case 34:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5607; /* pred_reduc_orvnx2sivnx1si */

    case 35:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5615; /* pred_reduc_orvnx4sivnx1si */

    case 36:
      if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
        return -1;
      return 5623; /* pred_reduc_orvnx8sivnx1si */

    default:
      return -1;
    }
}

static int
recog_8 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XVECEXP (x2, 0, 0);
  if (pattern70 (x3) != 0)
    return -1;
  x4 = XVECEXP (x3, 0, 0);
  operands[1] = x4;
  x5 = XVECEXP (x3, 0, 1);
  operands[5] = x5;
  if (!vector_length_operand (operands[5], E_VOIDmode))
    return -1;
  x6 = XVECEXP (x3, 0, 2);
  operands[6] = x6;
  if (!const_int_operand (operands[6], E_VOIDmode))
    return -1;
  x7 = XVECEXP (x3, 0, 3);
  operands[7] = x7;
  if (!const_int_operand (operands[7], E_VOIDmode))
    return -1;
  x8 = XVECEXP (x2, 0, 2);
  operands[2] = x8;
  x9 = XVECEXP (x2, 0, 1);
  switch (GET_CODE (x9))
    {
    case PLUS:
      switch (pattern230 (x2))
        {
        case 0:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5329; /* pred_reduc_sumvnx1qivnx8qi */

        case 1:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5337; /* pred_reduc_sumvnx2qivnx8qi */

        case 2:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5345; /* pred_reduc_sumvnx4qivnx8qi */

        case 3:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5353; /* pred_reduc_sumvnx8qivnx8qi */

        case 4:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5361; /* pred_reduc_sumvnx16qivnx8qi */

        case 5:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5369; /* pred_reduc_sumvnx32qivnx8qi */

        case 6:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5377; /* pred_reduc_sumvnx64qivnx8qi */

        case 7:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5385; /* pred_reduc_sumvnx1hivnx4hi */

        case 8:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5393; /* pred_reduc_sumvnx2hivnx4hi */

        case 9:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5401; /* pred_reduc_sumvnx4hivnx4hi */

        case 10:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5409; /* pred_reduc_sumvnx8hivnx4hi */

        case 11:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5417; /* pred_reduc_sumvnx16hivnx4hi */

        case 12:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5425; /* pred_reduc_sumvnx32hivnx4hi */

        case 13:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5433; /* pred_reduc_sumvnx1sivnx2si */

        case 14:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5441; /* pred_reduc_sumvnx2sivnx2si */

        case 15:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5449; /* pred_reduc_sumvnx4sivnx2si */

        case 16:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5457; /* pred_reduc_sumvnx8sivnx2si */

        case 17:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5465; /* pred_reduc_sumvnx16sivnx2si */

        case 18:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5473; /* pred_reduc_sumvnx1divnx1DI */

        case 19:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5481; /* pred_reduc_sumvnx2divnx1DI */

        case 20:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5489; /* pred_reduc_sumvnx4divnx1DI */

        case 21:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5497; /* pred_reduc_sumvnx8divnx1DI */

        case 22:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5505; /* pred_reduc_sumvnx1qivnx4qi */

        case 23:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5513; /* pred_reduc_sumvnx2qivnx4qi */

        case 24:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5521; /* pred_reduc_sumvnx4qivnx4qi */

        case 25:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5529; /* pred_reduc_sumvnx8qivnx4qi */

        case 26:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5537; /* pred_reduc_sumvnx16qivnx4qi */

        case 27:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5545; /* pred_reduc_sumvnx32qivnx4qi */

        case 28:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5553; /* pred_reduc_sumvnx1hivnx2hi */

        case 29:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5561; /* pred_reduc_sumvnx2hivnx2hi */

        case 30:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5569; /* pred_reduc_sumvnx4hivnx2hi */

        case 31:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5577; /* pred_reduc_sumvnx8hivnx2hi */

        case 32:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5585; /* pred_reduc_sumvnx16hivnx2hi */

        case 33:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5593; /* pred_reduc_sumvnx1sivnx1si */

        case 34:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5601; /* pred_reduc_sumvnx2sivnx1si */

        case 35:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5609; /* pred_reduc_sumvnx4sivnx1si */

        case 36:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5617; /* pred_reduc_sumvnx8sivnx1si */

        default:
          return -1;
        }

    case UMAX:
      switch (pattern230 (x2))
        {
        case 0:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5330; /* pred_reduc_maxuvnx1qivnx8qi */

        case 1:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5338; /* pred_reduc_maxuvnx2qivnx8qi */

        case 2:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5346; /* pred_reduc_maxuvnx4qivnx8qi */

        case 3:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5354; /* pred_reduc_maxuvnx8qivnx8qi */

        case 4:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5362; /* pred_reduc_maxuvnx16qivnx8qi */

        case 5:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5370; /* pred_reduc_maxuvnx32qivnx8qi */

        case 6:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5378; /* pred_reduc_maxuvnx64qivnx8qi */

        case 7:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5386; /* pred_reduc_maxuvnx1hivnx4hi */

        case 8:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5394; /* pred_reduc_maxuvnx2hivnx4hi */

        case 9:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5402; /* pred_reduc_maxuvnx4hivnx4hi */

        case 10:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5410; /* pred_reduc_maxuvnx8hivnx4hi */

        case 11:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5418; /* pred_reduc_maxuvnx16hivnx4hi */

        case 12:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5426; /* pred_reduc_maxuvnx32hivnx4hi */

        case 13:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5434; /* pred_reduc_maxuvnx1sivnx2si */

        case 14:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5442; /* pred_reduc_maxuvnx2sivnx2si */

        case 15:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5450; /* pred_reduc_maxuvnx4sivnx2si */

        case 16:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5458; /* pred_reduc_maxuvnx8sivnx2si */

        case 17:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5466; /* pred_reduc_maxuvnx16sivnx2si */

        case 18:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5474; /* pred_reduc_maxuvnx1divnx1DI */

        case 19:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5482; /* pred_reduc_maxuvnx2divnx1DI */

        case 20:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5490; /* pred_reduc_maxuvnx4divnx1DI */

        case 21:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5498; /* pred_reduc_maxuvnx8divnx1DI */

        case 22:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5506; /* pred_reduc_maxuvnx1qivnx4qi */

        case 23:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5514; /* pred_reduc_maxuvnx2qivnx4qi */

        case 24:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5522; /* pred_reduc_maxuvnx4qivnx4qi */

        case 25:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5530; /* pred_reduc_maxuvnx8qivnx4qi */

        case 26:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5538; /* pred_reduc_maxuvnx16qivnx4qi */

        case 27:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5546; /* pred_reduc_maxuvnx32qivnx4qi */

        case 28:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5554; /* pred_reduc_maxuvnx1hivnx2hi */

        case 29:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5562; /* pred_reduc_maxuvnx2hivnx2hi */

        case 30:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5570; /* pred_reduc_maxuvnx4hivnx2hi */

        case 31:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5578; /* pred_reduc_maxuvnx8hivnx2hi */

        case 32:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5586; /* pred_reduc_maxuvnx16hivnx2hi */

        case 33:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5594; /* pred_reduc_maxuvnx1sivnx1si */

        case 34:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5602; /* pred_reduc_maxuvnx2sivnx1si */

        case 35:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5610; /* pred_reduc_maxuvnx4sivnx1si */

        case 36:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5618; /* pred_reduc_maxuvnx8sivnx1si */

        default:
          return -1;
        }

    case SMAX:
      return recog_6 (x1, insn, pnum_clobbers);

    case UMIN:
      switch (pattern230 (x2))
        {
        case 0:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5332; /* pred_reduc_minuvnx1qivnx8qi */

        case 1:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5340; /* pred_reduc_minuvnx2qivnx8qi */

        case 2:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5348; /* pred_reduc_minuvnx4qivnx8qi */

        case 3:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5356; /* pred_reduc_minuvnx8qivnx8qi */

        case 4:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5364; /* pred_reduc_minuvnx16qivnx8qi */

        case 5:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5372; /* pred_reduc_minuvnx32qivnx8qi */

        case 6:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5380; /* pred_reduc_minuvnx64qivnx8qi */

        case 7:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5388; /* pred_reduc_minuvnx1hivnx4hi */

        case 8:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5396; /* pred_reduc_minuvnx2hivnx4hi */

        case 9:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5404; /* pred_reduc_minuvnx4hivnx4hi */

        case 10:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5412; /* pred_reduc_minuvnx8hivnx4hi */

        case 11:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5420; /* pred_reduc_minuvnx16hivnx4hi */

        case 12:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5428; /* pred_reduc_minuvnx32hivnx4hi */

        case 13:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5436; /* pred_reduc_minuvnx1sivnx2si */

        case 14:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5444; /* pred_reduc_minuvnx2sivnx2si */

        case 15:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5452; /* pred_reduc_minuvnx4sivnx2si */

        case 16:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5460; /* pred_reduc_minuvnx8sivnx2si */

        case 17:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5468; /* pred_reduc_minuvnx16sivnx2si */

        case 18:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5476; /* pred_reduc_minuvnx1divnx1DI */

        case 19:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5484; /* pred_reduc_minuvnx2divnx1DI */

        case 20:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5492; /* pred_reduc_minuvnx4divnx1DI */

        case 21:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5500; /* pred_reduc_minuvnx8divnx1DI */

        case 22:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5508; /* pred_reduc_minuvnx1qivnx4qi */

        case 23:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5516; /* pred_reduc_minuvnx2qivnx4qi */

        case 24:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5524; /* pred_reduc_minuvnx4qivnx4qi */

        case 25:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5532; /* pred_reduc_minuvnx8qivnx4qi */

        case 26:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5540; /* pred_reduc_minuvnx16qivnx4qi */

        case 27:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5548; /* pred_reduc_minuvnx32qivnx4qi */

        case 28:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5556; /* pred_reduc_minuvnx1hivnx2hi */

        case 29:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5564; /* pred_reduc_minuvnx2hivnx2hi */

        case 30:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5572; /* pred_reduc_minuvnx4hivnx2hi */

        case 31:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5580; /* pred_reduc_minuvnx8hivnx2hi */

        case 32:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5588; /* pred_reduc_minuvnx16hivnx2hi */

        case 33:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5596; /* pred_reduc_minuvnx1sivnx1si */

        case 34:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5604; /* pred_reduc_minuvnx2sivnx1si */

        case 35:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5612; /* pred_reduc_minuvnx4sivnx1si */

        case 36:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5620; /* pred_reduc_minuvnx8sivnx1si */

        default:
          return -1;
        }

    case SMIN:
      return recog_5 (x1, insn, pnum_clobbers);

    case AND:
      switch (pattern230 (x2))
        {
        case 0:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5334; /* pred_reduc_andvnx1qivnx8qi */

        case 1:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5342; /* pred_reduc_andvnx2qivnx8qi */

        case 2:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5350; /* pred_reduc_andvnx4qivnx8qi */

        case 3:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5358; /* pred_reduc_andvnx8qivnx8qi */

        case 4:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5366; /* pred_reduc_andvnx16qivnx8qi */

        case 5:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5374; /* pred_reduc_andvnx32qivnx8qi */

        case 6:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5382; /* pred_reduc_andvnx64qivnx8qi */

        case 7:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5390; /* pred_reduc_andvnx1hivnx4hi */

        case 8:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5398; /* pred_reduc_andvnx2hivnx4hi */

        case 9:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5406; /* pred_reduc_andvnx4hivnx4hi */

        case 10:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5414; /* pred_reduc_andvnx8hivnx4hi */

        case 11:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5422; /* pred_reduc_andvnx16hivnx4hi */

        case 12:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5430; /* pred_reduc_andvnx32hivnx4hi */

        case 13:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5438; /* pred_reduc_andvnx1sivnx2si */

        case 14:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5446; /* pred_reduc_andvnx2sivnx2si */

        case 15:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5454; /* pred_reduc_andvnx4sivnx2si */

        case 16:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5462; /* pred_reduc_andvnx8sivnx2si */

        case 17:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5470; /* pred_reduc_andvnx16sivnx2si */

        case 18:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5478; /* pred_reduc_andvnx1divnx1DI */

        case 19:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5486; /* pred_reduc_andvnx2divnx1DI */

        case 20:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5494; /* pred_reduc_andvnx4divnx1DI */

        case 21:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5502; /* pred_reduc_andvnx8divnx1DI */

        case 22:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5510; /* pred_reduc_andvnx1qivnx4qi */

        case 23:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5518; /* pred_reduc_andvnx2qivnx4qi */

        case 24:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5526; /* pred_reduc_andvnx4qivnx4qi */

        case 25:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5534; /* pred_reduc_andvnx8qivnx4qi */

        case 26:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5542; /* pred_reduc_andvnx16qivnx4qi */

        case 27:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5550; /* pred_reduc_andvnx32qivnx4qi */

        case 28:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5558; /* pred_reduc_andvnx1hivnx2hi */

        case 29:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5566; /* pred_reduc_andvnx2hivnx2hi */

        case 30:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5574; /* pred_reduc_andvnx4hivnx2hi */

        case 31:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5582; /* pred_reduc_andvnx8hivnx2hi */

        case 32:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5590; /* pred_reduc_andvnx16hivnx2hi */

        case 33:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5598; /* pred_reduc_andvnx1sivnx1si */

        case 34:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5606; /* pred_reduc_andvnx2sivnx1si */

        case 35:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5614; /* pred_reduc_andvnx4sivnx1si */

        case 36:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5622; /* pred_reduc_andvnx8sivnx1si */

        default:
          return -1;
        }

    case IOR:
      return recog_7 (x1, insn, pnum_clobbers);

    case XOR:
      switch (pattern230 (x2))
        {
        case 0:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5336; /* pred_reduc_xorvnx1qivnx8qi */

        case 1:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5344; /* pred_reduc_xorvnx2qivnx8qi */

        case 2:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5352; /* pred_reduc_xorvnx4qivnx8qi */

        case 3:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5360; /* pred_reduc_xorvnx8qivnx8qi */

        case 4:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5368; /* pred_reduc_xorvnx16qivnx8qi */

        case 5:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5376; /* pred_reduc_xorvnx32qivnx8qi */

        case 6:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5384; /* pred_reduc_xorvnx64qivnx8qi */

        case 7:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5392; /* pred_reduc_xorvnx1hivnx4hi */

        case 8:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5400; /* pred_reduc_xorvnx2hivnx4hi */

        case 9:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5408; /* pred_reduc_xorvnx4hivnx4hi */

        case 10:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5416; /* pred_reduc_xorvnx8hivnx4hi */

        case 11:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5424; /* pred_reduc_xorvnx16hivnx4hi */

        case 12:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5432; /* pred_reduc_xorvnx32hivnx4hi */

        case 13:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5440; /* pred_reduc_xorvnx1sivnx2si */

        case 14:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5448; /* pred_reduc_xorvnx2sivnx2si */

        case 15:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5456; /* pred_reduc_xorvnx4sivnx2si */

        case 16:
          if (!
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5464; /* pred_reduc_xorvnx8sivnx2si */

        case 17:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5472; /* pred_reduc_xorvnx16sivnx2si */

        case 18:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5480; /* pred_reduc_xorvnx1divnx1DI */

        case 19:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5488; /* pred_reduc_xorvnx2divnx1DI */

        case 20:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5496; /* pred_reduc_xorvnx4divnx1DI */

        case 21:
          if (!(
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5504; /* pred_reduc_xorvnx8divnx1DI */

        case 22:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5512; /* pred_reduc_xorvnx1qivnx4qi */

        case 23:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5520; /* pred_reduc_xorvnx2qivnx4qi */

        case 24:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5528; /* pred_reduc_xorvnx4qivnx4qi */

        case 25:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5536; /* pred_reduc_xorvnx8qivnx4qi */

        case 26:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5544; /* pred_reduc_xorvnx16qivnx4qi */

        case 27:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5552; /* pred_reduc_xorvnx32qivnx4qi */

        case 28:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5560; /* pred_reduc_xorvnx1hivnx2hi */

        case 29:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5568; /* pred_reduc_xorvnx2hivnx2hi */

        case 30:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5576; /* pred_reduc_xorvnx4hivnx2hi */

        case 31:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5584; /* pred_reduc_xorvnx8hivnx2hi */

        case 32:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5592; /* pred_reduc_xorvnx16hivnx2hi */

        case 33:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5600; /* pred_reduc_xorvnx1sivnx1si */

        case 34:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5608; /* pred_reduc_xorvnx2sivnx1si */

        case 35:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5616; /* pred_reduc_xorvnx4sivnx1si */

        case 36:
          if (!
#line 6787 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5624; /* pred_reduc_xorvnx8sivnx1si */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_9 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern69 (x2, PLUS))
    {
    case 0:
      if (pattern234 (x2, E_VNx1BImode) != 0)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      switch (pattern255 (x3))
        {
        case 0:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2552; /* pred_madcvnx1qi */

        case 1:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2559; /* pred_madcvnx1hi */

        case 2:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2565; /* pred_madcvnx1si */

        case 3:
          if (!(
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2570; /* pred_madcvnx1di */

        default:
          return -1;
        }

    case 1:
      if (pattern234 (x2, E_VNx2BImode) != 0)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      switch (pattern256 (x3))
        {
        case 0:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2553; /* pred_madcvnx2qi */

        case 1:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2560; /* pred_madcvnx2hi */

        case 2:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2566; /* pred_madcvnx2si */

        case 3:
          if (!(
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2571; /* pred_madcvnx2di */

        default:
          return -1;
        }

    case 2:
      if (pattern234 (x2, E_VNx4BImode) != 0)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      switch (pattern257 (x3))
        {
        case 0:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2554; /* pred_madcvnx4qi */

        case 1:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2561; /* pred_madcvnx4hi */

        case 2:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2567; /* pred_madcvnx4si */

        case 3:
          if (!(
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2572; /* pred_madcvnx4di */

        default:
          return -1;
        }

    case 3:
      if (pattern234 (x2, E_VNx8BImode) != 0)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      switch (pattern258 (x3))
        {
        case 0:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2555; /* pred_madcvnx8qi */

        case 1:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2562; /* pred_madcvnx8hi */

        case 2:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2568; /* pred_madcvnx8si */

        case 3:
          if (!(
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2573; /* pred_madcvnx8di */

        default:
          return -1;
        }

    case 4:
      if (pattern234 (x2, E_VNx16BImode) != 0)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      switch (pattern259 (x3))
        {
        case 0:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2556; /* pred_madcvnx16qi */

        case 1:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2563; /* pred_madcvnx16hi */

        case 2:
          if (!(
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2569; /* pred_madcvnx16si */

        default:
          return -1;
        }

    case 5:
      if (pattern234 (x2, E_VNx32BImode) != 0)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      switch (pattern260 (x3))
        {
        case 0:
          if (!
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2557; /* pred_madcvnx32qi */

        case 1:
          if (!(
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2564; /* pred_madcvnx32hi */

        default:
          return -1;
        }

    case 6:
      if (pattern220 (x2) != 0
          || !register_operand (operands[3], E_VNx64BImode))
        return -1;
      x4 = XVECEXP (x2, 0, 2);
      if (GET_MODE (x4) != E_VNx64BImode
          || !(
#line 2430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2558; /* pred_madcvnx64qi */

    case 7:
      if (!register_operand (operands[0], E_VNx1BImode)
          || GET_MODE (x2) != E_VNx1BImode
          || !register_operand (operands[3], E_VNx1BImode))
        return -1;
      x4 = XVECEXP (x2, 0, 2);
      if (GET_MODE (x4) != E_VNx1BImode)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      switch (GET_MODE (x3))
        {
        case E_VNx1QImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx1QImode
              || !register_operand (operands[2], E_QImode)
              || !register_operand (operands[1], E_VNx1QImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2596; /* pred_madcvnx1qi_scalar */

        case E_VNx1HImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx1HImode
              || !register_operand (operands[2], E_HImode)
              || !register_operand (operands[1], E_VNx1HImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2603; /* pred_madcvnx1hi_scalar */

        case E_VNx1SImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx1SImode
              || !register_operand (operands[2], E_SImode)
              || !register_operand (operands[1], E_VNx1SImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2609; /* pred_madcvnx1si_scalar */

        case E_VNx1DImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx1DImode
              || !reg_or_0_operand (operands[2], E_DImode)
              || !register_operand (operands[1], E_VNx1DImode)
              || !(
#line 2538 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2632; /* *pred_madcvnx1di_scalar */

        default:
          return -1;
        }

    case 8:
      if (!register_operand (operands[0], E_VNx2BImode)
          || GET_MODE (x2) != E_VNx2BImode
          || !register_operand (operands[3], E_VNx2BImode))
        return -1;
      x4 = XVECEXP (x2, 0, 2);
      if (GET_MODE (x4) != E_VNx2BImode)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      switch (GET_MODE (x3))
        {
        case E_VNx2QImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx2QImode
              || !register_operand (operands[2], E_QImode)
              || !register_operand (operands[1], E_VNx2QImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2597; /* pred_madcvnx2qi_scalar */

        case E_VNx2HImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx2HImode
              || !register_operand (operands[2], E_HImode)
              || !register_operand (operands[1], E_VNx2HImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2604; /* pred_madcvnx2hi_scalar */

        case E_VNx2SImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx2SImode
              || !register_operand (operands[2], E_SImode)
              || !register_operand (operands[1], E_VNx2SImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2610; /* pred_madcvnx2si_scalar */

        case E_VNx2DImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx2DImode
              || !reg_or_0_operand (operands[2], E_DImode)
              || !register_operand (operands[1], E_VNx2DImode)
              || !(
#line 2538 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2633; /* *pred_madcvnx2di_scalar */

        default:
          return -1;
        }

    case 9:
      if (!register_operand (operands[0], E_VNx4BImode)
          || GET_MODE (x2) != E_VNx4BImode
          || !register_operand (operands[3], E_VNx4BImode))
        return -1;
      x4 = XVECEXP (x2, 0, 2);
      if (GET_MODE (x4) != E_VNx4BImode)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      switch (GET_MODE (x3))
        {
        case E_VNx4QImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx4QImode
              || !register_operand (operands[2], E_QImode)
              || !register_operand (operands[1], E_VNx4QImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2598; /* pred_madcvnx4qi_scalar */

        case E_VNx4HImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx4HImode
              || !register_operand (operands[2], E_HImode)
              || !register_operand (operands[1], E_VNx4HImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2605; /* pred_madcvnx4hi_scalar */

        case E_VNx4SImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx4SImode
              || !register_operand (operands[2], E_SImode)
              || !register_operand (operands[1], E_VNx4SImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2611; /* pred_madcvnx4si_scalar */

        case E_VNx4DImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx4DImode
              || !reg_or_0_operand (operands[2], E_DImode)
              || !register_operand (operands[1], E_VNx4DImode)
              || !(
#line 2538 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2634; /* *pred_madcvnx4di_scalar */

        default:
          return -1;
        }

    case 10:
      if (!register_operand (operands[0], E_VNx8BImode)
          || GET_MODE (x2) != E_VNx8BImode
          || !register_operand (operands[3], E_VNx8BImode))
        return -1;
      x4 = XVECEXP (x2, 0, 2);
      if (GET_MODE (x4) != E_VNx8BImode)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      switch (GET_MODE (x3))
        {
        case E_VNx8QImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx8QImode
              || !register_operand (operands[2], E_QImode)
              || !register_operand (operands[1], E_VNx8QImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2599; /* pred_madcvnx8qi_scalar */

        case E_VNx8HImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx8HImode
              || !register_operand (operands[2], E_HImode)
              || !register_operand (operands[1], E_VNx8HImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2606; /* pred_madcvnx8hi_scalar */

        case E_VNx8SImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx8SImode
              || !register_operand (operands[2], E_SImode)
              || !register_operand (operands[1], E_VNx8SImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2612; /* pred_madcvnx8si_scalar */

        case E_VNx8DImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx8DImode
              || !reg_or_0_operand (operands[2], E_DImode)
              || !register_operand (operands[1], E_VNx8DImode)
              || !(
#line 2538 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2635; /* *pred_madcvnx8di_scalar */

        default:
          return -1;
        }

    case 11:
      if (!register_operand (operands[0], E_VNx16BImode)
          || GET_MODE (x2) != E_VNx16BImode
          || !register_operand (operands[3], E_VNx16BImode))
        return -1;
      x4 = XVECEXP (x2, 0, 2);
      if (GET_MODE (x4) != E_VNx16BImode)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      switch (GET_MODE (x3))
        {
        case E_VNx16QImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx16QImode
              || !register_operand (operands[2], E_QImode)
              || !register_operand (operands[1], E_VNx16QImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2600; /* pred_madcvnx16qi_scalar */

        case E_VNx16HImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx16HImode
              || !register_operand (operands[2], E_HImode)
              || !register_operand (operands[1], E_VNx16HImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2607; /* pred_madcvnx16hi_scalar */

        case E_VNx16SImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx16SImode
              || !register_operand (operands[2], E_SImode)
              || !register_operand (operands[1], E_VNx16SImode)
              || !(
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2613; /* pred_madcvnx16si_scalar */

        default:
          return -1;
        }

    case 12:
      if (!register_operand (operands[0], E_VNx32BImode)
          || GET_MODE (x2) != E_VNx32BImode
          || !register_operand (operands[3], E_VNx32BImode))
        return -1;
      x4 = XVECEXP (x2, 0, 2);
      if (GET_MODE (x4) != E_VNx32BImode)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      switch (GET_MODE (x3))
        {
        case E_VNx32QImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx32QImode
              || !register_operand (operands[2], E_QImode)
              || !register_operand (operands[1], E_VNx32QImode)
              || !
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2601; /* pred_madcvnx32qi_scalar */

        case E_VNx32HImode:
          x5 = XEXP (x3, 0);
          if (GET_MODE (x5) != E_VNx32HImode
              || !register_operand (operands[2], E_HImode)
              || !register_operand (operands[1], E_VNx32HImode)
              || !(
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2608; /* pred_madcvnx32hi_scalar */

        default:
          return -1;
        }

    case 13:
      if (!register_operand (operands[0], E_VNx64BImode)
          || GET_MODE (x2) != E_VNx64BImode)
        return -1;
      x3 = XVECEXP (x2, 0, 0);
      if (GET_MODE (x3) != E_VNx64QImode)
        return -1;
      x5 = XEXP (x3, 0);
      if (GET_MODE (x5) != E_VNx64QImode
          || !register_operand (operands[2], E_QImode)
          || !register_operand (operands[1], E_VNx64QImode)
          || !register_operand (operands[3], E_VNx64BImode))
        return -1;
      x4 = XVECEXP (x2, 0, 2);
      if (GET_MODE (x4) != E_VNx64BImode
          || !(
#line 2469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2602; /* pred_madcvnx64qi_scalar */

    case 14:
      if (!(
#line 2559 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2636; /* *pred_madcvnx1di_extended_scalar */

    case 15:
      if (!(
#line 2559 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2637; /* *pred_madcvnx2di_extended_scalar */

    case 16:
      if (!(
#line 2559 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2638; /* *pred_madcvnx4di_extended_scalar */

    case 17:
      if (!(
#line 2559 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2639; /* *pred_madcvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_10 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (pattern34 (x1))
    {
    case 0:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1257; /* pred_indexed_ustorevnx1qivnx1qi */

    case 1:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1265; /* pred_indexed_ustorevnx1hivnx1qi */

    case 2:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1273; /* pred_indexed_ustorevnx1sivnx1qi */

    case 3:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1281; /* pred_indexed_ustorevnx1divnx1qi */

    case 4:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 306 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1289; /* pred_indexed_ustorevnx1sfvnx1qi */

    case 5:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1297; /* pred_indexed_ustorevnx1dfvnx1qi */

    case 6:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1259; /* pred_indexed_ustorevnx1qivnx1hi */

    case 7:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1267; /* pred_indexed_ustorevnx1hivnx1hi */

    case 8:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1275; /* pred_indexed_ustorevnx1sivnx1hi */

    case 9:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1283; /* pred_indexed_ustorevnx1divnx1hi */

    case 10:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 306 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1291; /* pred_indexed_ustorevnx1sfvnx1hi */

    case 11:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1299; /* pred_indexed_ustorevnx1dfvnx1hi */

    case 12:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1261; /* pred_indexed_ustorevnx1qivnx1si */

    case 13:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1269; /* pred_indexed_ustorevnx1hivnx1si */

    case 14:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1277; /* pred_indexed_ustorevnx1sivnx1si */

    case 15:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1285; /* pred_indexed_ustorevnx1divnx1si */

    case 16:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 306 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1293; /* pred_indexed_ustorevnx1sfvnx1si */

    case 17:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1301; /* pred_indexed_ustorevnx1dfvnx1si */

    case 18:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 346 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1263; /* pred_indexed_ustorevnx1qivnx1di */

    case 19:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 346 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1271; /* pred_indexed_ustorevnx1hivnx1di */

    case 20:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 346 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1279; /* pred_indexed_ustorevnx1sivnx1di */

    case 21:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 346 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))))
        return -1;
      return 1287; /* pred_indexed_ustorevnx1divnx1di */

    case 22:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 346 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 306 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))))
        return -1;
      return 1295; /* pred_indexed_ustorevnx1sfvnx1di */

    case 23:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 346 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))))
        return -1;
      return 1303; /* pred_indexed_ustorevnx1dfvnx1di */

    case 24:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1305; /* pred_indexed_ustorevnx2qivnx2qi */

    case 25:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1307; /* pred_indexed_ustorevnx2hivnx2qi */

    case 26:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1309; /* pred_indexed_ustorevnx2sivnx2qi */

    case 27:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1311; /* pred_indexed_ustorevnx2divnx2qi */

    case 28:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 313 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1313; /* pred_indexed_ustorevnx2sfvnx2qi */

    case 29:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1315; /* pred_indexed_ustorevnx2dfvnx2qi */

    case 30:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1317; /* pred_indexed_ustorevnx2qivnx2hi */

    case 31:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1319; /* pred_indexed_ustorevnx2hivnx2hi */

    case 32:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1321; /* pred_indexed_ustorevnx2sivnx2hi */

    case 33:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1323; /* pred_indexed_ustorevnx2divnx2hi */

    case 34:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 313 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1325; /* pred_indexed_ustorevnx2sfvnx2hi */

    case 35:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1327; /* pred_indexed_ustorevnx2dfvnx2hi */

    case 36:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1329; /* pred_indexed_ustorevnx2qivnx2si */

    case 37:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1331; /* pred_indexed_ustorevnx2hivnx2si */

    case 38:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1333; /* pred_indexed_ustorevnx2sivnx2si */

    case 39:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1335; /* pred_indexed_ustorevnx2divnx2si */

    case 40:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 313 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1337; /* pred_indexed_ustorevnx2sfvnx2si */

    case 41:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1339; /* pred_indexed_ustorevnx2dfvnx2si */

    case 42:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1341; /* pred_indexed_ustorevnx2qivnx2di */

    case 43:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1343; /* pred_indexed_ustorevnx2hivnx2di */

    case 44:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1345; /* pred_indexed_ustorevnx2sivnx2di */

    case 45:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))))
        return -1;
      return 1347; /* pred_indexed_ustorevnx2divnx2di */

    case 46:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 313 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))))
        return -1;
      return 1349; /* pred_indexed_ustorevnx2sfvnx2di */

    case 47:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))))
        return -1;
      return 1351; /* pred_indexed_ustorevnx2dfvnx2di */

    case 48:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1353; /* pred_indexed_ustorevnx4qivnx4qi */

    case 49:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1355; /* pred_indexed_ustorevnx4hivnx4qi */

    case 50:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1357; /* pred_indexed_ustorevnx4sivnx4qi */

    case 51:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1359; /* pred_indexed_ustorevnx4divnx4qi */

    case 52:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1361; /* pred_indexed_ustorevnx4sfvnx4qi */

    case 53:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 321 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1363; /* pred_indexed_ustorevnx4dfvnx4qi */

    case 54:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1365; /* pred_indexed_ustorevnx4qivnx4hi */

    case 55:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1367; /* pred_indexed_ustorevnx4hivnx4hi */

    case 56:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1369; /* pred_indexed_ustorevnx4sivnx4hi */

    case 57:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1371; /* pred_indexed_ustorevnx4divnx4hi */

    case 58:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1373; /* pred_indexed_ustorevnx4sfvnx4hi */

    case 59:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 321 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1375; /* pred_indexed_ustorevnx4dfvnx4hi */

    case 60:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1377; /* pred_indexed_ustorevnx4qivnx4si */

    case 61:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1379; /* pred_indexed_ustorevnx4hivnx4si */

    case 62:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1381; /* pred_indexed_ustorevnx4sivnx4si */

    case 63:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1383; /* pred_indexed_ustorevnx4divnx4si */

    case 64:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1385; /* pred_indexed_ustorevnx4sfvnx4si */

    case 65:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 321 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1387; /* pred_indexed_ustorevnx4dfvnx4si */

    case 66:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1389; /* pred_indexed_ustorevnx4qivnx4di */

    case 67:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1391; /* pred_indexed_ustorevnx4hivnx4di */

    case 68:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1393; /* pred_indexed_ustorevnx4sivnx4di */

    case 69:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))))
        return -1;
      return 1395; /* pred_indexed_ustorevnx4divnx4di */

    case 70:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))))
        return -1;
      return 1397; /* pred_indexed_ustorevnx4sfvnx4di */

    case 71:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 321 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))))
        return -1;
      return 1399; /* pred_indexed_ustorevnx4dfvnx4di */

    case 72:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1401; /* pred_indexed_ustorevnx8qivnx8qi */

    case 73:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1403; /* pred_indexed_ustorevnx8hivnx8qi */

    case 74:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1405; /* pred_indexed_ustorevnx8sivnx8qi */

    case 75:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 326 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1407; /* pred_indexed_ustorevnx8divnx8qi */

    case 76:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 327 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1409; /* pred_indexed_ustorevnx8sfvnx8qi */

    case 77:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1411; /* pred_indexed_ustorevnx8dfvnx8qi */

    case 78:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1413; /* pred_indexed_ustorevnx8qivnx8hi */

    case 79:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1415; /* pred_indexed_ustorevnx8hivnx8hi */

    case 80:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1417; /* pred_indexed_ustorevnx8sivnx8hi */

    case 81:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 326 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1419; /* pred_indexed_ustorevnx8divnx8hi */

    case 82:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 327 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1421; /* pred_indexed_ustorevnx8sfvnx8hi */

    case 83:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1423; /* pred_indexed_ustorevnx8dfvnx8hi */

    case 84:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1425; /* pred_indexed_ustorevnx8qivnx8si */

    case 85:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1427; /* pred_indexed_ustorevnx8hivnx8si */

    case 86:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1429; /* pred_indexed_ustorevnx8sivnx8si */

    case 87:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 326 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1431; /* pred_indexed_ustorevnx8divnx8si */

    case 88:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 327 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1433; /* pred_indexed_ustorevnx8sfvnx8si */

    case 89:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1435; /* pred_indexed_ustorevnx8dfvnx8si */

    case 90:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1437; /* pred_indexed_ustorevnx8qivnx8di */

    case 91:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1439; /* pred_indexed_ustorevnx8hivnx8di */

    case 92:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1441; /* pred_indexed_ustorevnx8sivnx8di */

    case 93:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 326 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))))
        return -1;
      return 1443; /* pred_indexed_ustorevnx8divnx8di */

    case 94:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 327 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))))
        return -1;
      return 1445; /* pred_indexed_ustorevnx8sfvnx8di */

    case 95:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))))
        return -1;
      return 1447; /* pred_indexed_ustorevnx8dfvnx8di */

    case 96:
      if (!
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1449; /* pred_indexed_ustorevnx16qivnx16qi */

    case 97:
      if (!
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1451; /* pred_indexed_ustorevnx16hivnx16qi */

    case 98:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 332 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1453; /* pred_indexed_ustorevnx16sivnx16qi */

    case 99:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 333 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1455; /* pred_indexed_ustorevnx16sfvnx16qi */

    case 100:
      if (!
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1457; /* pred_indexed_ustorevnx16qivnx16hi */

    case 101:
      if (!
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1459; /* pred_indexed_ustorevnx16hivnx16hi */

    case 102:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 332 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1461; /* pred_indexed_ustorevnx16sivnx16hi */

    case 103:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 333 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1463; /* pred_indexed_ustorevnx16sfvnx16hi */

    case 104:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 365 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1465; /* pred_indexed_ustorevnx16qivnx16si */

    case 105:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 365 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1467; /* pred_indexed_ustorevnx16hivnx16si */

    case 106:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 365 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1469; /* pred_indexed_ustorevnx16sivnx16si */

    case 107:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 365 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 333 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))))
        return -1;
      return 1471; /* pred_indexed_ustorevnx16sfvnx16si */

    case 108:
      if (!
#line 1648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1473; /* pred_indexed_ustorevnx32qivnx32qi */

    case 109:
      if (!(
#line 1648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 337 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1477; /* pred_indexed_ustorevnx32hivnx32qi */

    case 110:
      if (!(
#line 1648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1475; /* pred_indexed_ustorevnx32qivnx32hi */

    case 111:
      if (!(
#line 1648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1479; /* pred_indexed_ustorevnx32hivnx32hi */

    case 112:
      if (!(
#line 1665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 341 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1481; /* pred_indexed_ustorevnx64qivnx64qi */

    default:
      return -1;
    }
}

static int
recog_11 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (pattern34 (x1))
    {
    case 0:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1256; /* pred_indexed_ostorevnx1qivnx1qi */

    case 1:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1264; /* pred_indexed_ostorevnx1hivnx1qi */

    case 2:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1272; /* pred_indexed_ostorevnx1sivnx1qi */

    case 3:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1280; /* pred_indexed_ostorevnx1divnx1qi */

    case 4:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 306 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1288; /* pred_indexed_ostorevnx1sfvnx1qi */

    case 5:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1296; /* pred_indexed_ostorevnx1dfvnx1qi */

    case 6:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1258; /* pred_indexed_ostorevnx1qivnx1hi */

    case 7:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1266; /* pred_indexed_ostorevnx1hivnx1hi */

    case 8:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1274; /* pred_indexed_ostorevnx1sivnx1hi */

    case 9:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1282; /* pred_indexed_ostorevnx1divnx1hi */

    case 10:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 306 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1290; /* pred_indexed_ostorevnx1sfvnx1hi */

    case 11:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1298; /* pred_indexed_ostorevnx1dfvnx1hi */

    case 12:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1260; /* pred_indexed_ostorevnx1qivnx1si */

    case 13:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1268; /* pred_indexed_ostorevnx1hivnx1si */

    case 14:
      if (!
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1276; /* pred_indexed_ostorevnx1sivnx1si */

    case 15:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1284; /* pred_indexed_ostorevnx1divnx1si */

    case 16:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 306 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1292; /* pred_indexed_ostorevnx1sfvnx1si */

    case 17:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1300; /* pred_indexed_ostorevnx1dfvnx1si */

    case 18:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 346 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1262; /* pred_indexed_ostorevnx1qivnx1di */

    case 19:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 346 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1270; /* pred_indexed_ostorevnx1hivnx1di */

    case 20:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 346 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1278; /* pred_indexed_ostorevnx1sivnx1di */

    case 21:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 346 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))))
        return -1;
      return 1286; /* pred_indexed_ostorevnx1divnx1di */

    case 22:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 346 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 306 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))))
        return -1;
      return 1294; /* pred_indexed_ostorevnx1sfvnx1di */

    case 23:
      if (!(
#line 1563 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 346 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))))
        return -1;
      return 1302; /* pred_indexed_ostorevnx1dfvnx1di */

    case 24:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1304; /* pred_indexed_ostorevnx2qivnx2qi */

    case 25:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1306; /* pred_indexed_ostorevnx2hivnx2qi */

    case 26:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1308; /* pred_indexed_ostorevnx2sivnx2qi */

    case 27:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1310; /* pred_indexed_ostorevnx2divnx2qi */

    case 28:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 313 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1312; /* pred_indexed_ostorevnx2sfvnx2qi */

    case 29:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1314; /* pred_indexed_ostorevnx2dfvnx2qi */

    case 30:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1316; /* pred_indexed_ostorevnx2qivnx2hi */

    case 31:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1318; /* pred_indexed_ostorevnx2hivnx2hi */

    case 32:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1320; /* pred_indexed_ostorevnx2sivnx2hi */

    case 33:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1322; /* pred_indexed_ostorevnx2divnx2hi */

    case 34:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 313 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1324; /* pred_indexed_ostorevnx2sfvnx2hi */

    case 35:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1326; /* pred_indexed_ostorevnx2dfvnx2hi */

    case 36:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1328; /* pred_indexed_ostorevnx2qivnx2si */

    case 37:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1330; /* pred_indexed_ostorevnx2hivnx2si */

    case 38:
      if (!
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1332; /* pred_indexed_ostorevnx2sivnx2si */

    case 39:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1334; /* pred_indexed_ostorevnx2divnx2si */

    case 40:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 313 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1336; /* pred_indexed_ostorevnx2sfvnx2si */

    case 41:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1338; /* pred_indexed_ostorevnx2dfvnx2si */

    case 42:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1340; /* pred_indexed_ostorevnx2qivnx2di */

    case 43:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1342; /* pred_indexed_ostorevnx2hivnx2di */

    case 44:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1344; /* pred_indexed_ostorevnx2sivnx2di */

    case 45:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))))
        return -1;
      return 1346; /* pred_indexed_ostorevnx2divnx2di */

    case 46:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 313 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))))
        return -1;
      return 1348; /* pred_indexed_ostorevnx2sfvnx2di */

    case 47:
      if (!(
#line 1580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))))
        return -1;
      return 1350; /* pred_indexed_ostorevnx2dfvnx2di */

    case 48:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1352; /* pred_indexed_ostorevnx4qivnx4qi */

    case 49:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1354; /* pred_indexed_ostorevnx4hivnx4qi */

    case 50:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1356; /* pred_indexed_ostorevnx4sivnx4qi */

    case 51:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1358; /* pred_indexed_ostorevnx4divnx4qi */

    case 52:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1360; /* pred_indexed_ostorevnx4sfvnx4qi */

    case 53:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 321 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1362; /* pred_indexed_ostorevnx4dfvnx4qi */

    case 54:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1364; /* pred_indexed_ostorevnx4qivnx4hi */

    case 55:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1366; /* pred_indexed_ostorevnx4hivnx4hi */

    case 56:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1368; /* pred_indexed_ostorevnx4sivnx4hi */

    case 57:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1370; /* pred_indexed_ostorevnx4divnx4hi */

    case 58:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1372; /* pred_indexed_ostorevnx4sfvnx4hi */

    case 59:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 321 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1374; /* pred_indexed_ostorevnx4dfvnx4hi */

    case 60:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1376; /* pred_indexed_ostorevnx4qivnx4si */

    case 61:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1378; /* pred_indexed_ostorevnx4hivnx4si */

    case 62:
      if (!
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1380; /* pred_indexed_ostorevnx4sivnx4si */

    case 63:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1382; /* pred_indexed_ostorevnx4divnx4si */

    case 64:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1384; /* pred_indexed_ostorevnx4sfvnx4si */

    case 65:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 321 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1386; /* pred_indexed_ostorevnx4dfvnx4si */

    case 66:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1388; /* pred_indexed_ostorevnx4qivnx4di */

    case 67:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1390; /* pred_indexed_ostorevnx4hivnx4di */

    case 68:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1392; /* pred_indexed_ostorevnx4sivnx4di */

    case 69:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))))
        return -1;
      return 1394; /* pred_indexed_ostorevnx4divnx4di */

    case 70:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))))
        return -1;
      return 1396; /* pred_indexed_ostorevnx4sfvnx4di */

    case 71:
      if (!(
#line 1597 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 321 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))))
        return -1;
      return 1398; /* pred_indexed_ostorevnx4dfvnx4di */

    case 72:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1400; /* pred_indexed_ostorevnx8qivnx8qi */

    case 73:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1402; /* pred_indexed_ostorevnx8hivnx8qi */

    case 74:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1404; /* pred_indexed_ostorevnx8sivnx8qi */

    case 75:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 326 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1406; /* pred_indexed_ostorevnx8divnx8qi */

    case 76:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 327 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1408; /* pred_indexed_ostorevnx8sfvnx8qi */

    case 77:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1410; /* pred_indexed_ostorevnx8dfvnx8qi */

    case 78:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1412; /* pred_indexed_ostorevnx8qivnx8hi */

    case 79:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1414; /* pred_indexed_ostorevnx8hivnx8hi */

    case 80:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1416; /* pred_indexed_ostorevnx8sivnx8hi */

    case 81:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 326 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1418; /* pred_indexed_ostorevnx8divnx8hi */

    case 82:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 327 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1420; /* pred_indexed_ostorevnx8sfvnx8hi */

    case 83:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1422; /* pred_indexed_ostorevnx8dfvnx8hi */

    case 84:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1424; /* pred_indexed_ostorevnx8qivnx8si */

    case 85:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1426; /* pred_indexed_ostorevnx8hivnx8si */

    case 86:
      if (!
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1428; /* pred_indexed_ostorevnx8sivnx8si */

    case 87:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 326 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1430; /* pred_indexed_ostorevnx8divnx8si */

    case 88:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 327 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1432; /* pred_indexed_ostorevnx8sfvnx8si */

    case 89:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1434; /* pred_indexed_ostorevnx8dfvnx8si */

    case 90:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1436; /* pred_indexed_ostorevnx8qivnx8di */

    case 91:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1438; /* pred_indexed_ostorevnx8hivnx8di */

    case 92:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1440; /* pred_indexed_ostorevnx8sivnx8di */

    case 93:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 326 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))))
        return -1;
      return 1442; /* pred_indexed_ostorevnx8divnx8di */

    case 94:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 327 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))))
        return -1;
      return 1444; /* pred_indexed_ostorevnx8sfvnx8di */

    case 95:
      if (!(
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))))
        return -1;
      return 1446; /* pred_indexed_ostorevnx8dfvnx8di */

    case 96:
      if (!
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1448; /* pred_indexed_ostorevnx16qivnx16qi */

    case 97:
      if (!
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1450; /* pred_indexed_ostorevnx16hivnx16qi */

    case 98:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 332 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1452; /* pred_indexed_ostorevnx16sivnx16qi */

    case 99:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 333 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1454; /* pred_indexed_ostorevnx16sfvnx16qi */

    case 100:
      if (!
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1456; /* pred_indexed_ostorevnx16qivnx16hi */

    case 101:
      if (!
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1458; /* pred_indexed_ostorevnx16hivnx16hi */

    case 102:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 332 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1460; /* pred_indexed_ostorevnx16sivnx16hi */

    case 103:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 333 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1462; /* pred_indexed_ostorevnx16sfvnx16hi */

    case 104:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 365 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1464; /* pred_indexed_ostorevnx16qivnx16si */

    case 105:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 365 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1466; /* pred_indexed_ostorevnx16hivnx16si */

    case 106:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 365 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1468; /* pred_indexed_ostorevnx16sivnx16si */

    case 107:
      if (!(
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 365 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 333 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))))
        return -1;
      return 1470; /* pred_indexed_ostorevnx16sfvnx16si */

    case 108:
      if (!
#line 1648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1472; /* pred_indexed_ostorevnx32qivnx32qi */

    case 109:
      if (!(
#line 1648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 337 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1476; /* pred_indexed_ostorevnx32hivnx32qi */

    case 110:
      if (!(
#line 1648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1474; /* pred_indexed_ostorevnx32qivnx32hi */

    case 111:
      if (!(
#line 1648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1478; /* pred_indexed_ostorevnx32hivnx32hi */

    case 112:
      if (!(
#line 1665 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 341 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1480; /* pred_indexed_ostorevnx64qivnx64qi */

    default:
      return -1;
    }
}

static int
recog_12 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (pattern38 (x1))
    {
    case 0:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5781; /* pred_slidedownvnx1qi */

    case 1:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5783; /* pred_slidedownvnx2qi */

    case 2:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5785; /* pred_slidedownvnx4qi */

    case 3:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5787; /* pred_slidedownvnx8qi */

    case 4:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5789; /* pred_slidedownvnx16qi */

    case 5:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5791; /* pred_slidedownvnx32qi */

    case 6:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5793; /* pred_slidedownvnx64qi */

    case 7:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5795; /* pred_slidedownvnx1hi */

    case 8:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5797; /* pred_slidedownvnx2hi */

    case 9:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5799; /* pred_slidedownvnx4hi */

    case 10:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5801; /* pred_slidedownvnx8hi */

    case 11:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5803; /* pred_slidedownvnx16hi */

    case 12:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5805; /* pred_slidedownvnx32hi */

    case 13:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5807; /* pred_slidedownvnx1si */

    case 14:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5809; /* pred_slidedownvnx2si */

    case 15:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5811; /* pred_slidedownvnx4si */

    case 16:
      if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5813; /* pred_slidedownvnx8si */

    case 17:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5815; /* pred_slidedownvnx16si */

    case 18:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5817; /* pred_slidedownvnx1di */

    case 19:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5819; /* pred_slidedownvnx2di */

    case 20:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5821; /* pred_slidedownvnx4di */

    case 21:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5823; /* pred_slidedownvnx8di */

    case 22:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5825; /* pred_slidedownvnx1sf */

    case 23:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5827; /* pred_slidedownvnx2sf */

    case 24:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5829; /* pred_slidedownvnx4sf */

    case 25:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5831; /* pred_slidedownvnx8sf */

    case 26:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 5833; /* pred_slidedownvnx16sf */

    case 27:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5835; /* pred_slidedownvnx1df */

    case 28:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5837; /* pred_slidedownvnx2df */

    case 29:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5839; /* pred_slidedownvnx4df */

    case 30:
      if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5841; /* pred_slidedownvnx8df */

    default:
      return -1;
    }
}

static int
recog_13 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  switch (XINT (x3, 1))
    {
    case 5:
      x4 = XVECEXP (x3, 0, 0);
      operands[1] = x4;
      x5 = XVECEXP (x3, 0, 1);
      operands[2] = x5;
      x6 = XVECEXP (x3, 0, 2);
      operands[3] = x6;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (pattern103 (x3, E_SImode) != 0
              || !
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
            return -1;
          return 166; /* tls_add_tp_lesi */

        case E_DImode:
          if (pattern103 (x3, E_DImode) != 0
              || !
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
            return -1;
          return 167; /* tls_add_tp_ledi */

        default:
          return -1;
        }

    case 8:
      x6 = XVECEXP (x3, 0, 2);
      if (GET_CODE (x6) != PC)
        return -1;
      x4 = XVECEXP (x3, 0, 0);
      operands[1] = x4;
      x5 = XVECEXP (x3, 0, 1);
      operands[2] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (pattern104 (x3, E_SImode) != 0
              || !
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
            return -1;
          return 172; /* auipcsi */

        case E_DImode:
          if (pattern104 (x3, E_DImode) != 0
              || !
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
            return -1;
          return 173; /* auipcdi */

        default:
          return -1;
        }

    case 28:
      if (pattern66 (x3) != 0
          || !
#line 177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKND && !TARGET_64BIT))
        return -1;
      return 440; /* riscv_aes32dsi */

    case 29:
      if (pattern66 (x3) != 0
          || !
#line 187 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKND && !TARGET_64BIT))
        return -1;
      return 441; /* riscv_aes32dsmi */

    case 37:
      if (pattern66 (x3) != 0
          || !
#line 243 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNE && !TARGET_64BIT))
        return -1;
      return 447; /* riscv_aes32esi */

    case 38:
      if (pattern66 (x3) != 0
          || !
#line 253 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNE && !TARGET_64BIT))
        return -1;
      return 448; /* riscv_aes32esmi */

    case 55:
      switch (pattern67 (x3))
        {
        case 0:
          if (!(
#line 423 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSED) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 473; /* riscv_sm4ed_si */

        case 1:
          if (!(
#line 423 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSED) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 474; /* riscv_sm4ed_di */

        default:
          return -1;
        }

    case 56:
      switch (pattern67 (x3))
        {
        case 0:
          if (!(
#line 433 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSED) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 475; /* riscv_sm4ks_si */

        case 1:
          if (!(
#line 433 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSED) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 476; /* riscv_sm4ks_di */

        default:
          return -1;
        }

    case 78:
      return recog_9 (x1, insn, pnum_clobbers);

    case 79:
      switch (pattern69 (x3, MINUS))
        {
        case 0:
          if (pattern234 (x3, E_VNx1BImode) != 0)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          switch (pattern261 (x4))
            {
            case 0:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2574; /* pred_msbcvnx1qi */

            case 1:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2581; /* pred_msbcvnx1hi */

            case 2:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2587; /* pred_msbcvnx1si */

            case 3:
              if (!(
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2592; /* pred_msbcvnx1di */

            default:
              return -1;
            }

        case 1:
          if (pattern234 (x3, E_VNx2BImode) != 0)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          switch (pattern262 (x4))
            {
            case 0:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2575; /* pred_msbcvnx2qi */

            case 1:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2582; /* pred_msbcvnx2hi */

            case 2:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2588; /* pred_msbcvnx2si */

            case 3:
              if (!(
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2593; /* pred_msbcvnx2di */

            default:
              return -1;
            }

        case 2:
          if (pattern234 (x3, E_VNx4BImode) != 0)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          switch (pattern263 (x4))
            {
            case 0:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2576; /* pred_msbcvnx4qi */

            case 1:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2583; /* pred_msbcvnx4hi */

            case 2:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2589; /* pred_msbcvnx4si */

            case 3:
              if (!(
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2594; /* pred_msbcvnx4di */

            default:
              return -1;
            }

        case 3:
          if (pattern234 (x3, E_VNx8BImode) != 0)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          switch (pattern264 (x4))
            {
            case 0:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2577; /* pred_msbcvnx8qi */

            case 1:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2584; /* pred_msbcvnx8hi */

            case 2:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2590; /* pred_msbcvnx8si */

            case 3:
              if (!(
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2595; /* pred_msbcvnx8di */

            default:
              return -1;
            }

        case 4:
          if (pattern234 (x3, E_VNx16BImode) != 0)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          switch (pattern265 (x4))
            {
            case 0:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2578; /* pred_msbcvnx16qi */

            case 1:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2585; /* pred_msbcvnx16hi */

            case 2:
              if (!(
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2591; /* pred_msbcvnx16si */

            default:
              return -1;
            }

        case 5:
          if (pattern234 (x3, E_VNx32BImode) != 0)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          switch (pattern266 (x4))
            {
            case 0:
              if (!
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2579; /* pred_msbcvnx32qi */

            case 1:
              if (!(
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2586; /* pred_msbcvnx32hi */

            default:
              return -1;
            }

        case 6:
          if (pattern221 (x3) != 0
              || !register_operand (operands[3], E_VNx64BImode))
            return -1;
          x6 = XVECEXP (x3, 0, 2);
          if (GET_MODE (x6) != E_VNx64BImode
              || !(
#line 2449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2580; /* pred_msbcvnx64qi */

        case 7:
          if (pattern234 (x3, E_VNx1BImode) != 0)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          switch (pattern174 (x4))
            {
            case 0:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2614; /* pred_msbcvnx1qi_scalar */

            case 1:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2621; /* pred_msbcvnx1hi_scalar */

            case 2:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2627; /* pred_msbcvnx1si_scalar */

            case 3:
              if (!(
#line 2608 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2640; /* *pred_msbcvnx1di_scalar */

            default:
              return -1;
            }

        case 8:
          if (pattern234 (x3, E_VNx2BImode) != 0)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          switch (pattern175 (x4))
            {
            case 0:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2615; /* pred_msbcvnx2qi_scalar */

            case 1:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2622; /* pred_msbcvnx2hi_scalar */

            case 2:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2628; /* pred_msbcvnx2si_scalar */

            case 3:
              if (!(
#line 2608 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2641; /* *pred_msbcvnx2di_scalar */

            default:
              return -1;
            }

        case 9:
          if (pattern234 (x3, E_VNx4BImode) != 0)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          switch (pattern176 (x4))
            {
            case 0:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2616; /* pred_msbcvnx4qi_scalar */

            case 1:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2623; /* pred_msbcvnx4hi_scalar */

            case 2:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2629; /* pred_msbcvnx4si_scalar */

            case 3:
              if (!(
#line 2608 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2642; /* *pred_msbcvnx4di_scalar */

            default:
              return -1;
            }

        case 10:
          if (pattern234 (x3, E_VNx8BImode) != 0)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          switch (pattern177 (x4))
            {
            case 0:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2617; /* pred_msbcvnx8qi_scalar */

            case 1:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2624; /* pred_msbcvnx8hi_scalar */

            case 2:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2630; /* pred_msbcvnx8si_scalar */

            case 3:
              if (!(
#line 2608 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2643; /* *pred_msbcvnx8di_scalar */

            default:
              return -1;
            }

        case 11:
          if (pattern234 (x3, E_VNx16BImode) != 0)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          switch (pattern178 (x4))
            {
            case 0:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2618; /* pred_msbcvnx16qi_scalar */

            case 1:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2625; /* pred_msbcvnx16hi_scalar */

            case 2:
              if (!(
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2631; /* pred_msbcvnx16si_scalar */

            default:
              return -1;
            }

        case 12:
          if (pattern234 (x3, E_VNx32BImode) != 0)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          switch (pattern179 (x4))
            {
            case 0:
              if (!
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2619; /* pred_msbcvnx32qi_scalar */

            case 1:
              if (!(
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2626; /* pred_msbcvnx32hi_scalar */

            default:
              return -1;
            }

        case 13:
          if (!register_operand (operands[0], E_VNx64BImode)
              || GET_MODE (x3) != E_VNx64BImode)
            return -1;
          x4 = XVECEXP (x3, 0, 0);
          if (GET_MODE (x4) != E_VNx64QImode)
            return -1;
          x7 = XEXP (x4, 0);
          if (GET_MODE (x7) != E_VNx64QImode
              || !reg_or_0_operand (operands[2], E_QImode)
              || !register_operand (operands[1], E_VNx64QImode)
              || !register_operand (operands[3], E_VNx64BImode))
            return -1;
          x6 = XVECEXP (x3, 0, 2);
          if (GET_MODE (x6) != E_VNx64BImode
              || !(
#line 2489 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2620; /* pred_msbcvnx64qi_scalar */

        case 14:
          if (!(
#line 2629 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2644; /* *pred_msbcvnx1di_extended_scalar */

        case 15:
          if (!(
#line 2629 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2645; /* *pred_msbcvnx2di_extended_scalar */

        case 16:
          if (!(
#line 2629 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2646; /* *pred_msbcvnx4di_extended_scalar */

        case 17:
          if (!(
#line 2629 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2647; /* *pred_msbcvnx8di_extended_scalar */

        default:
          return -1;
        }

    case 103:
      return recog_8 (x1, insn, pnum_clobbers);

    case 114:
      x4 = XVECEXP (x3, 0, 0);
      if (pattern70 (x4) != 0)
        return -1;
      x8 = XVECEXP (x4, 0, 0);
      operands[3] = x8;
      x9 = XVECEXP (x4, 0, 1);
      operands[4] = x9;
      if (!vector_length_operand (operands[4], E_VOIDmode))
        return -1;
      x10 = XVECEXP (x4, 0, 2);
      operands[5] = x10;
      if (!const_int_operand (operands[5], E_VOIDmode))
        return -1;
      x11 = XVECEXP (x4, 0, 3);
      operands[6] = x11;
      if (!const_int_operand (operands[6], E_VOIDmode))
        return -1;
      x5 = XVECEXP (x3, 0, 1);
      operands[2] = x5;
      x6 = XVECEXP (x3, 0, 2);
      operands[1] = x6;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          if (pattern235 (x3, E_VNx1QImode, E_VNx1BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6004; /* pred_compressvnx1qi */

        case E_VNx2QImode:
          if (pattern235 (x3, E_VNx2QImode, E_VNx2BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6005; /* pred_compressvnx2qi */

        case E_VNx4QImode:
          if (pattern235 (x3, E_VNx4QImode, E_VNx4BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6006; /* pred_compressvnx4qi */

        case E_VNx8QImode:
          if (pattern235 (x3, E_VNx8QImode, E_VNx8BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6007; /* pred_compressvnx8qi */

        case E_VNx16QImode:
          if (pattern235 (x3, E_VNx16QImode, E_VNx16BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6008; /* pred_compressvnx16qi */

        case E_VNx32QImode:
          if (pattern235 (x3, E_VNx32QImode, E_VNx32BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6009; /* pred_compressvnx32qi */

        case E_VNx64QImode:
          if (pattern235 (x3, E_VNx64QImode, E_VNx64BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 6010; /* pred_compressvnx64qi */

        case E_VNx1HImode:
          if (pattern235 (x3, E_VNx1HImode, E_VNx1BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6011; /* pred_compressvnx1hi */

        case E_VNx2HImode:
          if (pattern235 (x3, E_VNx2HImode, E_VNx2BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6012; /* pred_compressvnx2hi */

        case E_VNx4HImode:
          if (pattern235 (x3, E_VNx4HImode, E_VNx4BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6013; /* pred_compressvnx4hi */

        case E_VNx8HImode:
          if (pattern235 (x3, E_VNx8HImode, E_VNx8BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6014; /* pred_compressvnx8hi */

        case E_VNx16HImode:
          if (pattern235 (x3, E_VNx16HImode, E_VNx16BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6015; /* pred_compressvnx16hi */

        case E_VNx32HImode:
          if (pattern235 (x3, E_VNx32HImode, E_VNx32BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 6016; /* pred_compressvnx32hi */

        case E_VNx1SImode:
          if (pattern235 (x3, E_VNx1SImode, E_VNx1BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6017; /* pred_compressvnx1si */

        case E_VNx2SImode:
          if (pattern235 (x3, E_VNx2SImode, E_VNx2BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6018; /* pred_compressvnx2si */

        case E_VNx4SImode:
          if (pattern235 (x3, E_VNx4SImode, E_VNx4BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6019; /* pred_compressvnx4si */

        case E_VNx8SImode:
          if (pattern235 (x3, E_VNx8SImode, E_VNx8BImode) != 0
              || !
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6020; /* pred_compressvnx8si */

        case E_VNx16SImode:
          if (pattern235 (x3, E_VNx16SImode, E_VNx16BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 6021; /* pred_compressvnx16si */

        case E_VNx1DImode:
          if (pattern235 (x3, E_VNx1DImode, E_VNx1BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 6022; /* pred_compressvnx1di */

        case E_VNx2DImode:
          if (pattern235 (x3, E_VNx2DImode, E_VNx2BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 6023; /* pred_compressvnx2di */

        case E_VNx4DImode:
          if (pattern235 (x3, E_VNx4DImode, E_VNx4BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 6024; /* pred_compressvnx4di */

        case E_VNx8DImode:
          if (pattern235 (x3, E_VNx8DImode, E_VNx8BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 6025; /* pred_compressvnx8di */

        case E_VNx1SFmode:
          if (pattern235 (x3, E_VNx1SFmode, E_VNx1BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 6026; /* pred_compressvnx1sf */

        case E_VNx2SFmode:
          if (pattern235 (x3, E_VNx2SFmode, E_VNx2BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 6027; /* pred_compressvnx2sf */

        case E_VNx4SFmode:
          if (pattern235 (x3, E_VNx4SFmode, E_VNx4BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 6028; /* pred_compressvnx4sf */

        case E_VNx8SFmode:
          if (pattern235 (x3, E_VNx8SFmode, E_VNx8BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 6029; /* pred_compressvnx8sf */

        case E_VNx16SFmode:
          if (pattern235 (x3, E_VNx16SFmode, E_VNx16BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 6030; /* pred_compressvnx16sf */

        case E_VNx1DFmode:
          if (pattern235 (x3, E_VNx1DFmode, E_VNx1BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 6031; /* pred_compressvnx1df */

        case E_VNx2DFmode:
          if (pattern235 (x3, E_VNx2DFmode, E_VNx2BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 6032; /* pred_compressvnx2df */

        case E_VNx4DFmode:
          if (pattern235 (x3, E_VNx4DFmode, E_VNx4BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 6033; /* pred_compressvnx4df */

        case E_VNx8DFmode:
          if (pattern235 (x3, E_VNx8DFmode, E_VNx8BImode) != 0
              || !(
#line 7236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 6034; /* pred_compressvnx8df */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_14 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (XINT (x2, 1))
    {
    case 66:
      if (GET_MODE (x2) != E_SImode)
        return -1;
      x3 = XEXP (x1, 0);
      if (GET_CODE (x3) != REG
          || REGNO (x3) != 67
          || GET_MODE (x3) != E_SImode)
        return -1;
      x4 = XVECEXP (x2, 0, 0);
      operands[0] = x4;
      if (!const_int_operand (operands[0], E_VOIDmode))
        return -1;
      x5 = XVECEXP (x2, 0, 1);
      operands[1] = x5;
      if (!const_int_operand (operands[1], E_VOIDmode))
        return -1;
      x6 = XVECEXP (x2, 0, 2);
      operands[2] = x6;
      if (!const_int_operand (operands[2], E_VOIDmode))
        return -1;
      x7 = XVECEXP (x2, 0, 3);
      operands[3] = x7;
      if (!const_int_operand (operands[3], E_VOIDmode)
          || !
#line 853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 795; /* vsetvl_vtype_change_only */

    case 71:
      return recog_11 (x1, insn, pnum_clobbers);

    case 72:
      return recog_10 (x1, insn, pnum_clobbers);

    case 104:
      switch (pattern36 (x1))
        {
        case 0:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5625; /* pred_widen_reduc_plusvnx1qivnx4hi */

        case 1:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5627; /* pred_widen_reduc_plusvnx2qivnx4hi */

        case 2:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5629; /* pred_widen_reduc_plusvnx4qivnx4hi */

        case 3:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5631; /* pred_widen_reduc_plusvnx8qivnx4hi */

        case 4:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5633; /* pred_widen_reduc_plusvnx16qivnx4hi */

        case 5:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5635; /* pred_widen_reduc_plusvnx32qivnx4hi */

        case 6:
          if (!(
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 246 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5637; /* pred_widen_reduc_plusvnx64qivnx4hi */

        case 7:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5639; /* pred_widen_reduc_plusvnx1hivnx2si */

        case 8:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5641; /* pred_widen_reduc_plusvnx2hivnx2si */

        case 9:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5643; /* pred_widen_reduc_plusvnx4hivnx2si */

        case 10:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5645; /* pred_widen_reduc_plusvnx8hivnx2si */

        case 11:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5647; /* pred_widen_reduc_plusvnx16hivnx2si */

        case 12:
          if (!(
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5649; /* pred_widen_reduc_plusvnx32hivnx2si */

        case 13:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5651; /* pred_widen_reduc_plusvnx1sivnx2di */

        case 14:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5653; /* pred_widen_reduc_plusvnx2sivnx2di */

        case 15:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5655; /* pred_widen_reduc_plusvnx4sivnx2di */

        case 16:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5657; /* pred_widen_reduc_plusvnx8sivnx2di */

        case 17:
          if (!(
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 248 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5659; /* pred_widen_reduc_plusvnx16sivnx2di */

        case 18:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5661; /* pred_widen_reduc_plusvnx1qivnx2hi */

        case 19:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5663; /* pred_widen_reduc_plusvnx2qivnx2hi */

        case 20:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5665; /* pred_widen_reduc_plusvnx4qivnx2hi */

        case 21:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5667; /* pred_widen_reduc_plusvnx8qivnx2hi */

        case 22:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5669; /* pred_widen_reduc_plusvnx16qivnx2hi */

        case 23:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5671; /* pred_widen_reduc_plusvnx32qivnx2hi */

        case 24:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5673; /* pred_widen_reduc_plusvnx1hivnx1si */

        case 25:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5675; /* pred_widen_reduc_plusvnx2hivnx1si */

        case 26:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5677; /* pred_widen_reduc_plusvnx4hivnx1si */

        case 27:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5679; /* pred_widen_reduc_plusvnx8hivnx1si */

        case 28:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5681; /* pred_widen_reduc_plusvnx16hivnx1si */

        default:
          return -1;
        }

    case 105:
      switch (pattern36 (x1))
        {
        case 0:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5626; /* pred_widen_reduc_plusuvnx1qivnx4hi */

        case 1:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5628; /* pred_widen_reduc_plusuvnx2qivnx4hi */

        case 2:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5630; /* pred_widen_reduc_plusuvnx4qivnx4hi */

        case 3:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5632; /* pred_widen_reduc_plusuvnx8qivnx4hi */

        case 4:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5634; /* pred_widen_reduc_plusuvnx16qivnx4hi */

        case 5:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5636; /* pred_widen_reduc_plusuvnx32qivnx4hi */

        case 6:
          if (!(
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 246 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5638; /* pred_widen_reduc_plusuvnx64qivnx4hi */

        case 7:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5640; /* pred_widen_reduc_plusuvnx1hivnx2si */

        case 8:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5642; /* pred_widen_reduc_plusuvnx2hivnx2si */

        case 9:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5644; /* pred_widen_reduc_plusuvnx4hivnx2si */

        case 10:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5646; /* pred_widen_reduc_plusuvnx8hivnx2si */

        case 11:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5648; /* pred_widen_reduc_plusuvnx16hivnx2si */

        case 12:
          if (!(
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5650; /* pred_widen_reduc_plusuvnx32hivnx2si */

        case 13:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5652; /* pred_widen_reduc_plusuvnx1sivnx2di */

        case 14:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5654; /* pred_widen_reduc_plusuvnx2sivnx2di */

        case 15:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5656; /* pred_widen_reduc_plusuvnx4sivnx2di */

        case 16:
          if (!
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
            return -1;
          return 5658; /* pred_widen_reduc_plusuvnx8sivnx2di */

        case 17:
          if (!(
#line 6805 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 248 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5660; /* pred_widen_reduc_plusuvnx16sivnx2di */

        case 18:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5662; /* pred_widen_reduc_plusuvnx1qivnx2hi */

        case 19:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5664; /* pred_widen_reduc_plusuvnx2qivnx2hi */

        case 20:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5666; /* pred_widen_reduc_plusuvnx4qivnx2hi */

        case 21:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5668; /* pred_widen_reduc_plusuvnx8qivnx2hi */

        case 22:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5670; /* pred_widen_reduc_plusuvnx16qivnx2hi */

        case 23:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5672; /* pred_widen_reduc_plusuvnx32qivnx2hi */

        case 24:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5674; /* pred_widen_reduc_plusuvnx1hivnx1si */

        case 25:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5676; /* pred_widen_reduc_plusuvnx2hivnx1si */

        case 26:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5678; /* pred_widen_reduc_plusuvnx4hivnx1si */

        case 27:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5680; /* pred_widen_reduc_plusuvnx8hivnx1si */

        case 28:
          if (!
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32))
            return -1;
          return 5682; /* pred_widen_reduc_plusuvnx16hivnx1si */

        default:
          return -1;
        }

    case 106:
      switch (pattern38 (x1))
        {
        case 0:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5780; /* pred_slideupvnx1qi */

        case 1:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5782; /* pred_slideupvnx2qi */

        case 2:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5784; /* pred_slideupvnx4qi */

        case 3:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5786; /* pred_slideupvnx8qi */

        case 4:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5788; /* pred_slideupvnx16qi */

        case 5:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5790; /* pred_slideupvnx32qi */

        case 6:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5792; /* pred_slideupvnx64qi */

        case 7:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5794; /* pred_slideupvnx1hi */

        case 8:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5796; /* pred_slideupvnx2hi */

        case 9:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5798; /* pred_slideupvnx4hi */

        case 10:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5800; /* pred_slideupvnx8hi */

        case 11:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5802; /* pred_slideupvnx16hi */

        case 12:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5804; /* pred_slideupvnx32hi */

        case 13:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5806; /* pred_slideupvnx1si */

        case 14:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5808; /* pred_slideupvnx2si */

        case 15:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5810; /* pred_slideupvnx4si */

        case 16:
          if (!
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5812; /* pred_slideupvnx8si */

        case 17:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5814; /* pred_slideupvnx16si */

        case 18:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5816; /* pred_slideupvnx1di */

        case 19:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5818; /* pred_slideupvnx2di */

        case 20:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5820; /* pred_slideupvnx4di */

        case 21:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5822; /* pred_slideupvnx8di */

        case 22:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5824; /* pred_slideupvnx1sf */

        case 23:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5826; /* pred_slideupvnx2sf */

        case 24:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5828; /* pred_slideupvnx4sf */

        case 25:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5830; /* pred_slideupvnx8sf */

        case 26:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5832; /* pred_slideupvnx16sf */

        case 27:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5834; /* pred_slideupvnx1df */

        case 28:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5836; /* pred_slideupvnx2df */

        case 29:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5838; /* pred_slideupvnx4df */

        case 30:
          if (!(
#line 7055 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5840; /* pred_slideupvnx8df */

        default:
          return -1;
        }

    case 107:
      return recog_12 (x1, insn, pnum_clobbers);

    case 108:
      switch (pattern40 (x1))
        {
        case 0:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5842; /* pred_slide1upvnx1qi */

        case 1:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5844; /* pred_slide1upvnx2qi */

        case 2:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5846; /* pred_slide1upvnx4qi */

        case 3:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5848; /* pred_slide1upvnx8qi */

        case 4:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5850; /* pred_slide1upvnx16qi */

        case 5:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5852; /* pred_slide1upvnx32qi */

        case 6:
          if (!(
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5854; /* pred_slide1upvnx64qi */

        case 7:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5856; /* pred_slide1upvnx1hi */

        case 8:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5858; /* pred_slide1upvnx2hi */

        case 9:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5860; /* pred_slide1upvnx4hi */

        case 10:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5862; /* pred_slide1upvnx8hi */

        case 11:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5864; /* pred_slide1upvnx16hi */

        case 12:
          if (!(
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5866; /* pred_slide1upvnx32hi */

        case 13:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5868; /* pred_slide1upvnx1si */

        case 14:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5870; /* pred_slide1upvnx2si */

        case 15:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5872; /* pred_slide1upvnx4si */

        case 16:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5874; /* pred_slide1upvnx8si */

        case 17:
          if (!(
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5876; /* pred_slide1upvnx16si */

        case 18:
          if (!(
#line 7116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5878; /* *pred_slide1upvnx1di */

        case 19:
          if (!(
#line 7116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5880; /* *pred_slide1upvnx2di */

        case 20:
          if (!(
#line 7116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5882; /* *pred_slide1upvnx4di */

        case 21:
          if (!(
#line 7116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5884; /* *pred_slide1upvnx8di */

        case 22:
          if (!(
#line 7136 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5886; /* *pred_slide1upvnx1di_extended */

        case 23:
          if (!(
#line 7136 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5888; /* *pred_slide1upvnx2di_extended */

        case 24:
          if (!(
#line 7136 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5890; /* *pred_slide1upvnx4di_extended */

        case 25:
          if (!(
#line 7136 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5892; /* *pred_slide1upvnx8di_extended */

        default:
          return -1;
        }

    case 109:
      switch (pattern40 (x1))
        {
        case 0:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5843; /* pred_slide1downvnx1qi */

        case 1:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5845; /* pred_slide1downvnx2qi */

        case 2:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5847; /* pred_slide1downvnx4qi */

        case 3:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5849; /* pred_slide1downvnx8qi */

        case 4:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5851; /* pred_slide1downvnx16qi */

        case 5:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5853; /* pred_slide1downvnx32qi */

        case 6:
          if (!(
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5855; /* pred_slide1downvnx64qi */

        case 7:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5857; /* pred_slide1downvnx1hi */

        case 8:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5859; /* pred_slide1downvnx2hi */

        case 9:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5861; /* pred_slide1downvnx4hi */

        case 10:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5863; /* pred_slide1downvnx8hi */

        case 11:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5865; /* pred_slide1downvnx16hi */

        case 12:
          if (!(
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5867; /* pred_slide1downvnx32hi */

        case 13:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5869; /* pred_slide1downvnx1si */

        case 14:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5871; /* pred_slide1downvnx2si */

        case 15:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5873; /* pred_slide1downvnx4si */

        case 16:
          if (!
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 5875; /* pred_slide1downvnx8si */

        case 17:
          if (!(
#line 7075 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 5877; /* pred_slide1downvnx16si */

        case 18:
          if (!(
#line 7116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5879; /* *pred_slide1downvnx1di */

        case 19:
          if (!(
#line 7116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5881; /* *pred_slide1downvnx2di */

        case 20:
          if (!(
#line 7116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5883; /* *pred_slide1downvnx4di */

        case 21:
          if (!(
#line 7116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5885; /* *pred_slide1downvnx8di */

        case 22:
          if (!(
#line 7136 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5887; /* *pred_slide1downvnx1di_extended */

        case 23:
          if (!(
#line 7136 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5889; /* *pred_slide1downvnx2di_extended */

        case 24:
          if (!(
#line 7136 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5891; /* *pred_slide1downvnx4di_extended */

        case 25:
          if (!(
#line 7136 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5893; /* *pred_slide1downvnx8di_extended */

        default:
          return -1;
        }

    case 110:
      switch (pattern42 (x1))
        {
        case 0:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5894; /* pred_slide1upvnx1sf */

        case 1:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5896; /* pred_slide1upvnx2sf */

        case 2:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5898; /* pred_slide1upvnx4sf */

        case 3:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5900; /* pred_slide1upvnx8sf */

        case 4:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5902; /* pred_slide1upvnx16sf */

        case 5:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5904; /* pred_slide1upvnx1df */

        case 6:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5906; /* pred_slide1upvnx2df */

        case 7:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5908; /* pred_slide1upvnx4df */

        case 8:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5910; /* pred_slide1upvnx8df */

        default:
          return -1;
        }

    case 111:
      switch (pattern42 (x1))
        {
        case 0:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5895; /* pred_slide1downvnx1sf */

        case 1:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5897; /* pred_slide1downvnx2sf */

        case 2:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5899; /* pred_slide1downvnx4sf */

        case 3:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5901; /* pred_slide1downvnx8sf */

        case 4:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5903; /* pred_slide1downvnx16sf */

        case 5:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5905; /* pred_slide1downvnx1df */

        case 6:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5907; /* pred_slide1downvnx2df */

        case 7:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5909; /* pred_slide1downvnx4df */

        case 8:
          if (!(
#line 7156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5911; /* pred_slide1downvnx8df */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_15 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (XINT (x2, 1))
    {
    case 11:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XVECEXP (x2, 0, 0);
      operands[1] = x4;
      x5 = XVECEXP (x2, 0, 1);
      operands[2] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_SFmode:
          if (pattern24 (x2, E_SFmode) != 0
              || !
#line 1215 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
            return -1;
          return 77; /* copysignsf3 */

        case E_DFmode:
          if (pattern24 (x2, E_DFmode) != 0
              || !(
#line 1215 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 78; /* copysigndf3 */

        case E_HFmode:
          if (pattern24 (x2, E_HFmode) != 0
              || !(
#line 1215 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 79; /* copysignhf3 */

        default:
          return -1;
        }

    case 14:
      switch (pattern22 (x1))
        {
        case 0:
          if (!(
#line 1240 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (SFmode)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
            return -1;
          return 83; /* fminsf3 */

        case 1:
          if (!(
#line 1240 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (DFmode)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 84; /* fmindf3 */

        case 2:
          if (!(
#line 1240 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (HFmode)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 85; /* fminhf3 */

        default:
          return -1;
        }

    case 15:
      switch (pattern22 (x1))
        {
        case 0:
          if (!(
#line 1250 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (SFmode)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
            return -1;
          return 86; /* fmaxsf3 */

        case 1:
          if (!(
#line 1250 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (DFmode)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 87; /* fmaxdf3 */

        case 2:
          if (!(
#line 1250 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (HFmode)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 88; /* fmaxhf3 */

        default:
          return -1;
        }

    case 16:
      if (GET_MODE (x2) != E_BLKmode)
        return -1;
      x3 = XEXP (x1, 0);
      if (GET_CODE (x3) != MEM
          || GET_MODE (x3) != E_BLKmode)
        return -1;
      x6 = XEXP (x3, 0);
      if (GET_CODE (x6) != SCRATCH)
        return -1;
      x4 = XVECEXP (x2, 0, 0);
      operands[0] = x4;
      x5 = XVECEXP (x2, 0, 1);
      operands[1] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (!register_operand (operands[0], E_SImode)
              || !register_operand (operands[1], E_SImode)
              || !
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
            return -1;
          return 314; /* stack_tiesi */

        case E_DImode:
          if (!register_operand (operands[0], E_DImode)
              || !register_operand (operands[1], E_DImode)
              || !
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 315; /* stack_tiedi */

        default:
          return -1;
        }

    case 12:
      if (pnum_clobbers == NULL)
        return -1;
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XVECEXP (x2, 0, 0);
      operands[1] = x4;
      x5 = XVECEXP (x2, 0, 1);
      operands[2] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (pattern102 (x2, E_SImode) != 0)
            return -1;
          *pnum_clobbers = 1;
          return 318; /* stack_protect_test_si */

        case E_DImode:
          if (pattern102 (x2, E_DImode) != 0
              || !
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          *pnum_clobbers = 1;
          return 319; /* stack_protect_test_di */

        default:
          return -1;
        }

    case 21:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XVECEXP (x2, 0, 0);
      operands[1] = x4;
      x5 = XVECEXP (x2, 0, 1);
      operands[2] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          switch (pattern89 (x2, E_SImode))
            {
            case 0:
              if (!(
#line 107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 425; /* riscv_pack_sihi */

            case 1:
              if (!(
#line 107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 426; /* riscv_pack_sisi */

            default:
              return -1;
            }

        case E_DImode:
          switch (pattern89 (x2, E_DImode))
            {
            case 0:
              if (!(
#line 107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 427; /* riscv_pack_dihi */

            case 1:
              if (!(
#line 107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 428; /* riscv_pack_disi */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case 22:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XVECEXP (x2, 0, 0);
      operands[1] = x4;
      if (!register_operand (operands[1], E_QImode))
        return -1;
      x5 = XVECEXP (x2, 0, 1);
      operands[2] = x5;
      if (!register_operand (operands[2], E_QImode))
        return -1;
      switch (pattern86 (x2))
        {
        case 0:
          if (!(
#line 116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 429; /* riscv_packh_si */

        case 1:
          if (!(
#line 116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 430; /* riscv_packh_di */

        default:
          return -1;
        }

    case 23:
      if (pattern23 (x1, E_DImode, E_HImode) != 0
          || !
#line 125 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB && TARGET_64BIT))
        return -1;
      return 431; /* riscv_packw */

    case 24:
      switch (pattern25 (x1))
        {
        case 0:
          if (!(
#line 136 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 432; /* riscv_clmul_si */

        case 1:
          if (!(
#line 136 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 433; /* riscv_clmul_di */

        default:
          return -1;
        }

    case 25:
      switch (pattern25 (x1))
        {
        case 0:
          if (!(
#line 145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 434; /* riscv_clmulh_si */

        case 1:
          if (!(
#line 145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 435; /* riscv_clmulh_di */

        default:
          return -1;
        }

    case 27:
      switch (pattern25 (x1))
        {
        case 0:
          if (!(
#line 156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKX) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 436; /* riscv_xperm4_si */

        case 1:
          if (!(
#line 156 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKX) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 437; /* riscv_xperm4_di */

        default:
          return -1;
        }

    case 26:
      switch (pattern25 (x1))
        {
        case 0:
          if (!(
#line 165 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKX) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 438; /* riscv_xperm8_si */

        case 1:
          if (!(
#line 165 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKX) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 439; /* riscv_xperm8_di */

        default:
          return -1;
        }

    case 30:
      if (pattern26 (x1) != 0
          || !
#line 196 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKND && TARGET_64BIT))
        return -1;
      return 442; /* riscv_aes64ds */

    case 31:
      if (pattern26 (x1) != 0
          || !
#line 205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKND && TARGET_64BIT))
        return -1;
      return 443; /* riscv_aes64dsm */

    case 33:
      if (GET_MODE (x2) != E_DImode)
        return -1;
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      if (!register_operand (operands[0], E_DImode))
        return -1;
      x4 = XVECEXP (x2, 0, 0);
      operands[1] = x4;
      if (!register_operand (operands[1], E_DImode))
        return -1;
      x5 = XVECEXP (x2, 0, 1);
      operands[2] = x5;
      if (!register_operand (operands[2], E_SImode)
          || !
#line 222 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
((TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT))
        return -1;
      return 445; /* riscv_aes64ks1i */

    case 34:
      if (pattern26 (x1) != 0
          || !
#line 231 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
((TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT))
        return -1;
      return 446; /* riscv_aes64ks2 */

    case 35:
      if (pattern26 (x1) != 0
          || !
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNE && TARGET_64BIT))
        return -1;
      return 449; /* riscv_aes64es */

    case 36:
      if (pattern26 (x1) != 0
          || !
#line 271 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNE && TARGET_64BIT))
        return -1;
      return 450; /* riscv_aes64esm */

    case 44:
      if (pattern23 (x1, E_SImode, E_SImode) != 0
          || !
#line 316 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && !TARGET_64BIT))
        return -1;
      return 459; /* riscv_sha512sig0h */

    case 45:
      if (pattern23 (x1, E_SImode, E_SImode) != 0
          || !
#line 325 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && !TARGET_64BIT))
        return -1;
      return 460; /* riscv_sha512sig0l */

    case 47:
      if (pattern23 (x1, E_SImode, E_SImode) != 0
          || !
#line 334 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && !TARGET_64BIT))
        return -1;
      return 461; /* riscv_sha512sig1h */

    case 48:
      if (pattern23 (x1, E_SImode, E_SImode) != 0
          || !
#line 343 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && !TARGET_64BIT))
        return -1;
      return 462; /* riscv_sha512sig1l */

    case 50:
      if (pattern23 (x1, E_SImode, E_SImode) != 0
          || !
#line 352 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && !TARGET_64BIT))
        return -1;
      return 463; /* riscv_sha512sum0r */

    case 52:
      if (pattern23 (x1, E_SImode, E_SImode) != 0
          || !
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && !TARGET_64BIT))
        return -1;
      return 464; /* riscv_sha512sum1r */

    case 19:
      if (pattern23 (x1, E_DFmode, E_SImode) != 0
          || !
#line 152 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(!TARGET_64BIT && TARGET_XTHEADFMV))
        return -1;
      return 594; /* th_fmv_hw_w_x */

    case 80:
      return recog_3 (x1, insn, pnum_clobbers);

    case 68:
      if (pattern27 (x2) != 0)
        return -1;
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XVECEXP (x2, 0, 0);
      x7 = XEXP (x4, 0);
      operands[1] = x7;
      switch (GET_MODE (operands[0]))
        {
        case E_QImode:
          switch (pattern130 (x2))
            {
            case 0:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5745; /* *pred_extract_firstvnx1qi */

            case 1:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5746; /* *pred_extract_firstvnx2qi */

            case 2:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5747; /* *pred_extract_firstvnx4qi */

            case 3:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5748; /* *pred_extract_firstvnx8qi */

            case 4:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5749; /* *pred_extract_firstvnx16qi */

            case 5:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5750; /* *pred_extract_firstvnx32qi */

            case 6:
              if (!(
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 5751; /* *pred_extract_firstvnx64qi */

            default:
              return -1;
            }

        case E_HImode:
          switch (pattern131 (x2))
            {
            case 0:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5752; /* *pred_extract_firstvnx1hi */

            case 1:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5753; /* *pred_extract_firstvnx2hi */

            case 2:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5754; /* *pred_extract_firstvnx4hi */

            case 3:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5755; /* *pred_extract_firstvnx8hi */

            case 4:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5756; /* *pred_extract_firstvnx16hi */

            case 5:
              if (!(
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 5757; /* *pred_extract_firstvnx32hi */

            default:
              return -1;
            }

        case E_SImode:
          switch (pattern132 (x2))
            {
            case 0:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5758; /* *pred_extract_firstvnx1si */

            case 1:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5759; /* *pred_extract_firstvnx2si */

            case 2:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5760; /* *pred_extract_firstvnx4si */

            case 3:
              if (!
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 5761; /* *pred_extract_firstvnx8si */

            case 4:
              if (!(
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 5762; /* *pred_extract_firstvnx16si */

            default:
              return -1;
            }

        case E_DImode:
          switch (pattern133 (x2))
            {
            case 0:
              if (!(
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 5763; /* *pred_extract_firstvnx1di */

            case 1:
              if (!(
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 5764; /* *pred_extract_firstvnx2di */

            case 2:
              if (!(
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 5765; /* *pred_extract_firstvnx4di */

            case 3:
              if (!(
#line 6972 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 5766; /* *pred_extract_firstvnx8di */

            default:
              return -1;
            }

        case E_SFmode:
          if (!register_operand (operands[0], E_SFmode)
              || GET_MODE (x2) != E_SFmode
              || GET_MODE (x4) != E_SFmode)
            return -1;
          switch (GET_MODE (operands[1]))
            {
            case E_VNx1SFmode:
              if (!register_operand (operands[1], E_VNx1SFmode)
                  || !(
#line 7035 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5771; /* *pred_extract_firstvnx1sf */

            case E_VNx2SFmode:
              if (!register_operand (operands[1], E_VNx2SFmode)
                  || !(
#line 7035 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5772; /* *pred_extract_firstvnx2sf */

            case E_VNx4SFmode:
              if (!register_operand (operands[1], E_VNx4SFmode)
                  || !(
#line 7035 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5773; /* *pred_extract_firstvnx4sf */

            case E_VNx8SFmode:
              if (!register_operand (operands[1], E_VNx8SFmode)
                  || !(
#line 7035 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5774; /* *pred_extract_firstvnx8sf */

            case E_VNx16SFmode:
              if (!register_operand (operands[1], E_VNx16SFmode)
                  || !(
#line 7035 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return -1;
              return 5775; /* *pred_extract_firstvnx16sf */

            default:
              return -1;
            }

        case E_DFmode:
          if (!register_operand (operands[0], E_DFmode)
              || GET_MODE (x2) != E_DFmode
              || GET_MODE (x4) != E_DFmode)
            return -1;
          switch (GET_MODE (operands[1]))
            {
            case E_VNx1DFmode:
              if (!register_operand (operands[1], E_VNx1DFmode)
                  || !(
#line 7035 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5776; /* *pred_extract_firstvnx1df */

            case E_VNx2DFmode:
              if (!register_operand (operands[1], E_VNx2DFmode)
                  || !(
#line 7035 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5777; /* *pred_extract_firstvnx2df */

            case E_VNx4DFmode:
              if (!register_operand (operands[1], E_VNx4DFmode)
                  || !(
#line 7035 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5778; /* *pred_extract_firstvnx4df */

            case E_VNx8DFmode:
              if (!register_operand (operands[1], E_VNx8DFmode)
                  || !(
#line 7035 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5779; /* *pred_extract_firstvnx8df */

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_16 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  switch (GET_MODE (operands[0]))
    {
    case E_DImode:
      if (!register_operand (operands[0], E_DImode))
        return -1;
      x2 = XEXP (x1, 1);
      if (GET_MODE (x2) != E_DImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_SImode:
          if (!nonimmediate_operand (operands[1], E_SImode))
            return -1;
          if (
#line 1371 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && !(register_operand (operands[1], SImode)
        && reg_or_subregno (operands[1]) == VL_REGNUM)))
            return 110; /* *zero_extendsidi2_internal */
          if (!
#line 25 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA))
            return -1;
          return 331; /* *zero_extendsidi2_bitmanip */

        case E_HImode:
          if (!nonimmediate_operand (operands[1], E_HImode))
            return -1;
          if ((
#line 1398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return 112; /* *zero_extendhidi2 */
          if (!(
#line 269 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 354; /* *zero_extendhidi2_bitmanip */

        case E_QImode:
          if (!nonimmediate_operand (operands[1], E_QImode)
              || !
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 115; /* zero_extendqidi2 */

        default:
          return -1;
        }

    case E_SImode:
      if (!register_operand (operands[0], E_SImode))
        return -1;
      x2 = XEXP (x1, 1);
      if (GET_MODE (x2) != E_SImode)
        return -1;
      switch (GET_MODE (operands[1]))
        {
        case E_HImode:
          if (!nonimmediate_operand (operands[1], E_HImode))
            return -1;
          if (
#line 1398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB))
            return 111; /* *zero_extendhisi2 */
          if (!
#line 269 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB))
            return -1;
          return 353; /* *zero_extendhisi2_bitmanip */

        case E_QImode:
          if (!nonimmediate_operand (operands[1], E_QImode))
            return -1;
          return 114; /* zero_extendqisi2 */

        default:
          return -1;
        }

    case E_HImode:
      if (!register_operand (operands[0], E_HImode))
        return -1;
      x2 = XEXP (x1, 1);
      if (GET_MODE (x2) != E_HImode
          || !nonimmediate_operand (operands[1], E_QImode))
        return -1;
      return 113; /* zero_extendqihi2 */

    default:
      return -1;
    }
}

static int
recog_17 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  operands[1] = x2;
  switch (GET_MODE (operands[0]))
    {
    case E_HFmode:
      if (!nonimmediate_operand (operands[0], E_HFmode)
          || !move_operand (operands[1], E_HFmode))
        return -1;
      if (
#line 1513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZFHMIN
   && (register_operand (operands[0], HFmode)
       || reg_or_0_operand (operands[1], HFmode))))
        return 126; /* *movhf_hardfloat */
      if (!
#line 1523 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZFHMIN
   && (register_operand (operands[0], HFmode)
       || reg_or_0_operand (operands[1], HFmode))))
        return -1;
      return 127; /* *movhf_softfloat */

    case E_SImode:
      if (register_operand (operands[0], E_SImode)
          && splittable_const_int_operand (operands[1], E_SImode)
          && 
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!(p2m1_shift_operand (operands[1], SImode)
     || high_mask_shift_operand (operands[1], SImode))))
        return 176; /* *mvconst_internal */
      if (!nonimmediate_operand (operands[0], E_SImode)
          || !move_operand (operands[1], E_SImode)
          || !
#line 1752 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((register_operand (operands[0], SImode)
    || reg_or_0_operand (operands[1], SImode))
    && !(register_operand (operands[1], SImode)
         && reg_or_subregno (operands[1]) == VL_REGNUM)))
        return -1;
      return 180; /* *movsi_internal */

    case E_DImode:
      if (register_operand (operands[0], E_DImode)
          && splittable_const_int_operand (operands[1], E_DImode)
          && (
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!(p2m1_shift_operand (operands[1], DImode)
     || high_mask_shift_operand (operands[1], DImode))) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
        return 177; /* *mvconst_internal */
      if (!nonimmediate_operand (operands[0], E_DImode)
          || !move_operand (operands[1], E_DImode))
        return -1;
      if (
#line 1719 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_64BIT
   && (register_operand (operands[0], DImode)
       || reg_or_0_operand (operands[1], DImode))))
        return 178; /* *movdi_32bit */
      if (!
#line 1730 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (register_operand (operands[0], DImode)
       || reg_or_0_operand (operands[1], DImode))))
        return -1;
      return 179; /* *movdi_64bit */

    case E_HImode:
      if (!nonimmediate_operand (operands[0], E_HImode)
          || !move_operand (operands[1], E_HImode)
          || !
#line 1780 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((register_operand (operands[0], HImode)
    || reg_or_0_operand (operands[1], HImode))))
        return -1;
      return 181; /* *movhi_internal */

    case E_QImode:
      if (!nonimmediate_operand (operands[0], E_QImode)
          || !move_operand (operands[1], E_QImode)
          || !
#line 1823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((register_operand (operands[0], QImode)
    || reg_or_0_operand (operands[1], QImode))))
        return -1;
      return 186; /* *movqi_internal */

    case E_SFmode:
      if (!nonimmediate_operand (operands[0], E_SFmode)
          || !move_operand (operands[1], E_SFmode))
        return -1;
      if (
#line 1844 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT
   && (register_operand (operands[0], SFmode)
       || reg_or_0_operand (operands[1], SFmode))))
        return 187; /* *movsf_hardfloat */
      if (!
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_HARD_FLOAT
   && (register_operand (operands[0], SFmode)
       || reg_or_0_operand (operands[1], SFmode))))
        return -1;
      return 188; /* *movsf_softfloat */

    case E_DFmode:
      if (!nonimmediate_operand (operands[0], E_DFmode)
          || !move_operand (operands[1], E_DFmode))
        return -1;
      if (
#line 1878 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_64BIT && TARGET_DOUBLE_FLOAT
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode))))
        return 189; /* *movdf_hardfloat_rv32 */
      if (
#line 1888 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && TARGET_DOUBLE_FLOAT
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode))))
        return 190; /* *movdf_hardfloat_rv64 */
      if (!
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_DOUBLE_FLOAT
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode))))
        return -1;
      return 191; /* *movdf_softfloat */

    case E_VNx1SImode:
      if (reg_or_mem_operand (operands[0], E_VNx1SImode)
          && reg_or_mem_operand (operands[1], E_VNx1SImode)
          && (
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 375 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN == 32)))
        return 733; /* *movvnx1si_whole */
      if (register_operand (operands[0], E_VNx1SImode)
          && register_operand (operands[1], E_VNx1SImode)
          && (
#line 616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 756; /* *movvnx1si_fract */
      if (pnum_clobbers == NULL
          || !reg_or_mem_operand (operands[0], E_VNx1SImode)
          || !reg_or_mem_operand (operands[1], E_VNx1SImode))
        return -1;
      if ((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
        {
          *pnum_clobbers = 1;
          return 775; /* *movvnx1sisi_lra */
        }
      if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
        return -1;
      *pnum_clobbers = 1;
      return 776; /* *movvnx1sidi_lra */

    case E_VNx1DImode:
      if (!reg_or_mem_operand (operands[0], E_VNx1DImode)
          || !reg_or_mem_operand (operands[1], E_VNx1DImode)
          || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 376 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 738; /* *movvnx1di_whole */

    case E_VNx1SFmode:
      if (reg_or_mem_operand (operands[0], E_VNx1SFmode)
          && reg_or_mem_operand (operands[1], E_VNx1SFmode)
          && (
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 378 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN == 32)))
        return 742; /* *movvnx1sf_whole */
      if (register_operand (operands[0], E_VNx1SFmode)
          && register_operand (operands[1], E_VNx1SFmode)
          && (
#line 616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return 757; /* *movvnx1sf_fract */
      if (pnum_clobbers == NULL
          || !reg_or_mem_operand (operands[0], E_VNx1SFmode)
          || !reg_or_mem_operand (operands[1], E_VNx1SFmode))
        return -1;
      if ((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
        {
          *pnum_clobbers = 1;
          return 777; /* *movvnx1sfsi_lra */
        }
      if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
        return -1;
      *pnum_clobbers = 1;
      return 778; /* *movvnx1sfdi_lra */

    case E_VNx1DFmode:
      if (!reg_or_mem_operand (operands[0], E_VNx1DFmode)
          || !reg_or_mem_operand (operands[1], E_VNx1DFmode)
          || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 383 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 747; /* *movvnx1df_whole */

    case E_VNx1QImode:
      if (register_operand (operands[0], E_VNx1QImode)
          && register_operand (operands[1], E_VNx1QImode)
          && 
#line 616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 751; /* *movvnx1qi_fract */
      if (pnum_clobbers == NULL
          || !reg_or_mem_operand (operands[0], E_VNx1QImode)
          || !reg_or_mem_operand (operands[1], E_VNx1QImode))
        return -1;
      if ((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        {
          *pnum_clobbers = 1;
          return 765; /* *movvnx1qisi_lra */
        }
      if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return -1;
      *pnum_clobbers = 1;
      return 766; /* *movvnx1qidi_lra */

    case E_VNx1HImode:
      if (register_operand (operands[0], E_VNx1HImode)
          && register_operand (operands[1], E_VNx1HImode)
          && 
#line 616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 754; /* *movvnx1hi_fract */
      if (pnum_clobbers == NULL
          || !reg_or_mem_operand (operands[0], E_VNx1HImode)
          || !reg_or_mem_operand (operands[1], E_VNx1HImode))
        return -1;
      if ((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        {
          *pnum_clobbers = 1;
          return 771; /* *movvnx1hisi_lra */
        }
      if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return -1;
      *pnum_clobbers = 1;
      return 772; /* *movvnx1hidi_lra */

    case E_VNx1BImode:
      if (register_operand (operands[0], E_VNx1BImode)
          && register_operand (operands[1], E_VNx1BImode)
          && 
#line 633 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 758; /* *movvnx1bi */
      if (pnum_clobbers == NULL
          || !reg_or_mem_operand (operands[0], E_VNx1BImode)
          || !reg_or_mem_operand (operands[1], E_VNx1BImode))
        return -1;
      if ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        {
          *pnum_clobbers = 1;
          return 779; /* *movvnx1bisi_lra */
        }
      if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return -1;
      *pnum_clobbers = 1;
      return 786; /* *movvnx1bidi_lra */

    case E_VNx2BImode:
      if (register_operand (operands[0], E_VNx2BImode)
          && register_operand (operands[1], E_VNx2BImode)
          && 
#line 633 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 759; /* *movvnx2bi */
      if (pnum_clobbers == NULL
          || !reg_or_mem_operand (operands[0], E_VNx2BImode)
          || !reg_or_mem_operand (operands[1], E_VNx2BImode))
        return -1;
      if ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        {
          *pnum_clobbers = 1;
          return 780; /* *movvnx2bisi_lra */
        }
      if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return -1;
      *pnum_clobbers = 1;
      return 787; /* *movvnx2bidi_lra */

    case E_VNx4BImode:
      if (register_operand (operands[0], E_VNx4BImode)
          && register_operand (operands[1], E_VNx4BImode)
          && 
#line 633 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 760; /* *movvnx4bi */
      if (pnum_clobbers == NULL
          || !reg_or_mem_operand (operands[0], E_VNx4BImode)
          || !reg_or_mem_operand (operands[1], E_VNx4BImode))
        return -1;
      if ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        {
          *pnum_clobbers = 1;
          return 781; /* *movvnx4bisi_lra */
        }
      if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return -1;
      *pnum_clobbers = 1;
      return 788; /* *movvnx4bidi_lra */

    case E_VNx8BImode:
      if (register_operand (operands[0], E_VNx8BImode)
          && register_operand (operands[1], E_VNx8BImode)
          && 
#line 633 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 761; /* *movvnx8bi */
      if (pnum_clobbers == NULL
          || !reg_or_mem_operand (operands[0], E_VNx8BImode)
          || !reg_or_mem_operand (operands[1], E_VNx8BImode))
        return -1;
      if ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        {
          *pnum_clobbers = 1;
          return 782; /* *movvnx8bisi_lra */
        }
      if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return -1;
      *pnum_clobbers = 1;
      return 789; /* *movvnx8bidi_lra */

    case E_VNx16BImode:
      if (register_operand (operands[0], E_VNx16BImode)
          && register_operand (operands[1], E_VNx16BImode)
          && 
#line 633 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 762; /* *movvnx16bi */
      if (pnum_clobbers == NULL
          || !reg_or_mem_operand (operands[0], E_VNx16BImode)
          || !reg_or_mem_operand (operands[1], E_VNx16BImode))
        return -1;
      if ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        {
          *pnum_clobbers = 1;
          return 783; /* *movvnx16bisi_lra */
        }
      if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return -1;
      *pnum_clobbers = 1;
      return 790; /* *movvnx16bidi_lra */

    case E_VNx32BImode:
      if (register_operand (operands[0], E_VNx32BImode)
          && register_operand (operands[1], E_VNx32BImode)
          && 
#line 633 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 763; /* *movvnx32bi */
      if (pnum_clobbers == NULL
          || !reg_or_mem_operand (operands[0], E_VNx32BImode)
          || !reg_or_mem_operand (operands[1], E_VNx32BImode))
        return -1;
      if ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        {
          *pnum_clobbers = 1;
          return 784; /* *movvnx32bisi_lra */
        }
      if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return -1;
      *pnum_clobbers = 1;
      return 791; /* *movvnx32bidi_lra */

    case E_VNx64BImode:
      if (register_operand (operands[0], E_VNx64BImode)
          && register_operand (operands[1], E_VNx64BImode)
          && (
#line 633 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 764; /* *movvnx64bi */
      if (pnum_clobbers == NULL
          || !reg_or_mem_operand (operands[0], E_VNx64BImode)
          || !reg_or_mem_operand (operands[1], E_VNx64BImode))
        return -1;
      if ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
        {
          *pnum_clobbers = 1;
          return 785; /* *movvnx64bisi_lra */
        }
      if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
        return -1;
      *pnum_clobbers = 1;
      return 792; /* *movvnx64bidi_lra */

    default:
      return -1;
    }
}

static int
recog_18 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  res = recog_17 (x1, insn, pnum_clobbers);
  if (res >= 0)
    return res;
  if (pnum_clobbers == NULL
      || GET_CODE (x2) != MEM)
    return -1;
  x3 = XEXP (x2, 0);
  operands[0] = x3;
  if (!absolute_symbolic_operand (operands[0], E_VOIDmode))
    return -1;
  x4 = XEXP (x1, 1);
  operands[1] = x4;
  switch (GET_MODE (x2))
    {
    case E_QImode:
      if (!reg_or_0_operand (operands[1], E_QImode))
        return -1;
      if ((
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        {
          *pnum_clobbers = 1;
          return 546; /* *local_pic_storeqi */
        }
      if (!(
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return -1;
      *pnum_clobbers = 1;
      return 550; /* *local_pic_storeqi */

    case E_HImode:
      if (!reg_or_0_operand (operands[1], E_HImode))
        return -1;
      if ((
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        {
          *pnum_clobbers = 1;
          return 547; /* *local_pic_storehi */
        }
      if (!(
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return -1;
      *pnum_clobbers = 1;
      return 551; /* *local_pic_storehi */

    case E_SImode:
      if (!reg_or_0_operand (operands[1], E_SImode))
        return -1;
      if ((
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        {
          *pnum_clobbers = 1;
          return 548; /* *local_pic_storesi */
        }
      if (!(
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return -1;
      *pnum_clobbers = 1;
      return 552; /* *local_pic_storesi */

    case E_DImode:
      if (!reg_or_0_operand (operands[1], E_DImode))
        return -1;
      if ((
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
        {
          *pnum_clobbers = 1;
          return 549; /* *local_pic_storedi */
        }
      if (!(
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
        return -1;
      *pnum_clobbers = 1;
      return 553; /* *local_pic_storedi */

    case E_SFmode:
      if (!register_operand (operands[1], E_SFmode))
        return -1;
      if ((
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
        {
          *pnum_clobbers = 1;
          return 554; /* *local_pic_storesf */
        }
      if ((
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
        {
          *pnum_clobbers = 1;
          return 557; /* *local_pic_storesf */
        }
      if ((
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        {
          *pnum_clobbers = 1;
          return 566; /* *local_pic_store_sfsf */
        }
      if (!(
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return -1;
      *pnum_clobbers = 1;
      return 569; /* *local_pic_store_sfsf */

    case E_DFmode:
      if (!register_operand (operands[1], E_DFmode))
        return -1;
      if ((
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
        {
          *pnum_clobbers = 1;
          return 555; /* *local_pic_storedf */
        }
      if ((
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
        {
          *pnum_clobbers = 1;
          return 558; /* *local_pic_storedf */
        }
      if ((
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
        {
          *pnum_clobbers = 1;
          return 567; /* *local_pic_store_sfdf */
        }
      if (!(
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
        return -1;
      *pnum_clobbers = 1;
      return 570; /* *local_pic_store_sfdf */

    case E_HFmode:
      if (!register_operand (operands[1], E_HFmode))
        return -1;
      if ((
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
        {
          *pnum_clobbers = 1;
          return 556; /* *local_pic_storehf */
        }
      if ((
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
        {
          *pnum_clobbers = 1;
          return 559; /* *local_pic_storehf */
        }
      if ((
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFHMIN) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
        {
          *pnum_clobbers = 1;
          return 568; /* *local_pic_store_sfhf */
        }
      if (!(
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFHMIN) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
        return -1;
      *pnum_clobbers = 1;
      return 571; /* *local_pic_store_sfhf */

    default:
      return -1;
    }
}

static int
recog_19 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  operands[1] = x3;
  if (!absolute_symbolic_operand (operands[1], E_VOIDmode))
    return -1;
  switch (GET_MODE (operands[0]))
    {
    case E_QImode:
      if (!register_operand (operands[0], E_QImode)
          || GET_MODE (x2) != E_QImode
          || !
#line 28 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])))
        return -1;
      return 509; /* *local_pic_loadqi */

    case E_HImode:
      if (!register_operand (operands[0], E_HImode)
          || GET_MODE (x2) != E_HImode
          || !
#line 28 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])))
        return -1;
      return 510; /* *local_pic_loadhi */

    case E_SImode:
      if (!register_operand (operands[0], E_SImode)
          || GET_MODE (x2) != E_SImode
          || !
#line 28 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])))
        return -1;
      return 511; /* *local_pic_loadsi */

    case E_DImode:
      if (!register_operand (operands[0], E_DImode)
          || GET_MODE (x2) != E_DImode
          || !(
#line 28 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
        return -1;
      return 512; /* *local_pic_loaddi */

    case E_SFmode:
      if (!register_operand (operands[0], E_SFmode)
          || GET_MODE (x2) != E_SFmode)
        return -1;
      if (pnum_clobbers != NULL)
        {
          if ((
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            {
              *pnum_clobbers = 1;
              return 531; /* *local_pic_loadsf */
            }
          if ((
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            {
              *pnum_clobbers = 1;
              return 534; /* *local_pic_loadsf */
            }
          if ((
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            {
              *pnum_clobbers = 1;
              return 537; /* *local_pic_load_32dsf */
            }
          if ((
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            {
              *pnum_clobbers = 1;
              return 540; /* *local_pic_load_32dsf */
            }
        }
      if (
#line 76 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])))
        return 543; /* *local_pic_load_sfsf */
      if (pnum_clobbers == NULL)
        return -1;
      if ((
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
        {
          *pnum_clobbers = 1;
          return 560; /* *local_pic_store_32dsf */
        }
      if (!(
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
        return -1;
      *pnum_clobbers = 1;
      return 563; /* *local_pic_store_32dsf */

    case E_DFmode:
      if (!register_operand (operands[0], E_DFmode)
          || GET_MODE (x2) != E_DFmode)
        return -1;
      if (pnum_clobbers != NULL)
        {
          if ((
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            {
              *pnum_clobbers = 1;
              return 532; /* *local_pic_loaddf */
            }
          if ((
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            {
              *pnum_clobbers = 1;
              return 535; /* *local_pic_loaddf */
            }
          if ((
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            {
              *pnum_clobbers = 1;
              return 538; /* *local_pic_load_32ddf */
            }
          if ((
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            {
              *pnum_clobbers = 1;
              return 541; /* *local_pic_load_32ddf */
            }
        }
      if ((
#line 76 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
        return 544; /* *local_pic_load_sfdf */
      if (pnum_clobbers == NULL)
        return -1;
      if ((
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
        {
          *pnum_clobbers = 1;
          return 561; /* *local_pic_store_32ddf */
        }
      if (!(
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
        return -1;
      *pnum_clobbers = 1;
      return 564; /* *local_pic_store_32ddf */

    case E_HFmode:
      if (!register_operand (operands[0], E_HFmode)
          || GET_MODE (x2) != E_HFmode)
        return -1;
      if (pnum_clobbers != NULL)
        {
          if ((
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            {
              *pnum_clobbers = 1;
              return 533; /* *local_pic_loadhf */
            }
          if ((
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            {
              *pnum_clobbers = 1;
              return 536; /* *local_pic_loadhf */
            }
          if ((
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            {
              *pnum_clobbers = 1;
              return 539; /* *local_pic_load_32dhf */
            }
          if ((
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            {
              *pnum_clobbers = 1;
              return 542; /* *local_pic_load_32dhf */
            }
        }
      if ((
#line 76 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFHMIN)))
        return 545; /* *local_pic_load_sfhf */
      if (pnum_clobbers == NULL)
        return -1;
      if ((
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
        {
          *pnum_clobbers = 1;
          return 562; /* *local_pic_store_32dhf */
        }
      if (!(
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
        return -1;
      *pnum_clobbers = 1;
      return 565; /* *local_pic_store_32dhf */

    default:
      return -1;
    }
}

static int
recog_20 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XEXP (x3, 1);
  if (GET_CODE (x4) != CONST_INT)
    return -1;
  x5 = XEXP (x3, 0);
  switch (GET_CODE (x5))
    {
    case AND:
      if (pnum_clobbers == NULL)
        return -1;
      x6 = XEXP (x2, 1);
      if (GET_CODE (x6) != LABEL_REF)
        return -1;
      x7 = XEXP (x2, 2);
      if (GET_CODE (x7) != PC)
        return -1;
      x8 = XEXP (x1, 0);
      if (GET_CODE (x8) != PC)
        return -1;
      operands[1] = x3;
      x9 = XEXP (x5, 0);
      operands[2] = x9;
      x10 = XEXP (x5, 1);
      operands[3] = x10;
      x11 = XEXP (x6, 0);
      operands[0] = x11;
      if (XWINT (x4, 0) == 0L)
        {
          switch (GET_MODE (x5))
            {
            case E_QImode:
              if (register_operand (operands[2], E_QImode))
                {
                  if (shifted_const_arith_operand (operands[3], E_VOIDmode))
                    {
                      if ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 226; /* *branchqi_shiftedarith_equals_zero */
                        }
                      if ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 229; /* *branchqi_shiftedarith_equals_zero */
                        }
                    }
                  if (consecutive_bits_operand (operands[3], E_VOIDmode))
                    {
                      if ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 233; /* *branchqi_shiftedmask_equals_zero */
                        }
                      if ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 237; /* *branchqi_shiftedmask_equals_zero */
                        }
                    }
                }
              break;

            case E_HImode:
              if (register_operand (operands[2], E_HImode))
                {
                  if (shifted_const_arith_operand (operands[3], E_VOIDmode))
                    {
                      if ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 227; /* *branchhi_shiftedarith_equals_zero */
                        }
                      if ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 230; /* *branchhi_shiftedarith_equals_zero */
                        }
                    }
                  if (consecutive_bits_operand (operands[3], E_VOIDmode))
                    {
                      if ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 234; /* *branchhi_shiftedmask_equals_zero */
                        }
                      if ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 238; /* *branchhi_shiftedmask_equals_zero */
                        }
                    }
                }
              break;

            case E_SImode:
              if (register_operand (operands[2], E_SImode))
                {
                  if (shifted_const_arith_operand (operands[3], E_VOIDmode))
                    {
                      if ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 228; /* *branchsi_shiftedarith_equals_zero */
                        }
                      if ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 231; /* *branchsi_shiftedarith_equals_zero */
                        }
                    }
                  if (consecutive_bits_operand (operands[3], E_VOIDmode))
                    {
                      if ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 235; /* *branchsi_shiftedmask_equals_zero */
                        }
                      if ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 239; /* *branchsi_shiftedmask_equals_zero */
                        }
                    }
                }
              break;

            case E_DImode:
              if (register_operand (operands[2], E_DImode))
                {
                  if (shifted_const_arith_operand (operands[3], E_VOIDmode)
                      && (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    {
                      *pnum_clobbers = 1;
                      return 232; /* *branchdi_shiftedarith_equals_zero */
                    }
                  if (consecutive_bits_operand (operands[3], E_VOIDmode))
                    {
                      if ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && ((((
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))))
                        {
                          *pnum_clobbers = 1;
                          return 236; /* *branchdi_shiftedmask_equals_zero */
                        }
                      if ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                        {
                          *pnum_clobbers = 1;
                          return 240; /* *branchdi_shiftedmask_equals_zero */
                        }
                    }
                }
              break;

            default:
              break;
            }
        }
      operands[4] = x4;
      switch (GET_MODE (x5))
        {
        case E_SImode:
          if (!register_operand (operands[2], E_SImode)
              || !const_twobits_not_arith_operand (operands[3], E_SImode)
              || !single_bit_mask_operand (operands[4], E_SImode)
              || !(
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          *pnum_clobbers = 2;
          return 419; /* *branchsi_mask_twobits_equals_singlebit */

        case E_DImode:
          if (!register_operand (operands[2], E_DImode)
              || !const_twobits_not_arith_operand (operands[3], E_DImode)
              || !single_bit_mask_operand (operands[4], E_DImode)
              || !(
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          *pnum_clobbers = 2;
          return 420; /* *branchdi_mask_twobits_equals_singlebit */

        default:
          return -1;
        }

    case ZERO_EXTRACT:
      if (pnum_clobbers == NULL)
        return -1;
      x10 = XEXP (x5, 1);
      if (GET_CODE (x10) != CONST_INT
          || XWINT (x4, 0) != 0L)
        return -1;
      x6 = XEXP (x2, 1);
      if (GET_CODE (x6) != LABEL_REF)
        return -1;
      x7 = XEXP (x2, 2);
      if (GET_CODE (x7) != PC)
        return -1;
      x8 = XEXP (x1, 0);
      if (GET_CODE (x8) != PC)
        return -1;
      operands[0] = x3;
      x9 = XEXP (x5, 0);
      operands[2] = x9;
      x11 = XEXP (x6, 0);
      operands[1] = x11;
      if (XWINT (x10, 0) == 1L)
        {
          x12 = XEXP (x5, 2);
          operands[3] = x12;
          if (branch_on_bit_operand (operands[3], E_VOIDmode))
            {
              switch (GET_MODE (x5))
                {
                case E_SImode:
                  if (register_operand (operands[2], E_SImode)
                      && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
                    {
                      *pnum_clobbers = 1;
                      return 246; /* *branch_on_bitsi */
                    }
                  break;

                case E_DImode:
                  if (register_operand (operands[2], E_DImode)
                      && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
                    {
                      *pnum_clobbers = 1;
                      return 247; /* *branch_on_bitdi */
                    }
                  break;

                default:
                  break;
                }
            }
        }
      x12 = XEXP (x5, 2);
      if (x12 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
        return -1;
      operands[3] = x10;
      if (!branch_on_bit_operand (operands[3], E_VOIDmode))
        return -1;
      switch (GET_MODE (x5))
        {
        case E_SImode:
          if (!register_operand (operands[2], E_SImode)
              || !
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
            return -1;
          *pnum_clobbers = 1;
          return 248; /* *branch_on_bit_rangesi */

        case E_DImode:
          if (!register_operand (operands[2], E_DImode)
              || !
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          *pnum_clobbers = 1;
          return 249; /* *branch_on_bit_rangedi */

        default:
          return -1;
        }

    case REG:
    case SUBREG:
      operands[1] = x5;
      if (!register_operand (operands[1], E_SImode)
          || XWINT (x4, 0) != 0L)
        return -1;
      x8 = XEXP (x1, 0);
      operands[0] = x8;
      if (!register_operand (operands[0], E_DImode)
          || GET_MODE (x2) != E_DImode)
        return -1;
      operands[4] = x3;
      x6 = XEXP (x2, 1);
      operands[2] = x6;
      if (!reg_or_0_operand (operands[2], E_DImode))
        return -1;
      x7 = XEXP (x2, 2);
      operands[3] = x7;
      if (!reg_or_0_operand (operands[3], E_DImode)
          || !(
#line 115 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADCONDMOV) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
        return -1;
      return 587; /* *th_cond_movdisi */

    default:
      return -1;
    }
}

static int
recog_21 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  switch (GET_CODE (x3))
    {
    case LABEL_REF:
      x4 = XEXP (x2, 2);
      if (GET_CODE (x4) != PC)
        return -1;
      x5 = XEXP (x1, 0);
      if (GET_CODE (x5) != PC)
        return -1;
      x6 = XEXP (x2, 0);
      operands[1] = x6;
      x7 = XEXP (x6, 0);
      operands[2] = x7;
      x8 = XEXP (x6, 1);
      operands[3] = x8;
      x9 = XEXP (x3, 0);
      operands[0] = x9;
      switch (GET_MODE (operands[2]))
        {
        case E_SImode:
          if (!register_operand (operands[2], E_SImode)
              || !reg_or_0_operand (operands[3], E_SImode)
              || !
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
            return -1;
          return 241; /* *branchsi */

        case E_DImode:
          if (!register_operand (operands[2], E_DImode)
              || !reg_or_0_operand (operands[3], E_DImode)
              || !
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 242; /* *branchdi */

        default:
          return -1;
        }

    case REG:
    case SUBREG:
      operands[3] = x3;
      x5 = XEXP (x1, 0);
      operands[0] = x5;
      x6 = XEXP (x2, 0);
      operands[5] = x6;
      x7 = XEXP (x6, 0);
      operands[1] = x7;
      x8 = XEXP (x6, 1);
      operands[2] = x8;
      x4 = XEXP (x2, 2);
      operands[4] = x4;
      switch (pattern86 (x2))
        {
        case 0:
          if (!register_operand (operands[3], E_SImode)
              || !sfb_alu_operand (operands[4], E_SImode))
            return -1;
          switch (GET_MODE (operands[1]))
            {
            case E_SImode:
              if (!register_operand (operands[1], E_SImode)
                  || !reg_or_0_operand (operands[2], E_SImode)
                  || !(
#line 2345 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 243; /* *movsisicc */

            case E_DImode:
              if (!register_operand (operands[1], E_DImode)
                  || !reg_or_0_operand (operands[2], E_DImode)
                  || !(
#line 2345 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 244; /* *movsidicc */

            default:
              return -1;
            }

        case 1:
          if (!register_operand (operands[1], E_DImode)
              || !reg_or_0_operand (operands[2], E_DImode)
              || !register_operand (operands[3], E_DImode)
              || !sfb_alu_operand (operands[4], E_DImode)
              || !(
#line 2345 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 245; /* *movdidicc */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_22 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern313 (x2))
    {
    case 0:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1031; /* pred_indexed_uloadvnx1qi_same_eew */

    case 1:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1193; /* pred_indexed_uloadvnx1qi_x2_smaller_eew */

    case 2:
      if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1231; /* pred_indexed_uloadvnx1qi_x4_smaller_eew */

    case 3:
      if (!
#line 1546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1249; /* pred_indexed_uloadvnx1qi_x8_smaller_eew */

    case 4:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1033; /* pred_indexed_uloadvnx2qi_same_eew */

    case 5:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1195; /* pred_indexed_uloadvnx2qi_x2_smaller_eew */

    case 6:
      if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1233; /* pred_indexed_uloadvnx2qi_x4_smaller_eew */

    case 7:
      if (!
#line 1546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1251; /* pred_indexed_uloadvnx2qi_x8_smaller_eew */

    case 8:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1035; /* pred_indexed_uloadvnx4qi_same_eew */

    case 9:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1197; /* pred_indexed_uloadvnx4qi_x2_smaller_eew */

    case 10:
      if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1235; /* pred_indexed_uloadvnx4qi_x4_smaller_eew */

    case 11:
      if (!
#line 1546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1253; /* pred_indexed_uloadvnx4qi_x8_smaller_eew */

    case 12:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1037; /* pred_indexed_uloadvnx8qi_same_eew */

    case 13:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1199; /* pred_indexed_uloadvnx8qi_x2_smaller_eew */

    case 14:
      if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1237; /* pred_indexed_uloadvnx8qi_x4_smaller_eew */

    case 15:
      if (!
#line 1546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1255; /* pred_indexed_uloadvnx8qi_x8_smaller_eew */

    case 16:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1039; /* pred_indexed_uloadvnx16qi_same_eew */

    case 17:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1201; /* pred_indexed_uloadvnx16qi_x2_smaller_eew */

    case 18:
      if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1239; /* pred_indexed_uloadvnx16qi_x4_smaller_eew */

    case 19:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1041; /* pred_indexed_uloadvnx32qi_same_eew */

    case 20:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1203; /* pred_indexed_uloadvnx32qi_x2_smaller_eew */

    case 21:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1043; /* pred_indexed_uloadvnx64qi_same_eew */

    case 22:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1045; /* pred_indexed_uloadvnx1hi_same_eew */

    case 23:
      if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1093; /* pred_indexed_uloadvnx1hi_x2_greater_eew */

    case 24:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1205; /* pred_indexed_uloadvnx1hi_x2_smaller_eew */

    case 25:
      if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1241; /* pred_indexed_uloadvnx1hi_x4_smaller_eew */

    case 26:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1047; /* pred_indexed_uloadvnx2hi_same_eew */

    case 27:
      if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1095; /* pred_indexed_uloadvnx2hi_x2_greater_eew */

    case 28:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1207; /* pred_indexed_uloadvnx2hi_x2_smaller_eew */

    case 29:
      if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1243; /* pred_indexed_uloadvnx2hi_x4_smaller_eew */

    case 30:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1049; /* pred_indexed_uloadvnx4hi_same_eew */

    case 31:
      if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1097; /* pred_indexed_uloadvnx4hi_x2_greater_eew */

    case 32:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1209; /* pred_indexed_uloadvnx4hi_x2_smaller_eew */

    case 33:
      if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1245; /* pred_indexed_uloadvnx4hi_x4_smaller_eew */

    case 34:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1051; /* pred_indexed_uloadvnx8hi_same_eew */

    case 35:
      if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1099; /* pred_indexed_uloadvnx8hi_x2_greater_eew */

    case 36:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1211; /* pred_indexed_uloadvnx8hi_x2_smaller_eew */

    case 37:
      if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1247; /* pred_indexed_uloadvnx8hi_x4_smaller_eew */

    case 38:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1053; /* pred_indexed_uloadvnx16hi_same_eew */

    case 39:
      if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1101; /* pred_indexed_uloadvnx16hi_x2_greater_eew */

    case 40:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1213; /* pred_indexed_uloadvnx16hi_x2_smaller_eew */

    case 41:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1055; /* pred_indexed_uloadvnx32hi_same_eew */

    case 42:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 103 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1103; /* pred_indexed_uloadvnx32hi_x2_greater_eew */

    case 43:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1057; /* pred_indexed_uloadvnx1si_same_eew */

    case 44:
      if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1105; /* pred_indexed_uloadvnx1si_x2_greater_eew */

    case 45:
      if (!
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1141; /* pred_indexed_uloadvnx1si_x4_greater_eew */

    case 46:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1215; /* pred_indexed_uloadvnx1si_x2_smaller_eew */

    case 47:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1059; /* pred_indexed_uloadvnx2si_same_eew */

    case 48:
      if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1107; /* pred_indexed_uloadvnx2si_x2_greater_eew */

    case 49:
      if (!
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1143; /* pred_indexed_uloadvnx2si_x4_greater_eew */

    case 50:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1217; /* pred_indexed_uloadvnx2si_x2_smaller_eew */

    case 51:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1061; /* pred_indexed_uloadvnx4si_same_eew */

    case 52:
      if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1109; /* pred_indexed_uloadvnx4si_x2_greater_eew */

    case 53:
      if (!
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1145; /* pred_indexed_uloadvnx4si_x4_greater_eew */

    case 54:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1219; /* pred_indexed_uloadvnx4si_x2_smaller_eew */

    case 55:
      if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1063; /* pred_indexed_uloadvnx8si_same_eew */

    case 56:
      if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1111; /* pred_indexed_uloadvnx8si_x2_greater_eew */

    case 57:
      if (!
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1147; /* pred_indexed_uloadvnx8si_x4_greater_eew */

    case 58:
      if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1221; /* pred_indexed_uloadvnx8si_x2_smaller_eew */

    case 59:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1065; /* pred_indexed_uloadvnx16si_same_eew */

    case 60:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 104 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1113; /* pred_indexed_uloadvnx16si_x2_greater_eew */

    case 61:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1149; /* pred_indexed_uloadvnx16si_x4_greater_eew */

    case 62:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1067; /* pred_indexed_uloadvnx1di_same_eew */

    case 63:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 105 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1115; /* pred_indexed_uloadvnx1di_x2_greater_eew */

    case 64:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1151; /* pred_indexed_uloadvnx1di_x4_greater_eew */

    case 65:
      if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 134 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1177; /* pred_indexed_uloadvnx1di_x8_greater_eew */

    case 66:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1069; /* pred_indexed_uloadvnx2di_same_eew */

    case 67:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 105 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1117; /* pred_indexed_uloadvnx2di_x2_greater_eew */

    case 68:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1153; /* pred_indexed_uloadvnx2di_x4_greater_eew */

    case 69:
      if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 134 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1179; /* pred_indexed_uloadvnx2di_x8_greater_eew */

    case 70:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1071; /* pred_indexed_uloadvnx4di_same_eew */

    case 71:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 106 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1119; /* pred_indexed_uloadvnx4di_x2_greater_eew */

    case 72:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 121 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1155; /* pred_indexed_uloadvnx4di_x4_greater_eew */

    case 73:
      if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1181; /* pred_indexed_uloadvnx4di_x8_greater_eew */

    case 74:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1073; /* pred_indexed_uloadvnx8di_same_eew */

    case 75:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 106 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1121; /* pred_indexed_uloadvnx8di_x2_greater_eew */

    case 76:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 121 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1157; /* pred_indexed_uloadvnx8di_x4_greater_eew */

    case 77:
      if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1183; /* pred_indexed_uloadvnx8di_x8_greater_eew */

    case 78:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1075; /* pred_indexed_uloadvnx1sf_same_eew */

    case 79:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1123; /* pred_indexed_uloadvnx1sf_x2_greater_eew */

    case 80:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 122 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1159; /* pred_indexed_uloadvnx1sf_x4_greater_eew */

    case 81:
      if (!(
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1223; /* pred_indexed_uloadvnx1sf_x2_smaller_eew */

    case 82:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1077; /* pred_indexed_uloadvnx2sf_same_eew */

    case 83:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 108 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1125; /* pred_indexed_uloadvnx2sf_x2_greater_eew */

    case 84:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 123 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1161; /* pred_indexed_uloadvnx2sf_x4_greater_eew */

    case 85:
      if (!(
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 147 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1225; /* pred_indexed_uloadvnx2sf_x2_smaller_eew */

    case 86:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1079; /* pred_indexed_uloadvnx4sf_same_eew */

    case 87:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1127; /* pred_indexed_uloadvnx4sf_x2_greater_eew */

    case 88:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1163; /* pred_indexed_uloadvnx4sf_x4_greater_eew */

    case 89:
      if (!(
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 148 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1227; /* pred_indexed_uloadvnx4sf_x2_smaller_eew */

    case 90:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1081; /* pred_indexed_uloadvnx8sf_same_eew */

    case 91:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1129; /* pred_indexed_uloadvnx8sf_x2_greater_eew */

    case 92:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 125 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1165; /* pred_indexed_uloadvnx8sf_x4_greater_eew */

    case 93:
      if (!(
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 149 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 1229; /* pred_indexed_uloadvnx8sf_x2_smaller_eew */

    case 94:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1083; /* pred_indexed_uloadvnx16sf_same_eew */

    case 95:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 111 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1131; /* pred_indexed_uloadvnx16sf_x2_greater_eew */

    case 96:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 126 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 1167; /* pred_indexed_uloadvnx16sf_x4_greater_eew */

    case 97:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1085; /* pred_indexed_uloadvnx1df_same_eew */

    case 98:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 112 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1133; /* pred_indexed_uloadvnx1df_x2_greater_eew */

    case 99:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 127 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1169; /* pred_indexed_uloadvnx1df_x4_greater_eew */

    case 100:
      if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 136 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1185; /* pred_indexed_uloadvnx1df_x8_greater_eew */

    case 101:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1087; /* pred_indexed_uloadvnx2df_same_eew */

    case 102:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 113 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1135; /* pred_indexed_uloadvnx2df_x2_greater_eew */

    case 103:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 128 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1171; /* pred_indexed_uloadvnx2df_x4_greater_eew */

    case 104:
      if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1187; /* pred_indexed_uloadvnx2df_x8_greater_eew */

    case 105:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1089; /* pred_indexed_uloadvnx4df_same_eew */

    case 106:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 114 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1137; /* pred_indexed_uloadvnx4df_x2_greater_eew */

    case 107:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 129 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1173; /* pred_indexed_uloadvnx4df_x4_greater_eew */

    case 108:
      if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 138 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1189; /* pred_indexed_uloadvnx4df_x8_greater_eew */

    case 109:
      if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1091; /* pred_indexed_uloadvnx8df_same_eew */

    case 110:
      if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 115 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1139; /* pred_indexed_uloadvnx8df_x2_greater_eew */

    case 111:
      if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1175; /* pred_indexed_uloadvnx8df_x4_greater_eew */

    case 112:
      if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 139 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 1191; /* pred_indexed_uloadvnx8df_x8_greater_eew */

    default:
      return -1;
    }
}

static int
recog_23 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XVECEXP (x3, 0, 0);
  operands[3] = x4;
  x5 = XVECEXP (x3, 0, 1);
  operands[4] = x5;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      if (pattern243 (x2, E_VNx1QImode, E_VNx1BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx1QImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5912; /* pred_gathervnx1qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5943; /* pred_gathervnx1qi_scalar */

    case E_VNx2QImode:
      if (pattern243 (x2, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx2QImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5913; /* pred_gathervnx2qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5944; /* pred_gathervnx2qi_scalar */

    case E_VNx4QImode:
      if (pattern243 (x2, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx4QImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5914; /* pred_gathervnx4qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5945; /* pred_gathervnx4qi_scalar */

    case E_VNx8QImode:
      if (pattern243 (x2, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx8QImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5915; /* pred_gathervnx8qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5946; /* pred_gathervnx8qi_scalar */

    case E_VNx16QImode:
      if (pattern243 (x2, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx16QImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5916; /* pred_gathervnx16qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5947; /* pred_gathervnx16qi_scalar */

    case E_VNx32QImode:
      if (pattern243 (x2, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx32QImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5917; /* pred_gathervnx32qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5948; /* pred_gathervnx32qi_scalar */

    case E_VNx64QImode:
      if (pattern243 (x2, E_VNx64QImode, E_VNx64BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx64QImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 5918; /* pred_gathervnx64qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5949; /* pred_gathervnx64qi_scalar */

    case E_VNx1HImode:
      if (pattern243 (x2, E_VNx1HImode, E_VNx1BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx1HImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5919; /* pred_gathervnx1hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5950; /* pred_gathervnx1hi_scalar */

    case E_VNx2HImode:
      if (pattern243 (x2, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx2HImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5920; /* pred_gathervnx2hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5951; /* pred_gathervnx2hi_scalar */

    case E_VNx4HImode:
      if (pattern243 (x2, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx4HImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5921; /* pred_gathervnx4hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5952; /* pred_gathervnx4hi_scalar */

    case E_VNx8HImode:
      if (pattern243 (x2, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx8HImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5922; /* pred_gathervnx8hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5953; /* pred_gathervnx8hi_scalar */

    case E_VNx16HImode:
      if (pattern243 (x2, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx16HImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5923; /* pred_gathervnx16hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5954; /* pred_gathervnx16hi_scalar */

    case E_VNx32HImode:
      if (pattern243 (x2, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx32HImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 5924; /* pred_gathervnx32hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5955; /* pred_gathervnx32hi_scalar */

    case E_VNx1SImode:
      if (pattern243 (x2, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx1SImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5925; /* pred_gathervnx1si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5956; /* pred_gathervnx1si_scalar */

    case E_VNx2SImode:
      if (pattern243 (x2, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx2SImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5926; /* pred_gathervnx2si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5957; /* pred_gathervnx2si_scalar */

    case E_VNx4SImode:
      if (pattern243 (x2, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx4SImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5927; /* pred_gathervnx4si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5958; /* pred_gathervnx4si_scalar */

    case E_VNx8SImode:
      if (pattern243 (x2, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx8SImode)
          && 
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 5928; /* pred_gathervnx8si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5959; /* pred_gathervnx8si_scalar */

    case E_VNx16SImode:
      if (pattern243 (x2, E_VNx16SImode, E_VNx16BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx16SImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 5929; /* pred_gathervnx16si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5960; /* pred_gathervnx16si_scalar */

    case E_VNx1DImode:
      if (pattern243 (x2, E_VNx1DImode, E_VNx1BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx1DImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 5930; /* pred_gathervnx1di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5961; /* pred_gathervnx1di_scalar */

    case E_VNx2DImode:
      if (pattern243 (x2, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx2DImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 5931; /* pred_gathervnx2di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5962; /* pred_gathervnx2di_scalar */

    case E_VNx4DImode:
      if (pattern243 (x2, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx4DImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 5932; /* pred_gathervnx4di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5963; /* pred_gathervnx4di_scalar */

    case E_VNx8DImode:
      if (pattern243 (x2, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx8DImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 5933; /* pred_gathervnx8di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5964; /* pred_gathervnx8di_scalar */

    case E_VNx1SFmode:
      if (pattern243 (x2, E_VNx1SFmode, E_VNx1BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx1SImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 5934; /* pred_gathervnx1sf */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5965; /* pred_gathervnx1sf_scalar */

    case E_VNx2SFmode:
      if (pattern243 (x2, E_VNx2SFmode, E_VNx2BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx2SImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 5935; /* pred_gathervnx2sf */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5966; /* pred_gathervnx2sf_scalar */

    case E_VNx4SFmode:
      if (pattern243 (x2, E_VNx4SFmode, E_VNx4BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx4SImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 5936; /* pred_gathervnx4sf */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5967; /* pred_gathervnx4sf_scalar */

    case E_VNx8SFmode:
      if (pattern243 (x2, E_VNx8SFmode, E_VNx8BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx8SImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 5937; /* pred_gathervnx8sf */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5968; /* pred_gathervnx8sf_scalar */

    case E_VNx16SFmode:
      if (pattern243 (x2, E_VNx16SFmode, E_VNx16BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx16SImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return 5938; /* pred_gathervnx16sf */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 5969; /* pred_gathervnx16sf_scalar */

    case E_VNx1DFmode:
      if (pattern243 (x2, E_VNx1DFmode, E_VNx1BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx1DImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 5939; /* pred_gathervnx1df */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5970; /* pred_gathervnx1df_scalar */

    case E_VNx2DFmode:
      if (pattern243 (x2, E_VNx2DFmode, E_VNx2BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx2DImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 5940; /* pred_gathervnx2df */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5971; /* pred_gathervnx2df_scalar */

    case E_VNx4DFmode:
      if (pattern243 (x2, E_VNx4DFmode, E_VNx4BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx4DImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 5941; /* pred_gathervnx4df */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5972; /* pred_gathervnx4df_scalar */

    case E_VNx8DFmode:
      if (pattern243 (x2, E_VNx8DFmode, E_VNx8BImode) != 0)
        return -1;
      if (register_operand (operands[4], E_VNx8DImode)
          && (
#line 7177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 5942; /* pred_gathervnx8df */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 7197 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5973; /* pred_gathervnx8df_scalar */

    default:
      return -1;
    }
}

static int
recog_24 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern245 (x2))
    {
    case 0:
      if (register_operand (operands[4], E_VNx1QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3475; /* pred_smulvnx1qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3629; /* pred_smulvnx1qi_scalar */

    case 1:
      if (register_operand (operands[4], E_VNx2QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3482; /* pred_smulvnx2qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3634; /* pred_smulvnx2qi_scalar */

    case 2:
      if (register_operand (operands[4], E_VNx4QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3489; /* pred_smulvnx4qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3639; /* pred_smulvnx4qi_scalar */

    case 3:
      if (register_operand (operands[4], E_VNx8QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3496; /* pred_smulvnx8qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3644; /* pred_smulvnx8qi_scalar */

    case 4:
      if (register_operand (operands[4], E_VNx16QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3503; /* pred_smulvnx16qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3649; /* pred_smulvnx16qi_scalar */

    case 5:
      if (register_operand (operands[4], E_VNx32QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3510; /* pred_smulvnx32qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3654; /* pred_smulvnx32qi_scalar */

    case 6:
      if (register_operand (operands[4], E_VNx64QImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3517; /* pred_smulvnx64qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3659; /* pred_smulvnx64qi_scalar */

    case 7:
      if (register_operand (operands[4], E_VNx1HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3524; /* pred_smulvnx1hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3664; /* pred_smulvnx1hi_scalar */

    case 8:
      if (register_operand (operands[4], E_VNx2HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3531; /* pred_smulvnx2hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3669; /* pred_smulvnx2hi_scalar */

    case 9:
      if (register_operand (operands[4], E_VNx4HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3538; /* pred_smulvnx4hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3674; /* pred_smulvnx4hi_scalar */

    case 10:
      if (register_operand (operands[4], E_VNx8HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3545; /* pred_smulvnx8hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3679; /* pred_smulvnx8hi_scalar */

    case 11:
      if (register_operand (operands[4], E_VNx16HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3552; /* pred_smulvnx16hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3684; /* pred_smulvnx16hi_scalar */

    case 12:
      if (register_operand (operands[4], E_VNx32HImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3559; /* pred_smulvnx32hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3689; /* pred_smulvnx32hi_scalar */

    case 13:
      if (register_operand (operands[4], E_VNx1SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3566; /* pred_smulvnx1si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3694; /* pred_smulvnx1si_scalar */

    case 14:
      if (register_operand (operands[4], E_VNx2SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3573; /* pred_smulvnx2si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3699; /* pred_smulvnx2si_scalar */

    case 15:
      if (register_operand (operands[4], E_VNx4SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3580; /* pred_smulvnx4si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3704; /* pred_smulvnx4si_scalar */

    case 16:
      if (register_operand (operands[4], E_VNx8SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3587; /* pred_smulvnx8si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3709; /* pred_smulvnx8si_scalar */

    case 17:
      if (register_operand (operands[4], E_VNx16SImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3594; /* pred_smulvnx16si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3714; /* pred_smulvnx16si_scalar */

    case 18:
      if (register_operand (operands[4], E_VNx1DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3601; /* pred_smulvnx1di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3763; /* *pred_smulvnx1di_scalar */

    case 19:
      if (register_operand (operands[4], E_VNx2DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3608; /* pred_smulvnx2di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3768; /* *pred_smulvnx2di_scalar */

    case 20:
      if (register_operand (operands[4], E_VNx4DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3615; /* pred_smulvnx4di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3773; /* *pred_smulvnx4di_scalar */

    case 21:
      if (register_operand (operands[4], E_VNx8DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3622; /* pred_smulvnx8di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3778; /* *pred_smulvnx8di_scalar */

    case 22:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3783; /* *pred_smulvnx1di_extended_scalar */

    case 23:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3788; /* *pred_smulvnx2di_extended_scalar */

    case 24:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3793; /* *pred_smulvnx4di_extended_scalar */

    case 25:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3798; /* *pred_smulvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_25 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern245 (x2))
    {
    case 0:
      if (register_operand (operands[4], E_VNx1QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3474; /* pred_asubvnx1qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3628; /* pred_asubvnx1qi_scalar */

    case 1:
      if (register_operand (operands[4], E_VNx2QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3481; /* pred_asubvnx2qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3633; /* pred_asubvnx2qi_scalar */

    case 2:
      if (register_operand (operands[4], E_VNx4QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3488; /* pred_asubvnx4qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3638; /* pred_asubvnx4qi_scalar */

    case 3:
      if (register_operand (operands[4], E_VNx8QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3495; /* pred_asubvnx8qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3643; /* pred_asubvnx8qi_scalar */

    case 4:
      if (register_operand (operands[4], E_VNx16QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3502; /* pred_asubvnx16qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3648; /* pred_asubvnx16qi_scalar */

    case 5:
      if (register_operand (operands[4], E_VNx32QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3509; /* pred_asubvnx32qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3653; /* pred_asubvnx32qi_scalar */

    case 6:
      if (register_operand (operands[4], E_VNx64QImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3516; /* pred_asubvnx64qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3658; /* pred_asubvnx64qi_scalar */

    case 7:
      if (register_operand (operands[4], E_VNx1HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3523; /* pred_asubvnx1hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3663; /* pred_asubvnx1hi_scalar */

    case 8:
      if (register_operand (operands[4], E_VNx2HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3530; /* pred_asubvnx2hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3668; /* pred_asubvnx2hi_scalar */

    case 9:
      if (register_operand (operands[4], E_VNx4HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3537; /* pred_asubvnx4hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3673; /* pred_asubvnx4hi_scalar */

    case 10:
      if (register_operand (operands[4], E_VNx8HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3544; /* pred_asubvnx8hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3678; /* pred_asubvnx8hi_scalar */

    case 11:
      if (register_operand (operands[4], E_VNx16HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3551; /* pred_asubvnx16hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3683; /* pred_asubvnx16hi_scalar */

    case 12:
      if (register_operand (operands[4], E_VNx32HImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3558; /* pred_asubvnx32hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3688; /* pred_asubvnx32hi_scalar */

    case 13:
      if (register_operand (operands[4], E_VNx1SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3565; /* pred_asubvnx1si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3693; /* pred_asubvnx1si_scalar */

    case 14:
      if (register_operand (operands[4], E_VNx2SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3572; /* pred_asubvnx2si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3698; /* pred_asubvnx2si_scalar */

    case 15:
      if (register_operand (operands[4], E_VNx4SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3579; /* pred_asubvnx4si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3703; /* pred_asubvnx4si_scalar */

    case 16:
      if (register_operand (operands[4], E_VNx8SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3586; /* pred_asubvnx8si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3708; /* pred_asubvnx8si_scalar */

    case 17:
      if (register_operand (operands[4], E_VNx16SImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3593; /* pred_asubvnx16si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3713; /* pred_asubvnx16si_scalar */

    case 18:
      if (register_operand (operands[4], E_VNx1DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3600; /* pred_asubvnx1di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3762; /* *pred_asubvnx1di_scalar */

    case 19:
      if (register_operand (operands[4], E_VNx2DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3607; /* pred_asubvnx2di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3767; /* *pred_asubvnx2di_scalar */

    case 20:
      if (register_operand (operands[4], E_VNx4DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3614; /* pred_asubvnx4di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3772; /* *pred_asubvnx4di_scalar */

    case 21:
      if (register_operand (operands[4], E_VNx8DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3621; /* pred_asubvnx8di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3777; /* *pred_asubvnx8di_scalar */

    case 22:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3782; /* *pred_asubvnx1di_extended_scalar */

    case 23:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3787; /* *pred_asubvnx2di_extended_scalar */

    case 24:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3792; /* *pred_asubvnx4di_extended_scalar */

    case 25:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3797; /* *pred_asubvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_26 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern245 (x2))
    {
    case 0:
      if (register_operand (operands[4], E_VNx1QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3473; /* pred_asubuvnx1qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3627; /* pred_asubuvnx1qi_scalar */

    case 1:
      if (register_operand (operands[4], E_VNx2QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3480; /* pred_asubuvnx2qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3632; /* pred_asubuvnx2qi_scalar */

    case 2:
      if (register_operand (operands[4], E_VNx4QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3487; /* pred_asubuvnx4qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3637; /* pred_asubuvnx4qi_scalar */

    case 3:
      if (register_operand (operands[4], E_VNx8QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3494; /* pred_asubuvnx8qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3642; /* pred_asubuvnx8qi_scalar */

    case 4:
      if (register_operand (operands[4], E_VNx16QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3501; /* pred_asubuvnx16qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3647; /* pred_asubuvnx16qi_scalar */

    case 5:
      if (register_operand (operands[4], E_VNx32QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3508; /* pred_asubuvnx32qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3652; /* pred_asubuvnx32qi_scalar */

    case 6:
      if (register_operand (operands[4], E_VNx64QImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3515; /* pred_asubuvnx64qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3657; /* pred_asubuvnx64qi_scalar */

    case 7:
      if (register_operand (operands[4], E_VNx1HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3522; /* pred_asubuvnx1hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3662; /* pred_asubuvnx1hi_scalar */

    case 8:
      if (register_operand (operands[4], E_VNx2HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3529; /* pred_asubuvnx2hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3667; /* pred_asubuvnx2hi_scalar */

    case 9:
      if (register_operand (operands[4], E_VNx4HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3536; /* pred_asubuvnx4hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3672; /* pred_asubuvnx4hi_scalar */

    case 10:
      if (register_operand (operands[4], E_VNx8HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3543; /* pred_asubuvnx8hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3677; /* pred_asubuvnx8hi_scalar */

    case 11:
      if (register_operand (operands[4], E_VNx16HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3550; /* pred_asubuvnx16hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3682; /* pred_asubuvnx16hi_scalar */

    case 12:
      if (register_operand (operands[4], E_VNx32HImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3557; /* pred_asubuvnx32hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3687; /* pred_asubuvnx32hi_scalar */

    case 13:
      if (register_operand (operands[4], E_VNx1SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3564; /* pred_asubuvnx1si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3692; /* pred_asubuvnx1si_scalar */

    case 14:
      if (register_operand (operands[4], E_VNx2SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3571; /* pred_asubuvnx2si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3697; /* pred_asubuvnx2si_scalar */

    case 15:
      if (register_operand (operands[4], E_VNx4SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3578; /* pred_asubuvnx4si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3702; /* pred_asubuvnx4si_scalar */

    case 16:
      if (register_operand (operands[4], E_VNx8SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3585; /* pred_asubuvnx8si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3707; /* pred_asubuvnx8si_scalar */

    case 17:
      if (register_operand (operands[4], E_VNx16SImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3592; /* pred_asubuvnx16si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3712; /* pred_asubuvnx16si_scalar */

    case 18:
      if (register_operand (operands[4], E_VNx1DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3599; /* pred_asubuvnx1di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3761; /* *pred_asubuvnx1di_scalar */

    case 19:
      if (register_operand (operands[4], E_VNx2DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3606; /* pred_asubuvnx2di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3766; /* *pred_asubuvnx2di_scalar */

    case 20:
      if (register_operand (operands[4], E_VNx4DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3613; /* pred_asubuvnx4di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3771; /* *pred_asubuvnx4di_scalar */

    case 21:
      if (register_operand (operands[4], E_VNx8DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3620; /* pred_asubuvnx8di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3776; /* *pred_asubuvnx8di_scalar */

    case 22:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3781; /* *pred_asubuvnx1di_extended_scalar */

    case 23:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3786; /* *pred_asubuvnx2di_extended_scalar */

    case 24:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3791; /* *pred_asubuvnx4di_extended_scalar */

    case 25:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3796; /* *pred_asubuvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_27 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern245 (x2))
    {
    case 0:
      if (register_operand (operands[4], E_VNx1QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3472; /* pred_aaddvnx1qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3626; /* pred_aaddvnx1qi_scalar */

    case 1:
      if (register_operand (operands[4], E_VNx2QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3479; /* pred_aaddvnx2qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3631; /* pred_aaddvnx2qi_scalar */

    case 2:
      if (register_operand (operands[4], E_VNx4QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3486; /* pred_aaddvnx4qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3636; /* pred_aaddvnx4qi_scalar */

    case 3:
      if (register_operand (operands[4], E_VNx8QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3493; /* pred_aaddvnx8qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3641; /* pred_aaddvnx8qi_scalar */

    case 4:
      if (register_operand (operands[4], E_VNx16QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3500; /* pred_aaddvnx16qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3646; /* pred_aaddvnx16qi_scalar */

    case 5:
      if (register_operand (operands[4], E_VNx32QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3507; /* pred_aaddvnx32qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3651; /* pred_aaddvnx32qi_scalar */

    case 6:
      if (register_operand (operands[4], E_VNx64QImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3514; /* pred_aaddvnx64qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3656; /* pred_aaddvnx64qi_scalar */

    case 7:
      if (register_operand (operands[4], E_VNx1HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3521; /* pred_aaddvnx1hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3661; /* pred_aaddvnx1hi_scalar */

    case 8:
      if (register_operand (operands[4], E_VNx2HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3528; /* pred_aaddvnx2hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3666; /* pred_aaddvnx2hi_scalar */

    case 9:
      if (register_operand (operands[4], E_VNx4HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3535; /* pred_aaddvnx4hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3671; /* pred_aaddvnx4hi_scalar */

    case 10:
      if (register_operand (operands[4], E_VNx8HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3542; /* pred_aaddvnx8hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3676; /* pred_aaddvnx8hi_scalar */

    case 11:
      if (register_operand (operands[4], E_VNx16HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3549; /* pred_aaddvnx16hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3681; /* pred_aaddvnx16hi_scalar */

    case 12:
      if (register_operand (operands[4], E_VNx32HImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3556; /* pred_aaddvnx32hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3686; /* pred_aaddvnx32hi_scalar */

    case 13:
      if (register_operand (operands[4], E_VNx1SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3563; /* pred_aaddvnx1si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3691; /* pred_aaddvnx1si_scalar */

    case 14:
      if (register_operand (operands[4], E_VNx2SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3570; /* pred_aaddvnx2si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3696; /* pred_aaddvnx2si_scalar */

    case 15:
      if (register_operand (operands[4], E_VNx4SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3577; /* pred_aaddvnx4si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3701; /* pred_aaddvnx4si_scalar */

    case 16:
      if (register_operand (operands[4], E_VNx8SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3584; /* pred_aaddvnx8si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3706; /* pred_aaddvnx8si_scalar */

    case 17:
      if (register_operand (operands[4], E_VNx16SImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3591; /* pred_aaddvnx16si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3711; /* pred_aaddvnx16si_scalar */

    case 18:
      if (register_operand (operands[4], E_VNx1DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3598; /* pred_aaddvnx1di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3760; /* *pred_aaddvnx1di_scalar */

    case 19:
      if (register_operand (operands[4], E_VNx2DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3605; /* pred_aaddvnx2di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3765; /* *pred_aaddvnx2di_scalar */

    case 20:
      if (register_operand (operands[4], E_VNx4DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3612; /* pred_aaddvnx4di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3770; /* *pred_aaddvnx4di_scalar */

    case 21:
      if (register_operand (operands[4], E_VNx8DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3619; /* pred_aaddvnx8di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3775; /* *pred_aaddvnx8di_scalar */

    case 22:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3780; /* *pred_aaddvnx1di_extended_scalar */

    case 23:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3785; /* *pred_aaddvnx2di_extended_scalar */

    case 24:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3790; /* *pred_aaddvnx4di_extended_scalar */

    case 25:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3795; /* *pred_aaddvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_28 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern245 (x2))
    {
    case 0:
      if (register_operand (operands[4], E_VNx1QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3471; /* pred_aadduvnx1qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3625; /* pred_aadduvnx1qi_scalar */

    case 1:
      if (register_operand (operands[4], E_VNx2QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3478; /* pred_aadduvnx2qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3630; /* pred_aadduvnx2qi_scalar */

    case 2:
      if (register_operand (operands[4], E_VNx4QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3485; /* pred_aadduvnx4qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3635; /* pred_aadduvnx4qi_scalar */

    case 3:
      if (register_operand (operands[4], E_VNx8QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3492; /* pred_aadduvnx8qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3640; /* pred_aadduvnx8qi_scalar */

    case 4:
      if (register_operand (operands[4], E_VNx16QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3499; /* pred_aadduvnx16qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3645; /* pred_aadduvnx16qi_scalar */

    case 5:
      if (register_operand (operands[4], E_VNx32QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3506; /* pred_aadduvnx32qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3650; /* pred_aadduvnx32qi_scalar */

    case 6:
      if (register_operand (operands[4], E_VNx64QImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3513; /* pred_aadduvnx64qi */
      if (!reg_or_0_operand (operands[4], E_QImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3655; /* pred_aadduvnx64qi_scalar */

    case 7:
      if (register_operand (operands[4], E_VNx1HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3520; /* pred_aadduvnx1hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3660; /* pred_aadduvnx1hi_scalar */

    case 8:
      if (register_operand (operands[4], E_VNx2HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3527; /* pred_aadduvnx2hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3665; /* pred_aadduvnx2hi_scalar */

    case 9:
      if (register_operand (operands[4], E_VNx4HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3534; /* pred_aadduvnx4hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3670; /* pred_aadduvnx4hi_scalar */

    case 10:
      if (register_operand (operands[4], E_VNx8HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3541; /* pred_aadduvnx8hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3675; /* pred_aadduvnx8hi_scalar */

    case 11:
      if (register_operand (operands[4], E_VNx16HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3548; /* pred_aadduvnx16hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3680; /* pred_aadduvnx16hi_scalar */

    case 12:
      if (register_operand (operands[4], E_VNx32HImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3555; /* pred_aadduvnx32hi */
      if (!reg_or_0_operand (operands[4], E_HImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3685; /* pred_aadduvnx32hi_scalar */

    case 13:
      if (register_operand (operands[4], E_VNx1SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3562; /* pred_aadduvnx1si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3690; /* pred_aadduvnx1si_scalar */

    case 14:
      if (register_operand (operands[4], E_VNx2SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3569; /* pred_aadduvnx2si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3695; /* pred_aadduvnx2si_scalar */

    case 15:
      if (register_operand (operands[4], E_VNx4SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3576; /* pred_aadduvnx4si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3700; /* pred_aadduvnx4si_scalar */

    case 16:
      if (register_operand (operands[4], E_VNx8SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3583; /* pred_aadduvnx8si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3705; /* pred_aadduvnx8si_scalar */

    case 17:
      if (register_operand (operands[4], E_VNx16SImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3590; /* pred_aadduvnx16si */
      if (!reg_or_0_operand (operands[4], E_SImode)
          || !(
#line 3451 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3710; /* pred_aadduvnx16si_scalar */

    case 18:
      if (register_operand (operands[4], E_VNx1DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3597; /* pred_aadduvnx1di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3759; /* *pred_aadduvnx1di_scalar */

    case 19:
      if (register_operand (operands[4], E_VNx2DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3604; /* pred_aadduvnx2di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3764; /* *pred_aadduvnx2di_scalar */

    case 20:
      if (register_operand (operands[4], E_VNx4DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3611; /* pred_aadduvnx4di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3769; /* *pred_aadduvnx4di_scalar */

    case 21:
      if (register_operand (operands[4], E_VNx8DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3618; /* pred_aadduvnx8di */
      if (!reg_or_0_operand (operands[4], E_DImode)
          || !(
#line 3525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3774; /* *pred_aadduvnx8di_scalar */

    case 22:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3779; /* *pred_aadduvnx1di_extended_scalar */

    case 23:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3784; /* *pred_aadduvnx2di_extended_scalar */

    case 24:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3789; /* *pred_aadduvnx4di_extended_scalar */

    case 25:
      if (!(
#line 3546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3794; /* *pred_aadduvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_29 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XVECEXP (x3, 0, 0);
  operands[3] = x4;
  switch (pattern244 (x2))
    {
    case 0:
      if (register_operand (operands[4], E_VNx1QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3477; /* pred_ssravnx1qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3716; /* pred_ssravnx1qi_scalar */

    case 1:
      if (register_operand (operands[4], E_VNx2QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3484; /* pred_ssravnx2qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3718; /* pred_ssravnx2qi_scalar */

    case 2:
      if (register_operand (operands[4], E_VNx4QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3491; /* pred_ssravnx4qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3720; /* pred_ssravnx4qi_scalar */

    case 3:
      if (register_operand (operands[4], E_VNx8QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3498; /* pred_ssravnx8qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3722; /* pred_ssravnx8qi_scalar */

    case 4:
      if (register_operand (operands[4], E_VNx16QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3505; /* pred_ssravnx16qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3724; /* pred_ssravnx16qi_scalar */

    case 5:
      if (register_operand (operands[4], E_VNx32QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3512; /* pred_ssravnx32qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3726; /* pred_ssravnx32qi_scalar */

    case 6:
      if (register_operand (operands[4], E_VNx64QImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3519; /* pred_ssravnx64qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3728; /* pred_ssravnx64qi_scalar */

    case 7:
      if (register_operand (operands[4], E_VNx1HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3526; /* pred_ssravnx1hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3730; /* pred_ssravnx1hi_scalar */

    case 8:
      if (register_operand (operands[4], E_VNx2HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3533; /* pred_ssravnx2hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3732; /* pred_ssravnx2hi_scalar */

    case 9:
      if (register_operand (operands[4], E_VNx4HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3540; /* pred_ssravnx4hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3734; /* pred_ssravnx4hi_scalar */

    case 10:
      if (register_operand (operands[4], E_VNx8HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3547; /* pred_ssravnx8hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3736; /* pred_ssravnx8hi_scalar */

    case 11:
      if (register_operand (operands[4], E_VNx16HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3554; /* pred_ssravnx16hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3738; /* pred_ssravnx16hi_scalar */

    case 12:
      if (register_operand (operands[4], E_VNx32HImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3561; /* pred_ssravnx32hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3740; /* pred_ssravnx32hi_scalar */

    case 13:
      if (register_operand (operands[4], E_VNx1SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3568; /* pred_ssravnx1si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3742; /* pred_ssravnx1si_scalar */

    case 14:
      if (register_operand (operands[4], E_VNx2SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3575; /* pred_ssravnx2si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3744; /* pred_ssravnx2si_scalar */

    case 15:
      if (register_operand (operands[4], E_VNx4SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3582; /* pred_ssravnx4si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3746; /* pred_ssravnx4si_scalar */

    case 16:
      if (register_operand (operands[4], E_VNx8SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3589; /* pred_ssravnx8si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3748; /* pred_ssravnx8si_scalar */

    case 17:
      if (register_operand (operands[4], E_VNx16SImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3596; /* pred_ssravnx16si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3750; /* pred_ssravnx16si_scalar */

    case 18:
      if (register_operand (operands[4], E_VNx1DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3603; /* pred_ssravnx1di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3752; /* pred_ssravnx1di_scalar */

    case 19:
      if (register_operand (operands[4], E_VNx2DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3610; /* pred_ssravnx2di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3754; /* pred_ssravnx2di_scalar */

    case 20:
      if (register_operand (operands[4], E_VNx4DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3617; /* pred_ssravnx4di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3756; /* pred_ssravnx4di_scalar */

    case 21:
      if (register_operand (operands[4], E_VNx8DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3624; /* pred_ssravnx8di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3758; /* pred_ssravnx8di_scalar */

    default:
      return -1;
    }
}

static int
recog_30 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XVECEXP (x3, 0, 0);
  operands[3] = x4;
  switch (pattern244 (x2))
    {
    case 0:
      if (register_operand (operands[4], E_VNx1QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3476; /* pred_ssrlvnx1qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3715; /* pred_ssrlvnx1qi_scalar */

    case 1:
      if (register_operand (operands[4], E_VNx2QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3483; /* pred_ssrlvnx2qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3717; /* pred_ssrlvnx2qi_scalar */

    case 2:
      if (register_operand (operands[4], E_VNx4QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3490; /* pred_ssrlvnx4qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3719; /* pred_ssrlvnx4qi_scalar */

    case 3:
      if (register_operand (operands[4], E_VNx8QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3497; /* pred_ssrlvnx8qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3721; /* pred_ssrlvnx8qi_scalar */

    case 4:
      if (register_operand (operands[4], E_VNx16QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3504; /* pred_ssrlvnx16qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3723; /* pred_ssrlvnx16qi_scalar */

    case 5:
      if (register_operand (operands[4], E_VNx32QImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3511; /* pred_ssrlvnx32qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3725; /* pred_ssrlvnx32qi_scalar */

    case 6:
      if (register_operand (operands[4], E_VNx64QImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3518; /* pred_ssrlvnx64qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3727; /* pred_ssrlvnx64qi_scalar */

    case 7:
      if (register_operand (operands[4], E_VNx1HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3525; /* pred_ssrlvnx1hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3729; /* pred_ssrlvnx1hi_scalar */

    case 8:
      if (register_operand (operands[4], E_VNx2HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3532; /* pred_ssrlvnx2hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3731; /* pred_ssrlvnx2hi_scalar */

    case 9:
      if (register_operand (operands[4], E_VNx4HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3539; /* pred_ssrlvnx4hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3733; /* pred_ssrlvnx4hi_scalar */

    case 10:
      if (register_operand (operands[4], E_VNx8HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3546; /* pred_ssrlvnx8hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3735; /* pred_ssrlvnx8hi_scalar */

    case 11:
      if (register_operand (operands[4], E_VNx16HImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3553; /* pred_ssrlvnx16hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3737; /* pred_ssrlvnx16hi_scalar */

    case 12:
      if (register_operand (operands[4], E_VNx32HImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3560; /* pred_ssrlvnx32hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3739; /* pred_ssrlvnx32hi_scalar */

    case 13:
      if (register_operand (operands[4], E_VNx1SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3567; /* pred_ssrlvnx1si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3741; /* pred_ssrlvnx1si_scalar */

    case 14:
      if (register_operand (operands[4], E_VNx2SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3574; /* pred_ssrlvnx2si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3743; /* pred_ssrlvnx2si_scalar */

    case 15:
      if (register_operand (operands[4], E_VNx4SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3581; /* pred_ssrlvnx4si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3745; /* pred_ssrlvnx4si_scalar */

    case 16:
      if (register_operand (operands[4], E_VNx8SImode)
          && 
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3588; /* pred_ssrlvnx8si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3747; /* pred_ssrlvnx8si_scalar */

    case 17:
      if (register_operand (operands[4], E_VNx16SImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3595; /* pred_ssrlvnx16si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3749; /* pred_ssrlvnx16si_scalar */

    case 18:
      if (register_operand (operands[4], E_VNx1DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3602; /* pred_ssrlvnx1di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3751; /* pred_ssrlvnx1di_scalar */

    case 19:
      if (register_operand (operands[4], E_VNx2DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3609; /* pred_ssrlvnx2di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3753; /* pred_ssrlvnx2di_scalar */

    case 20:
      if (register_operand (operands[4], E_VNx4DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3616; /* pred_ssrlvnx4di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3755; /* pred_ssrlvnx4di_scalar */

    case 21:
      if (register_operand (operands[4], E_VNx8DImode)
          && (
#line 3430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3623; /* pred_ssrlvnx8di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3471 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3757; /* pred_ssrlvnx8di_scalar */

    default:
      return -1;
    }
}

static int
recog_31 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XVECEXP (x3, 0, 0);
  operands[3] = x4;
  x5 = XVECEXP (x3, 0, 1);
  operands[4] = x5;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      if (pattern285 (x2, E_VNx1QImode, E_VNx1HImode, E_VNx1BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5974; /* pred_gatherei16vnx1qi */

    case E_VNx2QImode:
      if (pattern285 (x2, E_VNx2QImode, E_VNx2HImode, E_VNx2BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5975; /* pred_gatherei16vnx2qi */

    case E_VNx4QImode:
      if (pattern285 (x2, E_VNx4QImode, E_VNx4HImode, E_VNx4BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5976; /* pred_gatherei16vnx4qi */

    case E_VNx8QImode:
      if (pattern285 (x2, E_VNx8QImode, E_VNx8HImode, E_VNx8BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5977; /* pred_gatherei16vnx8qi */

    case E_VNx16QImode:
      if (pattern285 (x2, E_VNx16QImode, E_VNx16HImode, E_VNx16BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5978; /* pred_gatherei16vnx16qi */

    case E_VNx32QImode:
      if (pattern285 (x2, E_VNx32QImode, E_VNx32HImode, E_VNx32BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5979; /* pred_gatherei16vnx32qi */

    case E_VNx1HImode:
      if (pattern239 (x2, E_VNx1HImode, E_VNx1BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5980; /* pred_gatherei16vnx1hi */

    case E_VNx2HImode:
      if (pattern239 (x2, E_VNx2HImode, E_VNx2BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5981; /* pred_gatherei16vnx2hi */

    case E_VNx4HImode:
      if (pattern239 (x2, E_VNx4HImode, E_VNx4BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5982; /* pred_gatherei16vnx4hi */

    case E_VNx8HImode:
      if (pattern239 (x2, E_VNx8HImode, E_VNx8BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5983; /* pred_gatherei16vnx8hi */

    case E_VNx16HImode:
      if (pattern239 (x2, E_VNx16HImode, E_VNx16BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5984; /* pred_gatherei16vnx16hi */

    case E_VNx32HImode:
      if (pattern239 (x2, E_VNx32HImode, E_VNx32BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5985; /* pred_gatherei16vnx32hi */

    case E_VNx1SImode:
      if (pattern285 (x2, E_VNx1SImode, E_VNx1HImode, E_VNx1BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5986; /* pred_gatherei16vnx1si */

    case E_VNx2SImode:
      if (pattern285 (x2, E_VNx2SImode, E_VNx2HImode, E_VNx2BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5987; /* pred_gatherei16vnx2si */

    case E_VNx4SImode:
      if (pattern285 (x2, E_VNx4SImode, E_VNx4HImode, E_VNx4BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5988; /* pred_gatherei16vnx4si */

    case E_VNx8SImode:
      if (pattern285 (x2, E_VNx8SImode, E_VNx8HImode, E_VNx8BImode) != 0
          || !
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 5989; /* pred_gatherei16vnx8si */

    case E_VNx16SImode:
      if (pattern285 (x2, E_VNx16SImode, E_VNx16HImode, E_VNx16BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 217 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 5990; /* pred_gatherei16vnx16si */

    case E_VNx1DImode:
      if (pattern285 (x2, E_VNx1DImode, E_VNx1HImode, E_VNx1BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5991; /* pred_gatherei16vnx1di */

    case E_VNx2DImode:
      if (pattern285 (x2, E_VNx2DImode, E_VNx2HImode, E_VNx2BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5992; /* pred_gatherei16vnx2di */

    case E_VNx4DImode:
      if (pattern285 (x2, E_VNx4DImode, E_VNx4HImode, E_VNx4BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5993; /* pred_gatherei16vnx4di */

    case E_VNx8DImode:
      if (pattern285 (x2, E_VNx8DImode, E_VNx8HImode, E_VNx8BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 5994; /* pred_gatherei16vnx8di */

    case E_VNx1SFmode:
      if (pattern285 (x2, E_VNx1SFmode, E_VNx1HImode, E_VNx1BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 220 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5995; /* pred_gatherei16vnx1sf */

    case E_VNx2SFmode:
      if (pattern285 (x2, E_VNx2SFmode, E_VNx2HImode, E_VNx2BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5996; /* pred_gatherei16vnx2sf */

    case E_VNx4SFmode:
      if (pattern285 (x2, E_VNx4SFmode, E_VNx4HImode, E_VNx4BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 222 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5997; /* pred_gatherei16vnx4sf */

    case E_VNx8SFmode:
      if (pattern285 (x2, E_VNx8SFmode, E_VNx8HImode, E_VNx8BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 223 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5998; /* pred_gatherei16vnx8sf */

    case E_VNx16SFmode:
      if (pattern285 (x2, E_VNx16SFmode, E_VNx16HImode, E_VNx16BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 224 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 5999; /* pred_gatherei16vnx16sf */

    case E_VNx1DFmode:
      if (pattern285 (x2, E_VNx1DFmode, E_VNx1HImode, E_VNx1BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 225 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 6000; /* pred_gatherei16vnx1df */

    case E_VNx2DFmode:
      if (pattern285 (x2, E_VNx2DFmode, E_VNx2HImode, E_VNx2BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 6001; /* pred_gatherei16vnx2df */

    case E_VNx4DFmode:
      if (pattern285 (x2, E_VNx4DFmode, E_VNx4HImode, E_VNx4BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 227 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 6002; /* pred_gatherei16vnx4df */

    case E_VNx8DFmode:
      if (pattern285 (x2, E_VNx8DFmode, E_VNx8HImode, E_VNx8BImode) != 0
          || !(
#line 7218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 228 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 6003; /* pred_gatherei16vnx8df */

    default:
      return -1;
    }
}

static int
recog_32 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern247 (x2))
    {
    case 0:
      if (vector_shift_operand (operands[4], E_VNx1QImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3800; /* pred_narrow_clipuvnx1hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3830; /* pred_narrow_clipuvnx1hi_scalar */

    case 1:
      if (vector_shift_operand (operands[4], E_VNx2QImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3802; /* pred_narrow_clipuvnx2hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3832; /* pred_narrow_clipuvnx2hi_scalar */

    case 2:
      if (vector_shift_operand (operands[4], E_VNx4QImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3804; /* pred_narrow_clipuvnx4hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3834; /* pred_narrow_clipuvnx4hi_scalar */

    case 3:
      if (vector_shift_operand (operands[4], E_VNx8QImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3806; /* pred_narrow_clipuvnx8hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3836; /* pred_narrow_clipuvnx8hi_scalar */

    case 4:
      if (vector_shift_operand (operands[4], E_VNx16QImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3808; /* pred_narrow_clipuvnx16hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3838; /* pred_narrow_clipuvnx16hi_scalar */

    case 5:
      if (vector_shift_operand (operands[4], E_VNx32QImode)
          && (
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3810; /* pred_narrow_clipuvnx32hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3840; /* pred_narrow_clipuvnx32hi_scalar */

    case 6:
      if (vector_shift_operand (operands[4], E_VNx1HImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3812; /* pred_narrow_clipuvnx1si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3842; /* pred_narrow_clipuvnx1si_scalar */

    case 7:
      if (vector_shift_operand (operands[4], E_VNx2HImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3814; /* pred_narrow_clipuvnx2si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3844; /* pred_narrow_clipuvnx2si_scalar */

    case 8:
      if (vector_shift_operand (operands[4], E_VNx4HImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3816; /* pred_narrow_clipuvnx4si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3846; /* pred_narrow_clipuvnx4si_scalar */

    case 9:
      if (vector_shift_operand (operands[4], E_VNx8HImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3818; /* pred_narrow_clipuvnx8si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3848; /* pred_narrow_clipuvnx8si_scalar */

    case 10:
      if (vector_shift_operand (operands[4], E_VNx16HImode)
          && (
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3820; /* pred_narrow_clipuvnx16si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3850; /* pred_narrow_clipuvnx16si_scalar */

    case 11:
      if (vector_shift_operand (operands[4], E_VNx1SImode)
          && (
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3822; /* pred_narrow_clipuvnx1di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3852; /* pred_narrow_clipuvnx1di_scalar */

    case 12:
      if (vector_shift_operand (operands[4], E_VNx2SImode)
          && (
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3824; /* pred_narrow_clipuvnx2di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3854; /* pred_narrow_clipuvnx2di_scalar */

    case 13:
      if (vector_shift_operand (operands[4], E_VNx4SImode)
          && (
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3826; /* pred_narrow_clipuvnx4di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3856; /* pred_narrow_clipuvnx4di_scalar */

    case 14:
      if (vector_shift_operand (operands[4], E_VNx8SImode)
          && (
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3828; /* pred_narrow_clipuvnx8di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3858; /* pred_narrow_clipuvnx8di_scalar */

    default:
      return -1;
    }
}

static int
recog_33 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern247 (x2))
    {
    case 0:
      if (vector_shift_operand (operands[4], E_VNx1QImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3799; /* pred_narrow_clipvnx1hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3829; /* pred_narrow_clipvnx1hi_scalar */

    case 1:
      if (vector_shift_operand (operands[4], E_VNx2QImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3801; /* pred_narrow_clipvnx2hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3831; /* pred_narrow_clipvnx2hi_scalar */

    case 2:
      if (vector_shift_operand (operands[4], E_VNx4QImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3803; /* pred_narrow_clipvnx4hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3833; /* pred_narrow_clipvnx4hi_scalar */

    case 3:
      if (vector_shift_operand (operands[4], E_VNx8QImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3805; /* pred_narrow_clipvnx8hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3835; /* pred_narrow_clipvnx8hi_scalar */

    case 4:
      if (vector_shift_operand (operands[4], E_VNx16QImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3807; /* pred_narrow_clipvnx16hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3837; /* pred_narrow_clipvnx16hi_scalar */

    case 5:
      if (vector_shift_operand (operands[4], E_VNx32QImode)
          && (
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3809; /* pred_narrow_clipvnx32hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3839; /* pred_narrow_clipvnx32hi_scalar */

    case 6:
      if (vector_shift_operand (operands[4], E_VNx1HImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3811; /* pred_narrow_clipvnx1si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3841; /* pred_narrow_clipvnx1si_scalar */

    case 7:
      if (vector_shift_operand (operands[4], E_VNx2HImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3813; /* pred_narrow_clipvnx2si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3843; /* pred_narrow_clipvnx2si_scalar */

    case 8:
      if (vector_shift_operand (operands[4], E_VNx4HImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3815; /* pred_narrow_clipvnx4si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3845; /* pred_narrow_clipvnx4si_scalar */

    case 9:
      if (vector_shift_operand (operands[4], E_VNx8HImode)
          && 
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 3817; /* pred_narrow_clipvnx8si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3847; /* pred_narrow_clipvnx8si_scalar */

    case 10:
      if (vector_shift_operand (operands[4], E_VNx16HImode)
          && (
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3819; /* pred_narrow_clipvnx16si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3849; /* pred_narrow_clipvnx16si_scalar */

    case 11:
      if (vector_shift_operand (operands[4], E_VNx1SImode)
          && (
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3821; /* pred_narrow_clipvnx1di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3851; /* pred_narrow_clipvnx1di_scalar */

    case 12:
      if (vector_shift_operand (operands[4], E_VNx2SImode)
          && (
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3823; /* pred_narrow_clipvnx2di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3853; /* pred_narrow_clipvnx2di_scalar */

    case 13:
      if (vector_shift_operand (operands[4], E_VNx4SImode)
          && (
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3825; /* pred_narrow_clipvnx4di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3855; /* pred_narrow_clipvnx4di_scalar */

    case 14:
      if (vector_shift_operand (operands[4], E_VNx8SImode)
          && (
#line 3567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 3827; /* pred_narrow_clipvnx8di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 3587 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3857; /* pred_narrow_clipvnx8di_scalar */

    default:
      return -1;
    }
}

static int
recog_34 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern242 (x2))
    {
    case 0:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2314; /* pred_mulhsuvnx1qi */

    case 1:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2317; /* pred_mulhsuvnx2qi */

    case 2:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2320; /* pred_mulhsuvnx4qi */

    case 3:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2323; /* pred_mulhsuvnx8qi */

    case 4:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2326; /* pred_mulhsuvnx16qi */

    case 5:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2329; /* pred_mulhsuvnx32qi */

    case 6:
      if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2332; /* pred_mulhsuvnx64qi */

    case 7:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2335; /* pred_mulhsuvnx1hi */

    case 8:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2338; /* pred_mulhsuvnx2hi */

    case 9:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2341; /* pred_mulhsuvnx4hi */

    case 10:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2344; /* pred_mulhsuvnx8hi */

    case 11:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2347; /* pred_mulhsuvnx16hi */

    case 12:
      if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 281 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2350; /* pred_mulhsuvnx32hi */

    case 13:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2353; /* pred_mulhsuvnx1si */

    case 14:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2356; /* pred_mulhsuvnx2si */

    case 15:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2359; /* pred_mulhsuvnx4si */

    case 16:
      if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2362; /* pred_mulhsuvnx8si */

    case 17:
      if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 282 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2365; /* pred_mulhsuvnx16si */

    case 18:
      if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 283 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
        return -1;
      return 2368; /* pred_mulhsuvnx1di */

    case 19:
      if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 283 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
        return -1;
      return 2371; /* pred_mulhsuvnx2di */

    case 20:
      if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
        return -1;
      return 2374; /* pred_mulhsuvnx4di */

    case 21:
      if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
        return -1;
      return 2377; /* pred_mulhsuvnx8di */

    case 22:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2380; /* pred_mulhsuvnx1qi_scalar */

    case 23:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2383; /* pred_mulhsuvnx2qi_scalar */

    case 24:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2386; /* pred_mulhsuvnx4qi_scalar */

    case 25:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2389; /* pred_mulhsuvnx8qi_scalar */

    case 26:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2392; /* pred_mulhsuvnx16qi_scalar */

    case 27:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2395; /* pred_mulhsuvnx32qi_scalar */

    case 28:
      if (!(
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2398; /* pred_mulhsuvnx64qi_scalar */

    case 29:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2401; /* pred_mulhsuvnx1hi_scalar */

    case 30:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2404; /* pred_mulhsuvnx2hi_scalar */

    case 31:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2407; /* pred_mulhsuvnx4hi_scalar */

    case 32:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2410; /* pred_mulhsuvnx8hi_scalar */

    case 33:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2413; /* pred_mulhsuvnx16hi_scalar */

    case 34:
      if (!(
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2416; /* pred_mulhsuvnx32hi_scalar */

    case 35:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2419; /* pred_mulhsuvnx1si_scalar */

    case 36:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2422; /* pred_mulhsuvnx2si_scalar */

    case 37:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2425; /* pred_mulhsuvnx4si_scalar */

    case 38:
      if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2428; /* pred_mulhsuvnx8si_scalar */

    case 39:
      if (!(
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2431; /* pred_mulhsuvnx16si_scalar */

    case 40:
      if (!(
#line 2124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
        return -1;
      return 2434; /* *pred_mulhsuvnx1di_scalar */

    case 41:
      if (!(
#line 2124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
        return -1;
      return 2437; /* *pred_mulhsuvnx2di_scalar */

    case 42:
      if (!(
#line 2124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
        return -1;
      return 2440; /* *pred_mulhsuvnx4di_scalar */

    case 43:
      if (!(
#line 2124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
        return -1;
      return 2443; /* *pred_mulhsuvnx8di_scalar */

    case 44:
      if (!(
#line 2146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
        return -1;
      return 2446; /* *pred_mulhsuvnx1di_extended_scalar */

    case 45:
      if (!(
#line 2146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
        return -1;
      return 2449; /* *pred_mulhsuvnx2di_extended_scalar */

    case 46:
      if (!(
#line 2146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
        return -1;
      return 2452; /* *pred_mulhsuvnx4di_extended_scalar */

    case 47:
      if (!(
#line 2146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
        return -1;
      return 2455; /* *pred_mulhsuvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_35 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  x8 = XEXP (x2, 1);
  switch (XINT (x8, 1))
    {
    case 73:
      switch (pattern242 (x2))
        {
        case 0:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2312; /* pred_mulhvnx1qi */

        case 1:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2315; /* pred_mulhvnx2qi */

        case 2:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2318; /* pred_mulhvnx4qi */

        case 3:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2321; /* pred_mulhvnx8qi */

        case 4:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2324; /* pred_mulhvnx16qi */

        case 5:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2327; /* pred_mulhvnx32qi */

        case 6:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2330; /* pred_mulhvnx64qi */

        case 7:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2333; /* pred_mulhvnx1hi */

        case 8:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2336; /* pred_mulhvnx2hi */

        case 9:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2339; /* pred_mulhvnx4hi */

        case 10:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2342; /* pred_mulhvnx8hi */

        case 11:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2345; /* pred_mulhvnx16hi */

        case 12:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 281 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2348; /* pred_mulhvnx32hi */

        case 13:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2351; /* pred_mulhvnx1si */

        case 14:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2354; /* pred_mulhvnx2si */

        case 15:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2357; /* pred_mulhvnx4si */

        case 16:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2360; /* pred_mulhvnx8si */

        case 17:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 282 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2363; /* pred_mulhvnx16si */

        case 18:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 283 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2366; /* pred_mulhvnx1di */

        case 19:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 283 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2369; /* pred_mulhvnx2di */

        case 20:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2372; /* pred_mulhvnx4di */

        case 21:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2375; /* pred_mulhvnx8di */

        case 22:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2378; /* pred_mulhvnx1qi_scalar */

        case 23:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2381; /* pred_mulhvnx2qi_scalar */

        case 24:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2384; /* pred_mulhvnx4qi_scalar */

        case 25:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2387; /* pred_mulhvnx8qi_scalar */

        case 26:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2390; /* pred_mulhvnx16qi_scalar */

        case 27:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2393; /* pred_mulhvnx32qi_scalar */

        case 28:
          if (!(
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2396; /* pred_mulhvnx64qi_scalar */

        case 29:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2399; /* pred_mulhvnx1hi_scalar */

        case 30:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2402; /* pred_mulhvnx2hi_scalar */

        case 31:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2405; /* pred_mulhvnx4hi_scalar */

        case 32:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2408; /* pred_mulhvnx8hi_scalar */

        case 33:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2411; /* pred_mulhvnx16hi_scalar */

        case 34:
          if (!(
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2414; /* pred_mulhvnx32hi_scalar */

        case 35:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2417; /* pred_mulhvnx1si_scalar */

        case 36:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2420; /* pred_mulhvnx2si_scalar */

        case 37:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2423; /* pred_mulhvnx4si_scalar */

        case 38:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2426; /* pred_mulhvnx8si_scalar */

        case 39:
          if (!(
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2429; /* pred_mulhvnx16si_scalar */

        case 40:
          if (!(
#line 2124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2432; /* *pred_mulhvnx1di_scalar */

        case 41:
          if (!(
#line 2124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2435; /* *pred_mulhvnx2di_scalar */

        case 42:
          if (!(
#line 2124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2438; /* *pred_mulhvnx4di_scalar */

        case 43:
          if (!(
#line 2124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2441; /* *pred_mulhvnx8di_scalar */

        case 44:
          if (!(
#line 2146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2444; /* *pred_mulhvnx1di_extended_scalar */

        case 45:
          if (!(
#line 2146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2447; /* *pred_mulhvnx2di_extended_scalar */

        case 46:
          if (!(
#line 2146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2450; /* *pred_mulhvnx4di_extended_scalar */

        case 47:
          if (!(
#line 2146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2453; /* *pred_mulhvnx8di_extended_scalar */

        default:
          return -1;
        }

    case 74:
      switch (pattern242 (x2))
        {
        case 0:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2313; /* pred_mulhuvnx1qi */

        case 1:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2316; /* pred_mulhuvnx2qi */

        case 2:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2319; /* pred_mulhuvnx4qi */

        case 3:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2322; /* pred_mulhuvnx8qi */

        case 4:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2325; /* pred_mulhuvnx16qi */

        case 5:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2328; /* pred_mulhuvnx32qi */

        case 6:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2331; /* pred_mulhuvnx64qi */

        case 7:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2334; /* pred_mulhuvnx1hi */

        case 8:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2337; /* pred_mulhuvnx2hi */

        case 9:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2340; /* pred_mulhuvnx4hi */

        case 10:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2343; /* pred_mulhuvnx8hi */

        case 11:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2346; /* pred_mulhuvnx16hi */

        case 12:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 281 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2349; /* pred_mulhuvnx32hi */

        case 13:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2352; /* pred_mulhuvnx1si */

        case 14:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2355; /* pred_mulhuvnx2si */

        case 15:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2358; /* pred_mulhuvnx4si */

        case 16:
          if (!
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2361; /* pred_mulhuvnx8si */

        case 17:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 282 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2364; /* pred_mulhuvnx16si */

        case 18:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 283 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2367; /* pred_mulhuvnx1di */

        case 19:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 283 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2370; /* pred_mulhuvnx2di */

        case 20:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2373; /* pred_mulhuvnx4di */

        case 21:
          if (!(
#line 2049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2376; /* pred_mulhuvnx8di */

        case 22:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2379; /* pred_mulhuvnx1qi_scalar */

        case 23:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2382; /* pred_mulhuvnx2qi_scalar */

        case 24:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2385; /* pred_mulhuvnx4qi_scalar */

        case 25:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2388; /* pred_mulhuvnx8qi_scalar */

        case 26:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2391; /* pred_mulhuvnx16qi_scalar */

        case 27:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2394; /* pred_mulhuvnx32qi_scalar */

        case 28:
          if (!(
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2397; /* pred_mulhuvnx64qi_scalar */

        case 29:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2400; /* pred_mulhuvnx1hi_scalar */

        case 30:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2403; /* pred_mulhuvnx2hi_scalar */

        case 31:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2406; /* pred_mulhuvnx4hi_scalar */

        case 32:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2409; /* pred_mulhuvnx8hi_scalar */

        case 33:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2412; /* pred_mulhuvnx16hi_scalar */

        case 34:
          if (!(
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2415; /* pred_mulhuvnx32hi_scalar */

        case 35:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2418; /* pred_mulhuvnx1si_scalar */

        case 36:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2421; /* pred_mulhuvnx2si_scalar */

        case 37:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2424; /* pred_mulhuvnx4si_scalar */

        case 38:
          if (!
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2427; /* pred_mulhuvnx8si_scalar */

        case 39:
          if (!(
#line 2070 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2430; /* pred_mulhuvnx16si_scalar */

        case 40:
          if (!(
#line 2124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2433; /* *pred_mulhuvnx1di_scalar */

        case 41:
          if (!(
#line 2124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2436; /* *pred_mulhuvnx2di_scalar */

        case 42:
          if (!(
#line 2124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2439; /* *pred_mulhuvnx4di_scalar */

        case 43:
          if (!(
#line 2124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2442; /* *pred_mulhuvnx8di_scalar */

        case 44:
          if (!(
#line 2146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2445; /* *pred_mulhuvnx1di_extended_scalar */

        case 45:
          if (!(
#line 2146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2448; /* *pred_mulhuvnx2di_extended_scalar */

        case 46:
          if (!(
#line 2146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2451; /* *pred_mulhuvnx4di_extended_scalar */

        case 47:
          if (!(
#line 2146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V)))
            return -1;
          return 2454; /* *pred_mulhuvnx8di_extended_scalar */

        default:
          return -1;
        }

    case 75:
      return recog_34 (x1, insn, pnum_clobbers);

    case 85:
      return recog_28 (x1, insn, pnum_clobbers);

    case 86:
      return recog_27 (x1, insn, pnum_clobbers);

    case 87:
      return recog_26 (x1, insn, pnum_clobbers);

    case 88:
      return recog_25 (x1, insn, pnum_clobbers);

    case 89:
      return recog_24 (x1, insn, pnum_clobbers);

    case 83:
      return recog_30 (x1, insn, pnum_clobbers);

    case 84:
      return recog_29 (x1, insn, pnum_clobbers);

    case 81:
      return recog_33 (x1, insn, pnum_clobbers);

    case 82:
      return recog_32 (x1, insn, pnum_clobbers);

    case 97:
      switch (pattern249 (x2))
        {
        case 0:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4726; /* pred_copysignvnx1sf */

        case 1:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4729; /* pred_copysignvnx2sf */

        case 2:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4732; /* pred_copysignvnx4sf */

        case 3:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4735; /* pred_copysignvnx8sf */

        case 4:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4738; /* pred_copysignvnx16sf */

        case 5:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4741; /* pred_copysignvnx1df */

        case 6:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4744; /* pred_copysignvnx2df */

        case 7:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4747; /* pred_copysignvnx4df */

        case 8:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4750; /* pred_copysignvnx8df */

        case 9:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4753; /* pred_copysignvnx1sf_scalar */

        case 10:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4756; /* pred_copysignvnx2sf_scalar */

        case 11:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4759; /* pred_copysignvnx4sf_scalar */

        case 12:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4762; /* pred_copysignvnx8sf_scalar */

        case 13:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4765; /* pred_copysignvnx16sf_scalar */

        case 14:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4768; /* pred_copysignvnx1df_scalar */

        case 15:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4771; /* pred_copysignvnx2df_scalar */

        case 16:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4774; /* pred_copysignvnx4df_scalar */

        case 17:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4777; /* pred_copysignvnx8df_scalar */

        default:
          return -1;
        }

    case 98:
      switch (pattern249 (x2))
        {
        case 0:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4727; /* pred_ncopysignvnx1sf */

        case 1:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4730; /* pred_ncopysignvnx2sf */

        case 2:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4733; /* pred_ncopysignvnx4sf */

        case 3:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4736; /* pred_ncopysignvnx8sf */

        case 4:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4739; /* pred_ncopysignvnx16sf */

        case 5:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4742; /* pred_ncopysignvnx1df */

        case 6:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4745; /* pred_ncopysignvnx2df */

        case 7:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4748; /* pred_ncopysignvnx4df */

        case 8:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4751; /* pred_ncopysignvnx8df */

        case 9:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4754; /* pred_ncopysignvnx1sf_scalar */

        case 10:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4757; /* pred_ncopysignvnx2sf_scalar */

        case 11:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4760; /* pred_ncopysignvnx4sf_scalar */

        case 12:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4763; /* pred_ncopysignvnx8sf_scalar */

        case 13:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4766; /* pred_ncopysignvnx16sf_scalar */

        case 14:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4769; /* pred_ncopysignvnx1df_scalar */

        case 15:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4772; /* pred_ncopysignvnx2df_scalar */

        case 16:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4775; /* pred_ncopysignvnx4df_scalar */

        case 17:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4778; /* pred_ncopysignvnx8df_scalar */

        default:
          return -1;
        }

    case 99:
      switch (pattern249 (x2))
        {
        case 0:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4728; /* pred_xorsignvnx1sf */

        case 1:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4731; /* pred_xorsignvnx2sf */

        case 2:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4734; /* pred_xorsignvnx4sf */

        case 3:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4737; /* pred_xorsignvnx8sf */

        case 4:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4740; /* pred_xorsignvnx16sf */

        case 5:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4743; /* pred_xorsignvnx1df */

        case 6:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4746; /* pred_xorsignvnx2df */

        case 7:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4749; /* pred_xorsignvnx4df */

        case 8:
          if (!(
#line 5470 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4752; /* pred_xorsignvnx8df */

        case 9:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4755; /* pred_xorsignvnx1sf_scalar */

        case 10:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4758; /* pred_xorsignvnx2sf_scalar */

        case 11:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4761; /* pred_xorsignvnx4sf_scalar */

        case 12:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4764; /* pred_xorsignvnx8sf_scalar */

        case 13:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4767; /* pred_xorsignvnx16sf_scalar */

        case 14:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4770; /* pred_xorsignvnx1df_scalar */

        case 15:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4773; /* pred_xorsignvnx2df_scalar */

        case 16:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4776; /* pred_xorsignvnx4df_scalar */

        case 17:
          if (!(
#line 5491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4779; /* pred_xorsignvnx8df_scalar */

        default:
          return -1;
        }

    case 112:
      return recog_23 (x1, insn, pnum_clobbers);

    case 113:
      return recog_31 (x1, insn, pnum_clobbers);

    default:
      return -1;
    }
}

static int
recog_36 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[4] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[5] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[6] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[7] = x7;
  x8 = XEXP (x2, 1);
  switch (XINT (x8, 1))
    {
    case 93:
      x9 = XVECEXP (x8, 0, 0);
      operands[3] = x9;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          if (pattern276 (x2, E_VNx1QImode, E_VNx1BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4556; /* pred_iotavnx1qi */

        case E_VNx2QImode:
          if (pattern276 (x2, E_VNx2QImode, E_VNx2BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4557; /* pred_iotavnx2qi */

        case E_VNx4QImode:
          if (pattern276 (x2, E_VNx4QImode, E_VNx4BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4558; /* pred_iotavnx4qi */

        case E_VNx8QImode:
          if (pattern276 (x2, E_VNx8QImode, E_VNx8BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4559; /* pred_iotavnx8qi */

        case E_VNx16QImode:
          if (pattern276 (x2, E_VNx16QImode, E_VNx16BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4560; /* pred_iotavnx16qi */

        case E_VNx32QImode:
          if (pattern276 (x2, E_VNx32QImode, E_VNx32BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4561; /* pred_iotavnx32qi */

        case E_VNx64QImode:
          if (pattern276 (x2, E_VNx64QImode, E_VNx64BImode) != 0
              || !(
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 4562; /* pred_iotavnx64qi */

        case E_VNx1HImode:
          if (pattern276 (x2, E_VNx1HImode, E_VNx1BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4563; /* pred_iotavnx1hi */

        case E_VNx2HImode:
          if (pattern276 (x2, E_VNx2HImode, E_VNx2BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4564; /* pred_iotavnx2hi */

        case E_VNx4HImode:
          if (pattern276 (x2, E_VNx4HImode, E_VNx4BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4565; /* pred_iotavnx4hi */

        case E_VNx8HImode:
          if (pattern276 (x2, E_VNx8HImode, E_VNx8BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4566; /* pred_iotavnx8hi */

        case E_VNx16HImode:
          if (pattern276 (x2, E_VNx16HImode, E_VNx16BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4567; /* pred_iotavnx16hi */

        case E_VNx32HImode:
          if (pattern276 (x2, E_VNx32HImode, E_VNx32BImode) != 0
              || !(
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 4568; /* pred_iotavnx32hi */

        case E_VNx1SImode:
          if (pattern276 (x2, E_VNx1SImode, E_VNx1BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4569; /* pred_iotavnx1si */

        case E_VNx2SImode:
          if (pattern276 (x2, E_VNx2SImode, E_VNx2BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4570; /* pred_iotavnx2si */

        case E_VNx4SImode:
          if (pattern276 (x2, E_VNx4SImode, E_VNx4BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4571; /* pred_iotavnx4si */

        case E_VNx8SImode:
          if (pattern276 (x2, E_VNx8SImode, E_VNx8BImode) != 0
              || !
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 4572; /* pred_iotavnx8si */

        case E_VNx16SImode:
          if (pattern276 (x2, E_VNx16SImode, E_VNx16BImode) != 0
              || !(
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 4573; /* pred_iotavnx16si */

        case E_VNx1DImode:
          if (pattern276 (x2, E_VNx1DImode, E_VNx1BImode) != 0
              || !(
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 4574; /* pred_iotavnx1di */

        case E_VNx2DImode:
          if (pattern276 (x2, E_VNx2DImode, E_VNx2BImode) != 0
              || !(
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 4575; /* pred_iotavnx2di */

        case E_VNx4DImode:
          if (pattern276 (x2, E_VNx4DImode, E_VNx4BImode) != 0
              || !(
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 4576; /* pred_iotavnx4di */

        case E_VNx8DImode:
          if (pattern276 (x2, E_VNx8DImode, E_VNx8BImode) != 0
              || !(
#line 5339 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 4577; /* pred_iotavnx8di */

        default:
          return -1;
        }

    case 94:
      switch (pattern250 (x2))
        {
        case 0:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5023; /* pred_rsqrt7vnx1sf */

        case 1:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5025; /* pred_rsqrt7vnx2sf */

        case 2:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5027; /* pred_rsqrt7vnx4sf */

        case 3:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5029; /* pred_rsqrt7vnx8sf */

        case 4:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5031; /* pred_rsqrt7vnx16sf */

        case 5:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5033; /* pred_rsqrt7vnx1df */

        case 6:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5035; /* pred_rsqrt7vnx2df */

        case 7:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5037; /* pred_rsqrt7vnx4df */

        case 8:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5039; /* pred_rsqrt7vnx8df */

        default:
          return -1;
        }

    case 95:
      switch (pattern250 (x2))
        {
        case 0:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5024; /* pred_rec7vnx1sf */

        case 1:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5026; /* pred_rec7vnx2sf */

        case 2:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5028; /* pred_rec7vnx4sf */

        case 3:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5030; /* pred_rec7vnx8sf */

        case 4:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5032; /* pred_rec7vnx16sf */

        case 5:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5034; /* pred_rec7vnx1df */

        case 6:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5036; /* pred_rec7vnx2df */

        case 7:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5038; /* pred_rec7vnx4df */

        case 8:
          if (!(
#line 6043 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5040; /* pred_rec7vnx8df */

        default:
          return -1;
        }

    case 96:
      x9 = XVECEXP (x8, 0, 0);
      operands[3] = x9;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1SImode:
          if (pattern246 (x2, E_VNx1SImode, E_VNx1SFmode, E_VNx1BImode) != 0
              || !(
#line 6062 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5041; /* pred_classvnx1sf */

        case E_VNx2SImode:
          if (pattern246 (x2, E_VNx2SImode, E_VNx2SFmode, E_VNx2BImode) != 0
              || !(
#line 6062 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5042; /* pred_classvnx2sf */

        case E_VNx4SImode:
          if (pattern246 (x2, E_VNx4SImode, E_VNx4SFmode, E_VNx4BImode) != 0
              || !(
#line 6062 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5043; /* pred_classvnx4sf */

        case E_VNx8SImode:
          if (pattern246 (x2, E_VNx8SImode, E_VNx8SFmode, E_VNx8BImode) != 0
              || !(
#line 6062 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5044; /* pred_classvnx8sf */

        case E_VNx16SImode:
          if (pattern246 (x2, E_VNx16SImode, E_VNx16SFmode, E_VNx16BImode) != 0
              || !(
#line 6062 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5045; /* pred_classvnx16sf */

        case E_VNx1DImode:
          if (pattern246 (x2, E_VNx1DImode, E_VNx1DFmode, E_VNx1BImode) != 0
              || !(
#line 6062 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5046; /* pred_classvnx1df */

        case E_VNx2DImode:
          if (pattern246 (x2, E_VNx2DImode, E_VNx2DFmode, E_VNx2BImode) != 0
              || !(
#line 6062 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5047; /* pred_classvnx2df */

        case E_VNx4DImode:
          if (pattern246 (x2, E_VNx4DImode, E_VNx4DFmode, E_VNx4BImode) != 0
              || !(
#line 6062 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5048; /* pred_classvnx4df */

        case E_VNx8DImode:
          if (pattern246 (x2, E_VNx8DImode, E_VNx8DFmode, E_VNx8BImode) != 0
              || !(
#line 6062 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5049; /* pred_classvnx8df */

        default:
          return -1;
        }

    case 100:
      switch (pattern251 (x2))
        {
        case 0:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5185; /* pred_fcvt_x_fvnx1sf */

        case 1:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5287; /* pred_narrow_fcvt_x_fvnx1df */

        case 2:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5187; /* pred_fcvt_x_fvnx2sf */

        case 3:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5289; /* pred_narrow_fcvt_x_fvnx2df */

        case 4:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5189; /* pred_fcvt_x_fvnx4sf */

        case 5:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5291; /* pred_narrow_fcvt_x_fvnx4df */

        case 6:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5191; /* pred_fcvt_x_fvnx8sf */

        case 7:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5293; /* pred_narrow_fcvt_x_fvnx8df */

        case 8:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5193; /* pred_fcvt_x_fvnx16sf */

        case 9:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5195; /* pred_fcvt_x_fvnx1df */

        case 10:
          if (!(
#line 6567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 416 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5239; /* pred_widen_fcvt_x_fvnx1di */

        case 11:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5197; /* pred_fcvt_x_fvnx2df */

        case 12:
          if (!(
#line 6567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 417 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5241; /* pred_widen_fcvt_x_fvnx2di */

        case 13:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5199; /* pred_fcvt_x_fvnx4df */

        case 14:
          if (!(
#line 6567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5243; /* pred_widen_fcvt_x_fvnx4di */

        case 15:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5201; /* pred_fcvt_x_fvnx8df */

        case 16:
          if (!(
#line 6567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 419 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5245; /* pred_widen_fcvt_x_fvnx8di */

        case 17:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5277; /* pred_narrow_fcvt_x_fvnx1sf */

        case 18:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5279; /* pred_narrow_fcvt_x_fvnx2sf */

        case 19:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5281; /* pred_narrow_fcvt_x_fvnx4sf */

        case 20:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5283; /* pred_narrow_fcvt_x_fvnx8sf */

        case 21:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5285; /* pred_narrow_fcvt_x_fvnx16sf */

        default:
          return -1;
        }

    case 101:
      switch (pattern251 (x2))
        {
        case 0:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5186; /* pred_fcvt_xu_fvnx1sf */

        case 1:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5288; /* pred_narrow_fcvt_xu_fvnx1df */

        case 2:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5188; /* pred_fcvt_xu_fvnx2sf */

        case 3:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5290; /* pred_narrow_fcvt_xu_fvnx2df */

        case 4:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5190; /* pred_fcvt_xu_fvnx4sf */

        case 5:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5292; /* pred_narrow_fcvt_xu_fvnx4df */

        case 6:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5192; /* pred_fcvt_xu_fvnx8sf */

        case 7:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5294; /* pred_narrow_fcvt_xu_fvnx8df */

        case 8:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5194; /* pred_fcvt_xu_fvnx16sf */

        case 9:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5196; /* pred_fcvt_xu_fvnx1df */

        case 10:
          if (!(
#line 6567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 416 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5240; /* pred_widen_fcvt_xu_fvnx1di */

        case 11:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5198; /* pred_fcvt_xu_fvnx2df */

        case 12:
          if (!(
#line 6567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 417 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5242; /* pred_widen_fcvt_xu_fvnx2di */

        case 13:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5200; /* pred_fcvt_xu_fvnx4df */

        case 14:
          if (!(
#line 6567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5244; /* pred_widen_fcvt_xu_fvnx4di */

        case 15:
          if (!(
#line 6503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5202; /* pred_fcvt_xu_fvnx8df */

        case 16:
          if (!(
#line 6567 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 419 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5246; /* pred_widen_fcvt_xu_fvnx8di */

        case 17:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5278; /* pred_narrow_fcvt_xu_fvnx1sf */

        case 18:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5280; /* pred_narrow_fcvt_xu_fvnx2sf */

        case 19:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5282; /* pred_narrow_fcvt_xu_fvnx4sf */

        case 20:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5284; /* pred_narrow_fcvt_xu_fvnx8sf */

        case 21:
          if (!(
#line 6650 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5286; /* pred_narrow_fcvt_xu_fvnx16sf */

        default:
          return -1;
        }

    case 102:
      x9 = XVECEXP (x8, 0, 0);
      if (GET_CODE (x9) != FLOAT_TRUNCATE)
        return -1;
      x10 = XEXP (x9, 0);
      operands[3] = x10;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1SFmode:
          if (pattern286 (x2, E_VNx1SFmode, E_VNx1DFmode, E_VNx1BImode) != 0
              || !(
#line 6727 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5325; /* pred_rod_truncvnx1df */

        case E_VNx2SFmode:
          if (pattern286 (x2, E_VNx2SFmode, E_VNx2DFmode, E_VNx2BImode) != 0
              || !(
#line 6727 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5326; /* pred_rod_truncvnx2df */

        case E_VNx4SFmode:
          if (pattern286 (x2, E_VNx4SFmode, E_VNx4DFmode, E_VNx4BImode) != 0
              || !(
#line 6727 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5327; /* pred_rod_truncvnx4df */

        case E_VNx8SFmode:
          if (pattern286 (x2, E_VNx8SFmode, E_VNx8DFmode, E_VNx8BImode) != 0
              || !(
#line 6727 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5328; /* pred_rod_truncvnx8df */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_37 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern236 (x2, E_VNx8DFmode, E_VNx8BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx8DFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[2])
          && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4796; /* *pred_maddvnx8df */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4814; /* *pred_maccvnx8df */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx8DFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx8DFmode)
      || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
    return -1;
  return 4832; /* *pred_mul_addvnx8df */
}

static int
recog_38 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern236 (x2, E_VNx4DFmode, E_VNx4BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx4DFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[2])
          && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4794; /* *pred_maddvnx4df */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4812; /* *pred_maccvnx4df */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx4DFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx4DFmode)
      || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
    return -1;
  return 4830; /* *pred_mul_addvnx4df */
}

static int
recog_39 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern236 (x2, E_VNx2DFmode, E_VNx2BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx2DFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[2])
          && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4792; /* *pred_maddvnx2df */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4810; /* *pred_maccvnx2df */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx2DFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx2DFmode)
      || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
    return -1;
  return 4828; /* *pred_mul_addvnx2df */
}

static int
recog_40 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern236 (x2, E_VNx1DFmode, E_VNx1BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx1DFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[2])
          && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4790; /* *pred_maddvnx1df */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4808; /* *pred_maccvnx1df */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx1DFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx1DFmode)
      || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
    return -1;
  return 4826; /* *pred_mul_addvnx1df */
}

static int
recog_41 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern236 (x2, E_VNx16SFmode, E_VNx16BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx16SFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[2])
          && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return 4788; /* *pred_maddvnx16sf */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return 4806; /* *pred_maccvnx16sf */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx16SFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx16SFmode)
      || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
    return -1;
  return 4824; /* *pred_mul_addvnx16sf */
}

static int
recog_42 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern236 (x2, E_VNx8SFmode, E_VNx8BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx8SFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[2])
          && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4786; /* *pred_maddvnx8sf */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4804; /* *pred_maccvnx8sf */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx8SFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx8SFmode)
      || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
    return -1;
  return 4822; /* *pred_mul_addvnx8sf */
}

static int
recog_43 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern236 (x2, E_VNx4SFmode, E_VNx4BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx4SFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[2])
          && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4784; /* *pred_maddvnx4sf */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4802; /* *pred_maccvnx4sf */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx4SFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx4SFmode)
      || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
    return -1;
  return 4820; /* *pred_mul_addvnx4sf */
}

static int
recog_44 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern236 (x2, E_VNx2SFmode, E_VNx2BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx2SFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[2])
          && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4782; /* *pred_maddvnx2sf */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4800; /* *pred_maccvnx2sf */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx2SFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx2SFmode)
      || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
    return -1;
  return 4818; /* *pred_mul_addvnx2sf */
}

static int
recog_45 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern236 (x2, E_VNx1SFmode, E_VNx1BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx1SFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[2])
          && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4780; /* *pred_maddvnx1sf */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4798; /* *pred_maccvnx1sf */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx1SFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx1SFmode)
      || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
    return -1;
  return 4816; /* *pred_mul_addvnx1sf */
}

static int
recog_46 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern277 (x2, E_VNx8DImode, E_VNx8BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx8DImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4529 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4186; /* *pred_maddvnx8di_extended_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4562 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4190; /* *pred_maccvnx8di_extended_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx8DImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx8DImode)
      || !(
#line 4595 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    return -1;
  return 4194; /* *pred_mul_plusvnx8di_extended_scalar */
}

static int
recog_47 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern277 (x2, E_VNx4DImode, E_VNx4BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx4DImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4529 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4185; /* *pred_maddvnx4di_extended_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4562 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4189; /* *pred_maccvnx4di_extended_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx4DImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx4DImode)
      || !(
#line 4595 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    return -1;
  return 4193; /* *pred_mul_plusvnx4di_extended_scalar */
}

static int
recog_48 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern277 (x2, E_VNx2DImode, E_VNx2BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx2DImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4529 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4184; /* *pred_maddvnx2di_extended_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4562 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4188; /* *pred_maccvnx2di_extended_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx2DImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx2DImode)
      || !(
#line 4595 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    return -1;
  return 4192; /* *pred_mul_plusvnx2di_extended_scalar */
}

static int
recog_49 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern277 (x2, E_VNx1DImode, E_VNx1BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx1DImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4529 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4183; /* *pred_maddvnx1di_extended_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4562 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4187; /* *pred_maccvnx1di_extended_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx1DImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx1DImode)
      || !(
#line 4595 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    return -1;
  return 4191; /* *pred_mul_plusvnx1di_extended_scalar */
}

static int
recog_50 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern237 (x2, E_VNx8DFmode, E_VNx8BImode, E_DFmode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx8DFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4850; /* *pred_maddvnx8df_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4868; /* *pred_maccvnx8df_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx8DFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx8DFmode)
      || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
    return -1;
  return 4886; /* *pred_mul_addvnx8df_scalar */
}

static int
recog_51 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern237 (x2, E_VNx4DFmode, E_VNx4BImode, E_DFmode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx4DFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4848; /* *pred_maddvnx4df_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4866; /* *pred_maccvnx4df_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx4DFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx4DFmode)
      || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
    return -1;
  return 4884; /* *pred_mul_addvnx4df_scalar */
}

static int
recog_52 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern237 (x2, E_VNx2DFmode, E_VNx2BImode, E_DFmode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx2DFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4846; /* *pred_maddvnx2df_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4864; /* *pred_maccvnx2df_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx2DFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx2DFmode)
      || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
    return -1;
  return 4882; /* *pred_mul_addvnx2df_scalar */
}

static int
recog_53 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern237 (x2, E_VNx1DFmode, E_VNx1BImode, E_DFmode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx1DFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4844; /* *pred_maddvnx1df_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 4862; /* *pred_maccvnx1df_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx1DFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx1DFmode)
      || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
    return -1;
  return 4880; /* *pred_mul_addvnx1df_scalar */
}

static int
recog_54 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern237 (x2, E_VNx16SFmode, E_VNx16BImode, E_SFmode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx16SFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return 4842; /* *pred_maddvnx16sf_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return 4860; /* *pred_maccvnx16sf_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx16SFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx16SFmode)
      || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
    return -1;
  return 4878; /* *pred_mul_addvnx16sf_scalar */
}

static int
recog_55 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern237 (x2, E_VNx8SFmode, E_VNx8BImode, E_SFmode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx8SFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4840; /* *pred_maddvnx8sf_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4858; /* *pred_maccvnx8sf_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx8SFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx8SFmode)
      || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
    return -1;
  return 4876; /* *pred_mul_addvnx8sf_scalar */
}

static int
recog_56 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern237 (x2, E_VNx4SFmode, E_VNx4BImode, E_SFmode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx4SFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4838; /* *pred_maddvnx4sf_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4856; /* *pred_maccvnx4sf_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx4SFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx4SFmode)
      || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
    return -1;
  return 4874; /* *pred_mul_addvnx4sf_scalar */
}

static int
recog_57 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern237 (x2, E_VNx2SFmode, E_VNx2BImode, E_SFmode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx2SFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4836; /* *pred_maddvnx2sf_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4854; /* *pred_maccvnx2sf_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx2SFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx2SFmode)
      || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
    return -1;
  return 4872; /* *pred_mul_addvnx2sf_scalar */
}

static int
recog_58 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern237 (x2, E_VNx1SFmode, E_VNx1BImode, E_SFmode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx1SFmode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4834; /* *pred_maddvnx1sf_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 4852; /* *pred_maccvnx1sf_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx1SFmode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx1SFmode)
      || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
    return -1;
  return 4870; /* *pred_mul_addvnx1sf_scalar */
}

static int
recog_59 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  x5 = XEXP (x4, 1);
  operands[3] = x5;
  x6 = XEXP (x3, 1);
  operands[4] = x6;
  x7 = XEXP (x4, 0);
  x8 = XEXP (x7, 0);
  switch (pattern219 (x8))
    {
    case 0:
      if (pattern237 (x2, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx1QImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4117; /* *pred_maddvnx1qi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4139; /* *pred_maccvnx1qi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx1QImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx1QImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4161; /* *pred_mul_plusvnx1qi_scalar */

    case 1:
      if (pattern237 (x2, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx2QImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4118; /* *pred_maddvnx2qi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4140; /* *pred_maccvnx2qi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx2QImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx2QImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4162; /* *pred_mul_plusvnx2qi_scalar */

    case 2:
      if (pattern237 (x2, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx4QImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4119; /* *pred_maddvnx4qi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4141; /* *pred_maccvnx4qi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx4QImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx4QImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4163; /* *pred_mul_plusvnx4qi_scalar */

    case 3:
      if (pattern237 (x2, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx8QImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4120; /* *pred_maddvnx8qi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4142; /* *pred_maccvnx8qi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx8QImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx8QImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4164; /* *pred_mul_plusvnx8qi_scalar */

    case 4:
      if (pattern237 (x2, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx16QImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4121; /* *pred_maddvnx16qi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4143; /* *pred_maccvnx16qi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx16QImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx16QImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4165; /* *pred_mul_plusvnx16qi_scalar */

    case 5:
      if (pattern237 (x2, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx32QImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4122; /* *pred_maddvnx32qi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4144; /* *pred_maccvnx32qi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx32QImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx32QImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4166; /* *pred_mul_plusvnx32qi_scalar */

    case 6:
      if (pattern237 (x2, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx64QImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && (
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4123; /* *pred_maddvnx64qi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && (
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4145; /* *pred_maccvnx64qi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx64QImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx64QImode)
          || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 4167; /* *pred_mul_plusvnx64qi_scalar */

    case 7:
      if (pattern237 (x2, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx1HImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4124; /* *pred_maddvnx1hi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4146; /* *pred_maccvnx1hi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx1HImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx1HImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4168; /* *pred_mul_plusvnx1hi_scalar */

    case 8:
      if (pattern237 (x2, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx2HImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4125; /* *pred_maddvnx2hi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4147; /* *pred_maccvnx2hi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx2HImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx2HImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4169; /* *pred_mul_plusvnx2hi_scalar */

    case 9:
      if (pattern237 (x2, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx4HImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4126; /* *pred_maddvnx4hi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4148; /* *pred_maccvnx4hi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx4HImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx4HImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4170; /* *pred_mul_plusvnx4hi_scalar */

    case 10:
      if (pattern237 (x2, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx8HImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4127; /* *pred_maddvnx8hi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4149; /* *pred_maccvnx8hi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx8HImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx8HImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4171; /* *pred_mul_plusvnx8hi_scalar */

    case 11:
      if (pattern237 (x2, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx16HImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4128; /* *pred_maddvnx16hi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4150; /* *pred_maccvnx16hi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx16HImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx16HImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4172; /* *pred_mul_plusvnx16hi_scalar */

    case 12:
      if (pattern237 (x2, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx32HImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && (
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4129; /* *pred_maddvnx32hi_scalar */
          if (rtx_equal_p (x14, operands[4])
              && (
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4151; /* *pred_maccvnx32hi_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx32HImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx32HImode)
          || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 4173; /* *pred_mul_plusvnx32hi_scalar */

    case 13:
      if (pattern237 (x2, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx1SImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4130; /* *pred_maddvnx1si_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4152; /* *pred_maccvnx1si_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx1SImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx1SImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4174; /* *pred_mul_plusvnx1si_scalar */

    case 14:
      if (pattern237 (x2, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx2SImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4131; /* *pred_maddvnx2si_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4153; /* *pred_maccvnx2si_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx2SImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx2SImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4175; /* *pred_mul_plusvnx2si_scalar */

    case 15:
      if (pattern237 (x2, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx4SImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4132; /* *pred_maddvnx4si_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4154; /* *pred_maccvnx4si_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx4SImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx4SImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4176; /* *pred_mul_plusvnx4si_scalar */

    case 16:
      if (pattern237 (x2, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx8SImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && 
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4133; /* *pred_maddvnx8si_scalar */
          if (rtx_equal_p (x14, operands[4])
              && 
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4155; /* *pred_maccvnx8si_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx8SImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx8SImode)
          || !
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4177; /* *pred_mul_plusvnx8si_scalar */

    case 17:
      if (pattern237 (x2, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx16SImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && (
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4134; /* *pred_maddvnx16si_scalar */
          if (rtx_equal_p (x14, operands[4])
              && (
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4156; /* *pred_maccvnx16si_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx16SImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx16SImode)
          || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 4178; /* *pred_mul_plusvnx16si_scalar */

    case 18:
      if (pattern237 (x2, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx1DImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && (
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4135; /* *pred_maddvnx1di_scalar */
          if (rtx_equal_p (x14, operands[4])
              && (
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4157; /* *pred_maccvnx1di_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx1DImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx1DImode)
          || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4179; /* *pred_mul_plusvnx1di_scalar */

    case 19:
      if (pattern237 (x2, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx2DImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && (
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4136; /* *pred_maddvnx2di_scalar */
          if (rtx_equal_p (x14, operands[4])
              && (
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4158; /* *pred_maccvnx2di_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx2DImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx2DImode)
          || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4180; /* *pred_mul_plusvnx2di_scalar */

    case 20:
      if (pattern237 (x2, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx4DImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && (
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4137; /* *pred_maddvnx4di_scalar */
          if (rtx_equal_p (x14, operands[4])
              && (
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4159; /* *pred_maccvnx4di_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx4DImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx4DImode)
          || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4181; /* *pred_mul_plusvnx4di_scalar */

    case 21:
      if (pattern237 (x2, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0)
        return -1;
      x9 = XEXP (x2, 0);
      x10 = XVECEXP (x9, 0, 1);
      operands[5] = x10;
      x11 = XVECEXP (x9, 0, 2);
      operands[6] = x11;
      x12 = XVECEXP (x9, 0, 3);
      operands[7] = x12;
      x13 = XVECEXP (x9, 0, 4);
      operands[8] = x13;
      if (register_operand (operands[4], E_VNx8DImode))
        {
          x14 = XEXP (x2, 2);
          if (rtx_equal_p (x14, operands[3])
              && (
#line 4382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4138; /* *pred_maddvnx8di_scalar */
          if (rtx_equal_p (x14, operands[4])
              && (
#line 4414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4160; /* *pred_maccvnx8di_scalar */
        }
      operands[6] = x10;
      operands[7] = x11;
      operands[8] = x12;
      operands[9] = x13;
      if (!vector_arith_operand (operands[4], E_VNx8DImode))
        return -1;
      x14 = XEXP (x2, 2);
      operands[5] = x14;
      if (!register_operand (operands[5], E_VNx8DImode)
          || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4182; /* *pred_mul_plusvnx8di_scalar */

    case 22:
      return recog_58 (x1, insn, pnum_clobbers);

    case 23:
      return recog_57 (x1, insn, pnum_clobbers);

    case 24:
      return recog_56 (x1, insn, pnum_clobbers);

    case 25:
      return recog_55 (x1, insn, pnum_clobbers);

    case 26:
      return recog_54 (x1, insn, pnum_clobbers);

    case 27:
      return recog_53 (x1, insn, pnum_clobbers);

    case 28:
      return recog_52 (x1, insn, pnum_clobbers);

    case 29:
      return recog_51 (x1, insn, pnum_clobbers);

    case 30:
      return recog_50 (x1, insn, pnum_clobbers);

    case 31:
      return recog_49 (x1, insn, pnum_clobbers);

    case 32:
      return recog_48 (x1, insn, pnum_clobbers);

    case 33:
      return recog_47 (x1, insn, pnum_clobbers);

    case 34:
      return recog_46 (x1, insn, pnum_clobbers);

    default:
      return -1;
    }
}

static int
recog_60 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  x5 = XEXP (x4, 0);
  operands[2] = x5;
  x6 = XEXP (x4, 1);
  operands[3] = x6;
  x7 = XEXP (x3, 1);
  operands[4] = x7;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      if (pattern236 (x2, E_VNx1QImode, E_VNx1BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx1QImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4051; /* *pred_maddvnx1qi */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4073; /* *pred_maccvnx1qi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx1QImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx1QImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4095; /* *pred_mul_plusvnx1qi */

    case E_VNx2QImode:
      if (pattern236 (x2, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx2QImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4052; /* *pred_maddvnx2qi */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4074; /* *pred_maccvnx2qi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx2QImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx2QImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4096; /* *pred_mul_plusvnx2qi */

    case E_VNx4QImode:
      if (pattern236 (x2, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx4QImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4053; /* *pred_maddvnx4qi */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4075; /* *pred_maccvnx4qi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx4QImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx4QImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4097; /* *pred_mul_plusvnx4qi */

    case E_VNx8QImode:
      if (pattern236 (x2, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx8QImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4054; /* *pred_maddvnx8qi */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4076; /* *pred_maccvnx8qi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx8QImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx8QImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4098; /* *pred_mul_plusvnx8qi */

    case E_VNx16QImode:
      if (pattern236 (x2, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx16QImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4055; /* *pred_maddvnx16qi */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4077; /* *pred_maccvnx16qi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx16QImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx16QImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4099; /* *pred_mul_plusvnx16qi */

    case E_VNx32QImode:
      if (pattern236 (x2, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx32QImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4056; /* *pred_maddvnx32qi */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4078; /* *pred_maccvnx32qi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx32QImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx32QImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4100; /* *pred_mul_plusvnx32qi */

    case E_VNx64QImode:
      if (pattern236 (x2, E_VNx64QImode, E_VNx64BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx64QImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && (
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4057; /* *pred_maddvnx64qi */
          if (rtx_equal_p (x13, operands[4])
              && (
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4079; /* *pred_maccvnx64qi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx64QImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx64QImode)
          || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 4101; /* *pred_mul_plusvnx64qi */

    case E_VNx1HImode:
      if (pattern236 (x2, E_VNx1HImode, E_VNx1BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx1HImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4058; /* *pred_maddvnx1hi */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4080; /* *pred_maccvnx1hi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx1HImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx1HImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4102; /* *pred_mul_plusvnx1hi */

    case E_VNx2HImode:
      if (pattern236 (x2, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx2HImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4059; /* *pred_maddvnx2hi */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4081; /* *pred_maccvnx2hi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx2HImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx2HImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4103; /* *pred_mul_plusvnx2hi */

    case E_VNx4HImode:
      if (pattern236 (x2, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx4HImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4060; /* *pred_maddvnx4hi */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4082; /* *pred_maccvnx4hi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx4HImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx4HImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4104; /* *pred_mul_plusvnx4hi */

    case E_VNx8HImode:
      if (pattern236 (x2, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx8HImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4061; /* *pred_maddvnx8hi */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4083; /* *pred_maccvnx8hi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx8HImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx8HImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4105; /* *pred_mul_plusvnx8hi */

    case E_VNx16HImode:
      if (pattern236 (x2, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx16HImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4062; /* *pred_maddvnx16hi */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4084; /* *pred_maccvnx16hi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx16HImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx16HImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4106; /* *pred_mul_plusvnx16hi */

    case E_VNx32HImode:
      if (pattern236 (x2, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx32HImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && (
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4063; /* *pred_maddvnx32hi */
          if (rtx_equal_p (x13, operands[4])
              && (
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4085; /* *pred_maccvnx32hi */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx32HImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx32HImode)
          || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 4107; /* *pred_mul_plusvnx32hi */

    case E_VNx1SImode:
      if (pattern236 (x2, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx1SImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4064; /* *pred_maddvnx1si */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4086; /* *pred_maccvnx1si */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx1SImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx1SImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4108; /* *pred_mul_plusvnx1si */

    case E_VNx2SImode:
      if (pattern236 (x2, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx2SImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4065; /* *pred_maddvnx2si */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4087; /* *pred_maccvnx2si */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx2SImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx2SImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4109; /* *pred_mul_plusvnx2si */

    case E_VNx4SImode:
      if (pattern236 (x2, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx4SImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4066; /* *pred_maddvnx4si */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4088; /* *pred_maccvnx4si */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx4SImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx4SImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4110; /* *pred_mul_plusvnx4si */

    case E_VNx8SImode:
      if (pattern236 (x2, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx8SImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && 
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4067; /* *pred_maddvnx8si */
          if (rtx_equal_p (x13, operands[4])
              && 
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4089; /* *pred_maccvnx8si */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx8SImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx8SImode)
          || !
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4111; /* *pred_mul_plusvnx8si */

    case E_VNx16SImode:
      if (pattern236 (x2, E_VNx16SImode, E_VNx16BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx16SImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && (
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4068; /* *pred_maddvnx16si */
          if (rtx_equal_p (x13, operands[4])
              && (
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4090; /* *pred_maccvnx16si */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx16SImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx16SImode)
          || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 4112; /* *pred_mul_plusvnx16si */

    case E_VNx1DImode:
      if (pattern236 (x2, E_VNx1DImode, E_VNx1BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx1DImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && (
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4069; /* *pred_maddvnx1di */
          if (rtx_equal_p (x13, operands[4])
              && (
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4091; /* *pred_maccvnx1di */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx1DImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx1DImode)
          || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4113; /* *pred_mul_plusvnx1di */

    case E_VNx2DImode:
      if (pattern236 (x2, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx2DImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && (
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4070; /* *pred_maddvnx2di */
          if (rtx_equal_p (x13, operands[4])
              && (
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4092; /* *pred_maccvnx2di */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx2DImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx2DImode)
          || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4114; /* *pred_mul_plusvnx2di */

    case E_VNx4DImode:
      if (pattern236 (x2, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx4DImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && (
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4071; /* *pred_maddvnx4di */
          if (rtx_equal_p (x13, operands[4])
              && (
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4093; /* *pred_maccvnx4di */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx4DImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx4DImode)
          || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4115; /* *pred_mul_plusvnx4di */

    case E_VNx8DImode:
      if (pattern236 (x2, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      x8 = XEXP (x2, 0);
      x9 = XVECEXP (x8, 0, 1);
      operands[5] = x9;
      x10 = XVECEXP (x8, 0, 2);
      operands[6] = x10;
      x11 = XVECEXP (x8, 0, 3);
      operands[7] = x11;
      x12 = XVECEXP (x8, 0, 4);
      operands[8] = x12;
      if (register_operand (operands[4], E_VNx8DImode))
        {
          x13 = XEXP (x2, 2);
          if (rtx_equal_p (x13, operands[2])
              && (
#line 4245 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4072; /* *pred_maddvnx8di */
          if (rtx_equal_p (x13, operands[4])
              && (
#line 4276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4094; /* *pred_maccvnx8di */
        }
      operands[6] = x9;
      operands[7] = x10;
      operands[8] = x11;
      operands[9] = x12;
      if (!vector_arith_operand (operands[4], E_VNx8DImode))
        return -1;
      x13 = XEXP (x2, 2);
      operands[5] = x13;
      if (!register_operand (operands[5], E_VNx8DImode)
          || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4116; /* *pred_mul_plusvnx8di */

    case E_VNx1SFmode:
      return recog_45 (x1, insn, pnum_clobbers);

    case E_VNx2SFmode:
      return recog_44 (x1, insn, pnum_clobbers);

    case E_VNx4SFmode:
      return recog_43 (x1, insn, pnum_clobbers);

    case E_VNx8SFmode:
      return recog_42 (x1, insn, pnum_clobbers);

    case E_VNx16SFmode:
      return recog_41 (x1, insn, pnum_clobbers);

    case E_VNx1DFmode:
      return recog_40 (x1, insn, pnum_clobbers);

    case E_VNx2DFmode:
      return recog_39 (x1, insn, pnum_clobbers);

    case E_VNx4DFmode:
      return recog_38 (x1, insn, pnum_clobbers);

    case E_VNx8DFmode:
      return recog_37 (x1, insn, pnum_clobbers);

    default:
      return -1;
    }
}

static int
recog_61 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern187 (x2))
    {
    case 0:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx1SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4888; /* *pred_nmsubvnx1sf */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4906; /* *pred_nmsacvnx1sf */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx1SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx1SFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4924; /* *pred_mul_neg_addvnx1sf */

    case 1:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx2SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4890; /* *pred_nmsubvnx2sf */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4908; /* *pred_nmsacvnx2sf */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx2SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx2SFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4926; /* *pred_mul_neg_addvnx2sf */

    case 2:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx4SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4892; /* *pred_nmsubvnx4sf */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4910; /* *pred_nmsacvnx4sf */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx4SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx4SFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4928; /* *pred_mul_neg_addvnx4sf */

    case 3:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx8SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4894; /* *pred_nmsubvnx8sf */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4912; /* *pred_nmsacvnx8sf */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx8SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx8SFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4930; /* *pred_mul_neg_addvnx8sf */

    case 4:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx16SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return 4896; /* *pred_nmsubvnx16sf */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return 4914; /* *pred_nmsacvnx16sf */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx16SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx16SFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 4932; /* *pred_mul_neg_addvnx16sf */

    case 5:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx1DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4898; /* *pred_nmsubvnx1df */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4916; /* *pred_nmsacvnx1df */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx1DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx1DFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4934; /* *pred_mul_neg_addvnx1df */

    case 6:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx2DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4900; /* *pred_nmsubvnx2df */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4918; /* *pred_nmsacvnx2df */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx2DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx2DFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4936; /* *pred_mul_neg_addvnx2df */

    case 7:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx4DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4902; /* *pred_nmsubvnx4df */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4920; /* *pred_nmsacvnx4df */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx4DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx4DFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4938; /* *pred_mul_neg_addvnx4df */

    case 8:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx8DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4904; /* *pred_nmsubvnx8df */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4922; /* *pred_nmsacvnx8df */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx8DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx8DFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4940; /* *pred_mul_neg_addvnx8df */

    case 9:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx1SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4942; /* *pred_nmsubvnx1sf_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4960; /* *pred_nmsacvnx1sf_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx1SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx1SFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4978; /* *pred_mul_neg_addvnx1sf_scalar */

    case 10:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx2SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4944; /* *pred_nmsubvnx2sf_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4962; /* *pred_nmsacvnx2sf_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx2SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx2SFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4980; /* *pred_mul_neg_addvnx2sf_scalar */

    case 11:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx4SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4946; /* *pred_nmsubvnx4sf_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4964; /* *pred_nmsacvnx4sf_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx4SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx4SFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4982; /* *pred_mul_neg_addvnx4sf_scalar */

    case 12:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx8SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4948; /* *pred_nmsubvnx8sf_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4966; /* *pred_nmsacvnx8sf_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx8SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx8SFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4984; /* *pred_mul_neg_addvnx8sf_scalar */

    case 13:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx16SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return 4950; /* *pred_nmsubvnx16sf_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return 4968; /* *pred_nmsacvnx16sf_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx16SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx16SFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 4986; /* *pred_mul_neg_addvnx16sf_scalar */

    case 14:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx1DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4952; /* *pred_nmsubvnx1df_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4970; /* *pred_nmsacvnx1df_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx1DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx1DFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4988; /* *pred_mul_neg_addvnx1df_scalar */

    case 15:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx2DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4954; /* *pred_nmsubvnx2df_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4972; /* *pred_nmsacvnx2df_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx2DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx2DFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4990; /* *pred_mul_neg_addvnx2df_scalar */

    case 16:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx4DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4956; /* *pred_nmsubvnx4df_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4974; /* *pred_nmsacvnx4df_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx4DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx4DFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4992; /* *pred_mul_neg_addvnx4df_scalar */

    case 17:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx8DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4958; /* *pred_nmsubvnx8df_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4976; /* *pred_nmsacvnx8df_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx8DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx8DFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4994; /* *pred_mul_neg_addvnx8df_scalar */

    case 18:
      if (!(
#line 6240 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5106; /* pred_widen_mul_neg_addvnx1df */

    case 19:
      if (!(
#line 6240 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5108; /* pred_widen_mul_neg_addvnx2df */

    case 20:
      if (!(
#line 6240 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5110; /* pred_widen_mul_neg_addvnx4df */

    case 21:
      if (!(
#line 6240 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5112; /* pred_widen_mul_neg_addvnx8df */

    case 22:
      if (!(
#line 6266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5114; /* pred_widen_mul_neg_addvnx1df_scalar */

    case 23:
      if (!(
#line 6266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5116; /* pred_widen_mul_neg_addvnx2df_scalar */

    case 24:
      if (!(
#line 6266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5118; /* pred_widen_mul_neg_addvnx4df_scalar */

    case 25:
      if (!(
#line 6266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5120; /* pred_widen_mul_neg_addvnx8df_scalar */

    default:
      return -1;
    }
}

static int
recog_62 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  operands[3] = x4;
  x5 = XEXP (x2, 0);
  x6 = XVECEXP (x5, 0, 1);
  operands[5] = x6;
  x7 = XVECEXP (x5, 0, 2);
  operands[6] = x7;
  x8 = XVECEXP (x5, 0, 3);
  operands[7] = x8;
  x9 = XVECEXP (x5, 0, 4);
  operands[8] = x9;
  x10 = XEXP (x2, 2);
  operands[2] = x10;
  x11 = XEXP (x3, 1);
  switch (GET_CODE (x11))
    {
    case CONST_VECTOR:
    case REG:
    case SUBREG:
      operands[4] = x11;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          if (pattern143 (x2, E_VNx1QImode, E_VNx1BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1482; /* pred_addvnx1qi */

        case E_VNx2QImode:
          if (pattern143 (x2, E_VNx2QImode, E_VNx2BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1499; /* pred_addvnx2qi */

        case E_VNx4QImode:
          if (pattern143 (x2, E_VNx4QImode, E_VNx4BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1516; /* pred_addvnx4qi */

        case E_VNx8QImode:
          if (pattern143 (x2, E_VNx8QImode, E_VNx8BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1533; /* pred_addvnx8qi */

        case E_VNx16QImode:
          if (pattern143 (x2, E_VNx16QImode, E_VNx16BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1550; /* pred_addvnx16qi */

        case E_VNx32QImode:
          if (pattern143 (x2, E_VNx32QImode, E_VNx32BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1567; /* pred_addvnx32qi */

        case E_VNx64QImode:
          if (pattern143 (x2, E_VNx64QImode, E_VNx64BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1584; /* pred_addvnx64qi */

        case E_VNx1HImode:
          if (pattern143 (x2, E_VNx1HImode, E_VNx1BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1601; /* pred_addvnx1hi */

        case E_VNx2HImode:
          if (pattern143 (x2, E_VNx2HImode, E_VNx2BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1618; /* pred_addvnx2hi */

        case E_VNx4HImode:
          if (pattern143 (x2, E_VNx4HImode, E_VNx4BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1635; /* pred_addvnx4hi */

        case E_VNx8HImode:
          if (pattern143 (x2, E_VNx8HImode, E_VNx8BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1652; /* pred_addvnx8hi */

        case E_VNx16HImode:
          if (pattern143 (x2, E_VNx16HImode, E_VNx16BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1669; /* pred_addvnx16hi */

        case E_VNx32HImode:
          if (pattern143 (x2, E_VNx32HImode, E_VNx32BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1686; /* pred_addvnx32hi */

        case E_VNx1SImode:
          if (pattern143 (x2, E_VNx1SImode, E_VNx1BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1703; /* pred_addvnx1si */

        case E_VNx2SImode:
          if (pattern143 (x2, E_VNx2SImode, E_VNx2BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1720; /* pred_addvnx2si */

        case E_VNx4SImode:
          if (pattern143 (x2, E_VNx4SImode, E_VNx4BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1737; /* pred_addvnx4si */

        case E_VNx8SImode:
          if (pattern143 (x2, E_VNx8SImode, E_VNx8BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1754; /* pred_addvnx8si */

        case E_VNx16SImode:
          if (pattern143 (x2, E_VNx16SImode, E_VNx16BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1771; /* pred_addvnx16si */

        case E_VNx1DImode:
          if (pattern143 (x2, E_VNx1DImode, E_VNx1BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1788; /* pred_addvnx1di */

        case E_VNx2DImode:
          if (pattern143 (x2, E_VNx2DImode, E_VNx2BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1805; /* pred_addvnx2di */

        case E_VNx4DImode:
          if (pattern143 (x2, E_VNx4DImode, E_VNx4BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1822; /* pred_addvnx4di */

        case E_VNx8DImode:
          if (pattern143 (x2, E_VNx8DImode, E_VNx8BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1839; /* pred_addvnx8di */

        case E_VNx1SFmode:
          if (pattern153 (x2, E_VNx1SFmode, E_VNx1BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4600; /* pred_addvnx1sf */

        case E_VNx2SFmode:
          if (pattern153 (x2, E_VNx2SFmode, E_VNx2BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4606; /* pred_addvnx2sf */

        case E_VNx4SFmode:
          if (pattern153 (x2, E_VNx4SFmode, E_VNx4BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4612; /* pred_addvnx4sf */

        case E_VNx8SFmode:
          if (pattern153 (x2, E_VNx8SFmode, E_VNx8BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4618; /* pred_addvnx8sf */

        case E_VNx16SFmode:
          if (pattern153 (x2, E_VNx16SFmode, E_VNx16BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4624; /* pred_addvnx16sf */

        case E_VNx1DFmode:
          if (pattern153 (x2, E_VNx1DFmode, E_VNx1BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4630; /* pred_addvnx1df */

        case E_VNx2DFmode:
          if (pattern153 (x2, E_VNx2DFmode, E_VNx2BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4636; /* pred_addvnx2df */

        case E_VNx4DFmode:
          if (pattern153 (x2, E_VNx4DFmode, E_VNx4BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4642; /* pred_addvnx4df */

        case E_VNx8DFmode:
          if (pattern153 (x2, E_VNx8DFmode, E_VNx8BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4648; /* pred_addvnx8df */

        default:
          return -1;
        }

    case SIGN_EXTEND:
      switch (pattern205 (x2))
        {
        case 0:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3024; /* pred_single_widen_addsvnx1hi */

        case 1:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3028; /* pred_single_widen_addsvnx2hi */

        case 2:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3032; /* pred_single_widen_addsvnx4hi */

        case 3:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3036; /* pred_single_widen_addsvnx8hi */

        case 4:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3040; /* pred_single_widen_addsvnx16hi */

        case 5:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3044; /* pred_single_widen_addsvnx32hi */

        case 6:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3048; /* pred_single_widen_addsvnx1si */

        case 7:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3052; /* pred_single_widen_addsvnx2si */

        case 8:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3056; /* pred_single_widen_addsvnx4si */

        case 9:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3060; /* pred_single_widen_addsvnx8si */

        case 10:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3064; /* pred_single_widen_addsvnx16si */

        case 11:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3068; /* pred_single_widen_addsvnx1di */

        case 12:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3072; /* pred_single_widen_addsvnx2di */

        case 13:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3076; /* pred_single_widen_addsvnx4di */

        case 14:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3080; /* pred_single_widen_addsvnx8di */

        case 15:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3084; /* pred_single_widen_addsvnx1hi_scalar */

        case 16:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3088; /* pred_single_widen_addsvnx2hi_scalar */

        case 17:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3092; /* pred_single_widen_addsvnx4hi_scalar */

        case 18:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3096; /* pred_single_widen_addsvnx8hi_scalar */

        case 19:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3100; /* pred_single_widen_addsvnx16hi_scalar */

        case 20:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3104; /* pred_single_widen_addsvnx32hi_scalar */

        case 21:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3108; /* pred_single_widen_addsvnx1si_scalar */

        case 22:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3112; /* pred_single_widen_addsvnx2si_scalar */

        case 23:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3116; /* pred_single_widen_addsvnx4si_scalar */

        case 24:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3120; /* pred_single_widen_addsvnx8si_scalar */

        case 25:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3124; /* pred_single_widen_addsvnx16si_scalar */

        case 26:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3128; /* pred_single_widen_addsvnx1di_scalar */

        case 27:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3132; /* pred_single_widen_addsvnx2di_scalar */

        case 28:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3136; /* pred_single_widen_addsvnx4di_scalar */

        case 29:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3140; /* pred_single_widen_addsvnx8di_scalar */

        default:
          return -1;
        }

    case ZERO_EXTEND:
      switch (pattern205 (x2))
        {
        case 0:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3026; /* pred_single_widen_adduvnx1hi */

        case 1:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3030; /* pred_single_widen_adduvnx2hi */

        case 2:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3034; /* pred_single_widen_adduvnx4hi */

        case 3:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3038; /* pred_single_widen_adduvnx8hi */

        case 4:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3042; /* pred_single_widen_adduvnx16hi */

        case 5:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3046; /* pred_single_widen_adduvnx32hi */

        case 6:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3050; /* pred_single_widen_adduvnx1si */

        case 7:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3054; /* pred_single_widen_adduvnx2si */

        case 8:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3058; /* pred_single_widen_adduvnx4si */

        case 9:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3062; /* pred_single_widen_adduvnx8si */

        case 10:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3066; /* pred_single_widen_adduvnx16si */

        case 11:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3070; /* pred_single_widen_adduvnx1di */

        case 12:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3074; /* pred_single_widen_adduvnx2di */

        case 13:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3078; /* pred_single_widen_adduvnx4di */

        case 14:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3082; /* pred_single_widen_adduvnx8di */

        case 15:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3086; /* pred_single_widen_adduvnx1hi_scalar */

        case 16:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3090; /* pred_single_widen_adduvnx2hi_scalar */

        case 17:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3094; /* pred_single_widen_adduvnx4hi_scalar */

        case 18:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3098; /* pred_single_widen_adduvnx8hi_scalar */

        case 19:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3102; /* pred_single_widen_adduvnx16hi_scalar */

        case 20:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3106; /* pred_single_widen_adduvnx32hi_scalar */

        case 21:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3110; /* pred_single_widen_adduvnx1si_scalar */

        case 22:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3114; /* pred_single_widen_adduvnx2si_scalar */

        case 23:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3118; /* pred_single_widen_adduvnx4si_scalar */

        case 24:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3122; /* pred_single_widen_adduvnx8si_scalar */

        case 25:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3126; /* pred_single_widen_adduvnx16si_scalar */

        case 26:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3130; /* pred_single_widen_adduvnx1di_scalar */

        case 27:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3134; /* pred_single_widen_adduvnx2di_scalar */

        case 28:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3138; /* pred_single_widen_adduvnx4di_scalar */

        case 29:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3142; /* pred_single_widen_adduvnx8di_scalar */

        default:
          return -1;
        }

    case FLOAT_EXTEND:
      switch (pattern268 (x2))
        {
        case 0:
          if (!(
#line 6137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5074; /* pred_single_widen_addvnx1df */

        case 1:
          if (!(
#line 6137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5076; /* pred_single_widen_addvnx2df */

        case 2:
          if (!(
#line 6137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5078; /* pred_single_widen_addvnx4df */

        case 3:
          if (!(
#line 6137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5080; /* pred_single_widen_addvnx8df */

        case 4:
          if (!(
#line 6159 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5082; /* pred_single_widen_addvnx1df_scalar */

        case 5:
          if (!(
#line 6159 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5084; /* pred_single_widen_addvnx2df_scalar */

        case 6:
          if (!(
#line 6159 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5086; /* pred_single_widen_addvnx4df_scalar */

        case 7:
          if (!(
#line 6159 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5088; /* pred_single_widen_addvnx8df_scalar */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_63 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  x5 = XEXP (x4, 0);
  switch (GET_CODE (x5))
    {
    case REG:
    case SUBREG:
      return recog_60 (x1, insn, pnum_clobbers);

    case VEC_DUPLICATE:
      return recog_59 (x1, insn, pnum_clobbers);

    case SIGN_EXTEND:
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      x11 = XEXP (x3, 1);
      operands[2] = x11;
      x12 = XEXP (x2, 2);
      if (!rtx_equal_p (x12, operands[2]))
        return -1;
      x13 = XEXP (x5, 0);
      switch (GET_CODE (x13))
        {
        case REG:
        case SUBREG:
          operands[3] = x13;
          x14 = XEXP (x4, 1);
          switch (GET_CODE (x14))
            {
            case SIGN_EXTEND:
              switch (pattern290 (x2))
                {
                case 0:
                  if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4339; /* pred_widen_mul_plussvnx1hi */

                case 1:
                  if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4341; /* pred_widen_mul_plussvnx2hi */

                case 2:
                  if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4343; /* pred_widen_mul_plussvnx4hi */

                case 3:
                  if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4345; /* pred_widen_mul_plussvnx8hi */

                case 4:
                  if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4347; /* pred_widen_mul_plussvnx16hi */

                case 5:
                  if (!(
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4349; /* pred_widen_mul_plussvnx32hi */

                case 6:
                  if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4351; /* pred_widen_mul_plussvnx1si */

                case 7:
                  if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4353; /* pred_widen_mul_plussvnx2si */

                case 8:
                  if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4355; /* pred_widen_mul_plussvnx4si */

                case 9:
                  if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4357; /* pred_widen_mul_plussvnx8si */

                case 10:
                  if (!(
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4359; /* pred_widen_mul_plussvnx16si */

                case 11:
                  if (!(
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4361; /* pred_widen_mul_plussvnx1di */

                case 12:
                  if (!(
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4363; /* pred_widen_mul_plussvnx2di */

                case 13:
                  if (!(
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4365; /* pred_widen_mul_plussvnx4di */

                case 14:
                  if (!(
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4367; /* pred_widen_mul_plussvnx8di */

                default:
                  return -1;
                }

            case ZERO_EXTEND:
              switch (pattern290 (x2))
                {
                case 0:
                  if (!
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4399; /* pred_widen_mul_plussuvnx1hi */

                case 1:
                  if (!
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4400; /* pred_widen_mul_plussuvnx2hi */

                case 2:
                  if (!
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4401; /* pred_widen_mul_plussuvnx4hi */

                case 3:
                  if (!
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4402; /* pred_widen_mul_plussuvnx8hi */

                case 4:
                  if (!
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4403; /* pred_widen_mul_plussuvnx16hi */

                case 5:
                  if (!(
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4404; /* pred_widen_mul_plussuvnx32hi */

                case 6:
                  if (!
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4405; /* pred_widen_mul_plussuvnx1si */

                case 7:
                  if (!
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4406; /* pred_widen_mul_plussuvnx2si */

                case 8:
                  if (!
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4407; /* pred_widen_mul_plussuvnx4si */

                case 9:
                  if (!
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4408; /* pred_widen_mul_plussuvnx8si */

                case 10:
                  if (!(
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4409; /* pred_widen_mul_plussuvnx16si */

                case 11:
                  if (!(
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4410; /* pred_widen_mul_plussuvnx1di */

                case 12:
                  if (!(
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4411; /* pred_widen_mul_plussuvnx2di */

                case 13:
                  if (!(
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4412; /* pred_widen_mul_plussuvnx4di */

                case 14:
                  if (!(
#line 5120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4413; /* pred_widen_mul_plussuvnx8di */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        case VEC_DUPLICATE:
          x15 = XEXP (x13, 0);
          operands[3] = x15;
          x14 = XEXP (x4, 1);
          switch (GET_CODE (x14))
            {
            case SIGN_EXTEND:
              switch (pattern292 (x2))
                {
                case 0:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4369; /* pred_widen_mul_plussvnx1hi_scalar */

                case 1:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4371; /* pred_widen_mul_plussvnx2hi_scalar */

                case 2:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4373; /* pred_widen_mul_plussvnx4hi_scalar */

                case 3:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4375; /* pred_widen_mul_plussvnx8hi_scalar */

                case 4:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4377; /* pred_widen_mul_plussvnx16hi_scalar */

                case 5:
                  if (!(
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4379; /* pred_widen_mul_plussvnx32hi_scalar */

                case 6:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4381; /* pred_widen_mul_plussvnx1si_scalar */

                case 7:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4383; /* pred_widen_mul_plussvnx2si_scalar */

                case 8:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4385; /* pred_widen_mul_plussvnx4si_scalar */

                case 9:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4387; /* pred_widen_mul_plussvnx8si_scalar */

                case 10:
                  if (!(
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4389; /* pred_widen_mul_plussvnx16si_scalar */

                case 11:
                  if (!(
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4391; /* pred_widen_mul_plussvnx1di_scalar */

                case 12:
                  if (!(
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4393; /* pred_widen_mul_plussvnx2di_scalar */

                case 13:
                  if (!(
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4395; /* pred_widen_mul_plussvnx4di_scalar */

                case 14:
                  if (!(
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4397; /* pred_widen_mul_plussvnx8di_scalar */

                default:
                  return -1;
                }

            case ZERO_EXTEND:
              switch (pattern292 (x2))
                {
                case 0:
                  if (!
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4414; /* pred_widen_mul_plussuvnx1hi_scalar */

                case 1:
                  if (!
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4415; /* pred_widen_mul_plussuvnx2hi_scalar */

                case 2:
                  if (!
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4416; /* pred_widen_mul_plussuvnx4hi_scalar */

                case 3:
                  if (!
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4417; /* pred_widen_mul_plussuvnx8hi_scalar */

                case 4:
                  if (!
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4418; /* pred_widen_mul_plussuvnx16hi_scalar */

                case 5:
                  if (!(
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4419; /* pred_widen_mul_plussuvnx32hi_scalar */

                case 6:
                  if (!
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4420; /* pred_widen_mul_plussuvnx1si_scalar */

                case 7:
                  if (!
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4421; /* pred_widen_mul_plussuvnx2si_scalar */

                case 8:
                  if (!
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4422; /* pred_widen_mul_plussuvnx4si_scalar */

                case 9:
                  if (!
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4423; /* pred_widen_mul_plussuvnx8si_scalar */

                case 10:
                  if (!(
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4424; /* pred_widen_mul_plussuvnx16si_scalar */

                case 11:
                  if (!(
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4425; /* pred_widen_mul_plussuvnx1di_scalar */

                case 12:
                  if (!(
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4426; /* pred_widen_mul_plussuvnx2di_scalar */

                case 13:
                  if (!(
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4427; /* pred_widen_mul_plussuvnx4di_scalar */

                case 14:
                  if (!(
#line 5145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4428; /* pred_widen_mul_plussuvnx8di_scalar */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        default:
          return -1;
        }

    case ZERO_EXTEND:
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      x11 = XEXP (x3, 1);
      operands[2] = x11;
      x12 = XEXP (x2, 2);
      if (!rtx_equal_p (x12, operands[2]))
        return -1;
      x13 = XEXP (x5, 0);
      switch (GET_CODE (x13))
        {
        case REG:
        case SUBREG:
          operands[3] = x13;
          x14 = XEXP (x4, 1);
          if (GET_CODE (x14) != ZERO_EXTEND)
            return -1;
          switch (pattern290 (x2))
            {
            case 0:
              if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 4340; /* pred_widen_mul_plusuvnx1hi */

            case 1:
              if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 4342; /* pred_widen_mul_plusuvnx2hi */

            case 2:
              if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 4344; /* pred_widen_mul_plusuvnx4hi */

            case 3:
              if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 4346; /* pred_widen_mul_plusuvnx8hi */

            case 4:
              if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 4348; /* pred_widen_mul_plusuvnx16hi */

            case 5:
              if (!(
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 4350; /* pred_widen_mul_plusuvnx32hi */

            case 6:
              if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 4352; /* pred_widen_mul_plusuvnx1si */

            case 7:
              if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 4354; /* pred_widen_mul_plusuvnx2si */

            case 8:
              if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 4356; /* pred_widen_mul_plusuvnx4si */

            case 9:
              if (!
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 4358; /* pred_widen_mul_plusuvnx8si */

            case 10:
              if (!(
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 4360; /* pred_widen_mul_plusuvnx16si */

            case 11:
              if (!(
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 4362; /* pred_widen_mul_plusuvnx1di */

            case 12:
              if (!(
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 4364; /* pred_widen_mul_plusuvnx2di */

            case 13:
              if (!(
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 4366; /* pred_widen_mul_plusuvnx4di */

            case 14:
              if (!(
#line 5071 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 4368; /* pred_widen_mul_plusuvnx8di */

            default:
              return -1;
            }

        case VEC_DUPLICATE:
          x15 = XEXP (x13, 0);
          operands[3] = x15;
          x14 = XEXP (x4, 1);
          switch (GET_CODE (x14))
            {
            case ZERO_EXTEND:
              switch (pattern292 (x2))
                {
                case 0:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4370; /* pred_widen_mul_plusuvnx1hi_scalar */

                case 1:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4372; /* pred_widen_mul_plusuvnx2hi_scalar */

                case 2:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4374; /* pred_widen_mul_plusuvnx4hi_scalar */

                case 3:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4376; /* pred_widen_mul_plusuvnx8hi_scalar */

                case 4:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4378; /* pred_widen_mul_plusuvnx16hi_scalar */

                case 5:
                  if (!(
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4380; /* pred_widen_mul_plusuvnx32hi_scalar */

                case 6:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4382; /* pred_widen_mul_plusuvnx1si_scalar */

                case 7:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4384; /* pred_widen_mul_plusuvnx2si_scalar */

                case 8:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4386; /* pred_widen_mul_plusuvnx4si_scalar */

                case 9:
                  if (!
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4388; /* pred_widen_mul_plusuvnx8si_scalar */

                case 10:
                  if (!(
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4390; /* pred_widen_mul_plusuvnx16si_scalar */

                case 11:
                  if (!(
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4392; /* pred_widen_mul_plusuvnx1di_scalar */

                case 12:
                  if (!(
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4394; /* pred_widen_mul_plusuvnx2di_scalar */

                case 13:
                  if (!(
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4396; /* pred_widen_mul_plusuvnx4di_scalar */

                case 14:
                  if (!(
#line 5096 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4398; /* pred_widen_mul_plusuvnx8di_scalar */

                default:
                  return -1;
                }

            case SIGN_EXTEND:
              switch (pattern292 (x2))
                {
                case 0:
                  if (!
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4429; /* pred_widen_mul_plususvnx1hi_scalar */

                case 1:
                  if (!
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4430; /* pred_widen_mul_plususvnx2hi_scalar */

                case 2:
                  if (!
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4431; /* pred_widen_mul_plususvnx4hi_scalar */

                case 3:
                  if (!
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4432; /* pred_widen_mul_plususvnx8hi_scalar */

                case 4:
                  if (!
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4433; /* pred_widen_mul_plususvnx16hi_scalar */

                case 5:
                  if (!(
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4434; /* pred_widen_mul_plususvnx32hi_scalar */

                case 6:
                  if (!
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4435; /* pred_widen_mul_plususvnx1si_scalar */

                case 7:
                  if (!
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4436; /* pred_widen_mul_plususvnx2si_scalar */

                case 8:
                  if (!
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4437; /* pred_widen_mul_plususvnx4si_scalar */

                case 9:
                  if (!
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4438; /* pred_widen_mul_plususvnx8si_scalar */

                case 10:
                  if (!(
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4439; /* pred_widen_mul_plususvnx16si_scalar */

                case 11:
                  if (!(
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4440; /* pred_widen_mul_plususvnx1di_scalar */

                case 12:
                  if (!(
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4441; /* pred_widen_mul_plususvnx2di_scalar */

                case 13:
                  if (!(
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4442; /* pred_widen_mul_plususvnx4di_scalar */

                case 14:
                  if (!(
#line 5170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4443; /* pred_widen_mul_plususvnx8di_scalar */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        default:
          return -1;
        }

    case FLOAT_EXTEND:
      switch (pattern202 (x2))
        {
        case 0:
          if (!(
#line 6190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5090; /* pred_widen_mul_addvnx1df */

        case 1:
          if (!(
#line 6190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5092; /* pred_widen_mul_addvnx2df */

        case 2:
          if (!(
#line 6190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5094; /* pred_widen_mul_addvnx4df */

        case 3:
          if (!(
#line 6190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5096; /* pred_widen_mul_addvnx8df */

        case 4:
          if (!(
#line 6215 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5098; /* pred_widen_mul_addvnx1df_scalar */

        case 5:
          if (!(
#line 6215 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5100; /* pred_widen_mul_addvnx2df_scalar */

        case 6:
          if (!(
#line 6215 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5102; /* pred_widen_mul_addvnx4df_scalar */

        case 7:
          if (!(
#line 6215 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5104; /* pred_widen_mul_addvnx8df_scalar */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_64 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern288 (x2, E_VNx8DImode, E_VNx8BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx8DImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4950 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4330; /* *pred_nmsubvnx8di_extended_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4983 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4334; /* *pred_nmsacvnx8di_extended_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx8DImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx8DImode)
      || !(
#line 5016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    return -1;
  return 4338; /* *pred_minus_mulvnx8di_extended_scalar */
}

static int
recog_65 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern288 (x2, E_VNx4DImode, E_VNx4BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx4DImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4950 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4329; /* *pred_nmsubvnx4di_extended_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4983 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4333; /* *pred_nmsacvnx4di_extended_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx4DImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx4DImode)
      || !(
#line 5016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    return -1;
  return 4337; /* *pred_minus_mulvnx4di_extended_scalar */
}

static int
recog_66 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern288 (x2, E_VNx2DImode, E_VNx2BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx2DImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4950 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4328; /* *pred_nmsubvnx2di_extended_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4983 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4332; /* *pred_nmsacvnx2di_extended_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx2DImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx2DImode)
      || !(
#line 5016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    return -1;
  return 4336; /* *pred_minus_mulvnx2di_extended_scalar */
}

static int
recog_67 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern288 (x2, E_VNx1DImode, E_VNx1BImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx1DImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4950 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4327; /* *pred_nmsubvnx1di_extended_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4983 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4331; /* *pred_nmsacvnx1di_extended_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx1DImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx1DImode)
      || !(
#line 5016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    return -1;
  return 4335; /* *pred_minus_mulvnx1di_extended_scalar */
}

static int
recog_68 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx8DImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4282; /* *pred_nmsubvnx8di_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4304; /* *pred_nmsacvnx8di_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx8DImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx8DImode)
      || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    return -1;
  return 4326; /* *pred_minus_mulvnx8di_scalar */
}

static int
recog_69 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx4DImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4281; /* *pred_nmsubvnx4di_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4303; /* *pred_nmsacvnx4di_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx4DImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx4DImode)
      || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    return -1;
  return 4325; /* *pred_minus_mulvnx4di_scalar */
}

static int
recog_70 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx2DImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4280; /* *pred_nmsubvnx2di_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4302; /* *pred_nmsacvnx2di_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx2DImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx2DImode)
      || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    return -1;
  return 4324; /* *pred_minus_mulvnx2di_scalar */
}

static int
recog_71 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx1DImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4279; /* *pred_nmsubvnx1di_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 4301; /* *pred_nmsacvnx1di_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx1DImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx1DImode)
      || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    return -1;
  return 4323; /* *pred_minus_mulvnx1di_scalar */
}

static int
recog_72 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx16SImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 4278; /* *pred_nmsubvnx16si_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 4300; /* *pred_nmsacvnx16si_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx16SImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx16SImode)
      || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
    return -1;
  return 4322; /* *pred_minus_mulvnx16si_scalar */
}

static int
recog_73 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx8SImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4277; /* *pred_nmsubvnx8si_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4299; /* *pred_nmsacvnx8si_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx8SImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx8SImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4321; /* *pred_minus_mulvnx8si_scalar */
}

static int
recog_74 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx4SImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4276; /* *pred_nmsubvnx4si_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4298; /* *pred_nmsacvnx4si_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx4SImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx4SImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4320; /* *pred_minus_mulvnx4si_scalar */
}

static int
recog_75 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx2SImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4275; /* *pred_nmsubvnx2si_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4297; /* *pred_nmsacvnx2si_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx2SImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx2SImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4319; /* *pred_minus_mulvnx2si_scalar */
}

static int
recog_76 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx1SImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4274; /* *pred_nmsubvnx1si_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4296; /* *pred_nmsacvnx1si_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx1SImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx1SImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4318; /* *pred_minus_mulvnx1si_scalar */
}

static int
recog_77 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx32HImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 4273; /* *pred_nmsubvnx32hi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 4295; /* *pred_nmsacvnx32hi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx32HImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx32HImode)
      || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
    return -1;
  return 4317; /* *pred_minus_mulvnx32hi_scalar */
}

static int
recog_78 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx16HImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4272; /* *pred_nmsubvnx16hi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4294; /* *pred_nmsacvnx16hi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx16HImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx16HImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4316; /* *pred_minus_mulvnx16hi_scalar */
}

static int
recog_79 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx8HImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4271; /* *pred_nmsubvnx8hi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4293; /* *pred_nmsacvnx8hi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx8HImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx8HImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4315; /* *pred_minus_mulvnx8hi_scalar */
}

static int
recog_80 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx4HImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4270; /* *pred_nmsubvnx4hi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4292; /* *pred_nmsacvnx4hi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx4HImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx4HImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4314; /* *pred_minus_mulvnx4hi_scalar */
}

static int
recog_81 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx2HImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4269; /* *pred_nmsubvnx2hi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4291; /* *pred_nmsacvnx2hi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx2HImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx2HImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4313; /* *pred_minus_mulvnx2hi_scalar */
}

static int
recog_82 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx1HImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4268; /* *pred_nmsubvnx1hi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4290; /* *pred_nmsacvnx1hi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx1HImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx1HImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4312; /* *pred_minus_mulvnx1hi_scalar */
}

static int
recog_83 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx64QImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && (
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 4267; /* *pred_nmsubvnx64qi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && (
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 4289; /* *pred_nmsacvnx64qi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx64QImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx64QImode)
      || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
    return -1;
  return 4311; /* *pred_minus_mulvnx64qi_scalar */
}

static int
recog_84 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx32QImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4266; /* *pred_nmsubvnx32qi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4288; /* *pred_nmsacvnx32qi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx32QImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx32QImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4310; /* *pred_minus_mulvnx32qi_scalar */
}

static int
recog_85 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx16QImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4265; /* *pred_nmsubvnx16qi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4287; /* *pred_nmsacvnx16qi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx16QImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx16QImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4309; /* *pred_minus_mulvnx16qi_scalar */
}

static int
recog_86 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx8QImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4264; /* *pred_nmsubvnx8qi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4286; /* *pred_nmsacvnx8qi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx8QImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx8QImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4308; /* *pred_minus_mulvnx8qi_scalar */
}

static int
recog_87 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx4QImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4263; /* *pred_nmsubvnx4qi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4285; /* *pred_nmsacvnx4qi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx4QImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx4QImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4307; /* *pred_minus_mulvnx4qi_scalar */
}

static int
recog_88 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx2QImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4262; /* *pred_nmsubvnx2qi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4284; /* *pred_nmsacvnx2qi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx2QImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx2QImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4306; /* *pred_minus_mulvnx2qi_scalar */
}

static int
recog_89 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  if (pattern270 (x2, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0)
    return -1;
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  if (register_operand (operands[4], E_VNx1QImode))
    {
      x8 = XEXP (x2, 2);
      if (rtx_equal_p (x8, operands[3])
          && 
#line 4803 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4261; /* *pred_nmsubvnx1qi_scalar */
      if (rtx_equal_p (x8, operands[4])
          && 
#line 4835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 4283; /* *pred_nmsacvnx1qi_scalar */
    }
  operands[6] = x4;
  operands[7] = x5;
  operands[8] = x6;
  operands[9] = x7;
  if (!vector_arith_operand (operands[4], E_VNx1QImode))
    return -1;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  if (!register_operand (operands[5], E_VNx1QImode)
      || !
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
    return -1;
  return 4305; /* *pred_minus_mulvnx1qi_scalar */
}

static int
recog_90 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  operands[4] = x4;
  x5 = XEXP (x3, 1);
  switch (pattern212 (x5))
    {
    case 0:
      if (pattern252 (x2, E_VNx1QImode, E_VNx1BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx1QImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4195; /* *pred_nmsubvnx1qi */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4217; /* *pred_nmsacvnx1qi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx1QImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx1QImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4239; /* *pred_minus_mulvnx1qi */

    case 1:
      if (pattern252 (x2, E_VNx2QImode, E_VNx2BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx2QImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4196; /* *pred_nmsubvnx2qi */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4218; /* *pred_nmsacvnx2qi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx2QImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx2QImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4240; /* *pred_minus_mulvnx2qi */

    case 2:
      if (pattern252 (x2, E_VNx4QImode, E_VNx4BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx4QImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4197; /* *pred_nmsubvnx4qi */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4219; /* *pred_nmsacvnx4qi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx4QImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx4QImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4241; /* *pred_minus_mulvnx4qi */

    case 3:
      if (pattern252 (x2, E_VNx8QImode, E_VNx8BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx8QImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4198; /* *pred_nmsubvnx8qi */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4220; /* *pred_nmsacvnx8qi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx8QImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx8QImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4242; /* *pred_minus_mulvnx8qi */

    case 4:
      if (pattern252 (x2, E_VNx16QImode, E_VNx16BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx16QImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4199; /* *pred_nmsubvnx16qi */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4221; /* *pred_nmsacvnx16qi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx16QImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx16QImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4243; /* *pred_minus_mulvnx16qi */

    case 5:
      if (pattern252 (x2, E_VNx32QImode, E_VNx32BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx32QImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4200; /* *pred_nmsubvnx32qi */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4222; /* *pred_nmsacvnx32qi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx32QImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx32QImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4244; /* *pred_minus_mulvnx32qi */

    case 6:
      if (pattern252 (x2, E_VNx64QImode, E_VNx64BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx64QImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && (
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4201; /* *pred_nmsubvnx64qi */
          if (rtx_equal_p (x11, operands[4])
              && (
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4223; /* *pred_nmsacvnx64qi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx64QImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx64QImode)
          || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 4245; /* *pred_minus_mulvnx64qi */

    case 7:
      if (pattern252 (x2, E_VNx1HImode, E_VNx1BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx1HImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4202; /* *pred_nmsubvnx1hi */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4224; /* *pred_nmsacvnx1hi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx1HImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx1HImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4246; /* *pred_minus_mulvnx1hi */

    case 8:
      if (pattern252 (x2, E_VNx2HImode, E_VNx2BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx2HImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4203; /* *pred_nmsubvnx2hi */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4225; /* *pred_nmsacvnx2hi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx2HImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx2HImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4247; /* *pred_minus_mulvnx2hi */

    case 9:
      if (pattern252 (x2, E_VNx4HImode, E_VNx4BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx4HImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4204; /* *pred_nmsubvnx4hi */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4226; /* *pred_nmsacvnx4hi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx4HImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx4HImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4248; /* *pred_minus_mulvnx4hi */

    case 10:
      if (pattern252 (x2, E_VNx8HImode, E_VNx8BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx8HImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4205; /* *pred_nmsubvnx8hi */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4227; /* *pred_nmsacvnx8hi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx8HImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx8HImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4249; /* *pred_minus_mulvnx8hi */

    case 11:
      if (pattern252 (x2, E_VNx16HImode, E_VNx16BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx16HImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4206; /* *pred_nmsubvnx16hi */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4228; /* *pred_nmsacvnx16hi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx16HImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx16HImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4250; /* *pred_minus_mulvnx16hi */

    case 12:
      if (pattern252 (x2, E_VNx32HImode, E_VNx32BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx32HImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && (
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4207; /* *pred_nmsubvnx32hi */
          if (rtx_equal_p (x11, operands[4])
              && (
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4229; /* *pred_nmsacvnx32hi */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx32HImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx32HImode)
          || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 4251; /* *pred_minus_mulvnx32hi */

    case 13:
      if (pattern252 (x2, E_VNx1SImode, E_VNx1BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx1SImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4208; /* *pred_nmsubvnx1si */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4230; /* *pred_nmsacvnx1si */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx1SImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx1SImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4252; /* *pred_minus_mulvnx1si */

    case 14:
      if (pattern252 (x2, E_VNx2SImode, E_VNx2BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx2SImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4209; /* *pred_nmsubvnx2si */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4231; /* *pred_nmsacvnx2si */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx2SImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx2SImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4253; /* *pred_minus_mulvnx2si */

    case 15:
      if (pattern252 (x2, E_VNx4SImode, E_VNx4BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx4SImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4210; /* *pred_nmsubvnx4si */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4232; /* *pred_nmsacvnx4si */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx4SImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx4SImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4254; /* *pred_minus_mulvnx4si */

    case 16:
      if (pattern252 (x2, E_VNx8SImode, E_VNx8BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx8SImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && 
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4211; /* *pred_nmsubvnx8si */
          if (rtx_equal_p (x11, operands[4])
              && 
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 4233; /* *pred_nmsacvnx8si */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx8SImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx8SImode)
          || !
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])))
        return -1;
      return 4255; /* *pred_minus_mulvnx8si */

    case 17:
      if (pattern252 (x2, E_VNx16SImode, E_VNx16BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx16SImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && (
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4212; /* *pred_nmsubvnx16si */
          if (rtx_equal_p (x11, operands[4])
              && (
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 4234; /* *pred_nmsacvnx16si */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx16SImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx16SImode)
          || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 4256; /* *pred_minus_mulvnx16si */

    case 18:
      if (pattern252 (x2, E_VNx1DImode, E_VNx1BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx1DImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && (
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4213; /* *pred_nmsubvnx1di */
          if (rtx_equal_p (x11, operands[4])
              && (
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4235; /* *pred_nmsacvnx1di */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx1DImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx1DImode)
          || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4257; /* *pred_minus_mulvnx1di */

    case 19:
      if (pattern252 (x2, E_VNx2DImode, E_VNx2BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx2DImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && (
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4214; /* *pred_nmsubvnx2di */
          if (rtx_equal_p (x11, operands[4])
              && (
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4236; /* *pred_nmsacvnx2di */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx2DImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx2DImode)
          || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4258; /* *pred_minus_mulvnx2di */

    case 20:
      if (pattern252 (x2, E_VNx4DImode, E_VNx4BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx4DImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && (
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4215; /* *pred_nmsubvnx4di */
          if (rtx_equal_p (x11, operands[4])
              && (
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4237; /* *pred_nmsacvnx4di */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx4DImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx4DImode)
          || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4259; /* *pred_minus_mulvnx4di */

    case 21:
      if (pattern252 (x2, E_VNx8DImode, E_VNx8BImode) != 0)
        return -1;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[5] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[6] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[7] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[8] = x10;
      if (register_operand (operands[4], E_VNx8DImode))
        {
          x11 = XEXP (x2, 2);
          if (rtx_equal_p (x11, operands[2])
              && (
#line 4666 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4216; /* *pred_nmsubvnx8di */
          if (rtx_equal_p (x11, operands[4])
              && (
#line 4697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4238; /* *pred_nmsacvnx8di */
        }
      operands[6] = x7;
      operands[7] = x8;
      operands[8] = x9;
      operands[9] = x10;
      if (!vector_arith_operand (operands[4], E_VNx8DImode))
        return -1;
      x11 = XEXP (x2, 2);
      operands[5] = x11;
      if (!register_operand (operands[5], E_VNx8DImode)
          || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4260; /* *pred_minus_mulvnx8di */

    case 22:
      return recog_89 (x1, insn, pnum_clobbers);

    case 23:
      return recog_88 (x1, insn, pnum_clobbers);

    case 24:
      return recog_87 (x1, insn, pnum_clobbers);

    case 25:
      return recog_86 (x1, insn, pnum_clobbers);

    case 26:
      return recog_85 (x1, insn, pnum_clobbers);

    case 27:
      return recog_84 (x1, insn, pnum_clobbers);

    case 28:
      return recog_83 (x1, insn, pnum_clobbers);

    case 29:
      return recog_82 (x1, insn, pnum_clobbers);

    case 30:
      return recog_81 (x1, insn, pnum_clobbers);

    case 31:
      return recog_80 (x1, insn, pnum_clobbers);

    case 32:
      return recog_79 (x1, insn, pnum_clobbers);

    case 33:
      return recog_78 (x1, insn, pnum_clobbers);

    case 34:
      return recog_77 (x1, insn, pnum_clobbers);

    case 35:
      return recog_76 (x1, insn, pnum_clobbers);

    case 36:
      return recog_75 (x1, insn, pnum_clobbers);

    case 37:
      return recog_74 (x1, insn, pnum_clobbers);

    case 38:
      return recog_73 (x1, insn, pnum_clobbers);

    case 39:
      return recog_72 (x1, insn, pnum_clobbers);

    case 40:
      return recog_71 (x1, insn, pnum_clobbers);

    case 41:
      return recog_70 (x1, insn, pnum_clobbers);

    case 42:
      return recog_69 (x1, insn, pnum_clobbers);

    case 43:
      return recog_68 (x1, insn, pnum_clobbers);

    case 44:
      return recog_67 (x1, insn, pnum_clobbers);

    case 45:
      return recog_66 (x1, insn, pnum_clobbers);

    case 46:
      return recog_65 (x1, insn, pnum_clobbers);

    case 47:
      return recog_64 (x1, insn, pnum_clobbers);

    default:
      return -1;
    }
}

static int
recog_91 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  x5 = XEXP (x4, 0);
  switch (GET_CODE (x5))
    {
    case REG:
    case SUBREG:
      operands[2] = x5;
      x6 = XEXP (x4, 1);
      operands[3] = x6;
      x7 = XEXP (x3, 1);
      operands[4] = x7;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1SFmode:
          if (pattern236 (x2, E_VNx1SFmode, E_VNx1BImode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx1SFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[2])
                  && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4781; /* *pred_msubvnx1sf */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4799; /* *pred_msacvnx1sf */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx1SFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx1SFmode)
              || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4817; /* *pred_mul_subvnx1sf */

        case E_VNx2SFmode:
          if (pattern236 (x2, E_VNx2SFmode, E_VNx2BImode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx2SFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[2])
                  && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4783; /* *pred_msubvnx2sf */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4801; /* *pred_msacvnx2sf */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx2SFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx2SFmode)
              || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4819; /* *pred_mul_subvnx2sf */

        case E_VNx4SFmode:
          if (pattern236 (x2, E_VNx4SFmode, E_VNx4BImode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx4SFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[2])
                  && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4785; /* *pred_msubvnx4sf */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4803; /* *pred_msacvnx4sf */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx4SFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx4SFmode)
              || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4821; /* *pred_mul_subvnx4sf */

        case E_VNx8SFmode:
          if (pattern236 (x2, E_VNx8SFmode, E_VNx8BImode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx8SFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[2])
                  && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4787; /* *pred_msubvnx8sf */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4805; /* *pred_msacvnx8sf */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx8SFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx8SFmode)
              || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4823; /* *pred_mul_subvnx8sf */

        case E_VNx16SFmode:
          if (pattern236 (x2, E_VNx16SFmode, E_VNx16BImode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx16SFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[2])
                  && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return 4789; /* *pred_msubvnx16sf */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return 4807; /* *pred_msacvnx16sf */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx16SFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx16SFmode)
              || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4825; /* *pred_mul_subvnx16sf */

        case E_VNx1DFmode:
          if (pattern236 (x2, E_VNx1DFmode, E_VNx1BImode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx1DFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[2])
                  && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4791; /* *pred_msubvnx1df */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4809; /* *pred_msacvnx1df */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx1DFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx1DFmode)
              || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4827; /* *pred_mul_subvnx1df */

        case E_VNx2DFmode:
          if (pattern236 (x2, E_VNx2DFmode, E_VNx2BImode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx2DFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[2])
                  && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4793; /* *pred_msubvnx2df */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4811; /* *pred_msacvnx2df */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx2DFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx2DFmode)
              || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4829; /* *pred_mul_subvnx2df */

        case E_VNx4DFmode:
          if (pattern236 (x2, E_VNx4DFmode, E_VNx4BImode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx4DFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[2])
                  && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4795; /* *pred_msubvnx4df */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4813; /* *pred_msacvnx4df */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx4DFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx4DFmode)
              || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4831; /* *pred_mul_subvnx4df */

        case E_VNx8DFmode:
          if (pattern236 (x2, E_VNx8DFmode, E_VNx8BImode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx8DFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[2])
                  && (
#line 5545 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4797; /* *pred_msubvnx8df */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5576 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4815; /* *pred_msacvnx8df */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx8DFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx8DFmode)
              || !(
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4833; /* *pred_mul_subvnx8df */

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x14 = XEXP (x5, 0);
      operands[2] = x14;
      x6 = XEXP (x4, 1);
      operands[3] = x6;
      x7 = XEXP (x3, 1);
      operands[4] = x7;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1SFmode:
          if (pattern237 (x2, E_VNx1SFmode, E_VNx1BImode, E_SFmode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx1SFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[3])
                  && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4835; /* *pred_msubvnx1sf_scalar */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4853; /* *pred_msacvnx1sf_scalar */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx1SFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx1SFmode)
              || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4871; /* *pred_mul_subvnx1sf_scalar */

        case E_VNx2SFmode:
          if (pattern237 (x2, E_VNx2SFmode, E_VNx2BImode, E_SFmode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx2SFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[3])
                  && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4837; /* *pred_msubvnx2sf_scalar */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4855; /* *pred_msacvnx2sf_scalar */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx2SFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx2SFmode)
              || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4873; /* *pred_mul_subvnx2sf_scalar */

        case E_VNx4SFmode:
          if (pattern237 (x2, E_VNx4SFmode, E_VNx4BImode, E_SFmode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx4SFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[3])
                  && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4839; /* *pred_msubvnx4sf_scalar */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4857; /* *pred_msacvnx4sf_scalar */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx4SFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx4SFmode)
              || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4875; /* *pred_mul_subvnx4sf_scalar */

        case E_VNx8SFmode:
          if (pattern237 (x2, E_VNx8SFmode, E_VNx8BImode, E_SFmode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx8SFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[3])
                  && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4841; /* *pred_msubvnx8sf_scalar */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 4859; /* *pred_msacvnx8sf_scalar */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx8SFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx8SFmode)
              || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4877; /* *pred_mul_subvnx8sf_scalar */

        case E_VNx16SFmode:
          if (pattern237 (x2, E_VNx16SFmode, E_VNx16BImode, E_SFmode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx16SFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[3])
                  && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return 4843; /* *pred_msubvnx16sf_scalar */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return 4861; /* *pred_msacvnx16sf_scalar */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx16SFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx16SFmode)
              || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4879; /* *pred_mul_subvnx16sf_scalar */

        case E_VNx1DFmode:
          if (pattern237 (x2, E_VNx1DFmode, E_VNx1BImode, E_DFmode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx1DFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[3])
                  && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4845; /* *pred_msubvnx1df_scalar */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4863; /* *pred_msacvnx1df_scalar */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx1DFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx1DFmode)
              || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4881; /* *pred_mul_subvnx1df_scalar */

        case E_VNx2DFmode:
          if (pattern237 (x2, E_VNx2DFmode, E_VNx2BImode, E_DFmode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx2DFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[3])
                  && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4847; /* *pred_msubvnx2df_scalar */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4865; /* *pred_msacvnx2df_scalar */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx2DFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx2DFmode)
              || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4883; /* *pred_mul_subvnx2df_scalar */

        case E_VNx4DFmode:
          if (pattern237 (x2, E_VNx4DFmode, E_VNx4BImode, E_DFmode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx4DFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[3])
                  && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4849; /* *pred_msubvnx4df_scalar */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4867; /* *pred_msacvnx4df_scalar */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx4DFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx4DFmode)
              || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4885; /* *pred_mul_subvnx4df_scalar */

        case E_VNx8DFmode:
          if (pattern237 (x2, E_VNx8DFmode, E_VNx8BImode, E_DFmode) != 0)
            return -1;
          x8 = XEXP (x2, 0);
          x9 = XVECEXP (x8, 0, 1);
          operands[5] = x9;
          x10 = XVECEXP (x8, 0, 2);
          operands[6] = x10;
          x11 = XVECEXP (x8, 0, 3);
          operands[7] = x11;
          x12 = XVECEXP (x8, 0, 4);
          operands[8] = x12;
          if (register_operand (operands[4], E_VNx8DFmode))
            {
              x13 = XEXP (x2, 2);
              if (rtx_equal_p (x13, operands[3])
                  && (
#line 5664 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4851; /* *pred_msubvnx8df_scalar */
              if (rtx_equal_p (x13, operands[4])
                  && (
#line 5696 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return 4869; /* *pred_msacvnx8df_scalar */
            }
          operands[6] = x9;
          operands[7] = x10;
          operands[8] = x11;
          operands[9] = x12;
          if (!vector_arith_operand (operands[4], E_VNx8DFmode))
            return -1;
          x13 = XEXP (x2, 2);
          operands[5] = x13;
          if (!register_operand (operands[5], E_VNx8DFmode)
              || !(
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4887; /* *pred_mul_subvnx8df_scalar */

        default:
          return -1;
        }

    case FLOAT_EXTEND:
      switch (pattern202 (x2))
        {
        case 0:
          if (!(
#line 6190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5091; /* pred_widen_mul_subvnx1df */

        case 1:
          if (!(
#line 6190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5093; /* pred_widen_mul_subvnx2df */

        case 2:
          if (!(
#line 6190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5095; /* pred_widen_mul_subvnx4df */

        case 3:
          if (!(
#line 6190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5097; /* pred_widen_mul_subvnx8df */

        case 4:
          if (!(
#line 6215 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5099; /* pred_widen_mul_subvnx1df_scalar */

        case 5:
          if (!(
#line 6215 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5101; /* pred_widen_mul_subvnx2df_scalar */

        case 6:
          if (!(
#line 6215 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5103; /* pred_widen_mul_subvnx4df_scalar */

        case 7:
          if (!(
#line 6215 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5105; /* pred_widen_mul_subvnx8df_scalar */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_92 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 1);
  switch (GET_CODE (x4))
    {
    case CONST_VECTOR:
    case REG:
    case SUBREG:
      operands[4] = x4;
      x5 = XEXP (x2, 0);
      x6 = XVECEXP (x5, 0, 1);
      operands[5] = x6;
      x7 = XVECEXP (x5, 0, 2);
      operands[6] = x7;
      x8 = XVECEXP (x5, 0, 3);
      operands[7] = x8;
      x9 = XVECEXP (x5, 0, 4);
      operands[8] = x9;
      x10 = XEXP (x3, 0);
      operands[3] = x10;
      x11 = XEXP (x2, 2);
      operands[2] = x11;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          if (pattern287 (x2, E_VNx1QImode, E_VNx1BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1483; /* pred_subvnx1qi */

        case E_VNx2QImode:
          if (pattern287 (x2, E_VNx2QImode, E_VNx2BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1500; /* pred_subvnx2qi */

        case E_VNx4QImode:
          if (pattern287 (x2, E_VNx4QImode, E_VNx4BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1517; /* pred_subvnx4qi */

        case E_VNx8QImode:
          if (pattern287 (x2, E_VNx8QImode, E_VNx8BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1534; /* pred_subvnx8qi */

        case E_VNx16QImode:
          if (pattern287 (x2, E_VNx16QImode, E_VNx16BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1551; /* pred_subvnx16qi */

        case E_VNx32QImode:
          if (pattern287 (x2, E_VNx32QImode, E_VNx32BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1568; /* pred_subvnx32qi */

        case E_VNx64QImode:
          if (pattern287 (x2, E_VNx64QImode, E_VNx64BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1585; /* pred_subvnx64qi */

        case E_VNx1HImode:
          if (pattern287 (x2, E_VNx1HImode, E_VNx1BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1602; /* pred_subvnx1hi */

        case E_VNx2HImode:
          if (pattern287 (x2, E_VNx2HImode, E_VNx2BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1619; /* pred_subvnx2hi */

        case E_VNx4HImode:
          if (pattern287 (x2, E_VNx4HImode, E_VNx4BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1636; /* pred_subvnx4hi */

        case E_VNx8HImode:
          if (pattern287 (x2, E_VNx8HImode, E_VNx8BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1653; /* pred_subvnx8hi */

        case E_VNx16HImode:
          if (pattern287 (x2, E_VNx16HImode, E_VNx16BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1670; /* pred_subvnx16hi */

        case E_VNx32HImode:
          if (pattern287 (x2, E_VNx32HImode, E_VNx32BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1687; /* pred_subvnx32hi */

        case E_VNx1SImode:
          if (pattern287 (x2, E_VNx1SImode, E_VNx1BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1704; /* pred_subvnx1si */

        case E_VNx2SImode:
          if (pattern287 (x2, E_VNx2SImode, E_VNx2BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1721; /* pred_subvnx2si */

        case E_VNx4SImode:
          if (pattern287 (x2, E_VNx4SImode, E_VNx4BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1738; /* pred_subvnx4si */

        case E_VNx8SImode:
          if (pattern287 (x2, E_VNx8SImode, E_VNx8BImode) != 0
              || !
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1755; /* pred_subvnx8si */

        case E_VNx16SImode:
          if (pattern287 (x2, E_VNx16SImode, E_VNx16BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1772; /* pred_subvnx16si */

        case E_VNx1DImode:
          if (pattern287 (x2, E_VNx1DImode, E_VNx1BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1789; /* pred_subvnx1di */

        case E_VNx2DImode:
          if (pattern287 (x2, E_VNx2DImode, E_VNx2BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1806; /* pred_subvnx2di */

        case E_VNx4DImode:
          if (pattern287 (x2, E_VNx4DImode, E_VNx4BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1823; /* pred_subvnx4di */

        case E_VNx8DImode:
          if (pattern287 (x2, E_VNx8DImode, E_VNx8BImode) != 0
              || !(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1840; /* pred_subvnx8di */

        case E_VNx1SFmode:
          if (pattern153 (x2, E_VNx1SFmode, E_VNx1BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4604; /* pred_subvnx1sf */

        case E_VNx2SFmode:
          if (pattern153 (x2, E_VNx2SFmode, E_VNx2BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4610; /* pred_subvnx2sf */

        case E_VNx4SFmode:
          if (pattern153 (x2, E_VNx4SFmode, E_VNx4BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4616; /* pred_subvnx4sf */

        case E_VNx8SFmode:
          if (pattern153 (x2, E_VNx8SFmode, E_VNx8BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4622; /* pred_subvnx8sf */

        case E_VNx16SFmode:
          if (pattern153 (x2, E_VNx16SFmode, E_VNx16BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4628; /* pred_subvnx16sf */

        case E_VNx1DFmode:
          if (pattern153 (x2, E_VNx1DFmode, E_VNx1BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4634; /* pred_subvnx1df */

        case E_VNx2DFmode:
          if (pattern153 (x2, E_VNx2DFmode, E_VNx2BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4640; /* pred_subvnx2df */

        case E_VNx4DFmode:
          if (pattern153 (x2, E_VNx4DFmode, E_VNx4BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4646; /* pred_subvnx4df */

        case E_VNx8DFmode:
          if (pattern153 (x2, E_VNx8DFmode, E_VNx8BImode) != 0
              || !(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4652; /* pred_subvnx8df */

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x5 = XEXP (x2, 0);
      x6 = XVECEXP (x5, 0, 1);
      operands[5] = x6;
      x7 = XVECEXP (x5, 0, 2);
      operands[6] = x7;
      x8 = XVECEXP (x5, 0, 3);
      operands[7] = x8;
      x9 = XVECEXP (x5, 0, 4);
      operands[8] = x9;
      x10 = XEXP (x3, 0);
      operands[3] = x10;
      x11 = XEXP (x2, 2);
      operands[2] = x11;
      switch (pattern269 (x2))
        {
        case 0:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2084; /* pred_subvnx1qi_scalar */

        case 1:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2089; /* pred_subvnx2qi_scalar */

        case 2:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2094; /* pred_subvnx4qi_scalar */

        case 3:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2099; /* pred_subvnx8qi_scalar */

        case 4:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2104; /* pred_subvnx16qi_scalar */

        case 5:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2109; /* pred_subvnx32qi_scalar */

        case 6:
          if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2114; /* pred_subvnx64qi_scalar */

        case 7:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2119; /* pred_subvnx1hi_scalar */

        case 8:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2124; /* pred_subvnx2hi_scalar */

        case 9:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2129; /* pred_subvnx4hi_scalar */

        case 10:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2134; /* pred_subvnx8hi_scalar */

        case 11:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2139; /* pred_subvnx16hi_scalar */

        case 12:
          if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2144; /* pred_subvnx32hi_scalar */

        case 13:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2149; /* pred_subvnx1si_scalar */

        case 14:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2154; /* pred_subvnx2si_scalar */

        case 15:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2159; /* pred_subvnx4si_scalar */

        case 16:
          if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2164; /* pred_subvnx8si_scalar */

        case 17:
          if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2169; /* pred_subvnx16si_scalar */

        case 18:
          if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2264; /* *pred_subvnx1di_scalar */

        case 19:
          if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2269; /* *pred_subvnx2di_scalar */

        case 20:
          if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2274; /* *pred_subvnx4di_scalar */

        case 21:
          if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2279; /* *pred_subvnx8di_scalar */

        case 22:
          if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4690; /* pred_subvnx1sf_scalar */

        case 23:
          if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4692; /* pred_subvnx2sf_scalar */

        case 24:
          if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4694; /* pred_subvnx4sf_scalar */

        case 25:
          if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4696; /* pred_subvnx8sf_scalar */

        case 26:
          if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4698; /* pred_subvnx16sf_scalar */

        case 27:
          if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4700; /* pred_subvnx1df_scalar */

        case 28:
          if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4702; /* pred_subvnx2df_scalar */

        case 29:
          if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4704; /* pred_subvnx4df_scalar */

        case 30:
          if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4706; /* pred_subvnx8df_scalar */

        case 31:
          if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2284; /* *pred_subvnx1di_extended_scalar */

        case 32:
          if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2289; /* *pred_subvnx2di_extended_scalar */

        case 33:
          if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2294; /* *pred_subvnx4di_extended_scalar */

        case 34:
          if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2299; /* *pred_subvnx8di_extended_scalar */

        default:
          return -1;
        }

    case SIGN_EXTEND:
      switch (pattern206 (x2))
        {
        case 0:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3025; /* pred_single_widen_subsvnx1hi */

        case 1:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3029; /* pred_single_widen_subsvnx2hi */

        case 2:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3033; /* pred_single_widen_subsvnx4hi */

        case 3:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3037; /* pred_single_widen_subsvnx8hi */

        case 4:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3041; /* pred_single_widen_subsvnx16hi */

        case 5:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3045; /* pred_single_widen_subsvnx32hi */

        case 6:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3049; /* pred_single_widen_subsvnx1si */

        case 7:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3053; /* pred_single_widen_subsvnx2si */

        case 8:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3057; /* pred_single_widen_subsvnx4si */

        case 9:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3061; /* pred_single_widen_subsvnx8si */

        case 10:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3065; /* pred_single_widen_subsvnx16si */

        case 11:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3069; /* pred_single_widen_subsvnx1di */

        case 12:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3073; /* pred_single_widen_subsvnx2di */

        case 13:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3077; /* pred_single_widen_subsvnx4di */

        case 14:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3081; /* pred_single_widen_subsvnx8di */

        case 15:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3085; /* pred_single_widen_subsvnx1hi_scalar */

        case 16:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3089; /* pred_single_widen_subsvnx2hi_scalar */

        case 17:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3093; /* pred_single_widen_subsvnx4hi_scalar */

        case 18:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3097; /* pred_single_widen_subsvnx8hi_scalar */

        case 19:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3101; /* pred_single_widen_subsvnx16hi_scalar */

        case 20:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3105; /* pred_single_widen_subsvnx32hi_scalar */

        case 21:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3109; /* pred_single_widen_subsvnx1si_scalar */

        case 22:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3113; /* pred_single_widen_subsvnx2si_scalar */

        case 23:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3117; /* pred_single_widen_subsvnx4si_scalar */

        case 24:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3121; /* pred_single_widen_subsvnx8si_scalar */

        case 25:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3125; /* pred_single_widen_subsvnx16si_scalar */

        case 26:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3129; /* pred_single_widen_subsvnx1di_scalar */

        case 27:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3133; /* pred_single_widen_subsvnx2di_scalar */

        case 28:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3137; /* pred_single_widen_subsvnx4di_scalar */

        case 29:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3141; /* pred_single_widen_subsvnx8di_scalar */

        default:
          return -1;
        }

    case ZERO_EXTEND:
      switch (pattern206 (x2))
        {
        case 0:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3027; /* pred_single_widen_subuvnx1hi */

        case 1:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3031; /* pred_single_widen_subuvnx2hi */

        case 2:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3035; /* pred_single_widen_subuvnx4hi */

        case 3:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3039; /* pred_single_widen_subuvnx8hi */

        case 4:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3043; /* pred_single_widen_subuvnx16hi */

        case 5:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3047; /* pred_single_widen_subuvnx32hi */

        case 6:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3051; /* pred_single_widen_subuvnx1si */

        case 7:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3055; /* pred_single_widen_subuvnx2si */

        case 8:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3059; /* pred_single_widen_subuvnx4si */

        case 9:
          if (!
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3063; /* pred_single_widen_subuvnx8si */

        case 10:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3067; /* pred_single_widen_subuvnx16si */

        case 11:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3071; /* pred_single_widen_subuvnx1di */

        case 12:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3075; /* pred_single_widen_subuvnx2di */

        case 13:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3079; /* pred_single_widen_subuvnx4di */

        case 14:
          if (!(
#line 3005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3083; /* pred_single_widen_subuvnx8di */

        case 15:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3087; /* pred_single_widen_subuvnx1hi_scalar */

        case 16:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3091; /* pred_single_widen_subuvnx2hi_scalar */

        case 17:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3095; /* pred_single_widen_subuvnx4hi_scalar */

        case 18:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3099; /* pred_single_widen_subuvnx8hi_scalar */

        case 19:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3103; /* pred_single_widen_subuvnx16hi_scalar */

        case 20:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3107; /* pred_single_widen_subuvnx32hi_scalar */

        case 21:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3111; /* pred_single_widen_subuvnx1si_scalar */

        case 22:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3115; /* pred_single_widen_subuvnx2si_scalar */

        case 23:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3119; /* pred_single_widen_subuvnx4si_scalar */

        case 24:
          if (!
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3123; /* pred_single_widen_subuvnx8si_scalar */

        case 25:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3127; /* pred_single_widen_subuvnx16si_scalar */

        case 26:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3131; /* pred_single_widen_subuvnx1di_scalar */

        case 27:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3135; /* pred_single_widen_subuvnx2di_scalar */

        case 28:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3139; /* pred_single_widen_subuvnx4di_scalar */

        case 29:
          if (!(
#line 3027 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3143; /* pred_single_widen_subuvnx8di_scalar */

        default:
          return -1;
        }

    case MULT:
      return recog_90 (x1, insn, pnum_clobbers);

    case FLOAT_EXTEND:
      x5 = XEXP (x2, 0);
      x6 = XVECEXP (x5, 0, 1);
      operands[5] = x6;
      x7 = XVECEXP (x5, 0, 2);
      operands[6] = x7;
      x8 = XVECEXP (x5, 0, 3);
      operands[7] = x8;
      x9 = XVECEXP (x5, 0, 4);
      operands[8] = x9;
      x10 = XEXP (x3, 0);
      operands[3] = x10;
      x11 = XEXP (x2, 2);
      operands[2] = x11;
      switch (pattern268 (x2))
        {
        case 0:
          if (!(
#line 6137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5075; /* pred_single_widen_subvnx1df */

        case 1:
          if (!(
#line 6137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5077; /* pred_single_widen_subvnx2df */

        case 2:
          if (!(
#line 6137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5079; /* pred_single_widen_subvnx4df */

        case 3:
          if (!(
#line 6137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5081; /* pred_single_widen_subvnx8df */

        case 4:
          if (!(
#line 6159 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5083; /* pred_single_widen_subvnx1df_scalar */

        case 5:
          if (!(
#line 6159 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5085; /* pred_single_widen_subvnx2df_scalar */

        case 6:
          if (!(
#line 6159 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5087; /* pred_single_widen_subvnx4df_scalar */

        case 7:
          if (!(
#line 6159 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5089; /* pred_single_widen_subvnx8df_scalar */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_93 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern187 (x2))
    {
    case 0:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx1SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4889; /* *pred_nmaddvnx1sf */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4907; /* *pred_nmaccvnx1sf */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx1SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx1SFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4925; /* *pred_mul_neg_subvnx1sf */

    case 1:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx2SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4891; /* *pred_nmaddvnx2sf */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4909; /* *pred_nmaccvnx2sf */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx2SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx2SFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4927; /* *pred_mul_neg_subvnx2sf */

    case 2:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx4SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4893; /* *pred_nmaddvnx4sf */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4911; /* *pred_nmaccvnx4sf */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx4SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx4SFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4929; /* *pred_mul_neg_subvnx4sf */

    case 3:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx8SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4895; /* *pred_nmaddvnx8sf */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4913; /* *pred_nmaccvnx8sf */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx8SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx8SFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4931; /* *pred_mul_neg_subvnx8sf */

    case 4:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx16SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return 4897; /* *pred_nmaddvnx16sf */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return 4915; /* *pred_nmaccvnx16sf */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx16SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx16SFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 4933; /* *pred_mul_neg_subvnx16sf */

    case 5:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx1DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4899; /* *pred_nmaddvnx1df */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4917; /* *pred_nmaccvnx1df */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx1DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx1DFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4935; /* *pred_mul_neg_subvnx1df */

    case 6:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx2DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4901; /* *pred_nmaddvnx2df */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4919; /* *pred_nmaccvnx2df */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx2DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx2DFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4937; /* *pred_mul_neg_subvnx2df */

    case 7:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx4DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4903; /* *pred_nmaddvnx4df */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4921; /* *pred_nmaccvnx4df */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx4DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx4DFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4939; /* *pred_mul_neg_subvnx4df */

    case 8:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx8DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[2])
              && (
#line 5789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4905; /* *pred_nmaddvnx8df */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5821 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4923; /* *pred_nmaccvnx8df */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx8DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx8DFmode)
          || !(
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4941; /* *pred_mul_neg_subvnx8df */

    case 9:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx1SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4943; /* *pred_nmaddvnx1sf_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4961; /* *pred_nmaccvnx1sf_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx1SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx1SFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4979; /* *pred_mul_neg_subvnx1sf_scalar */

    case 10:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx2SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4945; /* *pred_nmaddvnx2sf_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4963; /* *pred_nmaccvnx2sf_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx2SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx2SFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4981; /* *pred_mul_neg_subvnx2sf_scalar */

    case 11:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx4SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4947; /* *pred_nmaddvnx4sf_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4965; /* *pred_nmaccvnx4sf_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx4SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx4SFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4983; /* *pred_mul_neg_subvnx4sf_scalar */

    case 12:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx8SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4949; /* *pred_nmaddvnx8sf_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return 4967; /* *pred_nmaccvnx8sf_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx8SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx8SFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4985; /* *pred_mul_neg_subvnx8sf_scalar */

    case 13:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx16SFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return 4951; /* *pred_nmaddvnx16sf_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return 4969; /* *pred_nmaccvnx16sf_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx16SFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx16SFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 4987; /* *pred_mul_neg_subvnx16sf_scalar */

    case 14:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx1DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4953; /* *pred_nmaddvnx1df_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4971; /* *pred_nmaccvnx1df_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx1DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx1DFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4989; /* *pred_mul_neg_subvnx1df_scalar */

    case 15:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx2DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4955; /* *pred_nmaddvnx2df_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4973; /* *pred_nmaccvnx2df_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx2DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx2DFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4991; /* *pred_mul_neg_subvnx2df_scalar */

    case 16:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx4DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4957; /* *pred_nmaddvnx4df_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4975; /* *pred_nmaccvnx4df_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx4DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx4DFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4993; /* *pred_mul_neg_subvnx4df_scalar */

    case 17:
      x3 = XEXP (x2, 0);
      x4 = XVECEXP (x3, 0, 1);
      operands[5] = x4;
      x5 = XVECEXP (x3, 0, 2);
      operands[6] = x5;
      x6 = XVECEXP (x3, 0, 3);
      operands[7] = x6;
      x7 = XVECEXP (x3, 0, 4);
      operands[8] = x7;
      if (register_operand (operands[4], E_VNx8DFmode))
        {
          x8 = XEXP (x2, 2);
          if (rtx_equal_p (x8, operands[3])
              && (
#line 5912 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4959; /* *pred_nmaddvnx8df_scalar */
          if (rtx_equal_p (x8, operands[4])
              && (
#line 5945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return 4977; /* *pred_nmaccvnx8df_scalar */
        }
      operands[6] = x4;
      operands[7] = x5;
      operands[8] = x6;
      operands[9] = x7;
      if (!vector_arith_operand (operands[4], E_VNx8DFmode))
        return -1;
      x8 = XEXP (x2, 2);
      operands[5] = x8;
      if (!register_operand (operands[5], E_VNx8DFmode)
          || !(
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4995; /* *pred_mul_neg_subvnx8df_scalar */

    case 18:
      if (!(
#line 6240 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5107; /* pred_widen_mul_neg_subvnx1df */

    case 19:
      if (!(
#line 6240 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5109; /* pred_widen_mul_neg_subvnx2df */

    case 20:
      if (!(
#line 6240 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5111; /* pred_widen_mul_neg_subvnx4df */

    case 21:
      if (!(
#line 6240 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5113; /* pred_widen_mul_neg_subvnx8df */

    case 22:
      if (!(
#line 6266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5115; /* pred_widen_mul_neg_subvnx1df_scalar */

    case 23:
      if (!(
#line 6266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5117; /* pred_widen_mul_neg_subvnx2df_scalar */

    case 24:
      if (!(
#line 6266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5119; /* pred_widen_mul_neg_subvnx4df_scalar */

    case 25:
      if (!(
#line 6266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5121; /* pred_widen_mul_neg_subvnx8df_scalar */

    default:
      return -1;
    }
}

static int
recog_94 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  x8 = XEXP (x2, 2);
  operands[2] = x8;
  x9 = XEXP (x2, 1);
  x10 = XEXP (x9, 0);
  switch (GET_CODE (x10))
    {
    case REG:
    case SUBREG:
      operands[3] = x10;
      switch (pattern154 (x2))
        {
        case 0:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1494; /* pred_mulvnx1qi */

        case 1:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1511; /* pred_mulvnx2qi */

        case 2:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1528; /* pred_mulvnx4qi */

        case 3:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1545; /* pred_mulvnx8qi */

        case 4:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1562; /* pred_mulvnx16qi */

        case 5:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1579; /* pred_mulvnx32qi */

        case 6:
          if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1596; /* pred_mulvnx64qi */

        case 7:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1613; /* pred_mulvnx1hi */

        case 8:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1630; /* pred_mulvnx2hi */

        case 9:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1647; /* pred_mulvnx4hi */

        case 10:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1664; /* pred_mulvnx8hi */

        case 11:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1681; /* pred_mulvnx16hi */

        case 12:
          if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1698; /* pred_mulvnx32hi */

        case 13:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1715; /* pred_mulvnx1si */

        case 14:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1732; /* pred_mulvnx2si */

        case 15:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1749; /* pred_mulvnx4si */

        case 16:
          if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1766; /* pred_mulvnx8si */

        case 17:
          if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1783; /* pred_mulvnx16si */

        case 18:
          if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1800; /* pred_mulvnx1di */

        case 19:
          if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1817; /* pred_mulvnx2di */

        case 20:
          if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1834; /* pred_mulvnx4di */

        case 21:
          if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1851; /* pred_mulvnx8di */

        case 22:
          if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4601; /* pred_mulvnx1sf */

        case 23:
          if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4607; /* pred_mulvnx2sf */

        case 24:
          if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4613; /* pred_mulvnx4sf */

        case 25:
          if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4619; /* pred_mulvnx8sf */

        case 26:
          if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4625; /* pred_mulvnx16sf */

        case 27:
          if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4631; /* pred_mulvnx1df */

        case 28:
          if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4637; /* pred_mulvnx2df */

        case 29:
          if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4643; /* pred_mulvnx4df */

        case 30:
          if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4649; /* pred_mulvnx8df */

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x11 = XEXP (x9, 1);
      operands[3] = x11;
      switch (pattern156 (x2))
        {
        case 0:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1930; /* pred_mulvnx1qi_scalar */

        case 1:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1939; /* pred_mulvnx2qi_scalar */

        case 2:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1948; /* pred_mulvnx4qi_scalar */

        case 3:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1957; /* pred_mulvnx8qi_scalar */

        case 4:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1966; /* pred_mulvnx16qi_scalar */

        case 5:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1975; /* pred_mulvnx32qi_scalar */

        case 6:
          if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1984; /* pred_mulvnx64qi_scalar */

        case 7:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1993; /* pred_mulvnx1hi_scalar */

        case 8:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2002; /* pred_mulvnx2hi_scalar */

        case 9:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2011; /* pred_mulvnx4hi_scalar */

        case 10:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2020; /* pred_mulvnx8hi_scalar */

        case 11:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2029; /* pred_mulvnx16hi_scalar */

        case 12:
          if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2038; /* pred_mulvnx32hi_scalar */

        case 13:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2047; /* pred_mulvnx1si_scalar */

        case 14:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2056; /* pred_mulvnx2si_scalar */

        case 15:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2065; /* pred_mulvnx4si_scalar */

        case 16:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2074; /* pred_mulvnx8si_scalar */

        case 17:
          if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2083; /* pred_mulvnx16si_scalar */

        case 18:
          if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2200; /* *pred_mulvnx1di_scalar */

        case 19:
          if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2209; /* *pred_mulvnx2di_scalar */

        case 20:
          if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2218; /* *pred_mulvnx4di_scalar */

        case 21:
          if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2227; /* *pred_mulvnx8di_scalar */

        case 22:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4655; /* pred_mulvnx1sf_scalar */

        case 23:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4659; /* pred_mulvnx2sf_scalar */

        case 24:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4663; /* pred_mulvnx4sf_scalar */

        case 25:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4667; /* pred_mulvnx8sf_scalar */

        case 26:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4671; /* pred_mulvnx16sf_scalar */

        case 27:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4675; /* pred_mulvnx1df_scalar */

        case 28:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4679; /* pred_mulvnx2df_scalar */

        case 29:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4683; /* pred_mulvnx4df_scalar */

        case 30:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4687; /* pred_mulvnx8df_scalar */

        case 31:
          if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2236; /* *pred_mulvnx1di_extended_scalar */

        case 32:
          if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2245; /* *pred_mulvnx2di_extended_scalar */

        case 33:
          if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2254; /* *pred_mulvnx4di_extended_scalar */

        case 34:
          if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2263; /* *pred_mulvnx8di_extended_scalar */

        default:
          return -1;
        }

    case SIGN_EXTEND:
      x12 = XEXP (x10, 0);
      operands[3] = x12;
      x11 = XEXP (x9, 1);
      switch (GET_CODE (x11))
        {
        case SIGN_EXTEND:
          switch (pattern194 (x2))
            {
            case 0:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2846; /* pred_dual_widen_mulsvnx1hi */

            case 1:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2852; /* pred_dual_widen_mulsvnx2hi */

            case 2:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2858; /* pred_dual_widen_mulsvnx4hi */

            case 3:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2864; /* pred_dual_widen_mulsvnx8hi */

            case 4:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2870; /* pred_dual_widen_mulsvnx16hi */

            case 5:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2876; /* pred_dual_widen_mulsvnx32hi */

            case 6:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2882; /* pred_dual_widen_mulsvnx1si */

            case 7:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2888; /* pred_dual_widen_mulsvnx2si */

            case 8:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2894; /* pred_dual_widen_mulsvnx4si */

            case 9:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2900; /* pred_dual_widen_mulsvnx8si */

            case 10:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2906; /* pred_dual_widen_mulsvnx16si */

            case 11:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2912; /* pred_dual_widen_mulsvnx1di */

            case 12:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2918; /* pred_dual_widen_mulsvnx2di */

            case 13:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2924; /* pred_dual_widen_mulsvnx4di */

            case 14:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2930; /* pred_dual_widen_mulsvnx8di */

            case 15:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2936; /* pred_dual_widen_mulsvnx1hi_scalar */

            case 16:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2942; /* pred_dual_widen_mulsvnx2hi_scalar */

            case 17:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2948; /* pred_dual_widen_mulsvnx4hi_scalar */

            case 18:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2954; /* pred_dual_widen_mulsvnx8hi_scalar */

            case 19:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2960; /* pred_dual_widen_mulsvnx16hi_scalar */

            case 20:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2966; /* pred_dual_widen_mulsvnx32hi_scalar */

            case 21:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2972; /* pred_dual_widen_mulsvnx1si_scalar */

            case 22:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2978; /* pred_dual_widen_mulsvnx2si_scalar */

            case 23:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2984; /* pred_dual_widen_mulsvnx4si_scalar */

            case 24:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2990; /* pred_dual_widen_mulsvnx8si_scalar */

            case 25:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2996; /* pred_dual_widen_mulsvnx16si_scalar */

            case 26:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3002; /* pred_dual_widen_mulsvnx1di_scalar */

            case 27:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3008; /* pred_dual_widen_mulsvnx2di_scalar */

            case 28:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3014; /* pred_dual_widen_mulsvnx4di_scalar */

            case 29:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3020; /* pred_dual_widen_mulsvnx8di_scalar */

            default:
              return -1;
            }

        case ZERO_EXTEND:
          switch (pattern194 (x2))
            {
            case 0:
              if (!
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3144; /* pred_widen_mulsuvnx1hi */

            case 1:
              if (!
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3145; /* pred_widen_mulsuvnx2hi */

            case 2:
              if (!
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3146; /* pred_widen_mulsuvnx4hi */

            case 3:
              if (!
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3147; /* pred_widen_mulsuvnx8hi */

            case 4:
              if (!
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3148; /* pred_widen_mulsuvnx16hi */

            case 5:
              if (!(
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 3149; /* pred_widen_mulsuvnx32hi */

            case 6:
              if (!
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3150; /* pred_widen_mulsuvnx1si */

            case 7:
              if (!
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3151; /* pred_widen_mulsuvnx2si */

            case 8:
              if (!
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3152; /* pred_widen_mulsuvnx4si */

            case 9:
              if (!
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3153; /* pred_widen_mulsuvnx8si */

            case 10:
              if (!(
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 3154; /* pred_widen_mulsuvnx16si */

            case 11:
              if (!(
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3155; /* pred_widen_mulsuvnx1di */

            case 12:
              if (!(
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3156; /* pred_widen_mulsuvnx2di */

            case 13:
              if (!(
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3157; /* pred_widen_mulsuvnx4di */

            case 14:
              if (!(
#line 3049 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3158; /* pred_widen_mulsuvnx8di */

            case 15:
              if (!
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3159; /* pred_widen_mulsuvnx1hi_scalar */

            case 16:
              if (!
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3160; /* pred_widen_mulsuvnx2hi_scalar */

            case 17:
              if (!
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3161; /* pred_widen_mulsuvnx4hi_scalar */

            case 18:
              if (!
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3162; /* pred_widen_mulsuvnx8hi_scalar */

            case 19:
              if (!
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3163; /* pred_widen_mulsuvnx16hi_scalar */

            case 20:
              if (!(
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 3164; /* pred_widen_mulsuvnx32hi_scalar */

            case 21:
              if (!
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3165; /* pred_widen_mulsuvnx1si_scalar */

            case 22:
              if (!
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3166; /* pred_widen_mulsuvnx2si_scalar */

            case 23:
              if (!
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3167; /* pred_widen_mulsuvnx4si_scalar */

            case 24:
              if (!
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3168; /* pred_widen_mulsuvnx8si_scalar */

            case 25:
              if (!(
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 3169; /* pred_widen_mulsuvnx16si_scalar */

            case 26:
              if (!(
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3170; /* pred_widen_mulsuvnx1di_scalar */

            case 27:
              if (!(
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3171; /* pred_widen_mulsuvnx2di_scalar */

            case 28:
              if (!(
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3172; /* pred_widen_mulsuvnx4di_scalar */

            case 29:
              if (!(
#line 3072 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3173; /* pred_widen_mulsuvnx8di_scalar */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case ZERO_EXTEND:
      x11 = XEXP (x9, 1);
      if (GET_CODE (x11) != ZERO_EXTEND)
        return -1;
      x12 = XEXP (x10, 0);
      operands[3] = x12;
      switch (pattern194 (x2))
        {
        case 0:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2849; /* pred_dual_widen_muluvnx1hi */

        case 1:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2855; /* pred_dual_widen_muluvnx2hi */

        case 2:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2861; /* pred_dual_widen_muluvnx4hi */

        case 3:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2867; /* pred_dual_widen_muluvnx8hi */

        case 4:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2873; /* pred_dual_widen_muluvnx16hi */

        case 5:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2879; /* pred_dual_widen_muluvnx32hi */

        case 6:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2885; /* pred_dual_widen_muluvnx1si */

        case 7:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2891; /* pred_dual_widen_muluvnx2si */

        case 8:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2897; /* pred_dual_widen_muluvnx4si */

        case 9:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2903; /* pred_dual_widen_muluvnx8si */

        case 10:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2909; /* pred_dual_widen_muluvnx16si */

        case 11:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2915; /* pred_dual_widen_muluvnx1di */

        case 12:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2921; /* pred_dual_widen_muluvnx2di */

        case 13:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2927; /* pred_dual_widen_muluvnx4di */

        case 14:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2933; /* pred_dual_widen_muluvnx8di */

        case 15:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2939; /* pred_dual_widen_muluvnx1hi_scalar */

        case 16:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2945; /* pred_dual_widen_muluvnx2hi_scalar */

        case 17:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2951; /* pred_dual_widen_muluvnx4hi_scalar */

        case 18:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2957; /* pred_dual_widen_muluvnx8hi_scalar */

        case 19:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2963; /* pred_dual_widen_muluvnx16hi_scalar */

        case 20:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2969; /* pred_dual_widen_muluvnx32hi_scalar */

        case 21:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2975; /* pred_dual_widen_muluvnx1si_scalar */

        case 22:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2981; /* pred_dual_widen_muluvnx2si_scalar */

        case 23:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2987; /* pred_dual_widen_muluvnx4si_scalar */

        case 24:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2993; /* pred_dual_widen_muluvnx8si_scalar */

        case 25:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2999; /* pred_dual_widen_muluvnx16si_scalar */

        case 26:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3005; /* pred_dual_widen_muluvnx1di_scalar */

        case 27:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3011; /* pred_dual_widen_muluvnx2di_scalar */

        case 28:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3017; /* pred_dual_widen_muluvnx4di_scalar */

        case 29:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3023; /* pred_dual_widen_muluvnx8di_scalar */

        default:
          return -1;
        }

    case FLOAT_EXTEND:
      x11 = XEXP (x9, 1);
      if (GET_CODE (x11) != FLOAT_EXTEND)
        return -1;
      x12 = XEXP (x10, 0);
      operands[3] = x12;
      switch (pattern190 (x2))
        {
        case 0:
          if (!(
#line 6093 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5052; /* pred_dual_widen_mulvnx1df */

        case 1:
          if (!(
#line 6093 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5055; /* pred_dual_widen_mulvnx2df */

        case 2:
          if (!(
#line 6093 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5058; /* pred_dual_widen_mulvnx4df */

        case 3:
          if (!(
#line 6093 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5061; /* pred_dual_widen_mulvnx8df */

        case 4:
          if (!(
#line 6116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5064; /* pred_dual_widen_mulvnx1df_scalar */

        case 5:
          if (!(
#line 6116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5067; /* pred_dual_widen_mulvnx2df_scalar */

        case 6:
          if (!(
#line 6116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5070; /* pred_dual_widen_mulvnx4df_scalar */

        case 7:
          if (!(
#line 6116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5073; /* pred_dual_widen_mulvnx8df_scalar */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_95 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 2);
  operands[2] = x3;
  x4 = XEXP (x2, 1);
  x5 = XEXP (x4, 0);
  switch (GET_CODE (x5))
    {
    case ASHIFTRT:
      switch (pattern208 (x2))
        {
        case 0:
          if (vector_shift_operand (operands[4], E_VNx1QImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3204; /* pred_narrow_ashrvnx1hi */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3234; /* pred_narrow_ashrvnx1hi_scalar */

        case 1:
          if (vector_shift_operand (operands[4], E_VNx2QImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3206; /* pred_narrow_ashrvnx2hi */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3236; /* pred_narrow_ashrvnx2hi_scalar */

        case 2:
          if (vector_shift_operand (operands[4], E_VNx4QImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3208; /* pred_narrow_ashrvnx4hi */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3238; /* pred_narrow_ashrvnx4hi_scalar */

        case 3:
          if (vector_shift_operand (operands[4], E_VNx8QImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3210; /* pred_narrow_ashrvnx8hi */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3240; /* pred_narrow_ashrvnx8hi_scalar */

        case 4:
          if (vector_shift_operand (operands[4], E_VNx16QImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3212; /* pred_narrow_ashrvnx16hi */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3242; /* pred_narrow_ashrvnx16hi_scalar */

        case 5:
          if (vector_shift_operand (operands[4], E_VNx32QImode)
              && (
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 3214; /* pred_narrow_ashrvnx32hi */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !(
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3244; /* pred_narrow_ashrvnx32hi_scalar */

        case 6:
          if (vector_shift_operand (operands[4], E_VNx1HImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3216; /* pred_narrow_ashrvnx1si */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3246; /* pred_narrow_ashrvnx1si_scalar */

        case 7:
          if (vector_shift_operand (operands[4], E_VNx2HImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3218; /* pred_narrow_ashrvnx2si */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3248; /* pred_narrow_ashrvnx2si_scalar */

        case 8:
          if (vector_shift_operand (operands[4], E_VNx4HImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3220; /* pred_narrow_ashrvnx4si */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3250; /* pred_narrow_ashrvnx4si_scalar */

        case 9:
          if (vector_shift_operand (operands[4], E_VNx8HImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3222; /* pred_narrow_ashrvnx8si */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3252; /* pred_narrow_ashrvnx8si_scalar */

        case 10:
          if (vector_shift_operand (operands[4], E_VNx16HImode)
              && (
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 3224; /* pred_narrow_ashrvnx16si */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !(
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3254; /* pred_narrow_ashrvnx16si_scalar */

        case 11:
          if (vector_shift_operand (operands[4], E_VNx1SImode)
              && (
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3226; /* pred_narrow_ashrvnx1di */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !(
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3256; /* pred_narrow_ashrvnx1di_scalar */

        case 12:
          if (vector_shift_operand (operands[4], E_VNx2SImode)
              && (
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3228; /* pred_narrow_ashrvnx2di */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !(
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3258; /* pred_narrow_ashrvnx2di_scalar */

        case 13:
          if (vector_shift_operand (operands[4], E_VNx4SImode)
              && (
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3230; /* pred_narrow_ashrvnx4di */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !(
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3260; /* pred_narrow_ashrvnx4di_scalar */

        case 14:
          if (vector_shift_operand (operands[4], E_VNx8SImode)
              && (
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3232; /* pred_narrow_ashrvnx8di */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !(
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3262; /* pred_narrow_ashrvnx8di_scalar */

        default:
          return -1;
        }

    case LSHIFTRT:
      switch (pattern208 (x2))
        {
        case 0:
          if (vector_shift_operand (operands[4], E_VNx1QImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3205; /* pred_narrow_lshrvnx1hi */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3235; /* pred_narrow_lshrvnx1hi_scalar */

        case 1:
          if (vector_shift_operand (operands[4], E_VNx2QImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3207; /* pred_narrow_lshrvnx2hi */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3237; /* pred_narrow_lshrvnx2hi_scalar */

        case 2:
          if (vector_shift_operand (operands[4], E_VNx4QImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3209; /* pred_narrow_lshrvnx4hi */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3239; /* pred_narrow_lshrvnx4hi_scalar */

        case 3:
          if (vector_shift_operand (operands[4], E_VNx8QImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3211; /* pred_narrow_lshrvnx8hi */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3241; /* pred_narrow_lshrvnx8hi_scalar */

        case 4:
          if (vector_shift_operand (operands[4], E_VNx16QImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3213; /* pred_narrow_lshrvnx16hi */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3243; /* pred_narrow_lshrvnx16hi_scalar */

        case 5:
          if (vector_shift_operand (operands[4], E_VNx32QImode)
              && (
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 3215; /* pred_narrow_lshrvnx32hi */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !(
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3245; /* pred_narrow_lshrvnx32hi_scalar */

        case 6:
          if (vector_shift_operand (operands[4], E_VNx1HImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3217; /* pred_narrow_lshrvnx1si */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3247; /* pred_narrow_lshrvnx1si_scalar */

        case 7:
          if (vector_shift_operand (operands[4], E_VNx2HImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3219; /* pred_narrow_lshrvnx2si */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3249; /* pred_narrow_lshrvnx2si_scalar */

        case 8:
          if (vector_shift_operand (operands[4], E_VNx4HImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3221; /* pred_narrow_lshrvnx4si */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3251; /* pred_narrow_lshrvnx4si_scalar */

        case 9:
          if (vector_shift_operand (operands[4], E_VNx8HImode)
              && 
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 3223; /* pred_narrow_lshrvnx8si */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3253; /* pred_narrow_lshrvnx8si_scalar */

        case 10:
          if (vector_shift_operand (operands[4], E_VNx16HImode)
              && (
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 3225; /* pred_narrow_lshrvnx16si */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !(
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3255; /* pred_narrow_lshrvnx16si_scalar */

        case 11:
          if (vector_shift_operand (operands[4], E_VNx1SImode)
              && (
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3227; /* pred_narrow_lshrvnx1di */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !(
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3257; /* pred_narrow_lshrvnx1di_scalar */

        case 12:
          if (vector_shift_operand (operands[4], E_VNx2SImode)
              && (
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3229; /* pred_narrow_lshrvnx2di */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !(
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3259; /* pred_narrow_lshrvnx2di_scalar */

        case 13:
          if (vector_shift_operand (operands[4], E_VNx4SImode)
              && (
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3231; /* pred_narrow_lshrvnx4di */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !(
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3261; /* pred_narrow_lshrvnx4di_scalar */

        case 14:
          if (vector_shift_operand (operands[4], E_VNx8SImode)
              && (
#line 3130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3233; /* pred_narrow_lshrvnx8di */
          if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
              || !(
#line 3151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3263; /* pred_narrow_lshrvnx8di_scalar */

        default:
          return -1;
        }

    case REG:
    case SUBREG:
      operands[3] = x5;
      x6 = XEXP (x2, 0);
      x7 = XVECEXP (x6, 0, 1);
      operands[4] = x7;
      x8 = XVECEXP (x6, 0, 2);
      operands[5] = x8;
      x9 = XVECEXP (x6, 0, 3);
      operands[6] = x9;
      x10 = XVECEXP (x6, 0, 4);
      operands[7] = x10;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          if (pattern164 (x2, E_VNx1QImode, E_VNx1HImode, E_VNx1BImode) != 0
              || !
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3264; /* pred_truncvnx1hi */

        case E_VNx2QImode:
          if (pattern164 (x2, E_VNx2QImode, E_VNx2HImode, E_VNx2BImode) != 0
              || !
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3265; /* pred_truncvnx2hi */

        case E_VNx4QImode:
          if (pattern164 (x2, E_VNx4QImode, E_VNx4HImode, E_VNx4BImode) != 0
              || !
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3266; /* pred_truncvnx4hi */

        case E_VNx8QImode:
          if (pattern164 (x2, E_VNx8QImode, E_VNx8HImode, E_VNx8BImode) != 0
              || !
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3267; /* pred_truncvnx8hi */

        case E_VNx16QImode:
          if (pattern164 (x2, E_VNx16QImode, E_VNx16HImode, E_VNx16BImode) != 0
              || !
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3268; /* pred_truncvnx16hi */

        case E_VNx32QImode:
          if (pattern164 (x2, E_VNx32QImode, E_VNx32HImode, E_VNx32BImode) != 0
              || !(
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3269; /* pred_truncvnx32hi */

        case E_VNx1HImode:
          if (pattern164 (x2, E_VNx1HImode, E_VNx1SImode, E_VNx1BImode) != 0
              || !
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3270; /* pred_truncvnx1si */

        case E_VNx2HImode:
          if (pattern164 (x2, E_VNx2HImode, E_VNx2SImode, E_VNx2BImode) != 0
              || !
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3271; /* pred_truncvnx2si */

        case E_VNx4HImode:
          if (pattern164 (x2, E_VNx4HImode, E_VNx4SImode, E_VNx4BImode) != 0
              || !
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3272; /* pred_truncvnx4si */

        case E_VNx8HImode:
          if (pattern164 (x2, E_VNx8HImode, E_VNx8SImode, E_VNx8BImode) != 0
              || !
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3273; /* pred_truncvnx8si */

        case E_VNx16HImode:
          if (pattern164 (x2, E_VNx16HImode, E_VNx16SImode, E_VNx16BImode) != 0
              || !(
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3274; /* pred_truncvnx16si */

        case E_VNx1SImode:
          if (pattern164 (x2, E_VNx1SImode, E_VNx1DImode, E_VNx1BImode) != 0
              || !(
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3275; /* pred_truncvnx1di */

        case E_VNx2SImode:
          if (pattern164 (x2, E_VNx2SImode, E_VNx2DImode, E_VNx2BImode) != 0
              || !(
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3276; /* pred_truncvnx2di */

        case E_VNx4SImode:
          if (pattern164 (x2, E_VNx4SImode, E_VNx4DImode, E_VNx4BImode) != 0
              || !(
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3277; /* pred_truncvnx4di */

        case E_VNx8SImode:
          if (pattern164 (x2, E_VNx8SImode, E_VNx8DImode, E_VNx8BImode) != 0
              || !(
#line 3171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3278; /* pred_truncvnx8di */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_96 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      return recog_62 (x1, insn, pnum_clobbers);

    case VEC_DUPLICATE:
      switch (pattern182 (x2))
        {
        case 0:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1922; /* pred_addvnx1qi_scalar */

        case 1:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1931; /* pred_addvnx2qi_scalar */

        case 2:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1940; /* pred_addvnx4qi_scalar */

        case 3:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1949; /* pred_addvnx8qi_scalar */

        case 4:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1958; /* pred_addvnx16qi_scalar */

        case 5:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1967; /* pred_addvnx32qi_scalar */

        case 6:
          if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1976; /* pred_addvnx64qi_scalar */

        case 7:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1985; /* pred_addvnx1hi_scalar */

        case 8:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1994; /* pred_addvnx2hi_scalar */

        case 9:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2003; /* pred_addvnx4hi_scalar */

        case 10:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2012; /* pred_addvnx8hi_scalar */

        case 11:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2021; /* pred_addvnx16hi_scalar */

        case 12:
          if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2030; /* pred_addvnx32hi_scalar */

        case 13:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2039; /* pred_addvnx1si_scalar */

        case 14:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2048; /* pred_addvnx2si_scalar */

        case 15:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2057; /* pred_addvnx4si_scalar */

        case 16:
          if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2066; /* pred_addvnx8si_scalar */

        case 17:
          if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2075; /* pred_addvnx16si_scalar */

        case 18:
          if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2192; /* *pred_addvnx1di_scalar */

        case 19:
          if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2201; /* *pred_addvnx2di_scalar */

        case 20:
          if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2210; /* *pred_addvnx4di_scalar */

        case 21:
          if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2219; /* *pred_addvnx8di_scalar */

        case 22:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4654; /* pred_addvnx1sf_scalar */

        case 23:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4658; /* pred_addvnx2sf_scalar */

        case 24:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4662; /* pred_addvnx4sf_scalar */

        case 25:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4666; /* pred_addvnx8sf_scalar */

        case 26:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4670; /* pred_addvnx16sf_scalar */

        case 27:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4674; /* pred_addvnx1df_scalar */

        case 28:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4678; /* pred_addvnx2df_scalar */

        case 29:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4682; /* pred_addvnx4df_scalar */

        case 30:
          if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4686; /* pred_addvnx8df_scalar */

        case 31:
          if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2228; /* *pred_addvnx1di_extended_scalar */

        case 32:
          if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2237; /* *pred_addvnx2di_extended_scalar */

        case 33:
          if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2246; /* *pred_addvnx4di_extended_scalar */

        case 34:
          if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2255; /* *pred_addvnx8di_extended_scalar */

        default:
          return -1;
        }

    case SIGN_EXTEND:
      x5 = XEXP (x4, 0);
      operands[3] = x5;
      x6 = XEXP (x2, 2);
      operands[2] = x6;
      x7 = XEXP (x3, 1);
      switch (GET_CODE (x7))
        {
        case SIGN_EXTEND:
          switch (pattern216 (x2))
            {
            case 0:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2844; /* pred_dual_widen_addsvnx1hi */

            case 1:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2850; /* pred_dual_widen_addsvnx2hi */

            case 2:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2856; /* pred_dual_widen_addsvnx4hi */

            case 3:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2862; /* pred_dual_widen_addsvnx8hi */

            case 4:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2868; /* pred_dual_widen_addsvnx16hi */

            case 5:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2874; /* pred_dual_widen_addsvnx32hi */

            case 6:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2880; /* pred_dual_widen_addsvnx1si */

            case 7:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2886; /* pred_dual_widen_addsvnx2si */

            case 8:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2892; /* pred_dual_widen_addsvnx4si */

            case 9:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2898; /* pred_dual_widen_addsvnx8si */

            case 10:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2904; /* pred_dual_widen_addsvnx16si */

            case 11:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2910; /* pred_dual_widen_addsvnx1di */

            case 12:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2916; /* pred_dual_widen_addsvnx2di */

            case 13:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2922; /* pred_dual_widen_addsvnx4di */

            case 14:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2928; /* pred_dual_widen_addsvnx8di */

            case 15:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2934; /* pred_dual_widen_addsvnx1hi_scalar */

            case 16:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2940; /* pred_dual_widen_addsvnx2hi_scalar */

            case 17:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2946; /* pred_dual_widen_addsvnx4hi_scalar */

            case 18:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2952; /* pred_dual_widen_addsvnx8hi_scalar */

            case 19:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2958; /* pred_dual_widen_addsvnx16hi_scalar */

            case 20:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2964; /* pred_dual_widen_addsvnx32hi_scalar */

            case 21:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2970; /* pred_dual_widen_addsvnx1si_scalar */

            case 22:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2976; /* pred_dual_widen_addsvnx2si_scalar */

            case 23:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2982; /* pred_dual_widen_addsvnx4si_scalar */

            case 24:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2988; /* pred_dual_widen_addsvnx8si_scalar */

            case 25:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2994; /* pred_dual_widen_addsvnx16si_scalar */

            case 26:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3000; /* pred_dual_widen_addsvnx1di_scalar */

            case 27:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3006; /* pred_dual_widen_addsvnx2di_scalar */

            case 28:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3012; /* pred_dual_widen_addsvnx4di_scalar */

            case 29:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3018; /* pred_dual_widen_addsvnx8di_scalar */

            default:
              return -1;
            }

        case VEC_DUPLICATE:
          switch (pattern218 (x2))
            {
            case 0:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3174; /* pred_extendvnx1hi */

            case 1:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3176; /* pred_extendvnx2hi */

            case 2:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3178; /* pred_extendvnx4hi */

            case 3:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3180; /* pred_extendvnx8hi */

            case 4:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3182; /* pred_extendvnx16hi */

            case 5:
              if (!(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 3184; /* pred_extendvnx32hi */

            case 6:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3186; /* pred_extendvnx1si */

            case 7:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3188; /* pred_extendvnx2si */

            case 8:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3190; /* pred_extendvnx4si */

            case 9:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3192; /* pred_extendvnx8si */

            case 10:
              if (!(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 3194; /* pred_extendvnx16si */

            case 11:
              if (!(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3196; /* pred_extendvnx1di */

            case 12:
              if (!(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3198; /* pred_extendvnx2di */

            case 13:
              if (!(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3200; /* pred_extendvnx4di */

            case 14:
              if (!(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3202; /* pred_extendvnx8di */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case ZERO_EXTEND:
      x5 = XEXP (x4, 0);
      operands[3] = x5;
      x6 = XEXP (x2, 2);
      operands[2] = x6;
      x7 = XEXP (x3, 1);
      switch (GET_CODE (x7))
        {
        case ZERO_EXTEND:
          switch (pattern216 (x2))
            {
            case 0:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2847; /* pred_dual_widen_adduvnx1hi */

            case 1:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2853; /* pred_dual_widen_adduvnx2hi */

            case 2:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2859; /* pred_dual_widen_adduvnx4hi */

            case 3:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2865; /* pred_dual_widen_adduvnx8hi */

            case 4:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2871; /* pred_dual_widen_adduvnx16hi */

            case 5:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2877; /* pred_dual_widen_adduvnx32hi */

            case 6:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2883; /* pred_dual_widen_adduvnx1si */

            case 7:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2889; /* pred_dual_widen_adduvnx2si */

            case 8:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2895; /* pred_dual_widen_adduvnx4si */

            case 9:
              if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2901; /* pred_dual_widen_adduvnx8si */

            case 10:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2907; /* pred_dual_widen_adduvnx16si */

            case 11:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2913; /* pred_dual_widen_adduvnx1di */

            case 12:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2919; /* pred_dual_widen_adduvnx2di */

            case 13:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2925; /* pred_dual_widen_adduvnx4di */

            case 14:
              if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2931; /* pred_dual_widen_adduvnx8di */

            case 15:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2937; /* pred_dual_widen_adduvnx1hi_scalar */

            case 16:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2943; /* pred_dual_widen_adduvnx2hi_scalar */

            case 17:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2949; /* pred_dual_widen_adduvnx4hi_scalar */

            case 18:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2955; /* pred_dual_widen_adduvnx8hi_scalar */

            case 19:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2961; /* pred_dual_widen_adduvnx16hi_scalar */

            case 20:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2967; /* pred_dual_widen_adduvnx32hi_scalar */

            case 21:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2973; /* pred_dual_widen_adduvnx1si_scalar */

            case 22:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2979; /* pred_dual_widen_adduvnx2si_scalar */

            case 23:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2985; /* pred_dual_widen_adduvnx4si_scalar */

            case 24:
              if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2991; /* pred_dual_widen_adduvnx8si_scalar */

            case 25:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2997; /* pred_dual_widen_adduvnx16si_scalar */

            case 26:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3003; /* pred_dual_widen_adduvnx1di_scalar */

            case 27:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3009; /* pred_dual_widen_adduvnx2di_scalar */

            case 28:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3015; /* pred_dual_widen_adduvnx4di_scalar */

            case 29:
              if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3021; /* pred_dual_widen_adduvnx8di_scalar */

            default:
              return -1;
            }

        case VEC_DUPLICATE:
          switch (pattern218 (x2))
            {
            case 0:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3175; /* pred_zero_extendvnx1hi */

            case 1:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3177; /* pred_zero_extendvnx2hi */

            case 2:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3179; /* pred_zero_extendvnx4hi */

            case 3:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3181; /* pred_zero_extendvnx8hi */

            case 4:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3183; /* pred_zero_extendvnx16hi */

            case 5:
              if (!(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 3185; /* pred_zero_extendvnx32hi */

            case 6:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3187; /* pred_zero_extendvnx1si */

            case 7:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3189; /* pred_zero_extendvnx2si */

            case 8:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3191; /* pred_zero_extendvnx4si */

            case 9:
              if (!
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 3193; /* pred_zero_extendvnx8si */

            case 10:
              if (!(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 3195; /* pred_zero_extendvnx16si */

            case 11:
              if (!(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3197; /* pred_zero_extendvnx1di */

            case 12:
              if (!(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3199; /* pred_zero_extendvnx2di */

            case 13:
              if (!(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3201; /* pred_zero_extendvnx4di */

            case 14:
              if (!(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 3203; /* pred_zero_extendvnx8di */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case MULT:
      return recog_63 (x1, insn, pnum_clobbers);

    case NEG:
      return recog_61 (x1, insn, pnum_clobbers);

    case FLOAT_EXTEND:
      switch (pattern191 (x2))
        {
        case 0:
          if (!(
#line 6093 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5050; /* pred_dual_widen_addvnx1df */

        case 1:
          if (!(
#line 6093 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5053; /* pred_dual_widen_addvnx2df */

        case 2:
          if (!(
#line 6093 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5056; /* pred_dual_widen_addvnx4df */

        case 3:
          if (!(
#line 6093 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5059; /* pred_dual_widen_addvnx8df */

        case 4:
          if (!(
#line 6116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5062; /* pred_dual_widen_addvnx1df_scalar */

        case 5:
          if (!(
#line 6116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5065; /* pred_dual_widen_addvnx2df_scalar */

        case 6:
          if (!(
#line 6116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5068; /* pred_dual_widen_addvnx4df_scalar */

        case 7:
          if (!(
#line 6116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5071; /* pred_dual_widen_addvnx8df_scalar */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_97 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 2);
  operands[2] = x3;
  x4 = XEXP (x2, 1);
  switch (XVECLEN (x4, 0))
    {
    case 3:
      x5 = XVECEXP (x4, 0, 1);
      if (GET_CODE (x5) != MEM
          || GET_MODE (x5) != E_BLKmode)
        return -1;
      x6 = XEXP (x5, 0);
      if (GET_CODE (x6) != SCRATCH)
        return -1;
      x7 = XEXP (x2, 0);
      x8 = XVECEXP (x7, 0, 1);
      operands[5] = x8;
      x9 = XVECEXP (x7, 0, 2);
      operands[6] = x9;
      x10 = XVECEXP (x7, 0, 3);
      operands[7] = x10;
      x11 = XVECEXP (x7, 0, 4);
      operands[8] = x11;
      x12 = XVECEXP (x4, 0, 0);
      operands[3] = x12;
      if (!pmode_register_operand (operands[3], E_VOIDmode))
        return -1;
      x13 = XVECEXP (x4, 0, 2);
      operands[4] = x13;
      switch (XINT (x4, 1))
        {
        case 71:
          switch (pattern313 (x2))
            {
            case 0:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1030; /* pred_indexed_oloadvnx1qi_same_eew */

            case 1:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1192; /* pred_indexed_oloadvnx1qi_x2_smaller_eew */

            case 2:
              if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1230; /* pred_indexed_oloadvnx1qi_x4_smaller_eew */

            case 3:
              if (!
#line 1546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1248; /* pred_indexed_oloadvnx1qi_x8_smaller_eew */

            case 4:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1032; /* pred_indexed_oloadvnx2qi_same_eew */

            case 5:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1194; /* pred_indexed_oloadvnx2qi_x2_smaller_eew */

            case 6:
              if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1232; /* pred_indexed_oloadvnx2qi_x4_smaller_eew */

            case 7:
              if (!
#line 1546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1250; /* pred_indexed_oloadvnx2qi_x8_smaller_eew */

            case 8:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1034; /* pred_indexed_oloadvnx4qi_same_eew */

            case 9:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1196; /* pred_indexed_oloadvnx4qi_x2_smaller_eew */

            case 10:
              if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1234; /* pred_indexed_oloadvnx4qi_x4_smaller_eew */

            case 11:
              if (!
#line 1546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1252; /* pred_indexed_oloadvnx4qi_x8_smaller_eew */

            case 12:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1036; /* pred_indexed_oloadvnx8qi_same_eew */

            case 13:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1198; /* pred_indexed_oloadvnx8qi_x2_smaller_eew */

            case 14:
              if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1236; /* pred_indexed_oloadvnx8qi_x4_smaller_eew */

            case 15:
              if (!
#line 1546 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1254; /* pred_indexed_oloadvnx8qi_x8_smaller_eew */

            case 16:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1038; /* pred_indexed_oloadvnx16qi_same_eew */

            case 17:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1200; /* pred_indexed_oloadvnx16qi_x2_smaller_eew */

            case 18:
              if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1238; /* pred_indexed_oloadvnx16qi_x4_smaller_eew */

            case 19:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1040; /* pred_indexed_oloadvnx32qi_same_eew */

            case 20:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1202; /* pred_indexed_oloadvnx32qi_x2_smaller_eew */

            case 21:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 1042; /* pred_indexed_oloadvnx64qi_same_eew */

            case 22:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1044; /* pred_indexed_oloadvnx1hi_same_eew */

            case 23:
              if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1092; /* pred_indexed_oloadvnx1hi_x2_greater_eew */

            case 24:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1204; /* pred_indexed_oloadvnx1hi_x2_smaller_eew */

            case 25:
              if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1240; /* pred_indexed_oloadvnx1hi_x4_smaller_eew */

            case 26:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1046; /* pred_indexed_oloadvnx2hi_same_eew */

            case 27:
              if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1094; /* pred_indexed_oloadvnx2hi_x2_greater_eew */

            case 28:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1206; /* pred_indexed_oloadvnx2hi_x2_smaller_eew */

            case 29:
              if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1242; /* pred_indexed_oloadvnx2hi_x4_smaller_eew */

            case 30:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1048; /* pred_indexed_oloadvnx4hi_same_eew */

            case 31:
              if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1096; /* pred_indexed_oloadvnx4hi_x2_greater_eew */

            case 32:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1208; /* pred_indexed_oloadvnx4hi_x2_smaller_eew */

            case 33:
              if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1244; /* pred_indexed_oloadvnx4hi_x4_smaller_eew */

            case 34:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1050; /* pred_indexed_oloadvnx8hi_same_eew */

            case 35:
              if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1098; /* pred_indexed_oloadvnx8hi_x2_greater_eew */

            case 36:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1210; /* pred_indexed_oloadvnx8hi_x2_smaller_eew */

            case 37:
              if (!
#line 1525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1246; /* pred_indexed_oloadvnx8hi_x4_smaller_eew */

            case 38:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1052; /* pred_indexed_oloadvnx16hi_same_eew */

            case 39:
              if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1100; /* pred_indexed_oloadvnx16hi_x2_greater_eew */

            case 40:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1212; /* pred_indexed_oloadvnx16hi_x2_smaller_eew */

            case 41:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 1054; /* pred_indexed_oloadvnx32hi_same_eew */

            case 42:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 103 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 1102; /* pred_indexed_oloadvnx32hi_x2_greater_eew */

            case 43:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1056; /* pred_indexed_oloadvnx1si_same_eew */

            case 44:
              if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1104; /* pred_indexed_oloadvnx1si_x2_greater_eew */

            case 45:
              if (!
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1140; /* pred_indexed_oloadvnx1si_x4_greater_eew */

            case 46:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1214; /* pred_indexed_oloadvnx1si_x2_smaller_eew */

            case 47:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1058; /* pred_indexed_oloadvnx2si_same_eew */

            case 48:
              if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1106; /* pred_indexed_oloadvnx2si_x2_greater_eew */

            case 49:
              if (!
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1142; /* pred_indexed_oloadvnx2si_x4_greater_eew */

            case 50:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1216; /* pred_indexed_oloadvnx2si_x2_smaller_eew */

            case 51:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1060; /* pred_indexed_oloadvnx4si_same_eew */

            case 52:
              if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1108; /* pred_indexed_oloadvnx4si_x2_greater_eew */

            case 53:
              if (!
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1144; /* pred_indexed_oloadvnx4si_x4_greater_eew */

            case 54:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1218; /* pred_indexed_oloadvnx4si_x2_smaller_eew */

            case 55:
              if (!
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1062; /* pred_indexed_oloadvnx8si_same_eew */

            case 56:
              if (!
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1110; /* pred_indexed_oloadvnx8si_x2_greater_eew */

            case 57:
              if (!
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1146; /* pred_indexed_oloadvnx8si_x4_greater_eew */

            case 58:
              if (!
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1220; /* pred_indexed_oloadvnx8si_x2_smaller_eew */

            case 59:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 1064; /* pred_indexed_oloadvnx16si_same_eew */

            case 60:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 104 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 1112; /* pred_indexed_oloadvnx16si_x2_greater_eew */

            case 61:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 1148; /* pred_indexed_oloadvnx16si_x4_greater_eew */

            case 62:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1066; /* pred_indexed_oloadvnx1di_same_eew */

            case 63:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 105 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1114; /* pred_indexed_oloadvnx1di_x2_greater_eew */

            case 64:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1150; /* pred_indexed_oloadvnx1di_x4_greater_eew */

            case 65:
              if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 134 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1176; /* pred_indexed_oloadvnx1di_x8_greater_eew */

            case 66:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1068; /* pred_indexed_oloadvnx2di_same_eew */

            case 67:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 105 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1116; /* pred_indexed_oloadvnx2di_x2_greater_eew */

            case 68:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 120 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1152; /* pred_indexed_oloadvnx2di_x4_greater_eew */

            case 69:
              if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 134 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1178; /* pred_indexed_oloadvnx2di_x8_greater_eew */

            case 70:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1070; /* pred_indexed_oloadvnx4di_same_eew */

            case 71:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 106 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1118; /* pred_indexed_oloadvnx4di_x2_greater_eew */

            case 72:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 121 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1154; /* pred_indexed_oloadvnx4di_x4_greater_eew */

            case 73:
              if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1180; /* pred_indexed_oloadvnx4di_x8_greater_eew */

            case 74:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1072; /* pred_indexed_oloadvnx8di_same_eew */

            case 75:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 106 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1120; /* pred_indexed_oloadvnx8di_x2_greater_eew */

            case 76:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 121 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1156; /* pred_indexed_oloadvnx8di_x4_greater_eew */

            case 77:
              if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1182; /* pred_indexed_oloadvnx8di_x8_greater_eew */

            case 78:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1074; /* pred_indexed_oloadvnx1sf_same_eew */

            case 79:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1122; /* pred_indexed_oloadvnx1sf_x2_greater_eew */

            case 80:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 122 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1158; /* pred_indexed_oloadvnx1sf_x4_greater_eew */

            case 81:
              if (!(
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 146 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1222; /* pred_indexed_oloadvnx1sf_x2_smaller_eew */

            case 82:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1076; /* pred_indexed_oloadvnx2sf_same_eew */

            case 83:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 108 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1124; /* pred_indexed_oloadvnx2sf_x2_greater_eew */

            case 84:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 123 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1160; /* pred_indexed_oloadvnx2sf_x4_greater_eew */

            case 85:
              if (!(
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 147 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1224; /* pred_indexed_oloadvnx2sf_x2_smaller_eew */

            case 86:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1078; /* pred_indexed_oloadvnx4sf_same_eew */

            case 87:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1126; /* pred_indexed_oloadvnx4sf_x2_greater_eew */

            case 88:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 124 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1162; /* pred_indexed_oloadvnx4sf_x4_greater_eew */

            case 89:
              if (!(
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 148 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1226; /* pred_indexed_oloadvnx4sf_x2_smaller_eew */

            case 90:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1080; /* pred_indexed_oloadvnx8sf_same_eew */

            case 91:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1128; /* pred_indexed_oloadvnx8sf_x2_greater_eew */

            case 92:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 125 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1164; /* pred_indexed_oloadvnx8sf_x4_greater_eew */

            case 93:
              if (!(
#line 1504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 149 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 1228; /* pred_indexed_oloadvnx8sf_x2_smaller_eew */

            case 94:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return -1;
              return 1082; /* pred_indexed_oloadvnx16sf_same_eew */

            case 95:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 111 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return -1;
              return 1130; /* pred_indexed_oloadvnx16sf_x2_greater_eew */

            case 96:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 126 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return -1;
              return 1166; /* pred_indexed_oloadvnx16sf_x4_greater_eew */

            case 97:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1084; /* pred_indexed_oloadvnx1df_same_eew */

            case 98:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 112 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1132; /* pred_indexed_oloadvnx1df_x2_greater_eew */

            case 99:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 127 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1168; /* pred_indexed_oloadvnx1df_x4_greater_eew */

            case 100:
              if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 136 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1184; /* pred_indexed_oloadvnx1df_x8_greater_eew */

            case 101:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1086; /* pred_indexed_oloadvnx2df_same_eew */

            case 102:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 113 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1134; /* pred_indexed_oloadvnx2df_x2_greater_eew */

            case 103:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 128 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1170; /* pred_indexed_oloadvnx2df_x4_greater_eew */

            case 104:
              if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1186; /* pred_indexed_oloadvnx2df_x8_greater_eew */

            case 105:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1088; /* pred_indexed_oloadvnx4df_same_eew */

            case 106:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 114 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1136; /* pred_indexed_oloadvnx4df_x2_greater_eew */

            case 107:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 129 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1172; /* pred_indexed_oloadvnx4df_x4_greater_eew */

            case 108:
              if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 138 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1188; /* pred_indexed_oloadvnx4df_x8_greater_eew */

            case 109:
              if (!(
#line 1418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1090; /* pred_indexed_oloadvnx8df_same_eew */

            case 110:
              if (!(
#line 1440 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 115 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1138; /* pred_indexed_oloadvnx8df_x2_greater_eew */

            case 111:
              if (!(
#line 1461 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 130 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1174; /* pred_indexed_oloadvnx8df_x4_greater_eew */

            case 112:
              if (!(
#line 1482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 139 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 1190; /* pred_indexed_oloadvnx8df_x8_greater_eew */

            default:
              return -1;
            }

        case 72:
          return recog_22 (x1, insn, pnum_clobbers);

        default:
          return -1;
        }

    case 2:
      return recog_35 (x1, insn, pnum_clobbers);

    case 1:
      return recog_36 (x1, insn, pnum_clobbers);

    default:
      return -1;
    }
}

static int
recog_98 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case CONST_VECTOR:
    case REG:
    case SUBREG:
      return recog_92 (x1, insn, pnum_clobbers);

    case VEC_DUPLICATE:
      switch (pattern182 (x2))
        {
        case 0:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2174; /* pred_subvnx1qi_reverse_scalar */

        case 1:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2175; /* pred_subvnx2qi_reverse_scalar */

        case 2:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2176; /* pred_subvnx4qi_reverse_scalar */

        case 3:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2177; /* pred_subvnx8qi_reverse_scalar */

        case 4:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2178; /* pred_subvnx16qi_reverse_scalar */

        case 5:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2179; /* pred_subvnx32qi_reverse_scalar */

        case 6:
          if (!(
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2180; /* pred_subvnx64qi_reverse_scalar */

        case 7:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2181; /* pred_subvnx1hi_reverse_scalar */

        case 8:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2182; /* pred_subvnx2hi_reverse_scalar */

        case 9:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2183; /* pred_subvnx4hi_reverse_scalar */

        case 10:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2184; /* pred_subvnx8hi_reverse_scalar */

        case 11:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2185; /* pred_subvnx16hi_reverse_scalar */

        case 12:
          if (!(
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2186; /* pred_subvnx32hi_reverse_scalar */

        case 13:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2187; /* pred_subvnx1si_reverse_scalar */

        case 14:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2188; /* pred_subvnx2si_reverse_scalar */

        case 15:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2189; /* pred_subvnx4si_reverse_scalar */

        case 16:
          if (!
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2190; /* pred_subvnx8si_reverse_scalar */

        case 17:
          if (!(
#line 1798 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2191; /* pred_subvnx16si_reverse_scalar */

        case 18:
          if (!(
#line 2006 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2304; /* *pred_subvnx1di_reverse_scalar */

        case 19:
          if (!(
#line 2006 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2305; /* *pred_subvnx2di_reverse_scalar */

        case 20:
          if (!(
#line 2006 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2306; /* *pred_subvnx4di_reverse_scalar */

        case 21:
          if (!(
#line 2006 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2307; /* *pred_subvnx8di_reverse_scalar */

        case 22:
          if (!(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4708; /* pred_subvnx1sf_reverse_scalar */

        case 23:
          if (!(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4710; /* pred_subvnx2sf_reverse_scalar */

        case 24:
          if (!(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4712; /* pred_subvnx4sf_reverse_scalar */

        case 25:
          if (!(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4714; /* pred_subvnx8sf_reverse_scalar */

        case 26:
          if (!(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4716; /* pred_subvnx16sf_reverse_scalar */

        case 27:
          if (!(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4718; /* pred_subvnx1df_reverse_scalar */

        case 28:
          if (!(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4720; /* pred_subvnx2df_reverse_scalar */

        case 29:
          if (!(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4722; /* pred_subvnx4df_reverse_scalar */

        case 30:
          if (!(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4724; /* pred_subvnx8df_reverse_scalar */

        case 31:
          if (!(
#line 2028 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2308; /* *pred_subvnx1di_extended_reverse_scalar */

        case 32:
          if (!(
#line 2028 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2309; /* *pred_subvnx2di_extended_reverse_scalar */

        case 33:
          if (!(
#line 2028 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2310; /* *pred_subvnx4di_extended_reverse_scalar */

        case 34:
          if (!(
#line 2028 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2311; /* *pred_subvnx8di_extended_reverse_scalar */

        default:
          return -1;
        }

    case SIGN_EXTEND:
      switch (pattern195 (x2, SIGN_EXTEND))
        {
        case 0:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2845; /* pred_dual_widen_subsvnx1hi */

        case 1:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2851; /* pred_dual_widen_subsvnx2hi */

        case 2:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2857; /* pred_dual_widen_subsvnx4hi */

        case 3:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2863; /* pred_dual_widen_subsvnx8hi */

        case 4:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2869; /* pred_dual_widen_subsvnx16hi */

        case 5:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2875; /* pred_dual_widen_subsvnx32hi */

        case 6:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2881; /* pred_dual_widen_subsvnx1si */

        case 7:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2887; /* pred_dual_widen_subsvnx2si */

        case 8:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2893; /* pred_dual_widen_subsvnx4si */

        case 9:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2899; /* pred_dual_widen_subsvnx8si */

        case 10:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2905; /* pred_dual_widen_subsvnx16si */

        case 11:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2911; /* pred_dual_widen_subsvnx1di */

        case 12:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2917; /* pred_dual_widen_subsvnx2di */

        case 13:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2923; /* pred_dual_widen_subsvnx4di */

        case 14:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2929; /* pred_dual_widen_subsvnx8di */

        case 15:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2935; /* pred_dual_widen_subsvnx1hi_scalar */

        case 16:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2941; /* pred_dual_widen_subsvnx2hi_scalar */

        case 17:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2947; /* pred_dual_widen_subsvnx4hi_scalar */

        case 18:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2953; /* pred_dual_widen_subsvnx8hi_scalar */

        case 19:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2959; /* pred_dual_widen_subsvnx16hi_scalar */

        case 20:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2965; /* pred_dual_widen_subsvnx32hi_scalar */

        case 21:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2971; /* pred_dual_widen_subsvnx1si_scalar */

        case 22:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2977; /* pred_dual_widen_subsvnx2si_scalar */

        case 23:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2983; /* pred_dual_widen_subsvnx4si_scalar */

        case 24:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2989; /* pred_dual_widen_subsvnx8si_scalar */

        case 25:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2995; /* pred_dual_widen_subsvnx16si_scalar */

        case 26:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3001; /* pred_dual_widen_subsvnx1di_scalar */

        case 27:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3007; /* pred_dual_widen_subsvnx2di_scalar */

        case 28:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3013; /* pred_dual_widen_subsvnx4di_scalar */

        case 29:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3019; /* pred_dual_widen_subsvnx8di_scalar */

        default:
          return -1;
        }

    case ZERO_EXTEND:
      switch (pattern195 (x2, ZERO_EXTEND))
        {
        case 0:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2848; /* pred_dual_widen_subuvnx1hi */

        case 1:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2854; /* pred_dual_widen_subuvnx2hi */

        case 2:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2860; /* pred_dual_widen_subuvnx4hi */

        case 3:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2866; /* pred_dual_widen_subuvnx8hi */

        case 4:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2872; /* pred_dual_widen_subuvnx16hi */

        case 5:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2878; /* pred_dual_widen_subuvnx32hi */

        case 6:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2884; /* pred_dual_widen_subuvnx1si */

        case 7:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2890; /* pred_dual_widen_subuvnx2si */

        case 8:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2896; /* pred_dual_widen_subuvnx4si */

        case 9:
          if (!
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2902; /* pred_dual_widen_subuvnx8si */

        case 10:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2908; /* pred_dual_widen_subuvnx16si */

        case 11:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2914; /* pred_dual_widen_subuvnx1di */

        case 12:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2920; /* pred_dual_widen_subuvnx2di */

        case 13:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2926; /* pred_dual_widen_subuvnx4di */

        case 14:
          if (!(
#line 2961 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2932; /* pred_dual_widen_subuvnx8di */

        case 15:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2938; /* pred_dual_widen_subuvnx1hi_scalar */

        case 16:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2944; /* pred_dual_widen_subuvnx2hi_scalar */

        case 17:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2950; /* pred_dual_widen_subuvnx4hi_scalar */

        case 18:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2956; /* pred_dual_widen_subuvnx8hi_scalar */

        case 19:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2962; /* pred_dual_widen_subuvnx16hi_scalar */

        case 20:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2968; /* pred_dual_widen_subuvnx32hi_scalar */

        case 21:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2974; /* pred_dual_widen_subuvnx1si_scalar */

        case 22:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2980; /* pred_dual_widen_subuvnx2si_scalar */

        case 23:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2986; /* pred_dual_widen_subuvnx4si_scalar */

        case 24:
          if (!
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2992; /* pred_dual_widen_subuvnx8si_scalar */

        case 25:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2998; /* pred_dual_widen_subuvnx16si_scalar */

        case 26:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3004; /* pred_dual_widen_subuvnx1di_scalar */

        case 27:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3010; /* pred_dual_widen_subuvnx2di_scalar */

        case 28:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3016; /* pred_dual_widen_subuvnx4di_scalar */

        case 29:
          if (!(
#line 2984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3022; /* pred_dual_widen_subuvnx8di_scalar */

        default:
          return -1;
        }

    case MULT:
      return recog_91 (x1, insn, pnum_clobbers);

    case NEG:
      return recog_93 (x1, insn, pnum_clobbers);

    case FLOAT_EXTEND:
      switch (pattern191 (x2))
        {
        case 0:
          if (!(
#line 6093 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5051; /* pred_dual_widen_subvnx1df */

        case 1:
          if (!(
#line 6093 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5054; /* pred_dual_widen_subvnx2df */

        case 2:
          if (!(
#line 6093 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5057; /* pred_dual_widen_subvnx4df */

        case 3:
          if (!(
#line 6093 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5060; /* pred_dual_widen_subvnx8df */

        case 4:
          if (!(
#line 6116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5063; /* pred_dual_widen_subvnx1df_scalar */

        case 5:
          if (!(
#line 6116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5066; /* pred_dual_widen_subvnx2df_scalar */

        case 6:
          if (!(
#line 6116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5069; /* pred_dual_widen_subvnx4df_scalar */

        case 7:
          if (!(
#line 6116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5072; /* pred_dual_widen_subvnx8df_scalar */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_99 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  x8 = XEXP (x2, 2);
  operands[2] = x8;
  x9 = XEXP (x2, 1);
  x10 = XEXP (x9, 0);
  switch (GET_CODE (x10))
    {
    case REG:
    case SUBREG:
      operands[3] = x10;
      x11 = XEXP (x9, 1);
      switch (GET_CODE (x11))
        {
        case REG:
        case SUBREG:
          switch (pattern154 (x2))
            {
            case 0:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1495; /* pred_divvnx1qi */

            case 1:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1512; /* pred_divvnx2qi */

            case 2:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1529; /* pred_divvnx4qi */

            case 3:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1546; /* pred_divvnx8qi */

            case 4:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1563; /* pred_divvnx16qi */

            case 5:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1580; /* pred_divvnx32qi */

            case 6:
              if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 1597; /* pred_divvnx64qi */

            case 7:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1614; /* pred_divvnx1hi */

            case 8:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1631; /* pred_divvnx2hi */

            case 9:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1648; /* pred_divvnx4hi */

            case 10:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1665; /* pred_divvnx8hi */

            case 11:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1682; /* pred_divvnx16hi */

            case 12:
              if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 1699; /* pred_divvnx32hi */

            case 13:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1716; /* pred_divvnx1si */

            case 14:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1733; /* pred_divvnx2si */

            case 15:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1750; /* pred_divvnx4si */

            case 16:
              if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 1767; /* pred_divvnx8si */

            case 17:
              if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 1784; /* pred_divvnx16si */

            case 18:
              if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1801; /* pred_divvnx1di */

            case 19:
              if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1818; /* pred_divvnx2di */

            case 20:
              if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1835; /* pred_divvnx4di */

            case 21:
              if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 1852; /* pred_divvnx8di */

            case 22:
              if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 4605; /* pred_divvnx1sf */

            case 23:
              if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 4611; /* pred_divvnx2sf */

            case 24:
              if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 4617; /* pred_divvnx4sf */

            case 25:
              if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 4623; /* pred_divvnx8sf */

            case 26:
              if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return -1;
              return 4629; /* pred_divvnx16sf */

            case 27:
              if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 4635; /* pred_divvnx1df */

            case 28:
              if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 4641; /* pred_divvnx2df */

            case 29:
              if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 4647; /* pred_divvnx4df */

            case 30:
              if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 4653; /* pred_divvnx8df */

            default:
              return -1;
            }

        case VEC_DUPLICATE:
          switch (pattern269 (x2))
            {
            case 0:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2085; /* pred_divvnx1qi_scalar */

            case 1:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2090; /* pred_divvnx2qi_scalar */

            case 2:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2095; /* pred_divvnx4qi_scalar */

            case 3:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2100; /* pred_divvnx8qi_scalar */

            case 4:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2105; /* pred_divvnx16qi_scalar */

            case 5:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2110; /* pred_divvnx32qi_scalar */

            case 6:
              if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2115; /* pred_divvnx64qi_scalar */

            case 7:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2120; /* pred_divvnx1hi_scalar */

            case 8:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2125; /* pred_divvnx2hi_scalar */

            case 9:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2130; /* pred_divvnx4hi_scalar */

            case 10:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2135; /* pred_divvnx8hi_scalar */

            case 11:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2140; /* pred_divvnx16hi_scalar */

            case 12:
              if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2145; /* pred_divvnx32hi_scalar */

            case 13:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2150; /* pred_divvnx1si_scalar */

            case 14:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2155; /* pred_divvnx2si_scalar */

            case 15:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2160; /* pred_divvnx4si_scalar */

            case 16:
              if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2165; /* pred_divvnx8si_scalar */

            case 17:
              if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2170; /* pred_divvnx16si_scalar */

            case 18:
              if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2265; /* *pred_divvnx1di_scalar */

            case 19:
              if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2270; /* *pred_divvnx2di_scalar */

            case 20:
              if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2275; /* *pred_divvnx4di_scalar */

            case 21:
              if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2280; /* *pred_divvnx8di_scalar */

            case 22:
              if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 4691; /* pred_divvnx1sf_scalar */

            case 23:
              if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 4693; /* pred_divvnx2sf_scalar */

            case 24:
              if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 4695; /* pred_divvnx4sf_scalar */

            case 25:
              if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 4697; /* pred_divvnx8sf_scalar */

            case 26:
              if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return -1;
              return 4699; /* pred_divvnx16sf_scalar */

            case 27:
              if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 4701; /* pred_divvnx1df_scalar */

            case 28:
              if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 4703; /* pred_divvnx2df_scalar */

            case 29:
              if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 4705; /* pred_divvnx4df_scalar */

            case 30:
              if (!(
#line 5429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 4707; /* pred_divvnx8df_scalar */

            case 31:
              if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2285; /* *pred_divvnx1di_extended_scalar */

            case 32:
              if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2290; /* *pred_divvnx2di_extended_scalar */

            case 33:
              if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2295; /* *pred_divvnx4di_extended_scalar */

            case 34:
              if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2300; /* *pred_divvnx8di_extended_scalar */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x12 = XEXP (x10, 0);
      operands[4] = x12;
      x11 = XEXP (x9, 1);
      operands[3] = x11;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1SFmode:
          if (pattern155 (x2, E_VNx1SFmode, E_VNx1BImode, E_SFmode) != 0
              || !(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4709; /* pred_divvnx1sf_reverse_scalar */

        case E_VNx2SFmode:
          if (pattern155 (x2, E_VNx2SFmode, E_VNx2BImode, E_SFmode) != 0
              || !(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4711; /* pred_divvnx2sf_reverse_scalar */

        case E_VNx4SFmode:
          if (pattern155 (x2, E_VNx4SFmode, E_VNx4BImode, E_SFmode) != 0
              || !(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4713; /* pred_divvnx4sf_reverse_scalar */

        case E_VNx8SFmode:
          if (pattern155 (x2, E_VNx8SFmode, E_VNx8BImode, E_SFmode) != 0
              || !(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4715; /* pred_divvnx8sf_reverse_scalar */

        case E_VNx16SFmode:
          if (pattern155 (x2, E_VNx16SFmode, E_VNx16BImode, E_SFmode) != 0
              || !(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 4717; /* pred_divvnx16sf_reverse_scalar */

        case E_VNx1DFmode:
          if (pattern155 (x2, E_VNx1DFmode, E_VNx1BImode, E_DFmode) != 0
              || !(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4719; /* pred_divvnx1df_reverse_scalar */

        case E_VNx2DFmode:
          if (pattern155 (x2, E_VNx2DFmode, E_VNx2BImode, E_DFmode) != 0
              || !(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4721; /* pred_divvnx2df_reverse_scalar */

        case E_VNx4DFmode:
          if (pattern155 (x2, E_VNx4DFmode, E_VNx4BImode, E_DFmode) != 0
              || !(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4723; /* pred_divvnx4df_reverse_scalar */

        case E_VNx8DFmode:
          if (pattern155 (x2, E_VNx8DFmode, E_VNx8BImode, E_DFmode) != 0
              || !(
#line 5450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 4725; /* pred_divvnx8df_reverse_scalar */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_100 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern152 (x2))
    {
    case 0:
      if (vector_shift_operand (operands[4], E_VNx1QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1489; /* pred_lshrvnx1qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1858; /* pred_lshrvnx1qi_scalar */

    case 1:
      if (vector_shift_operand (operands[4], E_VNx2QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1506; /* pred_lshrvnx2qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1861; /* pred_lshrvnx2qi_scalar */

    case 2:
      if (vector_shift_operand (operands[4], E_VNx4QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1523; /* pred_lshrvnx4qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1864; /* pred_lshrvnx4qi_scalar */

    case 3:
      if (vector_shift_operand (operands[4], E_VNx8QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1540; /* pred_lshrvnx8qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1867; /* pred_lshrvnx8qi_scalar */

    case 4:
      if (vector_shift_operand (operands[4], E_VNx16QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1557; /* pred_lshrvnx16qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1870; /* pred_lshrvnx16qi_scalar */

    case 5:
      if (vector_shift_operand (operands[4], E_VNx32QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1574; /* pred_lshrvnx32qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1873; /* pred_lshrvnx32qi_scalar */

    case 6:
      if (vector_shift_operand (operands[4], E_VNx64QImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 1591; /* pred_lshrvnx64qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1876; /* pred_lshrvnx64qi_scalar */

    case 7:
      if (vector_shift_operand (operands[4], E_VNx1HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1608; /* pred_lshrvnx1hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1879; /* pred_lshrvnx1hi_scalar */

    case 8:
      if (vector_shift_operand (operands[4], E_VNx2HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1625; /* pred_lshrvnx2hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1882; /* pred_lshrvnx2hi_scalar */

    case 9:
      if (vector_shift_operand (operands[4], E_VNx4HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1642; /* pred_lshrvnx4hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1885; /* pred_lshrvnx4hi_scalar */

    case 10:
      if (vector_shift_operand (operands[4], E_VNx8HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1659; /* pred_lshrvnx8hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1888; /* pred_lshrvnx8hi_scalar */

    case 11:
      if (vector_shift_operand (operands[4], E_VNx16HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1676; /* pred_lshrvnx16hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1891; /* pred_lshrvnx16hi_scalar */

    case 12:
      if (vector_shift_operand (operands[4], E_VNx32HImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 1693; /* pred_lshrvnx32hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1894; /* pred_lshrvnx32hi_scalar */

    case 13:
      if (vector_shift_operand (operands[4], E_VNx1SImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1710; /* pred_lshrvnx1si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1897; /* pred_lshrvnx1si_scalar */

    case 14:
      if (vector_shift_operand (operands[4], E_VNx2SImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1727; /* pred_lshrvnx2si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1900; /* pred_lshrvnx2si_scalar */

    case 15:
      if (vector_shift_operand (operands[4], E_VNx4SImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1744; /* pred_lshrvnx4si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1903; /* pred_lshrvnx4si_scalar */

    case 16:
      if (vector_shift_operand (operands[4], E_VNx8SImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1761; /* pred_lshrvnx8si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1906; /* pred_lshrvnx8si_scalar */

    case 17:
      if (vector_shift_operand (operands[4], E_VNx16SImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 1778; /* pred_lshrvnx16si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1909; /* pred_lshrvnx16si_scalar */

    case 18:
      if (vector_shift_operand (operands[4], E_VNx1DImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 1795; /* pred_lshrvnx1di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1912; /* pred_lshrvnx1di_scalar */

    case 19:
      if (vector_shift_operand (operands[4], E_VNx2DImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 1812; /* pred_lshrvnx2di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1915; /* pred_lshrvnx2di_scalar */

    case 20:
      if (vector_shift_operand (operands[4], E_VNx4DImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 1829; /* pred_lshrvnx4di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1918; /* pred_lshrvnx4di_scalar */

    case 21:
      if (vector_shift_operand (operands[4], E_VNx8DImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 1846; /* pred_lshrvnx8di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1921; /* pred_lshrvnx8di_scalar */

    default:
      return -1;
    }
}

static int
recog_101 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern152 (x2))
    {
    case 0:
      if (vector_shift_operand (operands[4], E_VNx1QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1488; /* pred_ashrvnx1qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1857; /* pred_ashrvnx1qi_scalar */

    case 1:
      if (vector_shift_operand (operands[4], E_VNx2QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1505; /* pred_ashrvnx2qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1860; /* pred_ashrvnx2qi_scalar */

    case 2:
      if (vector_shift_operand (operands[4], E_VNx4QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1522; /* pred_ashrvnx4qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1863; /* pred_ashrvnx4qi_scalar */

    case 3:
      if (vector_shift_operand (operands[4], E_VNx8QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1539; /* pred_ashrvnx8qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1866; /* pred_ashrvnx8qi_scalar */

    case 4:
      if (vector_shift_operand (operands[4], E_VNx16QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1556; /* pred_ashrvnx16qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1869; /* pred_ashrvnx16qi_scalar */

    case 5:
      if (vector_shift_operand (operands[4], E_VNx32QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1573; /* pred_ashrvnx32qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1872; /* pred_ashrvnx32qi_scalar */

    case 6:
      if (vector_shift_operand (operands[4], E_VNx64QImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 1590; /* pred_ashrvnx64qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1875; /* pred_ashrvnx64qi_scalar */

    case 7:
      if (vector_shift_operand (operands[4], E_VNx1HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1607; /* pred_ashrvnx1hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1878; /* pred_ashrvnx1hi_scalar */

    case 8:
      if (vector_shift_operand (operands[4], E_VNx2HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1624; /* pred_ashrvnx2hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1881; /* pred_ashrvnx2hi_scalar */

    case 9:
      if (vector_shift_operand (operands[4], E_VNx4HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1641; /* pred_ashrvnx4hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1884; /* pred_ashrvnx4hi_scalar */

    case 10:
      if (vector_shift_operand (operands[4], E_VNx8HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1658; /* pred_ashrvnx8hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1887; /* pred_ashrvnx8hi_scalar */

    case 11:
      if (vector_shift_operand (operands[4], E_VNx16HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1675; /* pred_ashrvnx16hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1890; /* pred_ashrvnx16hi_scalar */

    case 12:
      if (vector_shift_operand (operands[4], E_VNx32HImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 1692; /* pred_ashrvnx32hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1893; /* pred_ashrvnx32hi_scalar */

    case 13:
      if (vector_shift_operand (operands[4], E_VNx1SImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1709; /* pred_ashrvnx1si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1896; /* pred_ashrvnx1si_scalar */

    case 14:
      if (vector_shift_operand (operands[4], E_VNx2SImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1726; /* pred_ashrvnx2si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1899; /* pred_ashrvnx2si_scalar */

    case 15:
      if (vector_shift_operand (operands[4], E_VNx4SImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1743; /* pred_ashrvnx4si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1902; /* pred_ashrvnx4si_scalar */

    case 16:
      if (vector_shift_operand (operands[4], E_VNx8SImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1760; /* pred_ashrvnx8si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1905; /* pred_ashrvnx8si_scalar */

    case 17:
      if (vector_shift_operand (operands[4], E_VNx16SImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 1777; /* pred_ashrvnx16si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1908; /* pred_ashrvnx16si_scalar */

    case 18:
      if (vector_shift_operand (operands[4], E_VNx1DImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 1794; /* pred_ashrvnx1di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1911; /* pred_ashrvnx1di_scalar */

    case 19:
      if (vector_shift_operand (operands[4], E_VNx2DImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 1811; /* pred_ashrvnx2di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1914; /* pred_ashrvnx2di_scalar */

    case 20:
      if (vector_shift_operand (operands[4], E_VNx4DImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 1828; /* pred_ashrvnx4di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1917; /* pred_ashrvnx4di_scalar */

    case 21:
      if (vector_shift_operand (operands[4], E_VNx8DImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 1845; /* pred_ashrvnx8di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1920; /* pred_ashrvnx8di_scalar */

    default:
      return -1;
    }
}

static int
recog_102 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern152 (x2))
    {
    case 0:
      if (vector_shift_operand (operands[4], E_VNx1QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1487; /* pred_ashlvnx1qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1856; /* pred_ashlvnx1qi_scalar */

    case 1:
      if (vector_shift_operand (operands[4], E_VNx2QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1504; /* pred_ashlvnx2qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1859; /* pred_ashlvnx2qi_scalar */

    case 2:
      if (vector_shift_operand (operands[4], E_VNx4QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1521; /* pred_ashlvnx4qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1862; /* pred_ashlvnx4qi_scalar */

    case 3:
      if (vector_shift_operand (operands[4], E_VNx8QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1538; /* pred_ashlvnx8qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1865; /* pred_ashlvnx8qi_scalar */

    case 4:
      if (vector_shift_operand (operands[4], E_VNx16QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1555; /* pred_ashlvnx16qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1868; /* pred_ashlvnx16qi_scalar */

    case 5:
      if (vector_shift_operand (operands[4], E_VNx32QImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1572; /* pred_ashlvnx32qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1871; /* pred_ashlvnx32qi_scalar */

    case 6:
      if (vector_shift_operand (operands[4], E_VNx64QImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 1589; /* pred_ashlvnx64qi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1874; /* pred_ashlvnx64qi_scalar */

    case 7:
      if (vector_shift_operand (operands[4], E_VNx1HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1606; /* pred_ashlvnx1hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1877; /* pred_ashlvnx1hi_scalar */

    case 8:
      if (vector_shift_operand (operands[4], E_VNx2HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1623; /* pred_ashlvnx2hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1880; /* pred_ashlvnx2hi_scalar */

    case 9:
      if (vector_shift_operand (operands[4], E_VNx4HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1640; /* pred_ashlvnx4hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1883; /* pred_ashlvnx4hi_scalar */

    case 10:
      if (vector_shift_operand (operands[4], E_VNx8HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1657; /* pred_ashlvnx8hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1886; /* pred_ashlvnx8hi_scalar */

    case 11:
      if (vector_shift_operand (operands[4], E_VNx16HImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1674; /* pred_ashlvnx16hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1889; /* pred_ashlvnx16hi_scalar */

    case 12:
      if (vector_shift_operand (operands[4], E_VNx32HImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 1691; /* pred_ashlvnx32hi */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1892; /* pred_ashlvnx32hi_scalar */

    case 13:
      if (vector_shift_operand (operands[4], E_VNx1SImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1708; /* pred_ashlvnx1si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1895; /* pred_ashlvnx1si_scalar */

    case 14:
      if (vector_shift_operand (operands[4], E_VNx2SImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1725; /* pred_ashlvnx2si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1898; /* pred_ashlvnx2si_scalar */

    case 15:
      if (vector_shift_operand (operands[4], E_VNx4SImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1742; /* pred_ashlvnx4si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1901; /* pred_ashlvnx4si_scalar */

    case 16:
      if (vector_shift_operand (operands[4], E_VNx8SImode)
          && 
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 1759; /* pred_ashlvnx8si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1904; /* pred_ashlvnx8si_scalar */

    case 17:
      if (vector_shift_operand (operands[4], E_VNx16SImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 1776; /* pred_ashlvnx16si */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1907; /* pred_ashlvnx16si_scalar */

    case 18:
      if (vector_shift_operand (operands[4], E_VNx1DImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 1793; /* pred_ashlvnx1di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1910; /* pred_ashlvnx1di_scalar */

    case 19:
      if (vector_shift_operand (operands[4], E_VNx2DImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 1810; /* pred_ashlvnx2di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1913; /* pred_ashlvnx2di_scalar */

    case 20:
      if (vector_shift_operand (operands[4], E_VNx4DImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 1827; /* pred_ashlvnx4di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1916; /* pred_ashlvnx4di_scalar */

    case 21:
      if (vector_shift_operand (operands[4], E_VNx8DImode)
          && (
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 1844; /* pred_ashlvnx8di */
      if (!pmode_reg_or_uimm5_operand (operands[4], E_VOIDmode)
          || !(
#line 1734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1919; /* pred_ashlvnx8di_scalar */

    default:
      return -1;
    }
}

static int
recog_103 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[4] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[5] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[6] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[7] = x7;
  x8 = XEXP (x2, 1);
  x9 = XEXP (x8, 0);
  operands[3] = x9;
  x10 = XEXP (x2, 2);
  operands[2] = x10;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      if (pattern238 (x2, E_VNx1QImode, E_VNx1BImode, E_QImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 933; /* *pred_broadcastvnx1qi */
      break;

    case E_VNx2QImode:
      if (pattern238 (x2, E_VNx2QImode, E_VNx2BImode, E_QImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 934; /* *pred_broadcastvnx2qi */
      break;

    case E_VNx4QImode:
      if (pattern238 (x2, E_VNx4QImode, E_VNx4BImode, E_QImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 935; /* *pred_broadcastvnx4qi */
      break;

    case E_VNx8QImode:
      if (pattern238 (x2, E_VNx8QImode, E_VNx8BImode, E_QImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 936; /* *pred_broadcastvnx8qi */
      break;

    case E_VNx16QImode:
      if (pattern238 (x2, E_VNx16QImode, E_VNx16BImode, E_QImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 937; /* *pred_broadcastvnx16qi */
      break;

    case E_VNx32QImode:
      if (pattern238 (x2, E_VNx32QImode, E_VNx32BImode, E_QImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 938; /* *pred_broadcastvnx32qi */
      break;

    case E_VNx64QImode:
      if (pattern238 (x2, E_VNx64QImode, E_VNx64BImode, E_QImode) == 0
          && (
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 939; /* *pred_broadcastvnx64qi */
      break;

    case E_VNx1HImode:
      if (pattern238 (x2, E_VNx1HImode, E_VNx1BImode, E_HImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 940; /* *pred_broadcastvnx1hi */
      break;

    case E_VNx2HImode:
      if (pattern238 (x2, E_VNx2HImode, E_VNx2BImode, E_HImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 941; /* *pred_broadcastvnx2hi */
      break;

    case E_VNx4HImode:
      if (pattern238 (x2, E_VNx4HImode, E_VNx4BImode, E_HImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 942; /* *pred_broadcastvnx4hi */
      break;

    case E_VNx8HImode:
      if (pattern238 (x2, E_VNx8HImode, E_VNx8BImode, E_HImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 943; /* *pred_broadcastvnx8hi */
      break;

    case E_VNx16HImode:
      if (pattern238 (x2, E_VNx16HImode, E_VNx16BImode, E_HImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 944; /* *pred_broadcastvnx16hi */
      break;

    case E_VNx32HImode:
      if (pattern238 (x2, E_VNx32HImode, E_VNx32BImode, E_HImode) == 0
          && (
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 945; /* *pred_broadcastvnx32hi */
      break;

    case E_VNx1SImode:
      if (pattern238 (x2, E_VNx1SImode, E_VNx1BImode, E_SImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 946; /* *pred_broadcastvnx1si */
      break;

    case E_VNx2SImode:
      if (pattern238 (x2, E_VNx2SImode, E_VNx2BImode, E_SImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 947; /* *pred_broadcastvnx2si */
      break;

    case E_VNx4SImode:
      if (pattern238 (x2, E_VNx4SImode, E_VNx4BImode, E_SImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 948; /* *pred_broadcastvnx4si */
      break;

    case E_VNx8SImode:
      if (pattern238 (x2, E_VNx8SImode, E_VNx8BImode, E_SImode) == 0
          && 
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return 949; /* *pred_broadcastvnx8si */
      break;

    case E_VNx16SImode:
      if (pattern238 (x2, E_VNx16SImode, E_VNx16BImode, E_SImode) == 0
          && (
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 950; /* *pred_broadcastvnx16si */
      break;

    case E_VNx1DImode:
      if (pattern238 (x2, E_VNx1DImode, E_VNx1BImode, E_DImode) == 0
          && (
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 951; /* *pred_broadcastvnx1di */
      break;

    case E_VNx2DImode:
      if (pattern238 (x2, E_VNx2DImode, E_VNx2BImode, E_DImode) == 0
          && (
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 952; /* *pred_broadcastvnx2di */
      break;

    case E_VNx4DImode:
      if (pattern238 (x2, E_VNx4DImode, E_VNx4BImode, E_DImode) == 0
          && (
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 953; /* *pred_broadcastvnx4di */
      break;

    case E_VNx8DImode:
      if (pattern238 (x2, E_VNx8DImode, E_VNx8BImode, E_DImode) == 0
          && (
#line 1260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return 954; /* *pred_broadcastvnx8di */
      break;

    case E_VNx1SFmode:
      if (pattern238 (x2, E_VNx1SFmode, E_VNx1BImode, E_SFmode) == 0
          && (
#line 1314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 955; /* *pred_broadcastvnx1sf */
      break;

    case E_VNx2SFmode:
      if (pattern238 (x2, E_VNx2SFmode, E_VNx2BImode, E_SFmode) == 0
          && (
#line 1314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 956; /* *pred_broadcastvnx2sf */
      break;

    case E_VNx4SFmode:
      if (pattern238 (x2, E_VNx4SFmode, E_VNx4BImode, E_SFmode) == 0
          && (
#line 1314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 957; /* *pred_broadcastvnx4sf */
      break;

    case E_VNx8SFmode:
      if (pattern238 (x2, E_VNx8SFmode, E_VNx8BImode, E_SFmode) == 0
          && (
#line 1314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return 958; /* *pred_broadcastvnx8sf */
      break;

    case E_VNx16SFmode:
      if (pattern238 (x2, E_VNx16SFmode, E_VNx16BImode, E_SFmode) == 0
          && (
#line 1314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return 959; /* *pred_broadcastvnx16sf */
      break;

    case E_VNx1DFmode:
      if (pattern238 (x2, E_VNx1DFmode, E_VNx1BImode, E_DFmode) == 0
          && (
#line 1314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 960; /* *pred_broadcastvnx1df */
      break;

    case E_VNx2DFmode:
      if (pattern238 (x2, E_VNx2DFmode, E_VNx2BImode, E_DFmode) == 0
          && (
#line 1314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 961; /* *pred_broadcastvnx2df */
      break;

    case E_VNx4DFmode:
      if (pattern238 (x2, E_VNx4DFmode, E_VNx4BImode, E_DFmode) == 0
          && (
#line 1314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 962; /* *pred_broadcastvnx4df */
      break;

    case E_VNx8DFmode:
      if (pattern238 (x2, E_VNx8DFmode, E_VNx8BImode, E_DFmode) == 0
          && (
#line 1314 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return 963; /* *pred_broadcastvnx8df */
      break;

    default:
      break;
    }
  if (GET_CODE (x9) != SIGN_EXTEND
      || GET_MODE (x9) != E_DImode)
    return -1;
  x11 = XEXP (x9, 0);
  operands[3] = x11;
  if (!register_operand (operands[3], E_SImode))
    return -1;
  operands[2] = x10;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1DImode:
      if (pattern284 (x2, E_VNx1DImode, E_VNx1BImode) != 0
          || !(
#line 1342 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 964; /* *pred_broadcastvnx1di_extended_scalar */

    case E_VNx2DImode:
      if (pattern284 (x2, E_VNx2DImode, E_VNx2BImode) != 0
          || !(
#line 1342 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 965; /* *pred_broadcastvnx2di_extended_scalar */

    case E_VNx4DImode:
      if (pattern284 (x2, E_VNx4DImode, E_VNx4BImode) != 0
          || !(
#line 1342 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 966; /* *pred_broadcastvnx4di_extended_scalar */

    case E_VNx8DImode:
      if (pattern284 (x2, E_VNx8DImode, E_VNx8BImode) != 0
          || !(
#line 1342 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 967; /* *pred_broadcastvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_104 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  x8 = XEXP (x2, 1);
  x9 = XEXP (x8, 0);
  operands[3] = x9;
  x10 = XEXP (x2, 2);
  operands[2] = x10;
  x11 = XEXP (x8, 1);
  switch (GET_CODE (x11))
    {
    case CONST_VECTOR:
    case REG:
    case SUBREG:
      operands[4] = x11;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          if (pattern278 (x2, E_VNx1QImode, E_VNx1BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3280; /* pred_sssubvnx1qi */

        case E_VNx2QImode:
          if (pattern278 (x2, E_VNx2QImode, E_VNx2BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3284; /* pred_sssubvnx2qi */

        case E_VNx4QImode:
          if (pattern278 (x2, E_VNx4QImode, E_VNx4BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3288; /* pred_sssubvnx4qi */

        case E_VNx8QImode:
          if (pattern278 (x2, E_VNx8QImode, E_VNx8BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3292; /* pred_sssubvnx8qi */

        case E_VNx16QImode:
          if (pattern278 (x2, E_VNx16QImode, E_VNx16BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3296; /* pred_sssubvnx16qi */

        case E_VNx32QImode:
          if (pattern278 (x2, E_VNx32QImode, E_VNx32BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3300; /* pred_sssubvnx32qi */

        case E_VNx64QImode:
          if (pattern278 (x2, E_VNx64QImode, E_VNx64BImode) != 0
              || !(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3304; /* pred_sssubvnx64qi */

        case E_VNx1HImode:
          if (pattern278 (x2, E_VNx1HImode, E_VNx1BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3308; /* pred_sssubvnx1hi */

        case E_VNx2HImode:
          if (pattern278 (x2, E_VNx2HImode, E_VNx2BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3312; /* pred_sssubvnx2hi */

        case E_VNx4HImode:
          if (pattern278 (x2, E_VNx4HImode, E_VNx4BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3316; /* pred_sssubvnx4hi */

        case E_VNx8HImode:
          if (pattern278 (x2, E_VNx8HImode, E_VNx8BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3320; /* pred_sssubvnx8hi */

        case E_VNx16HImode:
          if (pattern278 (x2, E_VNx16HImode, E_VNx16BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3324; /* pred_sssubvnx16hi */

        case E_VNx32HImode:
          if (pattern278 (x2, E_VNx32HImode, E_VNx32BImode) != 0
              || !(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3328; /* pred_sssubvnx32hi */

        case E_VNx1SImode:
          if (pattern278 (x2, E_VNx1SImode, E_VNx1BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3332; /* pred_sssubvnx1si */

        case E_VNx2SImode:
          if (pattern278 (x2, E_VNx2SImode, E_VNx2BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3336; /* pred_sssubvnx2si */

        case E_VNx4SImode:
          if (pattern278 (x2, E_VNx4SImode, E_VNx4BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3340; /* pred_sssubvnx4si */

        case E_VNx8SImode:
          if (pattern278 (x2, E_VNx8SImode, E_VNx8BImode) != 0
              || !
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3344; /* pred_sssubvnx8si */

        case E_VNx16SImode:
          if (pattern278 (x2, E_VNx16SImode, E_VNx16BImode) != 0
              || !(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3348; /* pred_sssubvnx16si */

        case E_VNx1DImode:
          if (pattern278 (x2, E_VNx1DImode, E_VNx1BImode) != 0
              || !(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3352; /* pred_sssubvnx1di */

        case E_VNx2DImode:
          if (pattern278 (x2, E_VNx2DImode, E_VNx2BImode) != 0
              || !(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3356; /* pred_sssubvnx2di */

        case E_VNx4DImode:
          if (pattern278 (x2, E_VNx4DImode, E_VNx4BImode) != 0
              || !(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3360; /* pred_sssubvnx4di */

        case E_VNx8DImode:
          if (pattern278 (x2, E_VNx8DImode, E_VNx8BImode) != 0
              || !(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3364; /* pred_sssubvnx8di */

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      switch (pattern253 (x2))
        {
        case 0:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3403; /* pred_sssubvnx1qi_scalar */

        case 1:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3405; /* pred_sssubvnx2qi_scalar */

        case 2:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3407; /* pred_sssubvnx4qi_scalar */

        case 3:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3409; /* pred_sssubvnx8qi_scalar */

        case 4:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3411; /* pred_sssubvnx16qi_scalar */

        case 5:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3413; /* pred_sssubvnx32qi_scalar */

        case 6:
          if (!(
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3415; /* pred_sssubvnx64qi_scalar */

        case 7:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3417; /* pred_sssubvnx1hi_scalar */

        case 8:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3419; /* pred_sssubvnx2hi_scalar */

        case 9:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3421; /* pred_sssubvnx4hi_scalar */

        case 10:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3423; /* pred_sssubvnx8hi_scalar */

        case 11:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3425; /* pred_sssubvnx16hi_scalar */

        case 12:
          if (!(
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3427; /* pred_sssubvnx32hi_scalar */

        case 13:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3429; /* pred_sssubvnx1si_scalar */

        case 14:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3431; /* pred_sssubvnx2si_scalar */

        case 15:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3433; /* pred_sssubvnx4si_scalar */

        case 16:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3435; /* pred_sssubvnx8si_scalar */

        case 17:
          if (!(
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3437; /* pred_sssubvnx16si_scalar */

        case 18:
          if (!(
#line 3388 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3455; /* *pred_sssubvnx1di_scalar */

        case 19:
          if (!(
#line 3388 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3457; /* *pred_sssubvnx2di_scalar */

        case 20:
          if (!(
#line 3388 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3459; /* *pred_sssubvnx4di_scalar */

        case 21:
          if (!(
#line 3388 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3461; /* *pred_sssubvnx8di_scalar */

        case 22:
          if (!(
#line 3410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3463; /* *pred_sssubvnx1di_extended_scalar */

        case 23:
          if (!(
#line 3410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3465; /* *pred_sssubvnx2di_extended_scalar */

        case 24:
          if (!(
#line 3410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3467; /* *pred_sssubvnx4di_extended_scalar */

        case 25:
          if (!(
#line 3410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3469; /* *pred_sssubvnx8di_extended_scalar */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_105 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern157 (x2))
    {
    case 0:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1490; /* pred_smaxvnx1qi */

    case 1:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1507; /* pred_smaxvnx2qi */

    case 2:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1524; /* pred_smaxvnx4qi */

    case 3:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1541; /* pred_smaxvnx8qi */

    case 4:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1558; /* pred_smaxvnx16qi */

    case 5:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1575; /* pred_smaxvnx32qi */

    case 6:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1592; /* pred_smaxvnx64qi */

    case 7:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1609; /* pred_smaxvnx1hi */

    case 8:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1626; /* pred_smaxvnx2hi */

    case 9:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1643; /* pred_smaxvnx4hi */

    case 10:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1660; /* pred_smaxvnx8hi */

    case 11:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1677; /* pred_smaxvnx16hi */

    case 12:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1694; /* pred_smaxvnx32hi */

    case 13:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1711; /* pred_smaxvnx1si */

    case 14:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1728; /* pred_smaxvnx2si */

    case 15:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1745; /* pred_smaxvnx4si */

    case 16:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1762; /* pred_smaxvnx8si */

    case 17:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1779; /* pred_smaxvnx16si */

    case 18:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1796; /* pred_smaxvnx1di */

    case 19:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1813; /* pred_smaxvnx2di */

    case 20:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1830; /* pred_smaxvnx4di */

    case 21:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1847; /* pred_smaxvnx8di */

    case 22:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4602; /* pred_smaxvnx1sf */

    case 23:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4608; /* pred_smaxvnx2sf */

    case 24:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4614; /* pred_smaxvnx4sf */

    case 25:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4620; /* pred_smaxvnx8sf */

    case 26:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 4626; /* pred_smaxvnx16sf */

    case 27:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4632; /* pred_smaxvnx1df */

    case 28:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4638; /* pred_smaxvnx2df */

    case 29:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4644; /* pred_smaxvnx4df */

    case 30:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4650; /* pred_smaxvnx8df */

    case 31:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1926; /* pred_smaxvnx1qi_scalar */

    case 32:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1935; /* pred_smaxvnx2qi_scalar */

    case 33:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1944; /* pred_smaxvnx4qi_scalar */

    case 34:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1953; /* pred_smaxvnx8qi_scalar */

    case 35:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1962; /* pred_smaxvnx16qi_scalar */

    case 36:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1971; /* pred_smaxvnx32qi_scalar */

    case 37:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1980; /* pred_smaxvnx64qi_scalar */

    case 38:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1989; /* pred_smaxvnx1hi_scalar */

    case 39:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1998; /* pred_smaxvnx2hi_scalar */

    case 40:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2007; /* pred_smaxvnx4hi_scalar */

    case 41:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2016; /* pred_smaxvnx8hi_scalar */

    case 42:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2025; /* pred_smaxvnx16hi_scalar */

    case 43:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2034; /* pred_smaxvnx32hi_scalar */

    case 44:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2043; /* pred_smaxvnx1si_scalar */

    case 45:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2052; /* pred_smaxvnx2si_scalar */

    case 46:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2061; /* pred_smaxvnx4si_scalar */

    case 47:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2070; /* pred_smaxvnx8si_scalar */

    case 48:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2079; /* pred_smaxvnx16si_scalar */

    case 49:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2196; /* *pred_smaxvnx1di_scalar */

    case 50:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2205; /* *pred_smaxvnx2di_scalar */

    case 51:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2214; /* *pred_smaxvnx4di_scalar */

    case 52:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2223; /* *pred_smaxvnx8di_scalar */

    case 53:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4656; /* pred_smaxvnx1sf_scalar */

    case 54:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4660; /* pred_smaxvnx2sf_scalar */

    case 55:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4664; /* pred_smaxvnx4sf_scalar */

    case 56:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4668; /* pred_smaxvnx8sf_scalar */

    case 57:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 4672; /* pred_smaxvnx16sf_scalar */

    case 58:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4676; /* pred_smaxvnx1df_scalar */

    case 59:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4680; /* pred_smaxvnx2df_scalar */

    case 60:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4684; /* pred_smaxvnx4df_scalar */

    case 61:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4688; /* pred_smaxvnx8df_scalar */

    case 62:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2232; /* *pred_smaxvnx1di_extended_scalar */

    case 63:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2241; /* *pred_smaxvnx2di_extended_scalar */

    case 64:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2250; /* *pred_smaxvnx4di_extended_scalar */

    case 65:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2259; /* *pred_smaxvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_106 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern157 (x2))
    {
    case 0:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1492; /* pred_sminvnx1qi */

    case 1:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1509; /* pred_sminvnx2qi */

    case 2:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1526; /* pred_sminvnx4qi */

    case 3:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1543; /* pred_sminvnx8qi */

    case 4:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1560; /* pred_sminvnx16qi */

    case 5:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1577; /* pred_sminvnx32qi */

    case 6:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1594; /* pred_sminvnx64qi */

    case 7:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1611; /* pred_sminvnx1hi */

    case 8:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1628; /* pred_sminvnx2hi */

    case 9:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1645; /* pred_sminvnx4hi */

    case 10:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1662; /* pred_sminvnx8hi */

    case 11:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1679; /* pred_sminvnx16hi */

    case 12:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1696; /* pred_sminvnx32hi */

    case 13:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1713; /* pred_sminvnx1si */

    case 14:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1730; /* pred_sminvnx2si */

    case 15:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1747; /* pred_sminvnx4si */

    case 16:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1764; /* pred_sminvnx8si */

    case 17:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1781; /* pred_sminvnx16si */

    case 18:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1798; /* pred_sminvnx1di */

    case 19:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1815; /* pred_sminvnx2di */

    case 20:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1832; /* pred_sminvnx4di */

    case 21:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1849; /* pred_sminvnx8di */

    case 22:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4603; /* pred_sminvnx1sf */

    case 23:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4609; /* pred_sminvnx2sf */

    case 24:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4615; /* pred_sminvnx4sf */

    case 25:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4621; /* pred_sminvnx8sf */

    case 26:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 4627; /* pred_sminvnx16sf */

    case 27:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4633; /* pred_sminvnx1df */

    case 28:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4639; /* pred_sminvnx2df */

    case 29:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4645; /* pred_sminvnx4df */

    case 30:
      if (!(
#line 5387 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4651; /* pred_sminvnx8df */

    case 31:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1928; /* pred_sminvnx1qi_scalar */

    case 32:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1937; /* pred_sminvnx2qi_scalar */

    case 33:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1946; /* pred_sminvnx4qi_scalar */

    case 34:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1955; /* pred_sminvnx8qi_scalar */

    case 35:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1964; /* pred_sminvnx16qi_scalar */

    case 36:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1973; /* pred_sminvnx32qi_scalar */

    case 37:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1982; /* pred_sminvnx64qi_scalar */

    case 38:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1991; /* pred_sminvnx1hi_scalar */

    case 39:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2000; /* pred_sminvnx2hi_scalar */

    case 40:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2009; /* pred_sminvnx4hi_scalar */

    case 41:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2018; /* pred_sminvnx8hi_scalar */

    case 42:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2027; /* pred_sminvnx16hi_scalar */

    case 43:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2036; /* pred_sminvnx32hi_scalar */

    case 44:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2045; /* pred_sminvnx1si_scalar */

    case 45:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2054; /* pred_sminvnx2si_scalar */

    case 46:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2063; /* pred_sminvnx4si_scalar */

    case 47:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2072; /* pred_sminvnx8si_scalar */

    case 48:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2081; /* pred_sminvnx16si_scalar */

    case 49:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2198; /* *pred_sminvnx1di_scalar */

    case 50:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2207; /* *pred_sminvnx2di_scalar */

    case 51:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2216; /* *pred_sminvnx4di_scalar */

    case 52:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2225; /* *pred_sminvnx8di_scalar */

    case 53:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4657; /* pred_sminvnx1sf_scalar */

    case 54:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4661; /* pred_sminvnx2sf_scalar */

    case 55:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4665; /* pred_sminvnx4sf_scalar */

    case 56:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4669; /* pred_sminvnx8sf_scalar */

    case 57:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 4673; /* pred_sminvnx16sf_scalar */

    case 58:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4677; /* pred_sminvnx1df_scalar */

    case 59:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4681; /* pred_sminvnx2df_scalar */

    case 60:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4685; /* pred_sminvnx4df_scalar */

    case 61:
      if (!(
#line 5408 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 4689; /* pred_sminvnx8df_scalar */

    case 62:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2234; /* *pred_sminvnx1di_extended_scalar */

    case 63:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2243; /* *pred_sminvnx2di_extended_scalar */

    case 64:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2252; /* *pred_sminvnx4di_extended_scalar */

    case 65:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2261; /* *pred_sminvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_107 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[4] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[5] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[6] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[7] = x7;
  x8 = XEXP (x2, 1);
  x9 = XEXP (x8, 0);
  operands[3] = x9;
  x10 = XEXP (x2, 2);
  operands[2] = x10;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      if (pattern150 (x2, E_VNx1QImode, E_VNx1BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2744; /* pred_negvnx1qi */

    case E_VNx2QImode:
      if (pattern150 (x2, E_VNx2QImode, E_VNx2BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2746; /* pred_negvnx2qi */

    case E_VNx4QImode:
      if (pattern150 (x2, E_VNx4QImode, E_VNx4BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2748; /* pred_negvnx4qi */

    case E_VNx8QImode:
      if (pattern150 (x2, E_VNx8QImode, E_VNx8BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2750; /* pred_negvnx8qi */

    case E_VNx16QImode:
      if (pattern150 (x2, E_VNx16QImode, E_VNx16BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2752; /* pred_negvnx16qi */

    case E_VNx32QImode:
      if (pattern150 (x2, E_VNx32QImode, E_VNx32BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2754; /* pred_negvnx32qi */

    case E_VNx64QImode:
      if (pattern150 (x2, E_VNx64QImode, E_VNx64BImode) != 0
          || !(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2756; /* pred_negvnx64qi */

    case E_VNx1HImode:
      if (pattern150 (x2, E_VNx1HImode, E_VNx1BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2758; /* pred_negvnx1hi */

    case E_VNx2HImode:
      if (pattern150 (x2, E_VNx2HImode, E_VNx2BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2760; /* pred_negvnx2hi */

    case E_VNx4HImode:
      if (pattern150 (x2, E_VNx4HImode, E_VNx4BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2762; /* pred_negvnx4hi */

    case E_VNx8HImode:
      if (pattern150 (x2, E_VNx8HImode, E_VNx8BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2764; /* pred_negvnx8hi */

    case E_VNx16HImode:
      if (pattern150 (x2, E_VNx16HImode, E_VNx16BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2766; /* pred_negvnx16hi */

    case E_VNx32HImode:
      if (pattern150 (x2, E_VNx32HImode, E_VNx32BImode) != 0
          || !(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2768; /* pred_negvnx32hi */

    case E_VNx1SImode:
      if (pattern150 (x2, E_VNx1SImode, E_VNx1BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2770; /* pred_negvnx1si */

    case E_VNx2SImode:
      if (pattern150 (x2, E_VNx2SImode, E_VNx2BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2772; /* pred_negvnx2si */

    case E_VNx4SImode:
      if (pattern150 (x2, E_VNx4SImode, E_VNx4BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2774; /* pred_negvnx4si */

    case E_VNx8SImode:
      if (pattern150 (x2, E_VNx8SImode, E_VNx8BImode) != 0
          || !
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2776; /* pred_negvnx8si */

    case E_VNx16SImode:
      if (pattern150 (x2, E_VNx16SImode, E_VNx16BImode) != 0
          || !(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2778; /* pred_negvnx16si */

    case E_VNx1DImode:
      if (pattern150 (x2, E_VNx1DImode, E_VNx1BImode) != 0
          || !(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2780; /* pred_negvnx1di */

    case E_VNx2DImode:
      if (pattern150 (x2, E_VNx2DImode, E_VNx2BImode) != 0
          || !(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2782; /* pred_negvnx2di */

    case E_VNx4DImode:
      if (pattern150 (x2, E_VNx4DImode, E_VNx4BImode) != 0
          || !(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2784; /* pred_negvnx4di */

    case E_VNx8DImode:
      if (pattern150 (x2, E_VNx8DImode, E_VNx8BImode) != 0
          || !(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2786; /* pred_negvnx8di */

    case E_VNx1SFmode:
      if (pattern150 (x2, E_VNx1SFmode, E_VNx1BImode) != 0
          || !(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4996; /* pred_negvnx1sf */

    case E_VNx2SFmode:
      if (pattern150 (x2, E_VNx2SFmode, E_VNx2BImode) != 0
          || !(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 4999; /* pred_negvnx2sf */

    case E_VNx4SFmode:
      if (pattern150 (x2, E_VNx4SFmode, E_VNx4BImode) != 0
          || !(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5002; /* pred_negvnx4sf */

    case E_VNx8SFmode:
      if (pattern150 (x2, E_VNx8SFmode, E_VNx8BImode) != 0
          || !(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 5005; /* pred_negvnx8sf */

    case E_VNx16SFmode:
      if (pattern150 (x2, E_VNx16SFmode, E_VNx16BImode) != 0
          || !(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 5008; /* pred_negvnx16sf */

    case E_VNx1DFmode:
      if (pattern150 (x2, E_VNx1DFmode, E_VNx1BImode) != 0
          || !(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5011; /* pred_negvnx1df */

    case E_VNx2DFmode:
      if (pattern150 (x2, E_VNx2DFmode, E_VNx2BImode) != 0
          || !(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5014; /* pred_negvnx2df */

    case E_VNx4DFmode:
      if (pattern150 (x2, E_VNx4DFmode, E_VNx4BImode) != 0
          || !(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5017; /* pred_negvnx4df */

    case E_VNx8DFmode:
      if (pattern150 (x2, E_VNx8DFmode, E_VNx8BImode) != 0
          || !(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 5020; /* pred_negvnx8df */

    default:
      return -1;
    }
}

static int
recog_108 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[5] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[6] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[7] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[8] = x7;
  x8 = XEXP (x2, 1);
  x9 = XEXP (x8, 0);
  operands[3] = x9;
  x10 = XEXP (x2, 2);
  operands[2] = x10;
  x11 = XEXP (x8, 1);
  switch (GET_CODE (x11))
    {
    case REG:
    case SUBREG:
      switch (pattern158 (x2))
        {
        case 0:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3282; /* pred_ussubvnx1qi */

        case 1:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3286; /* pred_ussubvnx2qi */

        case 2:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3290; /* pred_ussubvnx4qi */

        case 3:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3294; /* pred_ussubvnx8qi */

        case 4:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3298; /* pred_ussubvnx16qi */

        case 5:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3302; /* pred_ussubvnx32qi */

        case 6:
          if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3306; /* pred_ussubvnx64qi */

        case 7:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3310; /* pred_ussubvnx1hi */

        case 8:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3314; /* pred_ussubvnx2hi */

        case 9:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3318; /* pred_ussubvnx4hi */

        case 10:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3322; /* pred_ussubvnx8hi */

        case 11:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3326; /* pred_ussubvnx16hi */

        case 12:
          if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3330; /* pred_ussubvnx32hi */

        case 13:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3334; /* pred_ussubvnx1si */

        case 14:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3338; /* pred_ussubvnx2si */

        case 15:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3342; /* pred_ussubvnx4si */

        case 16:
          if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3346; /* pred_ussubvnx8si */

        case 17:
          if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3350; /* pred_ussubvnx16si */

        case 18:
          if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3354; /* pred_ussubvnx1di */

        case 19:
          if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3358; /* pred_ussubvnx2di */

        case 20:
          if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3362; /* pred_ussubvnx4di */

        case 21:
          if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3366; /* pred_ussubvnx8di */

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      switch (pattern253 (x2))
        {
        case 0:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3404; /* pred_ussubvnx1qi_scalar */

        case 1:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3406; /* pred_ussubvnx2qi_scalar */

        case 2:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3408; /* pred_ussubvnx4qi_scalar */

        case 3:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3410; /* pred_ussubvnx8qi_scalar */

        case 4:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3412; /* pred_ussubvnx16qi_scalar */

        case 5:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3414; /* pred_ussubvnx32qi_scalar */

        case 6:
          if (!(
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3416; /* pred_ussubvnx64qi_scalar */

        case 7:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3418; /* pred_ussubvnx1hi_scalar */

        case 8:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3420; /* pred_ussubvnx2hi_scalar */

        case 9:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3422; /* pred_ussubvnx4hi_scalar */

        case 10:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3424; /* pred_ussubvnx8hi_scalar */

        case 11:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3426; /* pred_ussubvnx16hi_scalar */

        case 12:
          if (!(
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3428; /* pred_ussubvnx32hi_scalar */

        case 13:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3430; /* pred_ussubvnx1si_scalar */

        case 14:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3432; /* pred_ussubvnx2si_scalar */

        case 15:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3434; /* pred_ussubvnx4si_scalar */

        case 16:
          if (!
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 3436; /* pred_ussubvnx8si_scalar */

        case 17:
          if (!(
#line 3258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3438; /* pred_ussubvnx16si_scalar */

        case 18:
          if (!(
#line 3388 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3456; /* *pred_ussubvnx1di_scalar */

        case 19:
          if (!(
#line 3388 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3458; /* *pred_ussubvnx2di_scalar */

        case 20:
          if (!(
#line 3388 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3460; /* *pred_ussubvnx4di_scalar */

        case 21:
          if (!(
#line 3388 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3462; /* *pred_ussubvnx8di_scalar */

        case 22:
          if (!(
#line 3410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3464; /* *pred_ussubvnx1di_extended_scalar */

        case 23:
          if (!(
#line 3410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3466; /* *pred_ussubvnx2di_extended_scalar */

        case 24:
          if (!(
#line 3410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3468; /* *pred_ussubvnx4di_extended_scalar */

        case 25:
          if (!(
#line 3410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3470; /* *pred_ussubvnx8di_extended_scalar */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_109 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern166 (x2))
    {
    case 0:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3279; /* pred_ssaddvnx1qi */

    case 1:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3283; /* pred_ssaddvnx2qi */

    case 2:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3287; /* pred_ssaddvnx4qi */

    case 3:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3291; /* pred_ssaddvnx8qi */

    case 4:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3295; /* pred_ssaddvnx16qi */

    case 5:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3299; /* pred_ssaddvnx32qi */

    case 6:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3303; /* pred_ssaddvnx64qi */

    case 7:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3307; /* pred_ssaddvnx1hi */

    case 8:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3311; /* pred_ssaddvnx2hi */

    case 9:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3315; /* pred_ssaddvnx4hi */

    case 10:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3319; /* pred_ssaddvnx8hi */

    case 11:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3323; /* pred_ssaddvnx16hi */

    case 12:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3327; /* pred_ssaddvnx32hi */

    case 13:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3331; /* pred_ssaddvnx1si */

    case 14:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3335; /* pred_ssaddvnx2si */

    case 15:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3339; /* pred_ssaddvnx4si */

    case 16:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3343; /* pred_ssaddvnx8si */

    case 17:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3347; /* pred_ssaddvnx16si */

    case 18:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3351; /* pred_ssaddvnx1di */

    case 19:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3355; /* pred_ssaddvnx2di */

    case 20:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3359; /* pred_ssaddvnx4di */

    case 21:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3363; /* pred_ssaddvnx8di */

    case 22:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3367; /* pred_ssaddvnx1qi_scalar */

    case 23:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3369; /* pred_ssaddvnx2qi_scalar */

    case 24:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3371; /* pred_ssaddvnx4qi_scalar */

    case 25:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3373; /* pred_ssaddvnx8qi_scalar */

    case 26:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3375; /* pred_ssaddvnx16qi_scalar */

    case 27:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3377; /* pred_ssaddvnx32qi_scalar */

    case 28:
      if (!(
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3379; /* pred_ssaddvnx64qi_scalar */

    case 29:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3381; /* pred_ssaddvnx1hi_scalar */

    case 30:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3383; /* pred_ssaddvnx2hi_scalar */

    case 31:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3385; /* pred_ssaddvnx4hi_scalar */

    case 32:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3387; /* pred_ssaddvnx8hi_scalar */

    case 33:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3389; /* pred_ssaddvnx16hi_scalar */

    case 34:
      if (!(
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3391; /* pred_ssaddvnx32hi_scalar */

    case 35:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3393; /* pred_ssaddvnx1si_scalar */

    case 36:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3395; /* pred_ssaddvnx2si_scalar */

    case 37:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3397; /* pred_ssaddvnx4si_scalar */

    case 38:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3399; /* pred_ssaddvnx8si_scalar */

    case 39:
      if (!(
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3401; /* pred_ssaddvnx16si_scalar */

    case 40:
      if (!(
#line 3312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3439; /* *pred_ssaddvnx1di_scalar */

    case 41:
      if (!(
#line 3312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3441; /* *pred_ssaddvnx2di_scalar */

    case 42:
      if (!(
#line 3312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3443; /* *pred_ssaddvnx4di_scalar */

    case 43:
      if (!(
#line 3312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3445; /* *pred_ssaddvnx8di_scalar */

    case 44:
      if (!(
#line 3334 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3447; /* *pred_ssaddvnx1di_extended_scalar */

    case 45:
      if (!(
#line 3334 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3449; /* *pred_ssaddvnx2di_extended_scalar */

    case 46:
      if (!(
#line 3334 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3451; /* *pred_ssaddvnx4di_extended_scalar */

    case 47:
      if (!(
#line 3334 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3453; /* *pred_ssaddvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_110 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern166 (x2))
    {
    case 0:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3281; /* pred_usaddvnx1qi */

    case 1:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3285; /* pred_usaddvnx2qi */

    case 2:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3289; /* pred_usaddvnx4qi */

    case 3:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3293; /* pred_usaddvnx8qi */

    case 4:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3297; /* pred_usaddvnx16qi */

    case 5:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3301; /* pred_usaddvnx32qi */

    case 6:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3305; /* pred_usaddvnx64qi */

    case 7:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3309; /* pred_usaddvnx1hi */

    case 8:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3313; /* pred_usaddvnx2hi */

    case 9:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3317; /* pred_usaddvnx4hi */

    case 10:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3321; /* pred_usaddvnx8hi */

    case 11:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3325; /* pred_usaddvnx16hi */

    case 12:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3329; /* pred_usaddvnx32hi */

    case 13:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3333; /* pred_usaddvnx1si */

    case 14:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3337; /* pred_usaddvnx2si */

    case 15:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3341; /* pred_usaddvnx4si */

    case 16:
      if (!
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3345; /* pred_usaddvnx8si */

    case 17:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3349; /* pred_usaddvnx16si */

    case 18:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3353; /* pred_usaddvnx1di */

    case 19:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3357; /* pred_usaddvnx2di */

    case 20:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3361; /* pred_usaddvnx4di */

    case 21:
      if (!(
#line 3207 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3365; /* pred_usaddvnx8di */

    case 22:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3368; /* pred_usaddvnx1qi_scalar */

    case 23:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3370; /* pred_usaddvnx2qi_scalar */

    case 24:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3372; /* pred_usaddvnx4qi_scalar */

    case 25:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3374; /* pred_usaddvnx8qi_scalar */

    case 26:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3376; /* pred_usaddvnx16qi_scalar */

    case 27:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3378; /* pred_usaddvnx32qi_scalar */

    case 28:
      if (!(
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3380; /* pred_usaddvnx64qi_scalar */

    case 29:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3382; /* pred_usaddvnx1hi_scalar */

    case 30:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3384; /* pred_usaddvnx2hi_scalar */

    case 31:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3386; /* pred_usaddvnx4hi_scalar */

    case 32:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3388; /* pred_usaddvnx8hi_scalar */

    case 33:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3390; /* pred_usaddvnx16hi_scalar */

    case 34:
      if (!(
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3392; /* pred_usaddvnx32hi_scalar */

    case 35:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3394; /* pred_usaddvnx1si_scalar */

    case 36:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3396; /* pred_usaddvnx2si_scalar */

    case 37:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3398; /* pred_usaddvnx4si_scalar */

    case 38:
      if (!
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 3400; /* pred_usaddvnx8si_scalar */

    case 39:
      if (!(
#line 3237 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3402; /* pred_usaddvnx16si_scalar */

    case 40:
      if (!(
#line 3312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3440; /* *pred_usaddvnx1di_scalar */

    case 41:
      if (!(
#line 3312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3442; /* *pred_usaddvnx2di_scalar */

    case 42:
      if (!(
#line 3312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3444; /* *pred_usaddvnx4di_scalar */

    case 43:
      if (!(
#line 3312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3446; /* *pred_usaddvnx8di_scalar */

    case 44:
      if (!(
#line 3334 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3448; /* *pred_usaddvnx1di_extended_scalar */

    case 45:
      if (!(
#line 3334 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3450; /* *pred_usaddvnx2di_extended_scalar */

    case 46:
      if (!(
#line 3334 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3452; /* *pred_usaddvnx4di_extended_scalar */

    case 47:
      if (!(
#line 3334 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 3454; /* *pred_usaddvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_111 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern163 (x2))
    {
    case 0:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1498; /* pred_umodvnx1qi */

    case 1:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1515; /* pred_umodvnx2qi */

    case 2:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1532; /* pred_umodvnx4qi */

    case 3:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1549; /* pred_umodvnx8qi */

    case 4:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1566; /* pred_umodvnx16qi */

    case 5:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1583; /* pred_umodvnx32qi */

    case 6:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1600; /* pred_umodvnx64qi */

    case 7:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1617; /* pred_umodvnx1hi */

    case 8:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1634; /* pred_umodvnx2hi */

    case 9:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1651; /* pred_umodvnx4hi */

    case 10:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1668; /* pred_umodvnx8hi */

    case 11:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1685; /* pred_umodvnx16hi */

    case 12:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1702; /* pred_umodvnx32hi */

    case 13:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1719; /* pred_umodvnx1si */

    case 14:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1736; /* pred_umodvnx2si */

    case 15:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1753; /* pred_umodvnx4si */

    case 16:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1770; /* pred_umodvnx8si */

    case 17:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1787; /* pred_umodvnx16si */

    case 18:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1804; /* pred_umodvnx1di */

    case 19:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1821; /* pred_umodvnx2di */

    case 20:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1838; /* pred_umodvnx4di */

    case 21:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1855; /* pred_umodvnx8di */

    case 22:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2088; /* pred_umodvnx1qi_scalar */

    case 23:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2093; /* pred_umodvnx2qi_scalar */

    case 24:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2098; /* pred_umodvnx4qi_scalar */

    case 25:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2103; /* pred_umodvnx8qi_scalar */

    case 26:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2108; /* pred_umodvnx16qi_scalar */

    case 27:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2113; /* pred_umodvnx32qi_scalar */

    case 28:
      if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2118; /* pred_umodvnx64qi_scalar */

    case 29:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2123; /* pred_umodvnx1hi_scalar */

    case 30:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2128; /* pred_umodvnx2hi_scalar */

    case 31:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2133; /* pred_umodvnx4hi_scalar */

    case 32:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2138; /* pred_umodvnx8hi_scalar */

    case 33:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2143; /* pred_umodvnx16hi_scalar */

    case 34:
      if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2148; /* pred_umodvnx32hi_scalar */

    case 35:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2153; /* pred_umodvnx1si_scalar */

    case 36:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2158; /* pred_umodvnx2si_scalar */

    case 37:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2163; /* pred_umodvnx4si_scalar */

    case 38:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2168; /* pred_umodvnx8si_scalar */

    case 39:
      if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2173; /* pred_umodvnx16si_scalar */

    case 40:
      if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2268; /* *pred_umodvnx1di_scalar */

    case 41:
      if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2273; /* *pred_umodvnx2di_scalar */

    case 42:
      if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2278; /* *pred_umodvnx4di_scalar */

    case 43:
      if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2283; /* *pred_umodvnx8di_scalar */

    case 44:
      if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2288; /* *pred_umodvnx1di_extended_scalar */

    case 45:
      if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2293; /* *pred_umodvnx2di_extended_scalar */

    case 46:
      if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2298; /* *pred_umodvnx4di_extended_scalar */

    case 47:
      if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2303; /* *pred_umodvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_112 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern163 (x2))
    {
    case 0:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1497; /* pred_modvnx1qi */

    case 1:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1514; /* pred_modvnx2qi */

    case 2:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1531; /* pred_modvnx4qi */

    case 3:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1548; /* pred_modvnx8qi */

    case 4:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1565; /* pred_modvnx16qi */

    case 5:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1582; /* pred_modvnx32qi */

    case 6:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1599; /* pred_modvnx64qi */

    case 7:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1616; /* pred_modvnx1hi */

    case 8:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1633; /* pred_modvnx2hi */

    case 9:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1650; /* pred_modvnx4hi */

    case 10:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1667; /* pred_modvnx8hi */

    case 11:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1684; /* pred_modvnx16hi */

    case 12:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1701; /* pred_modvnx32hi */

    case 13:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1718; /* pred_modvnx1si */

    case 14:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1735; /* pred_modvnx2si */

    case 15:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1752; /* pred_modvnx4si */

    case 16:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1769; /* pred_modvnx8si */

    case 17:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1786; /* pred_modvnx16si */

    case 18:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1803; /* pred_modvnx1di */

    case 19:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1820; /* pred_modvnx2di */

    case 20:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1837; /* pred_modvnx4di */

    case 21:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1854; /* pred_modvnx8di */

    case 22:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2087; /* pred_modvnx1qi_scalar */

    case 23:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2092; /* pred_modvnx2qi_scalar */

    case 24:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2097; /* pred_modvnx4qi_scalar */

    case 25:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2102; /* pred_modvnx8qi_scalar */

    case 26:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2107; /* pred_modvnx16qi_scalar */

    case 27:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2112; /* pred_modvnx32qi_scalar */

    case 28:
      if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2117; /* pred_modvnx64qi_scalar */

    case 29:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2122; /* pred_modvnx1hi_scalar */

    case 30:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2127; /* pred_modvnx2hi_scalar */

    case 31:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2132; /* pred_modvnx4hi_scalar */

    case 32:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2137; /* pred_modvnx8hi_scalar */

    case 33:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2142; /* pred_modvnx16hi_scalar */

    case 34:
      if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2147; /* pred_modvnx32hi_scalar */

    case 35:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2152; /* pred_modvnx1si_scalar */

    case 36:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2157; /* pred_modvnx2si_scalar */

    case 37:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2162; /* pred_modvnx4si_scalar */

    case 38:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2167; /* pred_modvnx8si_scalar */

    case 39:
      if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2172; /* pred_modvnx16si_scalar */

    case 40:
      if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2267; /* *pred_modvnx1di_scalar */

    case 41:
      if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2272; /* *pred_modvnx2di_scalar */

    case 42:
      if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2277; /* *pred_modvnx4di_scalar */

    case 43:
      if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2282; /* *pred_modvnx8di_scalar */

    case 44:
      if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2287; /* *pred_modvnx1di_extended_scalar */

    case 45:
      if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2292; /* *pred_modvnx2di_extended_scalar */

    case 46:
      if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2297; /* *pred_modvnx4di_extended_scalar */

    case 47:
      if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2302; /* *pred_modvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_113 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern163 (x2))
    {
    case 0:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1496; /* pred_udivvnx1qi */

    case 1:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1513; /* pred_udivvnx2qi */

    case 2:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1530; /* pred_udivvnx4qi */

    case 3:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1547; /* pred_udivvnx8qi */

    case 4:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1564; /* pred_udivvnx16qi */

    case 5:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1581; /* pred_udivvnx32qi */

    case 6:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1598; /* pred_udivvnx64qi */

    case 7:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1615; /* pred_udivvnx1hi */

    case 8:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1632; /* pred_udivvnx2hi */

    case 9:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1649; /* pred_udivvnx4hi */

    case 10:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1666; /* pred_udivvnx8hi */

    case 11:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1683; /* pred_udivvnx16hi */

    case 12:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1700; /* pred_udivvnx32hi */

    case 13:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1717; /* pred_udivvnx1si */

    case 14:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1734; /* pred_udivvnx2si */

    case 15:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1751; /* pred_udivvnx4si */

    case 16:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1768; /* pred_udivvnx8si */

    case 17:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1785; /* pred_udivvnx16si */

    case 18:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1802; /* pred_udivvnx1di */

    case 19:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1819; /* pred_udivvnx2di */

    case 20:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1836; /* pred_udivvnx4di */

    case 21:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1853; /* pred_udivvnx8di */

    case 22:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2086; /* pred_udivvnx1qi_scalar */

    case 23:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2091; /* pred_udivvnx2qi_scalar */

    case 24:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2096; /* pred_udivvnx4qi_scalar */

    case 25:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2101; /* pred_udivvnx8qi_scalar */

    case 26:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2106; /* pred_udivvnx16qi_scalar */

    case 27:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2111; /* pred_udivvnx32qi_scalar */

    case 28:
      if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2116; /* pred_udivvnx64qi_scalar */

    case 29:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2121; /* pred_udivvnx1hi_scalar */

    case 30:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2126; /* pred_udivvnx2hi_scalar */

    case 31:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2131; /* pred_udivvnx4hi_scalar */

    case 32:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2136; /* pred_udivvnx8hi_scalar */

    case 33:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2141; /* pred_udivvnx16hi_scalar */

    case 34:
      if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2146; /* pred_udivvnx32hi_scalar */

    case 35:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2151; /* pred_udivvnx1si_scalar */

    case 36:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2156; /* pred_udivvnx2si_scalar */

    case 37:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2161; /* pred_udivvnx4si_scalar */

    case 38:
      if (!
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2166; /* pred_udivvnx8si_scalar */

    case 39:
      if (!(
#line 1777 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2171; /* pred_udivvnx16si_scalar */

    case 40:
      if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2266; /* *pred_udivvnx1di_scalar */

    case 41:
      if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2271; /* *pred_udivvnx2di_scalar */

    case 42:
      if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2276; /* *pred_udivvnx4di_scalar */

    case 43:
      if (!(
#line 1930 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2281; /* *pred_udivvnx8di_scalar */

    case 44:
      if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2286; /* *pred_udivvnx1di_extended_scalar */

    case 45:
      if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2291; /* *pred_udivvnx2di_extended_scalar */

    case 46:
      if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2296; /* *pred_udivvnx4di_extended_scalar */

    case 47:
      if (!(
#line 1952 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2301; /* *pred_udivvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_114 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern159 (x2))
    {
    case 0:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1493; /* pred_uminvnx1qi */

    case 1:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1510; /* pred_uminvnx2qi */

    case 2:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1527; /* pred_uminvnx4qi */

    case 3:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1544; /* pred_uminvnx8qi */

    case 4:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1561; /* pred_uminvnx16qi */

    case 5:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1578; /* pred_uminvnx32qi */

    case 6:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1595; /* pred_uminvnx64qi */

    case 7:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1612; /* pred_uminvnx1hi */

    case 8:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1629; /* pred_uminvnx2hi */

    case 9:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1646; /* pred_uminvnx4hi */

    case 10:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1663; /* pred_uminvnx8hi */

    case 11:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1680; /* pred_uminvnx16hi */

    case 12:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1697; /* pred_uminvnx32hi */

    case 13:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1714; /* pred_uminvnx1si */

    case 14:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1731; /* pred_uminvnx2si */

    case 15:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1748; /* pred_uminvnx4si */

    case 16:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1765; /* pred_uminvnx8si */

    case 17:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1782; /* pred_uminvnx16si */

    case 18:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1799; /* pred_uminvnx1di */

    case 19:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1816; /* pred_uminvnx2di */

    case 20:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1833; /* pred_uminvnx4di */

    case 21:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1850; /* pred_uminvnx8di */

    case 22:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1929; /* pred_uminvnx1qi_scalar */

    case 23:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1938; /* pred_uminvnx2qi_scalar */

    case 24:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1947; /* pred_uminvnx4qi_scalar */

    case 25:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1956; /* pred_uminvnx8qi_scalar */

    case 26:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1965; /* pred_uminvnx16qi_scalar */

    case 27:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1974; /* pred_uminvnx32qi_scalar */

    case 28:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1983; /* pred_uminvnx64qi_scalar */

    case 29:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1992; /* pred_uminvnx1hi_scalar */

    case 30:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2001; /* pred_uminvnx2hi_scalar */

    case 31:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2010; /* pred_uminvnx4hi_scalar */

    case 32:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2019; /* pred_uminvnx8hi_scalar */

    case 33:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2028; /* pred_uminvnx16hi_scalar */

    case 34:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2037; /* pred_uminvnx32hi_scalar */

    case 35:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2046; /* pred_uminvnx1si_scalar */

    case 36:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2055; /* pred_uminvnx2si_scalar */

    case 37:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2064; /* pred_uminvnx4si_scalar */

    case 38:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2073; /* pred_uminvnx8si_scalar */

    case 39:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2082; /* pred_uminvnx16si_scalar */

    case 40:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2199; /* *pred_uminvnx1di_scalar */

    case 41:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2208; /* *pred_uminvnx2di_scalar */

    case 42:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2217; /* *pred_uminvnx4di_scalar */

    case 43:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2226; /* *pred_uminvnx8di_scalar */

    case 44:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2235; /* *pred_uminvnx1di_extended_scalar */

    case 45:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2244; /* *pred_uminvnx2di_extended_scalar */

    case 46:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2253; /* *pred_uminvnx4di_extended_scalar */

    case 47:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2262; /* *pred_uminvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_115 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern159 (x2))
    {
    case 0:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1491; /* pred_umaxvnx1qi */

    case 1:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1508; /* pred_umaxvnx2qi */

    case 2:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1525; /* pred_umaxvnx4qi */

    case 3:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1542; /* pred_umaxvnx8qi */

    case 4:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1559; /* pred_umaxvnx16qi */

    case 5:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1576; /* pred_umaxvnx32qi */

    case 6:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1593; /* pred_umaxvnx64qi */

    case 7:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1610; /* pred_umaxvnx1hi */

    case 8:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1627; /* pred_umaxvnx2hi */

    case 9:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1644; /* pred_umaxvnx4hi */

    case 10:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1661; /* pred_umaxvnx8hi */

    case 11:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1678; /* pred_umaxvnx16hi */

    case 12:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1695; /* pred_umaxvnx32hi */

    case 13:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1712; /* pred_umaxvnx1si */

    case 14:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1729; /* pred_umaxvnx2si */

    case 15:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1746; /* pred_umaxvnx4si */

    case 16:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1763; /* pred_umaxvnx8si */

    case 17:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1780; /* pred_umaxvnx16si */

    case 18:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1797; /* pred_umaxvnx1di */

    case 19:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1814; /* pred_umaxvnx2di */

    case 20:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1831; /* pred_umaxvnx4di */

    case 21:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1848; /* pred_umaxvnx8di */

    case 22:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1927; /* pred_umaxvnx1qi_scalar */

    case 23:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1936; /* pred_umaxvnx2qi_scalar */

    case 24:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1945; /* pred_umaxvnx4qi_scalar */

    case 25:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1954; /* pred_umaxvnx8qi_scalar */

    case 26:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1963; /* pred_umaxvnx16qi_scalar */

    case 27:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1972; /* pred_umaxvnx32qi_scalar */

    case 28:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1981; /* pred_umaxvnx64qi_scalar */

    case 29:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1990; /* pred_umaxvnx1hi_scalar */

    case 30:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1999; /* pred_umaxvnx2hi_scalar */

    case 31:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2008; /* pred_umaxvnx4hi_scalar */

    case 32:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2017; /* pred_umaxvnx8hi_scalar */

    case 33:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2026; /* pred_umaxvnx16hi_scalar */

    case 34:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2035; /* pred_umaxvnx32hi_scalar */

    case 35:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2044; /* pred_umaxvnx1si_scalar */

    case 36:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2053; /* pred_umaxvnx2si_scalar */

    case 37:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2062; /* pred_umaxvnx4si_scalar */

    case 38:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2071; /* pred_umaxvnx8si_scalar */

    case 39:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2080; /* pred_umaxvnx16si_scalar */

    case 40:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2197; /* *pred_umaxvnx1di_scalar */

    case 41:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2206; /* *pred_umaxvnx2di_scalar */

    case 42:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2215; /* *pred_umaxvnx4di_scalar */

    case 43:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2224; /* *pred_umaxvnx8di_scalar */

    case 44:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2233; /* *pred_umaxvnx1di_extended_scalar */

    case 45:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2242; /* *pred_umaxvnx2di_extended_scalar */

    case 46:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2251; /* *pred_umaxvnx4di_extended_scalar */

    case 47:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2260; /* *pred_umaxvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_116 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern149 (x2))
    {
    case 0:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1485; /* pred_iorvnx1qi */

    case 1:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1502; /* pred_iorvnx2qi */

    case 2:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1519; /* pred_iorvnx4qi */

    case 3:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1536; /* pred_iorvnx8qi */

    case 4:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1553; /* pred_iorvnx16qi */

    case 5:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1570; /* pred_iorvnx32qi */

    case 6:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1587; /* pred_iorvnx64qi */

    case 7:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1604; /* pred_iorvnx1hi */

    case 8:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1621; /* pred_iorvnx2hi */

    case 9:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1638; /* pred_iorvnx4hi */

    case 10:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1655; /* pred_iorvnx8hi */

    case 11:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1672; /* pred_iorvnx16hi */

    case 12:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1689; /* pred_iorvnx32hi */

    case 13:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1706; /* pred_iorvnx1si */

    case 14:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1723; /* pred_iorvnx2si */

    case 15:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1740; /* pred_iorvnx4si */

    case 16:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1757; /* pred_iorvnx8si */

    case 17:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1774; /* pred_iorvnx16si */

    case 18:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1791; /* pred_iorvnx1di */

    case 19:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1808; /* pred_iorvnx2di */

    case 20:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1825; /* pred_iorvnx4di */

    case 21:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1842; /* pred_iorvnx8di */

    case 22:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1924; /* pred_iorvnx1qi_scalar */

    case 23:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1933; /* pred_iorvnx2qi_scalar */

    case 24:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1942; /* pred_iorvnx4qi_scalar */

    case 25:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1951; /* pred_iorvnx8qi_scalar */

    case 26:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1960; /* pred_iorvnx16qi_scalar */

    case 27:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1969; /* pred_iorvnx32qi_scalar */

    case 28:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1978; /* pred_iorvnx64qi_scalar */

    case 29:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1987; /* pred_iorvnx1hi_scalar */

    case 30:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1996; /* pred_iorvnx2hi_scalar */

    case 31:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2005; /* pred_iorvnx4hi_scalar */

    case 32:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2014; /* pred_iorvnx8hi_scalar */

    case 33:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2023; /* pred_iorvnx16hi_scalar */

    case 34:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2032; /* pred_iorvnx32hi_scalar */

    case 35:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2041; /* pred_iorvnx1si_scalar */

    case 36:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2050; /* pred_iorvnx2si_scalar */

    case 37:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2059; /* pred_iorvnx4si_scalar */

    case 38:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2068; /* pred_iorvnx8si_scalar */

    case 39:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2077; /* pred_iorvnx16si_scalar */

    case 40:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2194; /* *pred_iorvnx1di_scalar */

    case 41:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2203; /* *pred_iorvnx2di_scalar */

    case 42:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2212; /* *pred_iorvnx4di_scalar */

    case 43:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2221; /* *pred_iorvnx8di_scalar */

    case 44:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2230; /* *pred_iorvnx1di_extended_scalar */

    case 45:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2239; /* *pred_iorvnx2di_extended_scalar */

    case 46:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2248; /* *pred_iorvnx4di_extended_scalar */

    case 47:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2257; /* *pred_iorvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_117 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern149 (x2))
    {
    case 0:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1486; /* pred_xorvnx1qi */

    case 1:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1503; /* pred_xorvnx2qi */

    case 2:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1520; /* pred_xorvnx4qi */

    case 3:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1537; /* pred_xorvnx8qi */

    case 4:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1554; /* pred_xorvnx16qi */

    case 5:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1571; /* pred_xorvnx32qi */

    case 6:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1588; /* pred_xorvnx64qi */

    case 7:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1605; /* pred_xorvnx1hi */

    case 8:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1622; /* pred_xorvnx2hi */

    case 9:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1639; /* pred_xorvnx4hi */

    case 10:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1656; /* pred_xorvnx8hi */

    case 11:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1673; /* pred_xorvnx16hi */

    case 12:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1690; /* pred_xorvnx32hi */

    case 13:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1707; /* pred_xorvnx1si */

    case 14:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1724; /* pred_xorvnx2si */

    case 15:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1741; /* pred_xorvnx4si */

    case 16:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1758; /* pred_xorvnx8si */

    case 17:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1775; /* pred_xorvnx16si */

    case 18:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1792; /* pred_xorvnx1di */

    case 19:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1809; /* pred_xorvnx2di */

    case 20:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1826; /* pred_xorvnx4di */

    case 21:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1843; /* pred_xorvnx8di */

    case 22:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1925; /* pred_xorvnx1qi_scalar */

    case 23:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1934; /* pred_xorvnx2qi_scalar */

    case 24:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1943; /* pred_xorvnx4qi_scalar */

    case 25:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1952; /* pred_xorvnx8qi_scalar */

    case 26:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1961; /* pred_xorvnx16qi_scalar */

    case 27:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1970; /* pred_xorvnx32qi_scalar */

    case 28:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1979; /* pred_xorvnx64qi_scalar */

    case 29:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1988; /* pred_xorvnx1hi_scalar */

    case 30:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1997; /* pred_xorvnx2hi_scalar */

    case 31:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2006; /* pred_xorvnx4hi_scalar */

    case 32:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2015; /* pred_xorvnx8hi_scalar */

    case 33:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2024; /* pred_xorvnx16hi_scalar */

    case 34:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2033; /* pred_xorvnx32hi_scalar */

    case 35:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2042; /* pred_xorvnx1si_scalar */

    case 36:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2051; /* pred_xorvnx2si_scalar */

    case 37:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2060; /* pred_xorvnx4si_scalar */

    case 38:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2069; /* pred_xorvnx8si_scalar */

    case 39:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2078; /* pred_xorvnx16si_scalar */

    case 40:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2195; /* *pred_xorvnx1di_scalar */

    case 41:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2204; /* *pred_xorvnx2di_scalar */

    case 42:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2213; /* *pred_xorvnx4di_scalar */

    case 43:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2222; /* *pred_xorvnx8di_scalar */

    case 44:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2231; /* *pred_xorvnx1di_extended_scalar */

    case 45:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2240; /* *pred_xorvnx2di_extended_scalar */

    case 46:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2249; /* *pred_xorvnx4di_extended_scalar */

    case 47:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2258; /* *pred_xorvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_118 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern149 (x2))
    {
    case 0:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1484; /* pred_andvnx1qi */

    case 1:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1501; /* pred_andvnx2qi */

    case 2:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1518; /* pred_andvnx4qi */

    case 3:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1535; /* pred_andvnx8qi */

    case 4:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1552; /* pred_andvnx16qi */

    case 5:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1569; /* pred_andvnx32qi */

    case 6:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1586; /* pred_andvnx64qi */

    case 7:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1603; /* pred_andvnx1hi */

    case 8:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1620; /* pred_andvnx2hi */

    case 9:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1637; /* pred_andvnx4hi */

    case 10:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1654; /* pred_andvnx8hi */

    case 11:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1671; /* pred_andvnx16hi */

    case 12:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1688; /* pred_andvnx32hi */

    case 13:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1705; /* pred_andvnx1si */

    case 14:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1722; /* pred_andvnx2si */

    case 15:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1739; /* pred_andvnx4si */

    case 16:
      if (!
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1756; /* pred_andvnx8si */

    case 17:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1773; /* pred_andvnx16si */

    case 18:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1790; /* pred_andvnx1di */

    case 19:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1807; /* pred_andvnx2di */

    case 20:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1824; /* pred_andvnx4di */

    case 21:
      if (!(
#line 1698 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 1841; /* pred_andvnx8di */

    case 22:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1923; /* pred_andvnx1qi_scalar */

    case 23:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1932; /* pred_andvnx2qi_scalar */

    case 24:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1941; /* pred_andvnx4qi_scalar */

    case 25:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1950; /* pred_andvnx8qi_scalar */

    case 26:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1959; /* pred_andvnx16qi_scalar */

    case 27:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1968; /* pred_andvnx32qi_scalar */

    case 28:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 1977; /* pred_andvnx64qi_scalar */

    case 29:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1986; /* pred_andvnx1hi_scalar */

    case 30:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 1995; /* pred_andvnx2hi_scalar */

    case 31:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2004; /* pred_andvnx4hi_scalar */

    case 32:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2013; /* pred_andvnx8hi_scalar */

    case 33:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2022; /* pred_andvnx16hi_scalar */

    case 34:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2031; /* pred_andvnx32hi_scalar */

    case 35:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2040; /* pred_andvnx1si_scalar */

    case 36:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2049; /* pred_andvnx2si_scalar */

    case 37:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2058; /* pred_andvnx4si_scalar */

    case 38:
      if (!
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2067; /* pred_andvnx8si_scalar */

    case 39:
      if (!(
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2076; /* pred_andvnx16si_scalar */

    case 40:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2193; /* *pred_andvnx1di_scalar */

    case 41:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2202; /* *pred_andvnx2di_scalar */

    case 42:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2211; /* *pred_andvnx4di_scalar */

    case 43:
      if (!(
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2220; /* *pred_andvnx8di_scalar */

    case 44:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2229; /* *pred_andvnx1di_extended_scalar */

    case 45:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2238; /* *pred_andvnx2di_extended_scalar */

    case 46:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2247; /* *pred_andvnx4di_extended_scalar */

    case 47:
      if (!(
#line 1876 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2256; /* *pred_andvnx8di_extended_scalar */

    default:
      return -1;
    }
}

static int
recog_119 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  if (x4 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
    return -1;
  x5 = XEXP (x3, 1);
  if (x5 != const_int_rtx[MAX_SAVED_CONST_INT + 1])
    return -1;
  x6 = XEXP (x2, 0);
  x7 = XVECEXP (x6, 0, 1);
  operands[3] = x7;
  x8 = XVECEXP (x6, 0, 2);
  operands[4] = x8;
  x9 = XVECEXP (x6, 0, 3);
  operands[5] = x9;
  x10 = XVECEXP (x6, 0, 4);
  operands[6] = x10;
  x11 = XEXP (x2, 2);
  operands[2] = x11;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      if (pattern271 (x2, E_VNx1QImode, E_VNx1BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4578; /* pred_seriesvnx1qi */

    case E_VNx2QImode:
      if (pattern271 (x2, E_VNx2QImode, E_VNx2BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4579; /* pred_seriesvnx2qi */

    case E_VNx4QImode:
      if (pattern271 (x2, E_VNx4QImode, E_VNx4BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4580; /* pred_seriesvnx4qi */

    case E_VNx8QImode:
      if (pattern271 (x2, E_VNx8QImode, E_VNx8BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4581; /* pred_seriesvnx8qi */

    case E_VNx16QImode:
      if (pattern271 (x2, E_VNx16QImode, E_VNx16BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4582; /* pred_seriesvnx16qi */

    case E_VNx32QImode:
      if (pattern271 (x2, E_VNx32QImode, E_VNx32BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4583; /* pred_seriesvnx32qi */

    case E_VNx64QImode:
      if (pattern271 (x2, E_VNx64QImode, E_VNx64BImode) != 0
          || !(
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 4584; /* pred_seriesvnx64qi */

    case E_VNx1HImode:
      if (pattern271 (x2, E_VNx1HImode, E_VNx1BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4585; /* pred_seriesvnx1hi */

    case E_VNx2HImode:
      if (pattern271 (x2, E_VNx2HImode, E_VNx2BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4586; /* pred_seriesvnx2hi */

    case E_VNx4HImode:
      if (pattern271 (x2, E_VNx4HImode, E_VNx4BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4587; /* pred_seriesvnx4hi */

    case E_VNx8HImode:
      if (pattern271 (x2, E_VNx8HImode, E_VNx8BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4588; /* pred_seriesvnx8hi */

    case E_VNx16HImode:
      if (pattern271 (x2, E_VNx16HImode, E_VNx16BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4589; /* pred_seriesvnx16hi */

    case E_VNx32HImode:
      if (pattern271 (x2, E_VNx32HImode, E_VNx32BImode) != 0
          || !(
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 4590; /* pred_seriesvnx32hi */

    case E_VNx1SImode:
      if (pattern271 (x2, E_VNx1SImode, E_VNx1BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4591; /* pred_seriesvnx1si */

    case E_VNx2SImode:
      if (pattern271 (x2, E_VNx2SImode, E_VNx2BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4592; /* pred_seriesvnx2si */

    case E_VNx4SImode:
      if (pattern271 (x2, E_VNx4SImode, E_VNx4BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4593; /* pred_seriesvnx4si */

    case E_VNx8SImode:
      if (pattern271 (x2, E_VNx8SImode, E_VNx8BImode) != 0
          || !
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 4594; /* pred_seriesvnx8si */

    case E_VNx16SImode:
      if (pattern271 (x2, E_VNx16SImode, E_VNx16BImode) != 0
          || !(
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 4595; /* pred_seriesvnx16si */

    case E_VNx1DImode:
      if (pattern271 (x2, E_VNx1DImode, E_VNx1BImode) != 0
          || !(
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4596; /* pred_seriesvnx1di */

    case E_VNx2DImode:
      if (pattern271 (x2, E_VNx2DImode, E_VNx2BImode) != 0
          || !(
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4597; /* pred_seriesvnx2di */

    case E_VNx4DImode:
      if (pattern271 (x2, E_VNx4DImode, E_VNx4BImode) != 0
          || !(
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4598; /* pred_seriesvnx4di */

    case E_VNx8DImode:
      if (pattern271 (x2, E_VNx8DImode, E_VNx8BImode) != 0
          || !(
#line 5357 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 4599; /* pred_seriesvnx8di */

    default:
      return -1;
    }
}

static int
recog_120 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern142 (x2))
    {
    case 0:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 800; /* pred_movvnx1qi */

    case 1:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 801; /* pred_movvnx2qi */

    case 2:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 802; /* pred_movvnx4qi */

    case 3:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 803; /* pred_movvnx8qi */

    case 4:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 804; /* pred_movvnx16qi */

    case 5:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 805; /* pred_movvnx32qi */

    case 6:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 806; /* pred_movvnx64qi */

    case 7:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 807; /* pred_movvnx1hi */

    case 8:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 808; /* pred_movvnx2hi */

    case 9:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 809; /* pred_movvnx4hi */

    case 10:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 810; /* pred_movvnx8hi */

    case 11:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 811; /* pred_movvnx16hi */

    case 12:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 812; /* pred_movvnx32hi */

    case 13:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 813; /* pred_movvnx1si */

    case 14:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 814; /* pred_movvnx2si */

    case 15:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 815; /* pred_movvnx4si */

    case 16:
      if (!
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))))
        return -1;
      return 816; /* pred_movvnx8si */

    case 17:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 817; /* pred_movvnx16si */

    case 18:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 818; /* pred_movvnx1di */

    case 19:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 819; /* pred_movvnx2di */

    case 20:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 820; /* pred_movvnx4di */

    case 21:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 821; /* pred_movvnx8di */

    case 22:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 822; /* pred_movvnx1sf */

    case 23:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 823; /* pred_movvnx2sf */

    case 24:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 824; /* pred_movvnx4sf */

    case 25:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
        return -1;
      return 825; /* pred_movvnx8sf */

    case 26:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
        return -1;
      return 826; /* pred_movvnx16sf */

    case 27:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 827; /* pred_movvnx1df */

    case 28:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 828; /* pred_movvnx2df */

    case 29:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 829; /* pred_movvnx4df */

    case 30:
      if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
        return -1;
      return 830; /* pred_movvnx8df */

    default:
      return -1;
    }
}

static int
recog_121 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (pattern165 (x2))
    {
    case 0:
      if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2789; /* pred_zero_extendvnx1hi_vf2 */

    case 1:
      if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2791; /* pred_zero_extendvnx2hi_vf2 */

    case 2:
      if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2793; /* pred_zero_extendvnx4hi_vf2 */

    case 3:
      if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2795; /* pred_zero_extendvnx8hi_vf2 */

    case 4:
      if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2797; /* pred_zero_extendvnx16hi_vf2 */

    case 5:
      if (!(
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2799; /* pred_zero_extendvnx32hi_vf2 */

    case 6:
      if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2801; /* pred_zero_extendvnx1si_vf2 */

    case 7:
      if (!
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2819; /* pred_zero_extendvnx1si_vf4 */

    case 8:
      if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2803; /* pred_zero_extendvnx2si_vf2 */

    case 9:
      if (!
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2821; /* pred_zero_extendvnx2si_vf4 */

    case 10:
      if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2805; /* pred_zero_extendvnx4si_vf2 */

    case 11:
      if (!
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2823; /* pred_zero_extendvnx4si_vf4 */

    case 12:
      if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2807; /* pred_zero_extendvnx8si_vf2 */

    case 13:
      if (!
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
        return -1;
      return 2825; /* pred_zero_extendvnx8si_vf4 */

    case 14:
      if (!(
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2809; /* pred_zero_extendvnx16si_vf2 */

    case 15:
      if (!(
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 423 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 2827; /* pred_zero_extendvnx16si_vf4 */

    case 16:
      if (!(
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2811; /* pred_zero_extendvnx1di_vf2 */

    case 17:
      if (!(
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2829; /* pred_zero_extendvnx1di_vf4 */

    case 18:
      if (!(
#line 2938 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2837; /* pred_zero_extendvnx1di_vf8 */

    case 19:
      if (!(
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2813; /* pred_zero_extendvnx2di_vf2 */

    case 20:
      if (!(
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2831; /* pred_zero_extendvnx2di_vf4 */

    case 21:
      if (!(
#line 2938 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2839; /* pred_zero_extendvnx2di_vf8 */

    case 22:
      if (!(
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2815; /* pred_zero_extendvnx4di_vf2 */

    case 23:
      if (!(
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 425 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2833; /* pred_zero_extendvnx4di_vf4 */

    case 24:
      if (!(
#line 2938 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2841; /* pred_zero_extendvnx4di_vf8 */

    case 25:
      if (!(
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2817; /* pred_zero_extendvnx8di_vf2 */

    case 26:
      if (!(
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 425 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2835; /* pred_zero_extendvnx8di_vf4 */

    case 27:
      if (!(
#line 2938 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
        return -1;
      return 2843; /* pred_zero_extendvnx8di_vf8 */

    default:
      return -1;
    }
}

static int
recog_122 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XVECEXP (x3, 0, 0);
  if (GET_CODE (x4) != MINUS)
    return -1;
  x5 = XEXP (x4, 0);
  operands[2] = x5;
  x6 = XEXP (x4, 1);
  switch (GET_CODE (x6))
    {
    case REG:
    case SUBREG:
      operands[3] = x6;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          if (pattern295 (x2, E_VNx1QImode, E_VNx1BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2478; /* pred_sbcvnx1qi */

        case E_VNx2QImode:
          if (pattern295 (x2, E_VNx2QImode, E_VNx2BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2479; /* pred_sbcvnx2qi */

        case E_VNx4QImode:
          if (pattern295 (x2, E_VNx4QImode, E_VNx4BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2480; /* pred_sbcvnx4qi */

        case E_VNx8QImode:
          if (pattern295 (x2, E_VNx8QImode, E_VNx8BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2481; /* pred_sbcvnx8qi */

        case E_VNx16QImode:
          if (pattern295 (x2, E_VNx16QImode, E_VNx16BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2482; /* pred_sbcvnx16qi */

        case E_VNx32QImode:
          if (pattern295 (x2, E_VNx32QImode, E_VNx32BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2483; /* pred_sbcvnx32qi */

        case E_VNx64QImode:
          if (pattern295 (x2, E_VNx64QImode, E_VNx64BImode) != 0
              || !(
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2484; /* pred_sbcvnx64qi */

        case E_VNx1HImode:
          if (pattern295 (x2, E_VNx1HImode, E_VNx1BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2485; /* pred_sbcvnx1hi */

        case E_VNx2HImode:
          if (pattern295 (x2, E_VNx2HImode, E_VNx2BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2486; /* pred_sbcvnx2hi */

        case E_VNx4HImode:
          if (pattern295 (x2, E_VNx4HImode, E_VNx4BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2487; /* pred_sbcvnx4hi */

        case E_VNx8HImode:
          if (pattern295 (x2, E_VNx8HImode, E_VNx8BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2488; /* pred_sbcvnx8hi */

        case E_VNx16HImode:
          if (pattern295 (x2, E_VNx16HImode, E_VNx16BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2489; /* pred_sbcvnx16hi */

        case E_VNx32HImode:
          if (pattern295 (x2, E_VNx32HImode, E_VNx32BImode) != 0
              || !(
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2490; /* pred_sbcvnx32hi */

        case E_VNx1SImode:
          if (pattern295 (x2, E_VNx1SImode, E_VNx1BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2491; /* pred_sbcvnx1si */

        case E_VNx2SImode:
          if (pattern295 (x2, E_VNx2SImode, E_VNx2BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2492; /* pred_sbcvnx2si */

        case E_VNx4SImode:
          if (pattern295 (x2, E_VNx4SImode, E_VNx4BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2493; /* pred_sbcvnx4si */

        case E_VNx8SImode:
          if (pattern295 (x2, E_VNx8SImode, E_VNx8BImode) != 0
              || !
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2494; /* pred_sbcvnx8si */

        case E_VNx16SImode:
          if (pattern295 (x2, E_VNx16SImode, E_VNx16BImode) != 0
              || !(
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2495; /* pred_sbcvnx16si */

        case E_VNx1DImode:
          if (pattern295 (x2, E_VNx1DImode, E_VNx1BImode) != 0
              || !(
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2496; /* pred_sbcvnx1di */

        case E_VNx2DImode:
          if (pattern295 (x2, E_VNx2DImode, E_VNx2BImode) != 0
              || !(
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2497; /* pred_sbcvnx2di */

        case E_VNx4DImode:
          if (pattern295 (x2, E_VNx4DImode, E_VNx4BImode) != 0
              || !(
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2498; /* pred_sbcvnx4di */

        case E_VNx8DImode:
          if (pattern295 (x2, E_VNx8DImode, E_VNx8BImode) != 0
              || !(
#line 2191 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2499; /* pred_sbcvnx8di */

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x7 = XEXP (x6, 0);
      switch (GET_CODE (x7))
        {
        case CONST_INT:
        case CONST_WIDE_INT:
        case CONST_VECTOR:
        case REG:
        case SUBREG:
          operands[3] = x7;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1QImode:
              if (pattern301 (x2, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2518; /* pred_sbcvnx1qi_scalar */

            case E_VNx2QImode:
              if (pattern301 (x2, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2519; /* pred_sbcvnx2qi_scalar */

            case E_VNx4QImode:
              if (pattern301 (x2, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2520; /* pred_sbcvnx4qi_scalar */

            case E_VNx8QImode:
              if (pattern301 (x2, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2521; /* pred_sbcvnx8qi_scalar */

            case E_VNx16QImode:
              if (pattern301 (x2, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2522; /* pred_sbcvnx16qi_scalar */

            case E_VNx32QImode:
              if (pattern301 (x2, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2523; /* pred_sbcvnx32qi_scalar */

            case E_VNx64QImode:
              if (pattern301 (x2, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0
                  || !(
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2524; /* pred_sbcvnx64qi_scalar */

            case E_VNx1HImode:
              if (pattern301 (x2, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2525; /* pred_sbcvnx1hi_scalar */

            case E_VNx2HImode:
              if (pattern301 (x2, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2526; /* pred_sbcvnx2hi_scalar */

            case E_VNx4HImode:
              if (pattern301 (x2, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2527; /* pred_sbcvnx4hi_scalar */

            case E_VNx8HImode:
              if (pattern301 (x2, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2528; /* pred_sbcvnx8hi_scalar */

            case E_VNx16HImode:
              if (pattern301 (x2, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2529; /* pred_sbcvnx16hi_scalar */

            case E_VNx32HImode:
              if (pattern301 (x2, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0
                  || !(
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2530; /* pred_sbcvnx32hi_scalar */

            case E_VNx1SImode:
              if (pattern301 (x2, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2531; /* pred_sbcvnx1si_scalar */

            case E_VNx2SImode:
              if (pattern301 (x2, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2532; /* pred_sbcvnx2si_scalar */

            case E_VNx4SImode:
              if (pattern301 (x2, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2533; /* pred_sbcvnx4si_scalar */

            case E_VNx8SImode:
              if (pattern301 (x2, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0
                  || !
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 2534; /* pred_sbcvnx8si_scalar */

            case E_VNx16SImode:
              if (pattern301 (x2, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0
                  || !(
#line 2241 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 2535; /* pred_sbcvnx16si_scalar */

            case E_VNx1DImode:
              if (pattern301 (x2, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0
                  || !(
#line 2383 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2544; /* *pred_sbcvnx1di_scalar */

            case E_VNx2DImode:
              if (pattern301 (x2, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0
                  || !(
#line 2383 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2545; /* *pred_sbcvnx2di_scalar */

            case E_VNx4DImode:
              if (pattern301 (x2, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0
                  || !(
#line 2383 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2546; /* *pred_sbcvnx4di_scalar */

            case E_VNx8DImode:
              if (pattern301 (x2, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0
                  || !(
#line 2383 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2547; /* *pred_sbcvnx8di_scalar */

            default:
              return -1;
            }

        case SIGN_EXTEND:
          if (GET_MODE (x7) != E_DImode)
            return -1;
          x8 = XEXP (x7, 0);
          operands[3] = x8;
          if (!reg_or_0_operand (operands[3], E_SImode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1DImode:
              if (pattern317 (x2, E_VNx1DImode, E_VNx1BImode) != 0
                  || !(
#line 2409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2548; /* *pred_sbcvnx1di_extended_scalar */

            case E_VNx2DImode:
              if (pattern317 (x2, E_VNx2DImode, E_VNx2BImode) != 0
                  || !(
#line 2409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2549; /* *pred_sbcvnx2di_extended_scalar */

            case E_VNx4DImode:
              if (pattern317 (x2, E_VNx4DImode, E_VNx4BImode) != 0
                  || !(
#line 2409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2550; /* *pred_sbcvnx4di_extended_scalar */

            case E_VNx8DImode:
              if (pattern317 (x2, E_VNx8DImode, E_VNx8BImode) != 0
                  || !(
#line 2409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 2551; /* *pred_sbcvnx8di_extended_scalar */

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_123 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 1);
  operands[2] = x4;
  x5 = XEXP (x3, 2);
  operands[4] = x5;
  x6 = XEXP (x3, 0);
  switch (GET_CODE (x6))
    {
    case CONST_VECTOR:
    case REG:
    case SUBREG:
      operands[3] = x6;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          if (pattern272 (x2, E_VNx1QImode, E_VNx1BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 876; /* pred_mergevnx1qi */

        case E_VNx2QImode:
          if (pattern272 (x2, E_VNx2QImode, E_VNx2BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 877; /* pred_mergevnx2qi */

        case E_VNx4QImode:
          if (pattern272 (x2, E_VNx4QImode, E_VNx4BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 878; /* pred_mergevnx4qi */

        case E_VNx8QImode:
          if (pattern272 (x2, E_VNx8QImode, E_VNx8BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 879; /* pred_mergevnx8qi */

        case E_VNx16QImode:
          if (pattern272 (x2, E_VNx16QImode, E_VNx16BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 880; /* pred_mergevnx16qi */

        case E_VNx32QImode:
          if (pattern272 (x2, E_VNx32QImode, E_VNx32BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 881; /* pred_mergevnx32qi */

        case E_VNx64QImode:
          if (pattern272 (x2, E_VNx64QImode, E_VNx64BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 882; /* pred_mergevnx64qi */

        case E_VNx1HImode:
          if (pattern272 (x2, E_VNx1HImode, E_VNx1BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 883; /* pred_mergevnx1hi */

        case E_VNx2HImode:
          if (pattern272 (x2, E_VNx2HImode, E_VNx2BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 884; /* pred_mergevnx2hi */

        case E_VNx4HImode:
          if (pattern272 (x2, E_VNx4HImode, E_VNx4BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 885; /* pred_mergevnx4hi */

        case E_VNx8HImode:
          if (pattern272 (x2, E_VNx8HImode, E_VNx8BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 886; /* pred_mergevnx8hi */

        case E_VNx16HImode:
          if (pattern272 (x2, E_VNx16HImode, E_VNx16BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 887; /* pred_mergevnx16hi */

        case E_VNx32HImode:
          if (pattern272 (x2, E_VNx32HImode, E_VNx32BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 888; /* pred_mergevnx32hi */

        case E_VNx1SImode:
          if (pattern272 (x2, E_VNx1SImode, E_VNx1BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 889; /* pred_mergevnx1si */

        case E_VNx2SImode:
          if (pattern272 (x2, E_VNx2SImode, E_VNx2BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 890; /* pred_mergevnx2si */

        case E_VNx4SImode:
          if (pattern272 (x2, E_VNx4SImode, E_VNx4BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 891; /* pred_mergevnx4si */

        case E_VNx8SImode:
          if (pattern272 (x2, E_VNx8SImode, E_VNx8BImode) != 0
              || !
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 892; /* pred_mergevnx8si */

        case E_VNx16SImode:
          if (pattern272 (x2, E_VNx16SImode, E_VNx16BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 893; /* pred_mergevnx16si */

        case E_VNx1DImode:
          if (pattern272 (x2, E_VNx1DImode, E_VNx1BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 894; /* pred_mergevnx1di */

        case E_VNx2DImode:
          if (pattern272 (x2, E_VNx2DImode, E_VNx2BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 895; /* pred_mergevnx2di */

        case E_VNx4DImode:
          if (pattern272 (x2, E_VNx4DImode, E_VNx4BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 896; /* pred_mergevnx4di */

        case E_VNx8DImode:
          if (pattern272 (x2, E_VNx8DImode, E_VNx8BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 897; /* pred_mergevnx8di */

        case E_VNx1SFmode:
          if (pattern272 (x2, E_VNx1SFmode, E_VNx1BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 898; /* pred_mergevnx1sf */

        case E_VNx2SFmode:
          if (pattern272 (x2, E_VNx2SFmode, E_VNx2BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 899; /* pred_mergevnx2sf */

        case E_VNx4SFmode:
          if (pattern272 (x2, E_VNx4SFmode, E_VNx4BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 900; /* pred_mergevnx4sf */

        case E_VNx8SFmode:
          if (pattern272 (x2, E_VNx8SFmode, E_VNx8BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 901; /* pred_mergevnx8sf */

        case E_VNx16SFmode:
          if (pattern272 (x2, E_VNx16SFmode, E_VNx16BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 902; /* pred_mergevnx16sf */

        case E_VNx1DFmode:
          if (pattern272 (x2, E_VNx1DFmode, E_VNx1BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 903; /* pred_mergevnx1df */

        case E_VNx2DFmode:
          if (pattern272 (x2, E_VNx2DFmode, E_VNx2BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 904; /* pred_mergevnx2df */

        case E_VNx4DFmode:
          if (pattern272 (x2, E_VNx4DFmode, E_VNx4BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 905; /* pred_mergevnx4df */

        case E_VNx8DFmode:
          if (pattern272 (x2, E_VNx8DFmode, E_VNx8BImode) != 0
              || !(
#line 1087 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 906; /* pred_mergevnx8df */

        default:
          return -1;
        }

    case VEC_DUPLICATE:
      x7 = XEXP (x6, 0);
      switch (GET_CODE (x7))
        {
        case REG:
        case SUBREG:
          operands[3] = x7;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1QImode:
              if (pattern279 (x2, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 907; /* pred_mergevnx1qi_scalar */

            case E_VNx2QImode:
              if (pattern279 (x2, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 908; /* pred_mergevnx2qi_scalar */

            case E_VNx4QImode:
              if (pattern279 (x2, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 909; /* pred_mergevnx4qi_scalar */

            case E_VNx8QImode:
              if (pattern279 (x2, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 910; /* pred_mergevnx8qi_scalar */

            case E_VNx16QImode:
              if (pattern279 (x2, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 911; /* pred_mergevnx16qi_scalar */

            case E_VNx32QImode:
              if (pattern279 (x2, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 912; /* pred_mergevnx32qi_scalar */

            case E_VNx64QImode:
              if (pattern279 (x2, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0
                  || !(
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 913; /* pred_mergevnx64qi_scalar */

            case E_VNx1HImode:
              if (pattern279 (x2, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 914; /* pred_mergevnx1hi_scalar */

            case E_VNx2HImode:
              if (pattern279 (x2, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 915; /* pred_mergevnx2hi_scalar */

            case E_VNx4HImode:
              if (pattern279 (x2, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 916; /* pred_mergevnx4hi_scalar */

            case E_VNx8HImode:
              if (pattern279 (x2, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 917; /* pred_mergevnx8hi_scalar */

            case E_VNx16HImode:
              if (pattern279 (x2, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 918; /* pred_mergevnx16hi_scalar */

            case E_VNx32HImode:
              if (pattern279 (x2, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0
                  || !(
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 919; /* pred_mergevnx32hi_scalar */

            case E_VNx1SImode:
              if (pattern279 (x2, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 920; /* pred_mergevnx1si_scalar */

            case E_VNx2SImode:
              if (pattern279 (x2, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 921; /* pred_mergevnx2si_scalar */

            case E_VNx4SImode:
              if (pattern279 (x2, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 922; /* pred_mergevnx4si_scalar */

            case E_VNx8SImode:
              if (pattern279 (x2, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0
                  || !
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 923; /* pred_mergevnx8si_scalar */

            case E_VNx16SImode:
              if (pattern279 (x2, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0
                  || !(
#line 1107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 924; /* pred_mergevnx16si_scalar */

            case E_VNx1DImode:
              if (pattern279 (x2, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0
                  || !(
#line 1159 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 925; /* *pred_mergevnx1di_scalar */

            case E_VNx2DImode:
              if (pattern279 (x2, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0
                  || !(
#line 1159 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 926; /* *pred_mergevnx2di_scalar */

            case E_VNx4DImode:
              if (pattern279 (x2, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0
                  || !(
#line 1159 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 927; /* *pred_mergevnx4di_scalar */

            case E_VNx8DImode:
              if (pattern279 (x2, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0
                  || !(
#line 1159 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 928; /* *pred_mergevnx8di_scalar */

            case E_VNx1SFmode:
              if (pattern279 (x2, E_VNx1SFmode, E_VNx1BImode, E_SFmode) != 0
                  || !(
#line 6477 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5176; /* pred_mergevnx1sf_scalar */

            case E_VNx2SFmode:
              if (pattern279 (x2, E_VNx2SFmode, E_VNx2BImode, E_SFmode) != 0
                  || !(
#line 6477 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5177; /* pred_mergevnx2sf_scalar */

            case E_VNx4SFmode:
              if (pattern279 (x2, E_VNx4SFmode, E_VNx4BImode, E_SFmode) != 0
                  || !(
#line 6477 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5178; /* pred_mergevnx4sf_scalar */

            case E_VNx8SFmode:
              if (pattern279 (x2, E_VNx8SFmode, E_VNx8BImode, E_SFmode) != 0
                  || !(
#line 6477 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5179; /* pred_mergevnx8sf_scalar */

            case E_VNx16SFmode:
              if (pattern279 (x2, E_VNx16SFmode, E_VNx16BImode, E_SFmode) != 0
                  || !(
#line 6477 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return -1;
              return 5180; /* pred_mergevnx16sf_scalar */

            case E_VNx1DFmode:
              if (pattern279 (x2, E_VNx1DFmode, E_VNx1BImode, E_DFmode) != 0
                  || !(
#line 6477 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5181; /* pred_mergevnx1df_scalar */

            case E_VNx2DFmode:
              if (pattern279 (x2, E_VNx2DFmode, E_VNx2BImode, E_DFmode) != 0
                  || !(
#line 6477 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5182; /* pred_mergevnx2df_scalar */

            case E_VNx4DFmode:
              if (pattern279 (x2, E_VNx4DFmode, E_VNx4BImode, E_DFmode) != 0
                  || !(
#line 6477 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5183; /* pred_mergevnx4df_scalar */

            case E_VNx8DFmode:
              if (pattern279 (x2, E_VNx8DFmode, E_VNx8BImode, E_DFmode) != 0
                  || !(
#line 6477 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5184; /* pred_mergevnx8df_scalar */

            default:
              return -1;
            }

        case SIGN_EXTEND:
          if (GET_MODE (x7) != E_DImode)
            return -1;
          x8 = XEXP (x7, 0);
          operands[3] = x8;
          if (!register_operand (operands[3], E_SImode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1DImode:
              if (pattern293 (x2, E_VNx1DImode, E_VNx1BImode) != 0
                  || !(
#line 1180 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 929; /* *pred_mergevnx1di_extended_scalar */

            case E_VNx2DImode:
              if (pattern293 (x2, E_VNx2DImode, E_VNx2BImode) != 0
                  || !(
#line 1180 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 930; /* *pred_mergevnx2di_extended_scalar */

            case E_VNx4DImode:
              if (pattern293 (x2, E_VNx4DImode, E_VNx4BImode) != 0
                  || !(
#line 1180 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 931; /* *pred_mergevnx4di_extended_scalar */

            case E_VNx8DImode:
              if (pattern293 (x2, E_VNx8DImode, E_VNx8BImode) != 0
                  || !(
#line 1180 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 932; /* *pred_mergevnx8di_extended_scalar */

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_124 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 0);
  operands[5] = x4;
  if (!vector_length_operand (operands[5], E_VOIDmode))
    return -1;
  x5 = XVECEXP (x3, 0, 1);
  operands[6] = x5;
  if (!const_int_operand (operands[6], E_VOIDmode))
    return -1;
  x6 = XVECEXP (x3, 0, 2);
  operands[7] = x6;
  x7 = XEXP (x2, 2);
  operands[1] = x7;
  x8 = XEXP (x2, 1);
  switch (GET_CODE (x8))
    {
    case VEC_MERGE:
      return recog_123 (x1, insn, pnum_clobbers);

    case UNSPEC:
      if (XVECLEN (x8, 0) != 2)
        return -1;
      x9 = XVECEXP (x8, 0, 1);
      operands[4] = x9;
      switch (XINT (x8, 1))
        {
        case 76:
          x10 = XVECEXP (x8, 0, 0);
          if (GET_CODE (x10) != PLUS)
            return -1;
          x11 = XEXP (x10, 0);
          switch (GET_CODE (x11))
            {
            case REG:
            case SUBREG:
              operands[2] = x11;
              x12 = XEXP (x10, 1);
              operands[3] = x12;
              switch (GET_MODE (operands[0]))
                {
                case E_VNx1QImode:
                  if (pattern294 (x2, E_VNx1QImode, E_VNx1BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2456; /* pred_adcvnx1qi */

                case E_VNx2QImode:
                  if (pattern294 (x2, E_VNx2QImode, E_VNx2BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2457; /* pred_adcvnx2qi */

                case E_VNx4QImode:
                  if (pattern294 (x2, E_VNx4QImode, E_VNx4BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2458; /* pred_adcvnx4qi */

                case E_VNx8QImode:
                  if (pattern294 (x2, E_VNx8QImode, E_VNx8BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2459; /* pred_adcvnx8qi */

                case E_VNx16QImode:
                  if (pattern294 (x2, E_VNx16QImode, E_VNx16BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2460; /* pred_adcvnx16qi */

                case E_VNx32QImode:
                  if (pattern294 (x2, E_VNx32QImode, E_VNx32BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2461; /* pred_adcvnx32qi */

                case E_VNx64QImode:
                  if (pattern294 (x2, E_VNx64QImode, E_VNx64BImode) != 0
                      || !(
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 2462; /* pred_adcvnx64qi */

                case E_VNx1HImode:
                  if (pattern294 (x2, E_VNx1HImode, E_VNx1BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2463; /* pred_adcvnx1hi */

                case E_VNx2HImode:
                  if (pattern294 (x2, E_VNx2HImode, E_VNx2BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2464; /* pred_adcvnx2hi */

                case E_VNx4HImode:
                  if (pattern294 (x2, E_VNx4HImode, E_VNx4BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2465; /* pred_adcvnx4hi */

                case E_VNx8HImode:
                  if (pattern294 (x2, E_VNx8HImode, E_VNx8BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2466; /* pred_adcvnx8hi */

                case E_VNx16HImode:
                  if (pattern294 (x2, E_VNx16HImode, E_VNx16BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2467; /* pred_adcvnx16hi */

                case E_VNx32HImode:
                  if (pattern294 (x2, E_VNx32HImode, E_VNx32BImode) != 0
                      || !(
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 2468; /* pred_adcvnx32hi */

                case E_VNx1SImode:
                  if (pattern294 (x2, E_VNx1SImode, E_VNx1BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2469; /* pred_adcvnx1si */

                case E_VNx2SImode:
                  if (pattern294 (x2, E_VNx2SImode, E_VNx2BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2470; /* pred_adcvnx2si */

                case E_VNx4SImode:
                  if (pattern294 (x2, E_VNx4SImode, E_VNx4BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2471; /* pred_adcvnx4si */

                case E_VNx8SImode:
                  if (pattern294 (x2, E_VNx8SImode, E_VNx8BImode) != 0
                      || !
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 2472; /* pred_adcvnx8si */

                case E_VNx16SImode:
                  if (pattern294 (x2, E_VNx16SImode, E_VNx16BImode) != 0
                      || !(
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 2473; /* pred_adcvnx16si */

                case E_VNx1DImode:
                  if (pattern294 (x2, E_VNx1DImode, E_VNx1BImode) != 0
                      || !(
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 2474; /* pred_adcvnx1di */

                case E_VNx2DImode:
                  if (pattern294 (x2, E_VNx2DImode, E_VNx2BImode) != 0
                      || !(
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 2475; /* pred_adcvnx2di */

                case E_VNx4DImode:
                  if (pattern294 (x2, E_VNx4DImode, E_VNx4BImode) != 0
                      || !(
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 2476; /* pred_adcvnx4di */

                case E_VNx8DImode:
                  if (pattern294 (x2, E_VNx8DImode, E_VNx8BImode) != 0
                      || !(
#line 2167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 2477; /* pred_adcvnx8di */

                default:
                  return -1;
                }

            case VEC_DUPLICATE:
              x12 = XEXP (x10, 1);
              operands[2] = x12;
              x13 = XEXP (x11, 0);
              switch (GET_CODE (x13))
                {
                case CONST_INT:
                case CONST_WIDE_INT:
                case CONST_VECTOR:
                case REG:
                case SUBREG:
                  operands[3] = x13;
                  switch (GET_MODE (operands[0]))
                    {
                    case E_VNx1QImode:
                      if (pattern299 (x2, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2500; /* pred_adcvnx1qi_scalar */

                    case E_VNx2QImode:
                      if (pattern299 (x2, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2501; /* pred_adcvnx2qi_scalar */

                    case E_VNx4QImode:
                      if (pattern299 (x2, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2502; /* pred_adcvnx4qi_scalar */

                    case E_VNx8QImode:
                      if (pattern299 (x2, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2503; /* pred_adcvnx8qi_scalar */

                    case E_VNx16QImode:
                      if (pattern299 (x2, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2504; /* pred_adcvnx16qi_scalar */

                    case E_VNx32QImode:
                      if (pattern299 (x2, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2505; /* pred_adcvnx32qi_scalar */

                    case E_VNx64QImode:
                      if (pattern299 (x2, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0
                          || !(
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                        return -1;
                      return 2506; /* pred_adcvnx64qi_scalar */

                    case E_VNx1HImode:
                      if (pattern299 (x2, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2507; /* pred_adcvnx1hi_scalar */

                    case E_VNx2HImode:
                      if (pattern299 (x2, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2508; /* pred_adcvnx2hi_scalar */

                    case E_VNx4HImode:
                      if (pattern299 (x2, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2509; /* pred_adcvnx4hi_scalar */

                    case E_VNx8HImode:
                      if (pattern299 (x2, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2510; /* pred_adcvnx8hi_scalar */

                    case E_VNx16HImode:
                      if (pattern299 (x2, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2511; /* pred_adcvnx16hi_scalar */

                    case E_VNx32HImode:
                      if (pattern299 (x2, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0
                          || !(
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                        return -1;
                      return 2512; /* pred_adcvnx32hi_scalar */

                    case E_VNx1SImode:
                      if (pattern299 (x2, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2513; /* pred_adcvnx1si_scalar */

                    case E_VNx2SImode:
                      if (pattern299 (x2, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2514; /* pred_adcvnx2si_scalar */

                    case E_VNx4SImode:
                      if (pattern299 (x2, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2515; /* pred_adcvnx4si_scalar */

                    case E_VNx8SImode:
                      if (pattern299 (x2, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0
                          || !
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 2516; /* pred_adcvnx8si_scalar */

                    case E_VNx16SImode:
                      if (pattern299 (x2, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0
                          || !(
#line 2216 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                        return -1;
                      return 2517; /* pred_adcvnx16si_scalar */

                    case E_VNx1DImode:
                      if (pattern300 (x2, E_VNx1DImode, E_VNx1BImode) != 0
                          || !(
#line 2299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                        return -1;
                      return 2536; /* *pred_adcvnx1di_scalar */

                    case E_VNx2DImode:
                      if (pattern300 (x2, E_VNx2DImode, E_VNx2BImode) != 0
                          || !(
#line 2299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                        return -1;
                      return 2537; /* *pred_adcvnx2di_scalar */

                    case E_VNx4DImode:
                      if (pattern300 (x2, E_VNx4DImode, E_VNx4BImode) != 0
                          || !(
#line 2299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                        return -1;
                      return 2538; /* *pred_adcvnx4di_scalar */

                    case E_VNx8DImode:
                      if (pattern300 (x2, E_VNx8DImode, E_VNx8BImode) != 0
                          || !(
#line 2299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                        return -1;
                      return 2539; /* *pred_adcvnx8di_scalar */

                    default:
                      return -1;
                    }

                case SIGN_EXTEND:
                  if (GET_MODE (x13) != E_DImode)
                    return -1;
                  x14 = XEXP (x13, 0);
                  operands[3] = x14;
                  if (!reg_or_0_operand (operands[3], E_SImode))
                    return -1;
                  switch (GET_MODE (operands[0]))
                    {
                    case E_VNx1DImode:
                      if (pattern316 (x2, E_VNx1DImode, E_VNx1BImode) != 0
                          || !(
#line 2325 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                        return -1;
                      return 2540; /* *pred_adcvnx1di_extended_scalar */

                    case E_VNx2DImode:
                      if (pattern316 (x2, E_VNx2DImode, E_VNx2BImode) != 0
                          || !(
#line 2325 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                        return -1;
                      return 2541; /* *pred_adcvnx2di_extended_scalar */

                    case E_VNx4DImode:
                      if (pattern316 (x2, E_VNx4DImode, E_VNx4BImode) != 0
                          || !(
#line 2325 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                        return -1;
                      return 2542; /* *pred_adcvnx4di_extended_scalar */

                    case E_VNx8DImode:
                      if (pattern316 (x2, E_VNx8DImode, E_VNx8BImode) != 0
                          || !(
#line 2325 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                        return -1;
                      return 2543; /* *pred_adcvnx8di_extended_scalar */

                    default:
                      return -1;
                    }

                default:
                  return -1;
                }

            default:
              return -1;
            }

        case 77:
          return recog_122 (x1, insn, pnum_clobbers);

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_125 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 1);
  operands[5] = x4;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1BImode:
      if (pattern273 (x2, E_VNx1BImode) != 0
          || !vector_merge_operand (operands[2], E_VNx1BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx1QImode:
          if (!register_operand (operands[4], E_VNx1QImode)
              || !vector_arith_operand (operands[5], E_VNx1QImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR)))
            return 3859; /* *pred_cmpvnx1qi */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3881; /* *pred_cmpvnx1qi_narrow */

        case E_VNx1HImode:
          if (!register_operand (operands[4], E_VNx1HImode)
              || !vector_arith_operand (operands[5], E_VNx1HImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR)))
            return 3866; /* *pred_cmpvnx1hi */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3888; /* *pred_cmpvnx1hi_narrow */

        case E_VNx1SImode:
          if (!register_operand (operands[4], E_VNx1SImode)
              || !vector_arith_operand (operands[5], E_VNx1SImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR)))
            return 3872; /* *pred_cmpvnx1si */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3894; /* *pred_cmpvnx1si_narrow */

        case E_VNx1DImode:
          if (!register_operand (operands[4], E_VNx1DImode)
              || !vector_arith_operand (operands[5], E_VNx1DImode))
            return -1;
          if ((
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3877; /* *pred_cmpvnx1di */
          if (!(
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3899; /* *pred_cmpvnx1di_narrow */

        default:
          return -1;
        }

    case E_VNx2BImode:
      if (pattern273 (x2, E_VNx2BImode) != 0
          || !vector_merge_operand (operands[2], E_VNx2BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx2QImode:
          if (!register_operand (operands[4], E_VNx2QImode)
              || !vector_arith_operand (operands[5], E_VNx2QImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR)))
            return 3860; /* *pred_cmpvnx2qi */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3882; /* *pred_cmpvnx2qi_narrow */

        case E_VNx2HImode:
          if (!register_operand (operands[4], E_VNx2HImode)
              || !vector_arith_operand (operands[5], E_VNx2HImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR)))
            return 3867; /* *pred_cmpvnx2hi */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3889; /* *pred_cmpvnx2hi_narrow */

        case E_VNx2SImode:
          if (!register_operand (operands[4], E_VNx2SImode)
              || !vector_arith_operand (operands[5], E_VNx2SImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR)))
            return 3873; /* *pred_cmpvnx2si */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3895; /* *pred_cmpvnx2si_narrow */

        case E_VNx2DImode:
          if (!register_operand (operands[4], E_VNx2DImode)
              || !vector_arith_operand (operands[5], E_VNx2DImode))
            return -1;
          if ((
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3878; /* *pred_cmpvnx2di */
          if (!(
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3900; /* *pred_cmpvnx2di_narrow */

        default:
          return -1;
        }

    case E_VNx4BImode:
      if (pattern273 (x2, E_VNx4BImode) != 0
          || !vector_merge_operand (operands[2], E_VNx4BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx4QImode:
          if (!register_operand (operands[4], E_VNx4QImode)
              || !vector_arith_operand (operands[5], E_VNx4QImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR)))
            return 3861; /* *pred_cmpvnx4qi */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3883; /* *pred_cmpvnx4qi_narrow */

        case E_VNx4HImode:
          if (!register_operand (operands[4], E_VNx4HImode)
              || !vector_arith_operand (operands[5], E_VNx4HImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR)))
            return 3868; /* *pred_cmpvnx4hi */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3890; /* *pred_cmpvnx4hi_narrow */

        case E_VNx4SImode:
          if (!register_operand (operands[4], E_VNx4SImode)
              || !vector_arith_operand (operands[5], E_VNx4SImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR)))
            return 3874; /* *pred_cmpvnx4si */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3896; /* *pred_cmpvnx4si_narrow */

        case E_VNx4DImode:
          if (!register_operand (operands[4], E_VNx4DImode)
              || !vector_arith_operand (operands[5], E_VNx4DImode))
            return -1;
          if ((
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3879; /* *pred_cmpvnx4di */
          if (!(
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3901; /* *pred_cmpvnx4di_narrow */

        default:
          return -1;
        }

    case E_VNx8BImode:
      if (pattern273 (x2, E_VNx8BImode) != 0
          || !vector_merge_operand (operands[2], E_VNx8BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx8QImode:
          if (!register_operand (operands[4], E_VNx8QImode)
              || !vector_arith_operand (operands[5], E_VNx8QImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR)))
            return 3862; /* *pred_cmpvnx8qi */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3884; /* *pred_cmpvnx8qi_narrow */

        case E_VNx8HImode:
          if (!register_operand (operands[4], E_VNx8HImode)
              || !vector_arith_operand (operands[5], E_VNx8HImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR)))
            return 3869; /* *pred_cmpvnx8hi */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3891; /* *pred_cmpvnx8hi_narrow */

        case E_VNx8SImode:
          if (!register_operand (operands[4], E_VNx8SImode)
              || !vector_arith_operand (operands[5], E_VNx8SImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR)))
            return 3875; /* *pred_cmpvnx8si */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3897; /* *pred_cmpvnx8si_narrow */

        case E_VNx8DImode:
          if (!register_operand (operands[4], E_VNx8DImode)
              || !vector_arith_operand (operands[5], E_VNx8DImode))
            return -1;
          if ((
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3880; /* *pred_cmpvnx8di */
          if (!(
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3902; /* *pred_cmpvnx8di_narrow */

        default:
          return -1;
        }

    case E_VNx16BImode:
      if (pattern273 (x2, E_VNx16BImode) != 0
          || !vector_merge_operand (operands[2], E_VNx16BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx16QImode:
          if (!register_operand (operands[4], E_VNx16QImode)
              || !vector_arith_operand (operands[5], E_VNx16QImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR)))
            return 3863; /* *pred_cmpvnx16qi */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3885; /* *pred_cmpvnx16qi_narrow */

        case E_VNx16HImode:
          if (!register_operand (operands[4], E_VNx16HImode)
              || !vector_arith_operand (operands[5], E_VNx16HImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR)))
            return 3870; /* *pred_cmpvnx16hi */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3892; /* *pred_cmpvnx16hi_narrow */

        case E_VNx16SImode:
          if (!register_operand (operands[4], E_VNx16SImode)
              || !vector_arith_operand (operands[5], E_VNx16SImode))
            return -1;
          if ((
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 3876; /* *pred_cmpvnx16si */
          if (!(
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3898; /* *pred_cmpvnx16si_narrow */

        default:
          return -1;
        }

    case E_VNx32BImode:
      if (pattern273 (x2, E_VNx32BImode) != 0
          || !vector_merge_operand (operands[2], E_VNx32BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx32QImode:
          if (!register_operand (operands[4], E_VNx32QImode)
              || !vector_arith_operand (operands[5], E_VNx32QImode))
            return -1;
          if (
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR)))
            return 3864; /* *pred_cmpvnx32qi */
          if (!
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3886; /* *pred_cmpvnx32qi_narrow */

        case E_VNx32HImode:
          if (!register_operand (operands[4], E_VNx32HImode)
              || !vector_arith_operand (operands[5], E_VNx32HImode))
            return -1;
          if ((
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 3871; /* *pred_cmpvnx32hi */
          if (!(
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3893; /* *pred_cmpvnx32hi_narrow */

        default:
          return -1;
        }

    case E_VNx64BImode:
      if (pattern273 (x2, E_VNx64BImode) != 0
          || !register_operand (operands[4], E_VNx64QImode)
          || !vector_arith_operand (operands[5], E_VNx64QImode)
          || !vector_merge_operand (operands[2], E_VNx64BImode))
        return -1;
      if ((
#line 3631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3865; /* *pred_cmpvnx64qi */
      if (!(
#line 3651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3887; /* *pred_cmpvnx64qi_narrow */

    default:
      return -1;
    }
}

static int
recog_126 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  operands[4] = x4;
  res = recog_125 (x1, insn, pnum_clobbers);
  if (res >= 0)
    return res;
  switch (GET_CODE (operands[3]))
    {
    case NE:
    case EQ:
      if (GET_CODE (x4) != VEC_DUPLICATE)
        return -1;
      x5 = XEXP (x3, 1);
      operands[4] = x5;
      x6 = XEXP (x4, 0);
      switch (GET_CODE (x6))
        {
        case REG:
        case SUBREG:
          operands[5] = x6;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1BImode:
              if (pattern296 (x2, E_VNx1BImode) != 0)
                return -1;
              switch (GET_MODE (x4))
                {
                case E_VNx1QImode:
                  if (!register_operand (operands[5], E_QImode)
                      || !register_operand (operands[4], E_VNx1QImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR)))
                    return 3983; /* *pred_eqnevnx1qi_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4001; /* *pred_eqnevnx1qi_scalar_narrow */

                case E_VNx1HImode:
                  if (!register_operand (operands[5], E_HImode)
                      || !register_operand (operands[4], E_VNx1HImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR)))
                    return 3990; /* *pred_eqnevnx1hi_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4008; /* *pred_eqnevnx1hi_scalar_narrow */

                case E_VNx1SImode:
                  if (!register_operand (operands[5], E_SImode)
                      || !register_operand (operands[4], E_VNx1SImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR)))
                    return 3996; /* *pred_eqnevnx1si_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4014; /* *pred_eqnevnx1si_scalar_narrow */

                case E_VNx1DImode:
                  if (!register_operand (operands[5], E_DImode)
                      || !register_operand (operands[4], E_VNx1DImode))
                    return -1;
                  if ((
#line 3966 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return 4027; /* *pred_eqnevnx1di_scalar */
                  if (!(
#line 3987 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4031; /* *pred_eqnevnx1di_scalar_narrow */

                case E_VNx1SFmode:
                  if (!register_operand (operands[5], E_SFmode)
                      || !register_operand (operands[4], E_VNx1SFmode))
                    return -1;
                  if ((
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 5158; /* *pred_eqnevnx1sf_scalar */
                  if (!(
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return -1;
                  return 5167; /* *pred_eqnevnx1sf_scalar_narrow */

                case E_VNx1DFmode:
                  if (!register_operand (operands[5], E_DFmode)
                      || !register_operand (operands[4], E_VNx1DFmode))
                    return -1;
                  if ((
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 5163; /* *pred_eqnevnx1df_scalar */
                  if (!(
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return -1;
                  return 5172; /* *pred_eqnevnx1df_scalar_narrow */

                default:
                  return -1;
                }

            case E_VNx2BImode:
              if (pattern296 (x2, E_VNx2BImode) != 0)
                return -1;
              switch (GET_MODE (x4))
                {
                case E_VNx2QImode:
                  if (!register_operand (operands[5], E_QImode)
                      || !register_operand (operands[4], E_VNx2QImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR)))
                    return 3984; /* *pred_eqnevnx2qi_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4002; /* *pred_eqnevnx2qi_scalar_narrow */

                case E_VNx2HImode:
                  if (!register_operand (operands[5], E_HImode)
                      || !register_operand (operands[4], E_VNx2HImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR)))
                    return 3991; /* *pred_eqnevnx2hi_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4009; /* *pred_eqnevnx2hi_scalar_narrow */

                case E_VNx2SImode:
                  if (!register_operand (operands[5], E_SImode)
                      || !register_operand (operands[4], E_VNx2SImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR)))
                    return 3997; /* *pred_eqnevnx2si_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4015; /* *pred_eqnevnx2si_scalar_narrow */

                case E_VNx2DImode:
                  if (!register_operand (operands[5], E_DImode)
                      || !register_operand (operands[4], E_VNx2DImode))
                    return -1;
                  if ((
#line 3966 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return 4028; /* *pred_eqnevnx2di_scalar */
                  if (!(
#line 3987 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4032; /* *pred_eqnevnx2di_scalar_narrow */

                case E_VNx2SFmode:
                  if (!register_operand (operands[5], E_SFmode)
                      || !register_operand (operands[4], E_VNx2SFmode))
                    return -1;
                  if ((
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 5159; /* *pred_eqnevnx2sf_scalar */
                  if (!(
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return -1;
                  return 5168; /* *pred_eqnevnx2sf_scalar_narrow */

                case E_VNx2DFmode:
                  if (!register_operand (operands[5], E_DFmode)
                      || !register_operand (operands[4], E_VNx2DFmode))
                    return -1;
                  if ((
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 5164; /* *pred_eqnevnx2df_scalar */
                  if (!(
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return -1;
                  return 5173; /* *pred_eqnevnx2df_scalar_narrow */

                default:
                  return -1;
                }

            case E_VNx4BImode:
              if (pattern296 (x2, E_VNx4BImode) != 0)
                return -1;
              switch (GET_MODE (x4))
                {
                case E_VNx4QImode:
                  if (!register_operand (operands[5], E_QImode)
                      || !register_operand (operands[4], E_VNx4QImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR)))
                    return 3985; /* *pred_eqnevnx4qi_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4003; /* *pred_eqnevnx4qi_scalar_narrow */

                case E_VNx4HImode:
                  if (!register_operand (operands[5], E_HImode)
                      || !register_operand (operands[4], E_VNx4HImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR)))
                    return 3992; /* *pred_eqnevnx4hi_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4010; /* *pred_eqnevnx4hi_scalar_narrow */

                case E_VNx4SImode:
                  if (!register_operand (operands[5], E_SImode)
                      || !register_operand (operands[4], E_VNx4SImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR)))
                    return 3998; /* *pred_eqnevnx4si_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4016; /* *pred_eqnevnx4si_scalar_narrow */

                case E_VNx4DImode:
                  if (!register_operand (operands[5], E_DImode)
                      || !register_operand (operands[4], E_VNx4DImode))
                    return -1;
                  if ((
#line 3966 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return 4029; /* *pred_eqnevnx4di_scalar */
                  if (!(
#line 3987 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4033; /* *pred_eqnevnx4di_scalar_narrow */

                case E_VNx4SFmode:
                  if (!register_operand (operands[5], E_SFmode)
                      || !register_operand (operands[4], E_VNx4SFmode))
                    return -1;
                  if ((
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 5160; /* *pred_eqnevnx4sf_scalar */
                  if (!(
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return -1;
                  return 5169; /* *pred_eqnevnx4sf_scalar_narrow */

                case E_VNx4DFmode:
                  if (!register_operand (operands[5], E_DFmode)
                      || !register_operand (operands[4], E_VNx4DFmode))
                    return -1;
                  if ((
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 5165; /* *pred_eqnevnx4df_scalar */
                  if (!(
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return -1;
                  return 5174; /* *pred_eqnevnx4df_scalar_narrow */

                default:
                  return -1;
                }

            case E_VNx8BImode:
              if (pattern296 (x2, E_VNx8BImode) != 0)
                return -1;
              switch (GET_MODE (x4))
                {
                case E_VNx8QImode:
                  if (!register_operand (operands[5], E_QImode)
                      || !register_operand (operands[4], E_VNx8QImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR)))
                    return 3986; /* *pred_eqnevnx8qi_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4004; /* *pred_eqnevnx8qi_scalar_narrow */

                case E_VNx8HImode:
                  if (!register_operand (operands[5], E_HImode)
                      || !register_operand (operands[4], E_VNx8HImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR)))
                    return 3993; /* *pred_eqnevnx8hi_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4011; /* *pred_eqnevnx8hi_scalar_narrow */

                case E_VNx8SImode:
                  if (!register_operand (operands[5], E_SImode)
                      || !register_operand (operands[4], E_VNx8SImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR)))
                    return 3999; /* *pred_eqnevnx8si_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4017; /* *pred_eqnevnx8si_scalar_narrow */

                case E_VNx8DImode:
                  if (!register_operand (operands[5], E_DImode)
                      || !register_operand (operands[4], E_VNx8DImode))
                    return -1;
                  if ((
#line 3966 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return 4030; /* *pred_eqnevnx8di_scalar */
                  if (!(
#line 3987 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return -1;
                  return 4034; /* *pred_eqnevnx8di_scalar_narrow */

                case E_VNx8SFmode:
                  if (!register_operand (operands[5], E_SFmode)
                      || !register_operand (operands[4], E_VNx8SFmode))
                    return -1;
                  if ((
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 5161; /* *pred_eqnevnx8sf_scalar */
                  if (!(
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return -1;
                  return 5170; /* *pred_eqnevnx8sf_scalar_narrow */

                case E_VNx8DFmode:
                  if (!register_operand (operands[5], E_DFmode)
                      || !register_operand (operands[4], E_VNx8DFmode))
                    return -1;
                  if ((
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 5166; /* *pred_eqnevnx8df_scalar */
                  if (!(
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return -1;
                  return 5175; /* *pred_eqnevnx8df_scalar_narrow */

                default:
                  return -1;
                }

            case E_VNx16BImode:
              if (pattern296 (x2, E_VNx16BImode) != 0)
                return -1;
              switch (GET_MODE (x4))
                {
                case E_VNx16QImode:
                  if (!register_operand (operands[5], E_QImode)
                      || !register_operand (operands[4], E_VNx16QImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR)))
                    return 3987; /* *pred_eqnevnx16qi_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4005; /* *pred_eqnevnx16qi_scalar_narrow */

                case E_VNx16HImode:
                  if (!register_operand (operands[5], E_HImode)
                      || !register_operand (operands[4], E_VNx16HImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR)))
                    return 3994; /* *pred_eqnevnx16hi_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4012; /* *pred_eqnevnx16hi_scalar_narrow */

                case E_VNx16SImode:
                  if (!register_operand (operands[5], E_SImode)
                      || !register_operand (operands[4], E_VNx16SImode))
                    return -1;
                  if ((
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return 4000; /* *pred_eqnevnx16si_scalar */
                  if (!(
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4018; /* *pred_eqnevnx16si_scalar_narrow */

                case E_VNx16SFmode:
                  if (!register_operand (operands[5], E_SFmode)
                      || !register_operand (operands[4], E_VNx16SFmode))
                    return -1;
                  if ((
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                    return 5162; /* *pred_eqnevnx16sf_scalar */
                  if (!(
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 5171; /* *pred_eqnevnx16sf_scalar_narrow */

                default:
                  return -1;
                }

            case E_VNx32BImode:
              if (pattern296 (x2, E_VNx32BImode) != 0)
                return -1;
              switch (GET_MODE (x4))
                {
                case E_VNx32QImode:
                  if (!register_operand (operands[5], E_QImode)
                      || !register_operand (operands[4], E_VNx32QImode))
                    return -1;
                  if (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR)))
                    return 3988; /* *pred_eqnevnx32qi_scalar */
                  if (!
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR)))
                    return -1;
                  return 4006; /* *pred_eqnevnx32qi_scalar_narrow */

                case E_VNx32HImode:
                  if (!register_operand (operands[5], E_HImode)
                      || !register_operand (operands[4], E_VNx32HImode))
                    return -1;
                  if ((
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return 3995; /* *pred_eqnevnx32hi_scalar */
                  if (!(
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4013; /* *pred_eqnevnx32hi_scalar_narrow */

                default:
                  return -1;
                }

            case E_VNx64BImode:
              if (!register_operand (operands[0], E_VNx64BImode)
                  || GET_MODE (x2) != E_VNx64BImode)
                return -1;
              x7 = XEXP (x2, 0);
              if (GET_MODE (x7) != E_VNx64BImode
                  || !vector_mask_operand (operands[1], E_VNx64BImode)
                  || !equality_operator (operands[3], E_VNx64BImode)
                  || GET_MODE (x4) != E_VNx64QImode
                  || !register_operand (operands[5], E_QImode)
                  || !register_operand (operands[4], E_VNx64QImode)
                  || !vector_merge_operand (operands[2], E_VNx64BImode))
                return -1;
              if ((
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return 3989; /* *pred_eqnevnx64qi_scalar */
              if (!(
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 4007; /* *pred_eqnevnx64qi_scalar_narrow */

            default:
              return -1;
            }

        case SIGN_EXTEND:
          if (GET_MODE (x6) != E_DImode)
            return -1;
          x8 = XEXP (x6, 0);
          operands[5] = x8;
          if (!register_operand (operands[5], E_SImode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1BImode:
              if (pattern314 (x2, E_VNx1BImode, E_VNx1DImode) != 0)
                return -1;
              if ((
#line 4052 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return 4043; /* *pred_eqnevnx1di_extended_scalar */
              if (!(
#line 4073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 4047; /* *pred_eqnevnx1di_extended_scalar_narrow */

            case E_VNx2BImode:
              if (pattern314 (x2, E_VNx2BImode, E_VNx2DImode) != 0)
                return -1;
              if ((
#line 4052 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return 4044; /* *pred_eqnevnx2di_extended_scalar */
              if (!(
#line 4073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 4048; /* *pred_eqnevnx2di_extended_scalar_narrow */

            case E_VNx4BImode:
              if (pattern314 (x2, E_VNx4BImode, E_VNx4DImode) != 0)
                return -1;
              if ((
#line 4052 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return 4045; /* *pred_eqnevnx4di_extended_scalar */
              if (!(
#line 4073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 4049; /* *pred_eqnevnx4di_extended_scalar_narrow */

            case E_VNx8BImode:
              if (pattern314 (x2, E_VNx8BImode, E_VNx8DImode) != 0)
                return -1;
              if ((
#line 4052 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return 4046; /* *pred_eqnevnx8di_extended_scalar */
              if (!(
#line 4073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 4050; /* *pred_eqnevnx8di_extended_scalar_narrow */

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_127 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  operands[4] = x4;
  x5 = XEXP (x3, 1);
  operands[5] = x5;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1BImode:
      if (pattern274 (x2, E_VNx1BImode) != 0
          || !vector_merge_operand (operands[2], E_VNx1BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx1QImode:
          if (!register_operand (operands[4], E_VNx1QImode)
              || !vector_neg_arith_operand (operands[5], E_VNx1QImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR)))
            return 3903; /* *pred_ltgevnx1qi */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3925; /* *pred_ltgevnx1qi_narrow */

        case E_VNx1HImode:
          if (!register_operand (operands[4], E_VNx1HImode)
              || !vector_neg_arith_operand (operands[5], E_VNx1HImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR)))
            return 3910; /* *pred_ltgevnx1hi */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3932; /* *pred_ltgevnx1hi_narrow */

        case E_VNx1SImode:
          if (!register_operand (operands[4], E_VNx1SImode)
              || !vector_neg_arith_operand (operands[5], E_VNx1SImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR)))
            return 3916; /* *pred_ltgevnx1si */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3938; /* *pred_ltgevnx1si_narrow */

        case E_VNx1DImode:
          if (!register_operand (operands[4], E_VNx1DImode)
              || !vector_neg_arith_operand (operands[5], E_VNx1DImode))
            return -1;
          if ((
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3921; /* *pred_ltgevnx1di */
          if (!(
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3943; /* *pred_ltgevnx1di_narrow */

        default:
          return -1;
        }

    case E_VNx2BImode:
      if (pattern274 (x2, E_VNx2BImode) != 0
          || !vector_merge_operand (operands[2], E_VNx2BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx2QImode:
          if (!register_operand (operands[4], E_VNx2QImode)
              || !vector_neg_arith_operand (operands[5], E_VNx2QImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR)))
            return 3904; /* *pred_ltgevnx2qi */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3926; /* *pred_ltgevnx2qi_narrow */

        case E_VNx2HImode:
          if (!register_operand (operands[4], E_VNx2HImode)
              || !vector_neg_arith_operand (operands[5], E_VNx2HImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR)))
            return 3911; /* *pred_ltgevnx2hi */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3933; /* *pred_ltgevnx2hi_narrow */

        case E_VNx2SImode:
          if (!register_operand (operands[4], E_VNx2SImode)
              || !vector_neg_arith_operand (operands[5], E_VNx2SImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR)))
            return 3917; /* *pred_ltgevnx2si */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3939; /* *pred_ltgevnx2si_narrow */

        case E_VNx2DImode:
          if (!register_operand (operands[4], E_VNx2DImode)
              || !vector_neg_arith_operand (operands[5], E_VNx2DImode))
            return -1;
          if ((
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3922; /* *pred_ltgevnx2di */
          if (!(
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3944; /* *pred_ltgevnx2di_narrow */

        default:
          return -1;
        }

    case E_VNx4BImode:
      if (pattern274 (x2, E_VNx4BImode) != 0
          || !vector_merge_operand (operands[2], E_VNx4BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx4QImode:
          if (!register_operand (operands[4], E_VNx4QImode)
              || !vector_neg_arith_operand (operands[5], E_VNx4QImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR)))
            return 3905; /* *pred_ltgevnx4qi */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3927; /* *pred_ltgevnx4qi_narrow */

        case E_VNx4HImode:
          if (!register_operand (operands[4], E_VNx4HImode)
              || !vector_neg_arith_operand (operands[5], E_VNx4HImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR)))
            return 3912; /* *pred_ltgevnx4hi */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3934; /* *pred_ltgevnx4hi_narrow */

        case E_VNx4SImode:
          if (!register_operand (operands[4], E_VNx4SImode)
              || !vector_neg_arith_operand (operands[5], E_VNx4SImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR)))
            return 3918; /* *pred_ltgevnx4si */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3940; /* *pred_ltgevnx4si_narrow */

        case E_VNx4DImode:
          if (!register_operand (operands[4], E_VNx4DImode)
              || !vector_neg_arith_operand (operands[5], E_VNx4DImode))
            return -1;
          if ((
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3923; /* *pred_ltgevnx4di */
          if (!(
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3945; /* *pred_ltgevnx4di_narrow */

        default:
          return -1;
        }

    case E_VNx8BImode:
      if (pattern274 (x2, E_VNx8BImode) != 0
          || !vector_merge_operand (operands[2], E_VNx8BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx8QImode:
          if (!register_operand (operands[4], E_VNx8QImode)
              || !vector_neg_arith_operand (operands[5], E_VNx8QImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR)))
            return 3906; /* *pred_ltgevnx8qi */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3928; /* *pred_ltgevnx8qi_narrow */

        case E_VNx8HImode:
          if (!register_operand (operands[4], E_VNx8HImode)
              || !vector_neg_arith_operand (operands[5], E_VNx8HImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR)))
            return 3913; /* *pred_ltgevnx8hi */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3935; /* *pred_ltgevnx8hi_narrow */

        case E_VNx8SImode:
          if (!register_operand (operands[4], E_VNx8SImode)
              || !vector_neg_arith_operand (operands[5], E_VNx8SImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR)))
            return 3919; /* *pred_ltgevnx8si */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3941; /* *pred_ltgevnx8si_narrow */

        case E_VNx8DImode:
          if (!register_operand (operands[4], E_VNx8DImode)
              || !vector_neg_arith_operand (operands[5], E_VNx8DImode))
            return -1;
          if ((
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 3924; /* *pred_ltgevnx8di */
          if (!(
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 3946; /* *pred_ltgevnx8di_narrow */

        default:
          return -1;
        }

    case E_VNx16BImode:
      if (pattern274 (x2, E_VNx16BImode) != 0
          || !vector_merge_operand (operands[2], E_VNx16BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx16QImode:
          if (!register_operand (operands[4], E_VNx16QImode)
              || !vector_neg_arith_operand (operands[5], E_VNx16QImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR)))
            return 3907; /* *pred_ltgevnx16qi */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3929; /* *pred_ltgevnx16qi_narrow */

        case E_VNx16HImode:
          if (!register_operand (operands[4], E_VNx16HImode)
              || !vector_neg_arith_operand (operands[5], E_VNx16HImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR)))
            return 3914; /* *pred_ltgevnx16hi */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3936; /* *pred_ltgevnx16hi_narrow */

        case E_VNx16SImode:
          if (!register_operand (operands[4], E_VNx16SImode)
              || !vector_neg_arith_operand (operands[5], E_VNx16SImode))
            return -1;
          if ((
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 3920; /* *pred_ltgevnx16si */
          if (!(
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3942; /* *pred_ltgevnx16si_narrow */

        default:
          return -1;
        }

    case E_VNx32BImode:
      if (pattern274 (x2, E_VNx32BImode) != 0
          || !vector_merge_operand (operands[2], E_VNx32BImode))
        return -1;
      switch (GET_MODE (operands[4]))
        {
        case E_VNx32QImode:
          if (!register_operand (operands[4], E_VNx32QImode)
              || !vector_neg_arith_operand (operands[5], E_VNx32QImode))
            return -1;
          if (
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR)))
            return 3908; /* *pred_ltgevnx32qi */
          if (!
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR)))
            return -1;
          return 3930; /* *pred_ltgevnx32qi_narrow */

        case E_VNx32HImode:
          if (!register_operand (operands[4], E_VNx32HImode)
              || !vector_neg_arith_operand (operands[5], E_VNx32HImode))
            return -1;
          if ((
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 3915; /* *pred_ltgevnx32hi */
          if (!(
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3937; /* *pred_ltgevnx32hi_narrow */

        default:
          return -1;
        }

    case E_VNx64BImode:
      if (pattern274 (x2, E_VNx64BImode) != 0
          || !register_operand (operands[4], E_VNx64QImode)
          || !vector_neg_arith_operand (operands[5], E_VNx64QImode)
          || !vector_merge_operand (operands[2], E_VNx64BImode))
        return -1;
      if ((
#line 3688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return 3909; /* *pred_ltgevnx64qi */
      if (!(
#line 3708 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
        return -1;
      return 3931; /* *pred_ltgevnx64qi_narrow */

    default:
      return -1;
    }
}

static int
recog_128 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 1);
  if (GET_CODE (x4) != VEC_DUPLICATE)
    return -1;
  x5 = XEXP (x4, 0);
  switch (GET_CODE (x5))
    {
    case REG:
    case SUBREG:
      operands[5] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1BImode:
          if (pattern289 (x2, E_VNx1BImode) != 0
              || !vector_merge_operand (operands[2], E_VNx1BImode))
            return -1;
          switch (GET_MODE (operands[4]))
            {
            case E_VNx1QImode:
              if (!register_operand (operands[4], E_VNx1QImode)
                  || GET_MODE (x4) != E_VNx1QImode
                  || !register_operand (operands[5], E_QImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR)))
                return 3947; /* *pred_cmpvnx1qi_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3965; /* *pred_cmpvnx1qi_scalar_narrow */

            case E_VNx1HImode:
              if (!register_operand (operands[4], E_VNx1HImode)
                  || GET_MODE (x4) != E_VNx1HImode
                  || !register_operand (operands[5], E_HImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR)))
                return 3954; /* *pred_cmpvnx1hi_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3972; /* *pred_cmpvnx1hi_scalar_narrow */

            case E_VNx1SImode:
              if (!register_operand (operands[4], E_VNx1SImode)
                  || GET_MODE (x4) != E_VNx1SImode
                  || !register_operand (operands[5], E_SImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR)))
                return 3960; /* *pred_cmpvnx1si_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3978; /* *pred_cmpvnx1si_scalar_narrow */

            case E_VNx1DImode:
              if (!register_operand (operands[4], E_VNx1DImode)
                  || GET_MODE (x4) != E_VNx1DImode
                  || !register_operand (operands[5], E_DImode))
                return -1;
              if ((
#line 3924 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return 4019; /* *pred_cmpvnx1di_scalar */
              if (!(
#line 3945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 4023; /* *pred_cmpvnx1di_scalar_narrow */

            default:
              return -1;
            }

        case E_VNx2BImode:
          if (pattern289 (x2, E_VNx2BImode) != 0
              || !vector_merge_operand (operands[2], E_VNx2BImode))
            return -1;
          switch (GET_MODE (operands[4]))
            {
            case E_VNx2QImode:
              if (!register_operand (operands[4], E_VNx2QImode)
                  || GET_MODE (x4) != E_VNx2QImode
                  || !register_operand (operands[5], E_QImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR)))
                return 3948; /* *pred_cmpvnx2qi_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3966; /* *pred_cmpvnx2qi_scalar_narrow */

            case E_VNx2HImode:
              if (!register_operand (operands[4], E_VNx2HImode)
                  || GET_MODE (x4) != E_VNx2HImode
                  || !register_operand (operands[5], E_HImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR)))
                return 3955; /* *pred_cmpvnx2hi_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3973; /* *pred_cmpvnx2hi_scalar_narrow */

            case E_VNx2SImode:
              if (!register_operand (operands[4], E_VNx2SImode)
                  || GET_MODE (x4) != E_VNx2SImode
                  || !register_operand (operands[5], E_SImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR)))
                return 3961; /* *pred_cmpvnx2si_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3979; /* *pred_cmpvnx2si_scalar_narrow */

            case E_VNx2DImode:
              if (!register_operand (operands[4], E_VNx2DImode)
                  || GET_MODE (x4) != E_VNx2DImode
                  || !register_operand (operands[5], E_DImode))
                return -1;
              if ((
#line 3924 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return 4020; /* *pred_cmpvnx2di_scalar */
              if (!(
#line 3945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 4024; /* *pred_cmpvnx2di_scalar_narrow */

            default:
              return -1;
            }

        case E_VNx4BImode:
          if (pattern289 (x2, E_VNx4BImode) != 0
              || !vector_merge_operand (operands[2], E_VNx4BImode))
            return -1;
          switch (GET_MODE (operands[4]))
            {
            case E_VNx4QImode:
              if (!register_operand (operands[4], E_VNx4QImode)
                  || GET_MODE (x4) != E_VNx4QImode
                  || !register_operand (operands[5], E_QImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR)))
                return 3949; /* *pred_cmpvnx4qi_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3967; /* *pred_cmpvnx4qi_scalar_narrow */

            case E_VNx4HImode:
              if (!register_operand (operands[4], E_VNx4HImode)
                  || GET_MODE (x4) != E_VNx4HImode
                  || !register_operand (operands[5], E_HImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR)))
                return 3956; /* *pred_cmpvnx4hi_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3974; /* *pred_cmpvnx4hi_scalar_narrow */

            case E_VNx4SImode:
              if (!register_operand (operands[4], E_VNx4SImode)
                  || GET_MODE (x4) != E_VNx4SImode
                  || !register_operand (operands[5], E_SImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR)))
                return 3962; /* *pred_cmpvnx4si_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3980; /* *pred_cmpvnx4si_scalar_narrow */

            case E_VNx4DImode:
              if (!register_operand (operands[4], E_VNx4DImode)
                  || GET_MODE (x4) != E_VNx4DImode
                  || !register_operand (operands[5], E_DImode))
                return -1;
              if ((
#line 3924 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return 4021; /* *pred_cmpvnx4di_scalar */
              if (!(
#line 3945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 4025; /* *pred_cmpvnx4di_scalar_narrow */

            default:
              return -1;
            }

        case E_VNx8BImode:
          if (pattern289 (x2, E_VNx8BImode) != 0
              || !vector_merge_operand (operands[2], E_VNx8BImode))
            return -1;
          switch (GET_MODE (operands[4]))
            {
            case E_VNx8QImode:
              if (!register_operand (operands[4], E_VNx8QImode)
                  || GET_MODE (x4) != E_VNx8QImode
                  || !register_operand (operands[5], E_QImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR)))
                return 3950; /* *pred_cmpvnx8qi_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3968; /* *pred_cmpvnx8qi_scalar_narrow */

            case E_VNx8HImode:
              if (!register_operand (operands[4], E_VNx8HImode)
                  || GET_MODE (x4) != E_VNx8HImode
                  || !register_operand (operands[5], E_HImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR)))
                return 3957; /* *pred_cmpvnx8hi_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3975; /* *pred_cmpvnx8hi_scalar_narrow */

            case E_VNx8SImode:
              if (!register_operand (operands[4], E_VNx8SImode)
                  || GET_MODE (x4) != E_VNx8SImode
                  || !register_operand (operands[5], E_SImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR)))
                return 3963; /* *pred_cmpvnx8si_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3981; /* *pred_cmpvnx8si_scalar_narrow */

            case E_VNx8DImode:
              if (!register_operand (operands[4], E_VNx8DImode)
                  || GET_MODE (x4) != E_VNx8DImode
                  || !register_operand (operands[5], E_DImode))
                return -1;
              if ((
#line 3924 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return 4022; /* *pred_cmpvnx8di_scalar */
              if (!(
#line 3945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 4026; /* *pred_cmpvnx8di_scalar_narrow */

            default:
              return -1;
            }

        case E_VNx16BImode:
          if (pattern289 (x2, E_VNx16BImode) != 0
              || !vector_merge_operand (operands[2], E_VNx16BImode))
            return -1;
          switch (GET_MODE (operands[4]))
            {
            case E_VNx16QImode:
              if (!register_operand (operands[4], E_VNx16QImode)
                  || GET_MODE (x4) != E_VNx16QImode
                  || !register_operand (operands[5], E_QImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR)))
                return 3951; /* *pred_cmpvnx16qi_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3969; /* *pred_cmpvnx16qi_scalar_narrow */

            case E_VNx16HImode:
              if (!register_operand (operands[4], E_VNx16HImode)
                  || GET_MODE (x4) != E_VNx16HImode
                  || !register_operand (operands[5], E_HImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR)))
                return 3958; /* *pred_cmpvnx16hi_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3976; /* *pred_cmpvnx16hi_scalar_narrow */

            case E_VNx16SImode:
              if (!register_operand (operands[4], E_VNx16SImode)
                  || GET_MODE (x4) != E_VNx16SImode
                  || !register_operand (operands[5], E_SImode))
                return -1;
              if ((
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return 3964; /* *pred_cmpvnx16si_scalar */
              if (!(
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 3982; /* *pred_cmpvnx16si_scalar_narrow */

            default:
              return -1;
            }

        case E_VNx32BImode:
          if (pattern289 (x2, E_VNx32BImode) != 0
              || !vector_merge_operand (operands[2], E_VNx32BImode))
            return -1;
          switch (GET_MODE (operands[4]))
            {
            case E_VNx32QImode:
              if (!register_operand (operands[4], E_VNx32QImode)
                  || GET_MODE (x4) != E_VNx32QImode
                  || !register_operand (operands[5], E_QImode))
                return -1;
              if (
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR)))
                return 3952; /* *pred_cmpvnx32qi_scalar */
              if (!
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR)))
                return -1;
              return 3970; /* *pred_cmpvnx32qi_scalar_narrow */

            case E_VNx32HImode:
              if (!register_operand (operands[4], E_VNx32HImode)
                  || GET_MODE (x4) != E_VNx32HImode
                  || !register_operand (operands[5], E_HImode))
                return -1;
              if ((
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return 3959; /* *pred_cmpvnx32hi_scalar */
              if (!(
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 3977; /* *pred_cmpvnx32hi_scalar_narrow */

            default:
              return -1;
            }

        case E_VNx64BImode:
          if (pattern289 (x2, E_VNx64BImode) != 0
              || pattern318 (x4, E_VNx64BImode, E_QImode, E_VNx64QImode) != 0)
            return -1;
          if ((
#line 3747 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 3953; /* *pred_cmpvnx64qi_scalar */
          if (!(
#line 3768 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 3971; /* *pred_cmpvnx64qi_scalar_narrow */

        default:
          return -1;
        }

    case SIGN_EXTEND:
      if (GET_MODE (x5) != E_DImode)
        return -1;
      x6 = XEXP (x5, 0);
      operands[5] = x6;
      if (!register_operand (operands[5], E_SImode))
        return -1;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1BImode:
          if (pattern302 (x2, E_VNx1BImode, E_VNx1DImode) != 0)
            return -1;
          if ((
#line 4009 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4035; /* *pred_cmpvnx1di_extended_scalar */
          if (!(
#line 4030 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 4039; /* *pred_cmpvnx1di_extended_scalar_narrow */

        case E_VNx2BImode:
          if (pattern302 (x2, E_VNx2BImode, E_VNx2DImode) != 0)
            return -1;
          if ((
#line 4009 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4036; /* *pred_cmpvnx2di_extended_scalar */
          if (!(
#line 4030 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 4040; /* *pred_cmpvnx2di_extended_scalar_narrow */

        case E_VNx4BImode:
          if (pattern302 (x2, E_VNx4BImode, E_VNx4DImode) != 0)
            return -1;
          if ((
#line 4009 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4037; /* *pred_cmpvnx4di_extended_scalar */
          if (!(
#line 4030 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 4041; /* *pred_cmpvnx4di_extended_scalar_narrow */

        case E_VNx8BImode:
          if (pattern302 (x2, E_VNx8BImode, E_VNx8DImode) != 0)
            return -1;
          if ((
#line 4009 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return 4038; /* *pred_cmpvnx8di_extended_scalar */
          if (!(
#line 4030 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 4042; /* *pred_cmpvnx8di_extended_scalar_narrow */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_129 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 3);
  if (!const_int_operand (x4, E_VOIDmode))
    return -1;
  x5 = XEXP (x2, 2);
  operands[2] = x5;
  x6 = XEXP (x2, 1);
  switch (GET_CODE (x6))
    {
    case UNSPEC:
      switch (XVECLEN (x6, 0))
        {
        case 2:
          if (XINT (x6, 1) != 70)
            return -1;
          x7 = XVECEXP (x3, 0, 1);
          operands[5] = x7;
          x8 = XVECEXP (x3, 0, 2);
          operands[6] = x8;
          operands[7] = x4;
          x9 = XVECEXP (x6, 0, 0);
          operands[3] = x9;
          x10 = XVECEXP (x6, 0, 1);
          operands[4] = x10;
          if (!pmode_reg_or_0_operand (operands[4], E_VOIDmode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1QImode:
              if (pattern280 (x2, E_VNx1QImode, E_VNx1BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 968; /* pred_strided_loadvnx1qi */

            case E_VNx2QImode:
              if (pattern280 (x2, E_VNx2QImode, E_VNx2BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 969; /* pred_strided_loadvnx2qi */

            case E_VNx4QImode:
              if (pattern280 (x2, E_VNx4QImode, E_VNx4BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 970; /* pred_strided_loadvnx4qi */

            case E_VNx8QImode:
              if (pattern280 (x2, E_VNx8QImode, E_VNx8BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 971; /* pred_strided_loadvnx8qi */

            case E_VNx16QImode:
              if (pattern280 (x2, E_VNx16QImode, E_VNx16BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 972; /* pred_strided_loadvnx16qi */

            case E_VNx32QImode:
              if (pattern280 (x2, E_VNx32QImode, E_VNx32BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 973; /* pred_strided_loadvnx32qi */

            case E_VNx64QImode:
              if (pattern280 (x2, E_VNx64QImode, E_VNx64BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 974; /* pred_strided_loadvnx64qi */

            case E_VNx1HImode:
              if (pattern280 (x2, E_VNx1HImode, E_VNx1BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 975; /* pred_strided_loadvnx1hi */

            case E_VNx2HImode:
              if (pattern280 (x2, E_VNx2HImode, E_VNx2BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 976; /* pred_strided_loadvnx2hi */

            case E_VNx4HImode:
              if (pattern280 (x2, E_VNx4HImode, E_VNx4BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 977; /* pred_strided_loadvnx4hi */

            case E_VNx8HImode:
              if (pattern280 (x2, E_VNx8HImode, E_VNx8BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 978; /* pred_strided_loadvnx8hi */

            case E_VNx16HImode:
              if (pattern280 (x2, E_VNx16HImode, E_VNx16BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 979; /* pred_strided_loadvnx16hi */

            case E_VNx32HImode:
              if (pattern280 (x2, E_VNx32HImode, E_VNx32BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 980; /* pred_strided_loadvnx32hi */

            case E_VNx1SImode:
              if (pattern280 (x2, E_VNx1SImode, E_VNx1BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 981; /* pred_strided_loadvnx1si */

            case E_VNx2SImode:
              if (pattern280 (x2, E_VNx2SImode, E_VNx2BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 982; /* pred_strided_loadvnx2si */

            case E_VNx4SImode:
              if (pattern280 (x2, E_VNx4SImode, E_VNx4BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 983; /* pred_strided_loadvnx4si */

            case E_VNx8SImode:
              if (pattern280 (x2, E_VNx8SImode, E_VNx8BImode) != 0
                  || !
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return -1;
              return 984; /* pred_strided_loadvnx8si */

            case E_VNx16SImode:
              if (pattern280 (x2, E_VNx16SImode, E_VNx16BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 985; /* pred_strided_loadvnx16si */

            case E_VNx1DImode:
              if (pattern280 (x2, E_VNx1DImode, E_VNx1BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 986; /* pred_strided_loadvnx1di */

            case E_VNx2DImode:
              if (pattern280 (x2, E_VNx2DImode, E_VNx2BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 987; /* pred_strided_loadvnx2di */

            case E_VNx4DImode:
              if (pattern280 (x2, E_VNx4DImode, E_VNx4BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 988; /* pred_strided_loadvnx4di */

            case E_VNx8DImode:
              if (pattern280 (x2, E_VNx8DImode, E_VNx8BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return -1;
              return 989; /* pred_strided_loadvnx8di */

            case E_VNx1SFmode:
              if (pattern280 (x2, E_VNx1SFmode, E_VNx1BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 990; /* pred_strided_loadvnx1sf */

            case E_VNx2SFmode:
              if (pattern280 (x2, E_VNx2SFmode, E_VNx2BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 991; /* pred_strided_loadvnx2sf */

            case E_VNx4SFmode:
              if (pattern280 (x2, E_VNx4SFmode, E_VNx4BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 992; /* pred_strided_loadvnx4sf */

            case E_VNx8SFmode:
              if (pattern280 (x2, E_VNx8SFmode, E_VNx8BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 993; /* pred_strided_loadvnx8sf */

            case E_VNx16SFmode:
              if (pattern280 (x2, E_VNx16SFmode, E_VNx16BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return -1;
              return 994; /* pred_strided_loadvnx16sf */

            case E_VNx1DFmode:
              if (pattern280 (x2, E_VNx1DFmode, E_VNx1BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 995; /* pred_strided_loadvnx1df */

            case E_VNx2DFmode:
              if (pattern280 (x2, E_VNx2DFmode, E_VNx2BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 996; /* pred_strided_loadvnx2df */

            case E_VNx4DFmode:
              if (pattern280 (x2, E_VNx4DFmode, E_VNx4BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 997; /* pred_strided_loadvnx4df */

            case E_VNx8DFmode:
              if (pattern280 (x2, E_VNx8DFmode, E_VNx8BImode) != 0
                  || !(
#line 1372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 998; /* pred_strided_loadvnx8df */

            default:
              return -1;
            }

        case 1:
          x7 = XVECEXP (x3, 0, 1);
          operands[4] = x7;
          x8 = XVECEXP (x3, 0, 2);
          operands[5] = x8;
          operands[6] = x4;
          x9 = XVECEXP (x6, 0, 0);
          operands[3] = x9;
          switch (XINT (x6, 1))
            {
            case 90:
              switch (GET_MODE (operands[0]))
                {
                case E_VNx1BImode:
                  if (pattern254 (x2, E_VNx1BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4535; /* pred_sbfvnx1bi */

                case E_VNx2BImode:
                  if (pattern254 (x2, E_VNx2BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4538; /* pred_sbfvnx2bi */

                case E_VNx4BImode:
                  if (pattern254 (x2, E_VNx4BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4541; /* pred_sbfvnx4bi */

                case E_VNx8BImode:
                  if (pattern254 (x2, E_VNx8BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4544; /* pred_sbfvnx8bi */

                case E_VNx16BImode:
                  if (pattern254 (x2, E_VNx16BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4547; /* pred_sbfvnx16bi */

                case E_VNx32BImode:
                  if (pattern254 (x2, E_VNx32BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4550; /* pred_sbfvnx32bi */

                case E_VNx64BImode:
                  if (pattern254 (x2, E_VNx64BImode) != 0
                      || !(
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4553; /* pred_sbfvnx64bi */

                default:
                  return -1;
                }

            case 91:
              switch (GET_MODE (operands[0]))
                {
                case E_VNx1BImode:
                  if (pattern254 (x2, E_VNx1BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4536; /* pred_sifvnx1bi */

                case E_VNx2BImode:
                  if (pattern254 (x2, E_VNx2BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4539; /* pred_sifvnx2bi */

                case E_VNx4BImode:
                  if (pattern254 (x2, E_VNx4BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4542; /* pred_sifvnx4bi */

                case E_VNx8BImode:
                  if (pattern254 (x2, E_VNx8BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4545; /* pred_sifvnx8bi */

                case E_VNx16BImode:
                  if (pattern254 (x2, E_VNx16BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4548; /* pred_sifvnx16bi */

                case E_VNx32BImode:
                  if (pattern254 (x2, E_VNx32BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4551; /* pred_sifvnx32bi */

                case E_VNx64BImode:
                  if (pattern254 (x2, E_VNx64BImode) != 0
                      || !(
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4554; /* pred_sifvnx64bi */

                default:
                  return -1;
                }

            case 92:
              switch (GET_MODE (operands[0]))
                {
                case E_VNx1BImode:
                  if (pattern254 (x2, E_VNx1BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4537; /* pred_sofvnx1bi */

                case E_VNx2BImode:
                  if (pattern254 (x2, E_VNx2BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4540; /* pred_sofvnx2bi */

                case E_VNx4BImode:
                  if (pattern254 (x2, E_VNx4BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4543; /* pred_sofvnx4bi */

                case E_VNx8BImode:
                  if (pattern254 (x2, E_VNx8BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4546; /* pred_sofvnx8bi */

                case E_VNx16BImode:
                  if (pattern254 (x2, E_VNx16BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4549; /* pred_sofvnx16bi */

                case E_VNx32BImode:
                  if (pattern254 (x2, E_VNx32BImode) != 0
                      || !
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return -1;
                  return 4552; /* pred_sofvnx32bi */

                case E_VNx64BImode:
                  if (pattern254 (x2, E_VNx64BImode) != 0
                      || !(
#line 5320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 4555; /* pred_sofvnx64bi */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        default:
          return -1;
        }

    case NE:
    case EQ:
    case GE:
    case GT:
    case LE:
    case LT:
    case GEU:
    case GTU:
    case LEU:
    case LTU:
      x7 = XVECEXP (x3, 0, 1);
      operands[6] = x7;
      x8 = XVECEXP (x3, 0, 2);
      operands[7] = x8;
      operands[8] = x4;
      operands[3] = x6;
      switch (GET_CODE (operands[3]))
        {
        case NE:
        case EQ:
        case GT:
        case LE:
        case GTU:
        case LEU:
          res = recog_126 (x1, insn, pnum_clobbers);
          if (res >= 0)
            return res;
          break;

        case GE:
        case LT:
        case GEU:
        case LTU:
          res = recog_127 (x1, insn, pnum_clobbers);
          if (res >= 0)
            return res;
          break;

        default:
          break;
        }
      x11 = XEXP (x6, 0);
      operands[4] = x11;
      switch (GET_CODE (operands[3]))
        {
        case GT:
        case LE:
        case LT:
        case GTU:
        case LEU:
        case LTU:
          res = recog_128 (x1, insn, pnum_clobbers);
          if (res >= 0)
            return res;
          break;

        default:
          break;
        }
      switch (GET_CODE (operands[3]))
        {
        case NE:
        case EQ:
        case GE:
        case GT:
        case LE:
        case LT:
          x12 = XEXP (x6, 1);
          switch (GET_CODE (x12))
            {
            case REG:
            case SUBREG:
              operands[5] = x12;
              switch (pattern275 (x2))
                {
                case 0:
                  if (!register_operand (operands[4], E_VNx1SFmode)
                      || !register_operand (operands[5], E_VNx1SFmode))
                    return -1;
                  if ((
#line 6310 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 5122; /* *pred_cmpvnx1sf */
                  if (!(
#line 6330 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return -1;
                  return 5131; /* *pred_cmpvnx1sf_narrow */

                case 1:
                  if (!register_operand (operands[4], E_VNx1DFmode)
                      || !register_operand (operands[5], E_VNx1DFmode))
                    return -1;
                  if ((
#line 6310 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 5127; /* *pred_cmpvnx1df */
                  if (!(
#line 6330 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return -1;
                  return 5136; /* *pred_cmpvnx1df_narrow */

                case 2:
                  if (!register_operand (operands[4], E_VNx2SFmode)
                      || !register_operand (operands[5], E_VNx2SFmode))
                    return -1;
                  if ((
#line 6310 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 5123; /* *pred_cmpvnx2sf */
                  if (!(
#line 6330 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return -1;
                  return 5132; /* *pred_cmpvnx2sf_narrow */

                case 3:
                  if (!register_operand (operands[4], E_VNx2DFmode)
                      || !register_operand (operands[5], E_VNx2DFmode))
                    return -1;
                  if ((
#line 6310 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 5128; /* *pred_cmpvnx2df */
                  if (!(
#line 6330 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return -1;
                  return 5137; /* *pred_cmpvnx2df_narrow */

                case 4:
                  if (!register_operand (operands[4], E_VNx4SFmode)
                      || !register_operand (operands[5], E_VNx4SFmode))
                    return -1;
                  if ((
#line 6310 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 5124; /* *pred_cmpvnx4sf */
                  if (!(
#line 6330 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return -1;
                  return 5133; /* *pred_cmpvnx4sf_narrow */

                case 5:
                  if (!register_operand (operands[4], E_VNx4DFmode)
                      || !register_operand (operands[5], E_VNx4DFmode))
                    return -1;
                  if ((
#line 6310 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 5129; /* *pred_cmpvnx4df */
                  if (!(
#line 6330 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return -1;
                  return 5138; /* *pred_cmpvnx4df_narrow */

                case 6:
                  if (!register_operand (operands[4], E_VNx8SFmode)
                      || !register_operand (operands[5], E_VNx8SFmode))
                    return -1;
                  if ((
#line 6310 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 5125; /* *pred_cmpvnx8sf */
                  if (!(
#line 6330 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return -1;
                  return 5134; /* *pred_cmpvnx8sf_narrow */

                case 7:
                  if (!register_operand (operands[4], E_VNx8DFmode)
                      || !register_operand (operands[5], E_VNx8DFmode))
                    return -1;
                  if ((
#line 6310 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 5130; /* *pred_cmpvnx8df */
                  if (!(
#line 6330 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return -1;
                  return 5139; /* *pred_cmpvnx8df_narrow */

                case 8:
                  if (!register_operand (operands[4], E_VNx16SFmode)
                      || !register_operand (operands[5], E_VNx16SFmode)
                      || !vector_merge_operand (operands[2], E_VNx16BImode))
                    return -1;
                  if ((
#line 6310 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                    return 5126; /* *pred_cmpvnx16sf */
                  if (!(
#line 6330 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 5135; /* *pred_cmpvnx16sf_narrow */

                default:
                  return -1;
                }

            case VEC_DUPLICATE:
              x13 = XEXP (x12, 0);
              operands[5] = x13;
              switch (pattern275 (x2))
                {
                case 0:
                  if (!register_operand (operands[4], E_VNx1SFmode)
                      || GET_MODE (x12) != E_VNx1SFmode
                      || !register_operand (operands[5], E_SFmode))
                    return -1;
                  if ((
#line 6369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 5140; /* *pred_cmpvnx1sf_scalar */
                  if (!(
#line 6390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return -1;
                  return 5149; /* *pred_cmpvnx1sf_scalar_narrow */

                case 1:
                  if (!register_operand (operands[4], E_VNx1DFmode)
                      || GET_MODE (x12) != E_VNx1DFmode
                      || !register_operand (operands[5], E_DFmode))
                    return -1;
                  if ((
#line 6369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 5145; /* *pred_cmpvnx1df_scalar */
                  if (!(
#line 6390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return -1;
                  return 5154; /* *pred_cmpvnx1df_scalar_narrow */

                case 2:
                  if (!register_operand (operands[4], E_VNx2SFmode)
                      || GET_MODE (x12) != E_VNx2SFmode
                      || !register_operand (operands[5], E_SFmode))
                    return -1;
                  if ((
#line 6369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 5141; /* *pred_cmpvnx2sf_scalar */
                  if (!(
#line 6390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return -1;
                  return 5150; /* *pred_cmpvnx2sf_scalar_narrow */

                case 3:
                  if (!register_operand (operands[4], E_VNx2DFmode)
                      || GET_MODE (x12) != E_VNx2DFmode
                      || !register_operand (operands[5], E_DFmode))
                    return -1;
                  if ((
#line 6369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 5146; /* *pred_cmpvnx2df_scalar */
                  if (!(
#line 6390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return -1;
                  return 5155; /* *pred_cmpvnx2df_scalar_narrow */

                case 4:
                  if (!register_operand (operands[4], E_VNx4SFmode)
                      || GET_MODE (x12) != E_VNx4SFmode
                      || !register_operand (operands[5], E_SFmode))
                    return -1;
                  if ((
#line 6369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 5142; /* *pred_cmpvnx4sf_scalar */
                  if (!(
#line 6390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return -1;
                  return 5151; /* *pred_cmpvnx4sf_scalar_narrow */

                case 5:
                  if (!register_operand (operands[4], E_VNx4DFmode)
                      || GET_MODE (x12) != E_VNx4DFmode
                      || !register_operand (operands[5], E_DFmode))
                    return -1;
                  if ((
#line 6369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 5147; /* *pred_cmpvnx4df_scalar */
                  if (!(
#line 6390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return -1;
                  return 5156; /* *pred_cmpvnx4df_scalar_narrow */

                case 6:
                  if (!register_operand (operands[4], E_VNx8SFmode)
                      || GET_MODE (x12) != E_VNx8SFmode
                      || !register_operand (operands[5], E_SFmode))
                    return -1;
                  if ((
#line 6369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 5143; /* *pred_cmpvnx8sf_scalar */
                  if (!(
#line 6390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return -1;
                  return 5152; /* *pred_cmpvnx8sf_scalar_narrow */

                case 7:
                  if (!register_operand (operands[4], E_VNx8DFmode)
                      || GET_MODE (x12) != E_VNx8DFmode
                      || !register_operand (operands[5], E_DFmode))
                    return -1;
                  if ((
#line 6369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 5148; /* *pred_cmpvnx8df_scalar */
                  if (!(
#line 6390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return -1;
                  return 5157; /* *pred_cmpvnx8df_scalar_narrow */

                case 8:
                  if (pattern318 (x12, E_VNx16BImode, E_SFmode, E_VNx16SFmode) != 0)
                    return -1;
                  if ((
#line 6369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                    return 5144; /* *pred_cmpvnx16sf_scalar */
                  if (!(
#line 6390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                    return -1;
                  return 5153; /* *pred_cmpvnx16sf_scalar_narrow */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_130 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  if (pattern80 (x3) != 0)
    return -1;
  x4 = XEXP (x2, 1);
  switch (GET_CODE (x4))
    {
    case CONST_VECTOR:
    case REG:
    case SUBREG:
    case MEM:
      return recog_120 (x1, insn, pnum_clobbers);

    case VEC_DUPLICATE:
      return recog_103 (x1, insn, pnum_clobbers);

    case UNSPEC:
      return recog_97 (x1, insn, pnum_clobbers);

    case PLUS:
      return recog_96 (x1, insn, pnum_clobbers);

    case MINUS:
      return recog_98 (x1, insn, pnum_clobbers);

    case AND:
      return recog_118 (x1, insn, pnum_clobbers);

    case IOR:
      return recog_116 (x1, insn, pnum_clobbers);

    case XOR:
      return recog_117 (x1, insn, pnum_clobbers);

    case ASHIFT:
      return recog_102 (x1, insn, pnum_clobbers);

    case ASHIFTRT:
      return recog_101 (x1, insn, pnum_clobbers);

    case LSHIFTRT:
      return recog_100 (x1, insn, pnum_clobbers);

    case SMAX:
      return recog_105 (x1, insn, pnum_clobbers);

    case UMAX:
      return recog_115 (x1, insn, pnum_clobbers);

    case SMIN:
      return recog_106 (x1, insn, pnum_clobbers);

    case UMIN:
      return recog_114 (x1, insn, pnum_clobbers);

    case MULT:
      return recog_94 (x1, insn, pnum_clobbers);

    case DIV:
      return recog_99 (x1, insn, pnum_clobbers);

    case UDIV:
      return recog_113 (x1, insn, pnum_clobbers);

    case MOD:
      return recog_112 (x1, insn, pnum_clobbers);

    case UMOD:
      return recog_111 (x1, insn, pnum_clobbers);

    case NEG:
      return recog_107 (x1, insn, pnum_clobbers);

    case NOT:
      x5 = XVECEXP (x3, 0, 1);
      operands[4] = x5;
      x6 = XVECEXP (x3, 0, 2);
      operands[5] = x6;
      x7 = XVECEXP (x3, 0, 3);
      operands[6] = x7;
      x8 = XVECEXP (x3, 0, 4);
      operands[7] = x8;
      x9 = XEXP (x4, 0);
      operands[3] = x9;
      switch (pattern151 (x2))
        {
        case 0:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2745; /* pred_one_cmplvnx1qi */

        case 1:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2747; /* pred_one_cmplvnx2qi */

        case 2:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2749; /* pred_one_cmplvnx4qi */

        case 3:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2751; /* pred_one_cmplvnx8qi */

        case 4:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2753; /* pred_one_cmplvnx16qi */

        case 5:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2755; /* pred_one_cmplvnx32qi */

        case 6:
          if (!(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2757; /* pred_one_cmplvnx64qi */

        case 7:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2759; /* pred_one_cmplvnx1hi */

        case 8:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2761; /* pred_one_cmplvnx2hi */

        case 9:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2763; /* pred_one_cmplvnx4hi */

        case 10:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2765; /* pred_one_cmplvnx8hi */

        case 11:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2767; /* pred_one_cmplvnx16hi */

        case 12:
          if (!(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2769; /* pred_one_cmplvnx32hi */

        case 13:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2771; /* pred_one_cmplvnx1si */

        case 14:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2773; /* pred_one_cmplvnx2si */

        case 15:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2775; /* pred_one_cmplvnx4si */

        case 16:
          if (!
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2777; /* pred_one_cmplvnx8si */

        case 17:
          if (!(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2779; /* pred_one_cmplvnx16si */

        case 18:
          if (!(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2781; /* pred_one_cmplvnx1di */

        case 19:
          if (!(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2783; /* pred_one_cmplvnx2di */

        case 20:
          if (!(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2785; /* pred_one_cmplvnx4di */

        case 21:
          if (!(
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2787; /* pred_one_cmplvnx8di */

        default:
          return -1;
        }

    case SIGN_EXTEND:
      switch (pattern165 (x2))
        {
        case 0:
          if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2788; /* pred_extendvnx1hi_vf2 */

        case 1:
          if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2790; /* pred_extendvnx2hi_vf2 */

        case 2:
          if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2792; /* pred_extendvnx4hi_vf2 */

        case 3:
          if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2794; /* pred_extendvnx8hi_vf2 */

        case 4:
          if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2796; /* pred_extendvnx16hi_vf2 */

        case 5:
          if (!(
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2798; /* pred_extendvnx32hi_vf2 */

        case 6:
          if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2800; /* pred_extendvnx1si_vf2 */

        case 7:
          if (!
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2818; /* pred_extendvnx1si_vf4 */

        case 8:
          if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2802; /* pred_extendvnx2si_vf2 */

        case 9:
          if (!
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2820; /* pred_extendvnx2si_vf4 */

        case 10:
          if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2804; /* pred_extendvnx4si_vf2 */

        case 11:
          if (!
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2822; /* pred_extendvnx4si_vf4 */

        case 12:
          if (!
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2806; /* pred_extendvnx8si_vf2 */

        case 13:
          if (!
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 2824; /* pred_extendvnx8si_vf4 */

        case 14:
          if (!(
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2808; /* pred_extendvnx16si_vf2 */

        case 15:
          if (!(
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 423 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 2826; /* pred_extendvnx16si_vf4 */

        case 16:
          if (!(
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2810; /* pred_extendvnx1di_vf2 */

        case 17:
          if (!(
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2828; /* pred_extendvnx1di_vf4 */

        case 18:
          if (!(
#line 2938 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2836; /* pred_extendvnx1di_vf8 */

        case 19:
          if (!(
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 404 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2812; /* pred_extendvnx2di_vf2 */

        case 20:
          if (!(
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2830; /* pred_extendvnx2di_vf4 */

        case 21:
          if (!(
#line 2938 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2838; /* pred_extendvnx2di_vf8 */

        case 22:
          if (!(
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2814; /* pred_extendvnx4di_vf2 */

        case 23:
          if (!(
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 425 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2832; /* pred_extendvnx4di_vf4 */

        case 24:
          if (!(
#line 2938 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2840; /* pred_extendvnx4di_vf8 */

        case 25:
          if (!(
#line 2898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 405 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2816; /* pred_extendvnx8di_vf2 */

        case 26:
          if (!(
#line 2918 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 425 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2834; /* pred_extendvnx8di_vf4 */

        case 27:
          if (!(
#line 2938 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 2842; /* pred_extendvnx8di_vf8 */

        default:
          return -1;
        }

    case ZERO_EXTEND:
      return recog_121 (x1, insn, pnum_clobbers);

    case TRUNCATE:
      return recog_95 (x1, insn, pnum_clobbers);

    case SS_PLUS:
      return recog_109 (x1, insn, pnum_clobbers);

    case SS_MINUS:
      return recog_104 (x1, insn, pnum_clobbers);

    case US_PLUS:
      return recog_110 (x1, insn, pnum_clobbers);

    case US_MINUS:
      return recog_108 (x1, insn, pnum_clobbers);

    case VEC_SERIES:
      return recog_119 (x1, insn, pnum_clobbers);

    case ABS:
      switch (pattern167 (x2))
        {
        case 0:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4997; /* pred_absvnx1sf */

        case 1:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5000; /* pred_absvnx2sf */

        case 2:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5003; /* pred_absvnx4sf */

        case 3:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5006; /* pred_absvnx8sf */

        case 4:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5009; /* pred_absvnx16sf */

        case 5:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5012; /* pred_absvnx1df */

        case 6:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5015; /* pred_absvnx2df */

        case 7:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5018; /* pred_absvnx4df */

        case 8:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5021; /* pred_absvnx8df */

        default:
          return -1;
        }

    case SQRT:
      switch (pattern167 (x2))
        {
        case 0:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 4998; /* pred_sqrtvnx1sf */

        case 1:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5001; /* pred_sqrtvnx2sf */

        case 2:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5004; /* pred_sqrtvnx4sf */

        case 3:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5007; /* pred_sqrtvnx8sf */

        case 4:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5010; /* pred_sqrtvnx16sf */

        case 5:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5013; /* pred_sqrtvnx1df */

        case 6:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5016; /* pred_sqrtvnx2df */

        case 7:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5019; /* pred_sqrtvnx4df */

        case 8:
          if (!(
#line 6020 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5022; /* pred_sqrtvnx8df */

        default:
          return -1;
        }

    case FIX:
      switch (pattern168 (x2))
        {
        case 0:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5203; /* pred_fix_truncvnx1sf */

        case 1:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5305; /* pred_narrow_fix_truncvnx1df */

        case 2:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5205; /* pred_fix_truncvnx2sf */

        case 3:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5307; /* pred_narrow_fix_truncvnx2df */

        case 4:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5207; /* pred_fix_truncvnx4sf */

        case 5:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5309; /* pred_narrow_fix_truncvnx4df */

        case 6:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5209; /* pred_fix_truncvnx8sf */

        case 7:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5311; /* pred_narrow_fix_truncvnx8df */

        case 8:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5211; /* pred_fix_truncvnx16sf */

        case 9:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5213; /* pred_fix_truncvnx1df */

        case 10:
          if (!(
#line 6586 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 416 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5247; /* pred_widen_fix_truncvnx1di */

        case 11:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5215; /* pred_fix_truncvnx2df */

        case 12:
          if (!(
#line 6586 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 417 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5249; /* pred_widen_fix_truncvnx2di */

        case 13:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5217; /* pred_fix_truncvnx4df */

        case 14:
          if (!(
#line 6586 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5251; /* pred_widen_fix_truncvnx4di */

        case 15:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5219; /* pred_fix_truncvnx8df */

        case 16:
          if (!(
#line 6586 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 419 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5253; /* pred_widen_fix_truncvnx8di */

        case 17:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5295; /* pred_narrow_fix_truncvnx1sf */

        case 18:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5297; /* pred_narrow_fix_truncvnx2sf */

        case 19:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5299; /* pred_narrow_fix_truncvnx4sf */

        case 20:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5301; /* pred_narrow_fix_truncvnx8sf */

        case 21:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5303; /* pred_narrow_fix_truncvnx16sf */

        default:
          return -1;
        }

    case UNSIGNED_FIX:
      switch (pattern168 (x2))
        {
        case 0:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5204; /* pred_fixuns_truncvnx1sf */

        case 1:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5306; /* pred_narrow_fixuns_truncvnx1df */

        case 2:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5206; /* pred_fixuns_truncvnx2sf */

        case 3:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5308; /* pred_narrow_fixuns_truncvnx2df */

        case 4:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5208; /* pred_fixuns_truncvnx4sf */

        case 5:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5310; /* pred_narrow_fixuns_truncvnx4df */

        case 6:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5210; /* pred_fixuns_truncvnx8sf */

        case 7:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5312; /* pred_narrow_fixuns_truncvnx8df */

        case 8:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5212; /* pred_fixuns_truncvnx16sf */

        case 9:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5214; /* pred_fixuns_truncvnx1df */

        case 10:
          if (!(
#line 6586 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 416 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5248; /* pred_widen_fixuns_truncvnx1di */

        case 11:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5216; /* pred_fixuns_truncvnx2df */

        case 12:
          if (!(
#line 6586 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 417 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5250; /* pred_widen_fixuns_truncvnx2di */

        case 13:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5218; /* pred_fixuns_truncvnx4df */

        case 14:
          if (!(
#line 6586 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5252; /* pred_widen_fixuns_truncvnx4di */

        case 15:
          if (!(
#line 6522 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5220; /* pred_fixuns_truncvnx8df */

        case 16:
          if (!(
#line 6586 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 419 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5254; /* pred_widen_fixuns_truncvnx8di */

        case 17:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5296; /* pred_narrow_fixuns_truncvnx1sf */

        case 18:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5298; /* pred_narrow_fixuns_truncvnx2sf */

        case 19:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5300; /* pred_narrow_fixuns_truncvnx4sf */

        case 20:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5302; /* pred_narrow_fixuns_truncvnx8sf */

        case 21:
          if (!(
#line 6669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5304; /* pred_narrow_fixuns_truncvnx16sf */

        default:
          return -1;
        }

    case FLOAT:
      switch (pattern169 (x2))
        {
        case 0:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5221; /* pred_floatvnx1sf */

        case 1:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5255; /* pred_widen_floatvnx1sf */

        case 2:
          if (!(
#line 6688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 416 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5313; /* pred_narrow_floatvnx1di */

        case 3:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5223; /* pred_floatvnx2sf */

        case 4:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5257; /* pred_widen_floatvnx2sf */

        case 5:
          if (!(
#line 6688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 417 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5315; /* pred_narrow_floatvnx2di */

        case 6:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5225; /* pred_floatvnx4sf */

        case 7:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5259; /* pred_widen_floatvnx4sf */

        case 8:
          if (!(
#line 6688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5317; /* pred_narrow_floatvnx4di */

        case 9:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5227; /* pred_floatvnx8sf */

        case 10:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5261; /* pred_widen_floatvnx8sf */

        case 11:
          if (!(
#line 6688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 419 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5319; /* pred_narrow_floatvnx8di */

        case 12:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5229; /* pred_floatvnx16sf */

        case 13:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5263; /* pred_widen_floatvnx16sf */

        case 14:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5231; /* pred_floatvnx1df */

        case 15:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5265; /* pred_widen_floatvnx1df */

        case 16:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5233; /* pred_floatvnx2df */

        case 17:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5267; /* pred_widen_floatvnx2df */

        case 18:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5235; /* pred_floatvnx4df */

        case 19:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5269; /* pred_widen_floatvnx4df */

        case 20:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5237; /* pred_floatvnx8df */

        case 21:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5271; /* pred_widen_floatvnx8df */

        default:
          return -1;
        }

    case UNSIGNED_FLOAT:
      switch (pattern169 (x2))
        {
        case 0:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5222; /* pred_floatunsvnx1sf */

        case 1:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5256; /* pred_widen_floatunsvnx1sf */

        case 2:
          if (!(
#line 6688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 416 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5314; /* pred_narrow_floatunsvnx1di */

        case 3:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5224; /* pred_floatunsvnx2sf */

        case 4:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5258; /* pred_widen_floatunsvnx2sf */

        case 5:
          if (!(
#line 6688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 417 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5316; /* pred_narrow_floatunsvnx2di */

        case 6:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5226; /* pred_floatunsvnx4sf */

        case 7:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5260; /* pred_widen_floatunsvnx4sf */

        case 8:
          if (!(
#line 6688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 418 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5318; /* pred_narrow_floatunsvnx4di */

        case 9:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5228; /* pred_floatunsvnx8sf */

        case 10:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5262; /* pred_widen_floatunsvnx8sf */

        case 11:
          if (!(
#line 6688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 419 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 5320; /* pred_narrow_floatunsvnx8di */

        case 12:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5230; /* pred_floatunsvnx16sf */

        case 13:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 5264; /* pred_widen_floatunsvnx16sf */

        case 14:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5232; /* pred_floatunsvnx1df */

        case 15:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5266; /* pred_widen_floatunsvnx1df */

        case 16:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5234; /* pred_floatunsvnx2df */

        case 17:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5268; /* pred_widen_floatunsvnx2df */

        case 18:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5236; /* pred_floatunsvnx4df */

        case 19:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5270; /* pred_widen_floatunsvnx4df */

        case 20:
          if (!(
#line 6541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5238; /* pred_floatunsvnx8df */

        case 21:
          if (!(
#line 6605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5272; /* pred_widen_floatunsvnx8df */

        default:
          return -1;
        }

    case FLOAT_EXTEND:
      x5 = XVECEXP (x3, 0, 1);
      operands[4] = x5;
      x6 = XVECEXP (x3, 0, 2);
      operands[5] = x6;
      x7 = XVECEXP (x3, 0, 3);
      operands[6] = x7;
      x8 = XVECEXP (x3, 0, 4);
      operands[7] = x8;
      x9 = XEXP (x4, 0);
      operands[3] = x9;
      x10 = XEXP (x2, 2);
      operands[2] = x10;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1DFmode:
          if (pattern164 (x2, E_VNx1DFmode, E_VNx1SFmode, E_VNx1BImode) != 0
              || !(
#line 6624 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5273; /* pred_extendvnx1df */

        case E_VNx2DFmode:
          if (pattern164 (x2, E_VNx2DFmode, E_VNx2SFmode, E_VNx2BImode) != 0
              || !(
#line 6624 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5274; /* pred_extendvnx2df */

        case E_VNx4DFmode:
          if (pattern164 (x2, E_VNx4DFmode, E_VNx4SFmode, E_VNx4BImode) != 0
              || !(
#line 6624 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5275; /* pred_extendvnx4df */

        case E_VNx8DFmode:
          if (pattern164 (x2, E_VNx8DFmode, E_VNx8SFmode, E_VNx8BImode) != 0
              || !(
#line 6624 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5276; /* pred_extendvnx8df */

        default:
          return -1;
        }

    case FLOAT_TRUNCATE:
      x5 = XVECEXP (x3, 0, 1);
      operands[4] = x5;
      x6 = XVECEXP (x3, 0, 2);
      operands[5] = x6;
      x7 = XVECEXP (x3, 0, 3);
      operands[6] = x7;
      x8 = XVECEXP (x3, 0, 4);
      operands[7] = x8;
      x9 = XEXP (x4, 0);
      operands[3] = x9;
      x10 = XEXP (x2, 2);
      operands[2] = x10;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1SFmode:
          if (pattern164 (x2, E_VNx1SFmode, E_VNx1DFmode, E_VNx1BImode) != 0
              || !(
#line 6707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5321; /* pred_truncvnx1df */

        case E_VNx2SFmode:
          if (pattern164 (x2, E_VNx2SFmode, E_VNx2DFmode, E_VNx2BImode) != 0
              || !(
#line 6707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 410 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5322; /* pred_truncvnx2df */

        case E_VNx4SFmode:
          if (pattern164 (x2, E_VNx4SFmode, E_VNx4DFmode, E_VNx4BImode) != 0
              || !(
#line 6707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5323; /* pred_truncvnx4df */

        case E_VNx8SFmode:
          if (pattern164 (x2, E_VNx8SFmode, E_VNx8DFmode, E_VNx8BImode) != 0
              || !(
#line 6707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 412 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 5324; /* pred_truncvnx8df */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_131 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 2);
  if (GET_CODE (x4) != REG
      || REGNO (x4) != 66
      || GET_MODE (x4) != E_SImode)
    return -1;
  x5 = XVECEXP (x3, 0, 3);
  if (GET_CODE (x5) != REG
      || REGNO (x5) != 67
      || GET_MODE (x5) != E_SImode)
    return -1;
  x6 = XVECEXP (x3, 0, 0);
  operands[1] = x6;
  x7 = XVECEXP (x3, 0, 1);
  if (!vector_length_operand (x7, E_VOIDmode))
    return -1;
  x8 = XEXP (x2, 2);
  if (!rtx_equal_p (x8, operands[0]))
    return -1;
  x9 = XEXP (x2, 1);
  switch (GET_CODE (x9))
    {
    case REG:
    case SUBREG:
      operands[2] = x9;
      operands[3] = x7;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          if (pattern196 (x2, E_VNx1QImode, E_VNx1BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 831; /* pred_storevnx1qi */

        case E_VNx2QImode:
          if (pattern196 (x2, E_VNx2QImode, E_VNx2BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 832; /* pred_storevnx2qi */

        case E_VNx4QImode:
          if (pattern196 (x2, E_VNx4QImode, E_VNx4BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 833; /* pred_storevnx4qi */

        case E_VNx8QImode:
          if (pattern196 (x2, E_VNx8QImode, E_VNx8BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 834; /* pred_storevnx8qi */

        case E_VNx16QImode:
          if (pattern196 (x2, E_VNx16QImode, E_VNx16BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 835; /* pred_storevnx16qi */

        case E_VNx32QImode:
          if (pattern196 (x2, E_VNx32QImode, E_VNx32BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 836; /* pred_storevnx32qi */

        case E_VNx64QImode:
          if (pattern196 (x2, E_VNx64QImode, E_VNx64BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 837; /* pred_storevnx64qi */

        case E_VNx1HImode:
          if (pattern196 (x2, E_VNx1HImode, E_VNx1BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 838; /* pred_storevnx1hi */

        case E_VNx2HImode:
          if (pattern196 (x2, E_VNx2HImode, E_VNx2BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 839; /* pred_storevnx2hi */

        case E_VNx4HImode:
          if (pattern196 (x2, E_VNx4HImode, E_VNx4BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 840; /* pred_storevnx4hi */

        case E_VNx8HImode:
          if (pattern196 (x2, E_VNx8HImode, E_VNx8BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 841; /* pred_storevnx8hi */

        case E_VNx16HImode:
          if (pattern196 (x2, E_VNx16HImode, E_VNx16BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 842; /* pred_storevnx16hi */

        case E_VNx32HImode:
          if (pattern196 (x2, E_VNx32HImode, E_VNx32BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 843; /* pred_storevnx32hi */

        case E_VNx1SImode:
          if (pattern196 (x2, E_VNx1SImode, E_VNx1BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 844; /* pred_storevnx1si */

        case E_VNx2SImode:
          if (pattern196 (x2, E_VNx2SImode, E_VNx2BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 845; /* pred_storevnx2si */

        case E_VNx4SImode:
          if (pattern196 (x2, E_VNx4SImode, E_VNx4BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 846; /* pred_storevnx4si */

        case E_VNx8SImode:
          if (pattern196 (x2, E_VNx8SImode, E_VNx8BImode) != 0
              || !
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 847; /* pred_storevnx8si */

        case E_VNx16SImode:
          if (pattern196 (x2, E_VNx16SImode, E_VNx16BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 848; /* pred_storevnx16si */

        case E_VNx1DImode:
          if (pattern196 (x2, E_VNx1DImode, E_VNx1BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 849; /* pred_storevnx1di */

        case E_VNx2DImode:
          if (pattern196 (x2, E_VNx2DImode, E_VNx2BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 850; /* pred_storevnx2di */

        case E_VNx4DImode:
          if (pattern196 (x2, E_VNx4DImode, E_VNx4BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 851; /* pred_storevnx4di */

        case E_VNx8DImode:
          if (pattern196 (x2, E_VNx8DImode, E_VNx8BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 852; /* pred_storevnx8di */

        case E_VNx1SFmode:
          if (pattern196 (x2, E_VNx1SFmode, E_VNx1BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 853; /* pred_storevnx1sf */

        case E_VNx2SFmode:
          if (pattern196 (x2, E_VNx2SFmode, E_VNx2BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 854; /* pred_storevnx2sf */

        case E_VNx4SFmode:
          if (pattern196 (x2, E_VNx4SFmode, E_VNx4BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 855; /* pred_storevnx4sf */

        case E_VNx8SFmode:
          if (pattern196 (x2, E_VNx8SFmode, E_VNx8BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 856; /* pred_storevnx8sf */

        case E_VNx16SFmode:
          if (pattern196 (x2, E_VNx16SFmode, E_VNx16BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 857; /* pred_storevnx16sf */

        case E_VNx1DFmode:
          if (pattern196 (x2, E_VNx1DFmode, E_VNx1BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 858; /* pred_storevnx1df */

        case E_VNx2DFmode:
          if (pattern196 (x2, E_VNx2DFmode, E_VNx2BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 859; /* pred_storevnx2df */

        case E_VNx4DFmode:
          if (pattern196 (x2, E_VNx4DFmode, E_VNx4BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 860; /* pred_storevnx4df */

        case E_VNx8DFmode:
          if (pattern196 (x2, E_VNx8DFmode, E_VNx8BImode) != 0
              || !(
#line 1016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 861; /* pred_storevnx8df */

        case E_VNx1BImode:
          if (pattern197 (x2, E_VNx1BImode) != 0
              || !
#line 1066 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 869; /* pred_storevnx1bi */

        case E_VNx2BImode:
          if (pattern197 (x2, E_VNx2BImode) != 0
              || !
#line 1066 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 870; /* pred_storevnx2bi */

        case E_VNx4BImode:
          if (pattern197 (x2, E_VNx4BImode) != 0
              || !
#line 1066 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 871; /* pred_storevnx4bi */

        case E_VNx8BImode:
          if (pattern197 (x2, E_VNx8BImode) != 0
              || !
#line 1066 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 872; /* pred_storevnx8bi */

        case E_VNx16BImode:
          if (pattern197 (x2, E_VNx16BImode) != 0
              || !
#line 1066 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 873; /* pred_storevnx16bi */

        case E_VNx32BImode:
          if (pattern197 (x2, E_VNx32BImode) != 0
              || !
#line 1066 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 874; /* pred_storevnx32bi */

        case E_VNx64BImode:
          if (pattern197 (x2, E_VNx64BImode) != 0
              || !(
#line 1066 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 875; /* pred_storevnx64bi */

        default:
          return -1;
        }

    case UNSPEC:
      if (XVECLEN (x9, 0) != 2
          || XINT (x9, 1) != 70)
        return -1;
      operands[4] = x7;
      x10 = XVECEXP (x9, 0, 0);
      operands[2] = x10;
      if (!pmode_reg_or_0_operand (operands[2], E_VOIDmode))
        return -1;
      x11 = XVECEXP (x9, 0, 1);
      operands[3] = x11;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          if (pattern232 (x2, E_VNx1QImode, E_VNx1BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 999; /* pred_strided_storevnx1qi */

        case E_VNx2QImode:
          if (pattern232 (x2, E_VNx2QImode, E_VNx2BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1000; /* pred_strided_storevnx2qi */

        case E_VNx4QImode:
          if (pattern232 (x2, E_VNx4QImode, E_VNx4BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1001; /* pred_strided_storevnx4qi */

        case E_VNx8QImode:
          if (pattern232 (x2, E_VNx8QImode, E_VNx8BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1002; /* pred_strided_storevnx8qi */

        case E_VNx16QImode:
          if (pattern232 (x2, E_VNx16QImode, E_VNx16BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1003; /* pred_strided_storevnx16qi */

        case E_VNx32QImode:
          if (pattern232 (x2, E_VNx32QImode, E_VNx32BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1004; /* pred_strided_storevnx32qi */

        case E_VNx64QImode:
          if (pattern232 (x2, E_VNx64QImode, E_VNx64BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1005; /* pred_strided_storevnx64qi */

        case E_VNx1HImode:
          if (pattern232 (x2, E_VNx1HImode, E_VNx1BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1006; /* pred_strided_storevnx1hi */

        case E_VNx2HImode:
          if (pattern232 (x2, E_VNx2HImode, E_VNx2BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1007; /* pred_strided_storevnx2hi */

        case E_VNx4HImode:
          if (pattern232 (x2, E_VNx4HImode, E_VNx4BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1008; /* pred_strided_storevnx4hi */

        case E_VNx8HImode:
          if (pattern232 (x2, E_VNx8HImode, E_VNx8BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1009; /* pred_strided_storevnx8hi */

        case E_VNx16HImode:
          if (pattern232 (x2, E_VNx16HImode, E_VNx16BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1010; /* pred_strided_storevnx16hi */

        case E_VNx32HImode:
          if (pattern232 (x2, E_VNx32HImode, E_VNx32BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1011; /* pred_strided_storevnx32hi */

        case E_VNx1SImode:
          if (pattern232 (x2, E_VNx1SImode, E_VNx1BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1012; /* pred_strided_storevnx1si */

        case E_VNx2SImode:
          if (pattern232 (x2, E_VNx2SImode, E_VNx2BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1013; /* pred_strided_storevnx2si */

        case E_VNx4SImode:
          if (pattern232 (x2, E_VNx4SImode, E_VNx4BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1014; /* pred_strided_storevnx4si */

        case E_VNx8SImode:
          if (pattern232 (x2, E_VNx8SImode, E_VNx8BImode) != 0
              || !
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 1015; /* pred_strided_storevnx8si */

        case E_VNx16SImode:
          if (pattern232 (x2, E_VNx16SImode, E_VNx16BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 1016; /* pred_strided_storevnx16si */

        case E_VNx1DImode:
          if (pattern232 (x2, E_VNx1DImode, E_VNx1BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1017; /* pred_strided_storevnx1di */

        case E_VNx2DImode:
          if (pattern232 (x2, E_VNx2DImode, E_VNx2BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1018; /* pred_strided_storevnx2di */

        case E_VNx4DImode:
          if (pattern232 (x2, E_VNx4DImode, E_VNx4BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1019; /* pred_strided_storevnx4di */

        case E_VNx8DImode:
          if (pattern232 (x2, E_VNx8DImode, E_VNx8BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 1020; /* pred_strided_storevnx8di */

        case E_VNx1SFmode:
          if (pattern232 (x2, E_VNx1SFmode, E_VNx1BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 1021; /* pred_strided_storevnx1sf */

        case E_VNx2SFmode:
          if (pattern232 (x2, E_VNx2SFmode, E_VNx2BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 1022; /* pred_strided_storevnx2sf */

        case E_VNx4SFmode:
          if (pattern232 (x2, E_VNx4SFmode, E_VNx4BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 1023; /* pred_strided_storevnx4sf */

        case E_VNx8SFmode:
          if (pattern232 (x2, E_VNx8SFmode, E_VNx8BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 1024; /* pred_strided_storevnx8sf */

        case E_VNx16SFmode:
          if (pattern232 (x2, E_VNx16SFmode, E_VNx16BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 1025; /* pred_strided_storevnx16sf */

        case E_VNx1DFmode:
          if (pattern232 (x2, E_VNx1DFmode, E_VNx1BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 1026; /* pred_strided_storevnx1df */

        case E_VNx2DFmode:
          if (pattern232 (x2, E_VNx2DFmode, E_VNx2BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 1027; /* pred_strided_storevnx2df */

        case E_VNx4DFmode:
          if (pattern232 (x2, E_VNx4DFmode, E_VNx4BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 1028; /* pred_strided_storevnx4df */

        case E_VNx8DFmode:
          if (pattern232 (x2, E_VNx8DFmode, E_VNx8BImode) != 0
              || !(
#line 1389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 1029; /* pred_strided_storevnx8df */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_132 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  switch (GET_CODE (x2))
    {
    case REG:
    case SUBREG:
    case MEM:
      res = recog_18 (x1, insn, pnum_clobbers);
      if (res >= 0)
        return res;
      break;

    case PC:
      x3 = XEXP (x1, 1);
      operands[0] = x3;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (register_operand (operands[0], E_SImode)
              && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
            return 287; /* indirect_jumpsi */
          break;

        case E_DImode:
          if (register_operand (operands[0], E_DImode)
              && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
            return 288; /* indirect_jumpdi */
          break;

        default:
          break;
        }
      break;

    default:
      break;
    }
  x3 = XEXP (x1, 1);
  switch (GET_CODE (x3))
    {
    case LABEL_REF:
      if (GET_CODE (x2) != PC)
        return -1;
      x4 = XEXP (x3, 0);
      operands[0] = x4;
      return 286; /* jump */

    case REG:
    case SUBREG:
    case MEM:
      operands[0] = x2;
      switch (GET_CODE (x3))
        {
        case MEM:
          res = recog_19 (x1, insn, pnum_clobbers);
          if (res >= 0)
            return res;
          break;

        case REG:
        case SUBREG:
          switch (GET_CODE (x3))
            {
            case SUBREG:
              switch (pattern58 (x3))
                {
                case 0:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 653; /* *vlmul_extx2vnx1qi */
                  break;

                case 1:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 654; /* *vlmul_extx2vnx2qi */
                  break;

                case 2:
                  if (
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 678; /* *vlmul_extx4vnx1qi */
                  break;

                case 3:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 655; /* *vlmul_extx2vnx4qi */
                  break;

                case 4:
                  if (
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 679; /* *vlmul_extx4vnx2qi */
                  break;

                case 5:
                  if (
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 697; /* *vlmul_extx8vnx1qi */
                  break;

                case 6:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 656; /* *vlmul_extx2vnx8qi */
                  break;

                case 7:
                  if (
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 680; /* *vlmul_extx4vnx4qi */
                  break;

                case 8:
                  if (
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 698; /* *vlmul_extx8vnx2qi */
                  break;

                case 9:
                  if (
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 710; /* *vlmul_extx16vnx1qi */
                  break;

                case 10:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 657; /* *vlmul_extx2vnx16qi */
                  break;

                case 11:
                  if (
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 681; /* *vlmul_extx4vnx8qi */
                  break;

                case 12:
                  if (
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 699; /* *vlmul_extx8vnx4qi */
                  break;

                case 13:
                  if (
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 711; /* *vlmul_extx16vnx2qi */
                  break;

                case 14:
                  if (
#line 478 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 717; /* *vlmul_extx32vnx1qi */
                  break;

                case 15:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 658; /* *vlmul_extx2vnx32qi */
                  break;

                case 16:
                  if (
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 682; /* *vlmul_extx4vnx16qi */
                  break;

                case 17:
                  if (
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 700; /* *vlmul_extx8vnx8qi */
                  break;

                case 18:
                  if (
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 712; /* *vlmul_extx16vnx4qi */
                  break;

                case 19:
                  if (
#line 478 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 718; /* *vlmul_extx32vnx2qi */
                  break;

                case 20:
                  if (
#line 491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 720; /* *vlmul_extx64vnx1qi */
                  break;

                case 21:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 659; /* *vlmul_extx2vnx1hi */
                  break;

                case 22:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 660; /* *vlmul_extx2vnx2hi */
                  break;

                case 23:
                  if (
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 683; /* *vlmul_extx4vnx1hi */
                  break;

                case 24:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 661; /* *vlmul_extx2vnx4hi */
                  break;

                case 25:
                  if (
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 684; /* *vlmul_extx4vnx2hi */
                  break;

                case 26:
                  if (
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 701; /* *vlmul_extx8vnx1hi */
                  break;

                case 27:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 662; /* *vlmul_extx2vnx8hi */
                  break;

                case 28:
                  if (
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 685; /* *vlmul_extx4vnx4hi */
                  break;

                case 29:
                  if (
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 702; /* *vlmul_extx8vnx2hi */
                  break;

                case 30:
                  if (
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 713; /* *vlmul_extx16vnx1hi */
                  break;

                case 31:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 663; /* *vlmul_extx2vnx16hi */
                  break;

                case 32:
                  if (
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 686; /* *vlmul_extx4vnx8hi */
                  break;

                case 33:
                  if (
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 703; /* *vlmul_extx8vnx4hi */
                  break;

                case 34:
                  if (
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 714; /* *vlmul_extx16vnx2hi */
                  break;

                case 35:
                  if (
#line 478 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 719; /* *vlmul_extx32vnx1hi */
                  break;

                case 36:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 664; /* *vlmul_extx2vnx1si */
                  break;

                case 37:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 665; /* *vlmul_extx2vnx2si */
                  break;

                case 38:
                  if (
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 687; /* *vlmul_extx4vnx1si */
                  break;

                case 39:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 666; /* *vlmul_extx2vnx4si */
                  break;

                case 40:
                  if (
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 688; /* *vlmul_extx4vnx2si */
                  break;

                case 41:
                  if (
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 704; /* *vlmul_extx8vnx1si */
                  break;

                case 42:
                  if (
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 667; /* *vlmul_extx2vnx8si */
                  break;

                case 43:
                  if (
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 689; /* *vlmul_extx4vnx4si */
                  break;

                case 44:
                  if (
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 705; /* *vlmul_extx8vnx2si */
                  break;

                case 45:
                  if (
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                    return 715; /* *vlmul_extx16vnx1si */
                  break;

                case 46:
                  if ((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 165 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return 668; /* *vlmul_extx2vnx1di */
                  break;

                case 47:
                  if ((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 165 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return 669; /* *vlmul_extx2vnx2di */
                  break;

                case 48:
                  if ((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 180 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return 690; /* *vlmul_extx4vnx1di */
                  break;

                case 49:
                  if ((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 166 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return 670; /* *vlmul_extx2vnx4di */
                  break;

                case 50:
                  if ((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 180 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return 691; /* *vlmul_extx4vnx2di */
                  break;

                case 51:
                  if ((
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 192 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                    return 706; /* *vlmul_extx8vnx1di */
                  break;

                case 52:
                  if ((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 671; /* *vlmul_extx2vnx1sf */
                  break;

                case 53:
                  if ((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 168 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 672; /* *vlmul_extx2vnx2sf */
                  break;

                case 54:
                  if ((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 181 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 692; /* *vlmul_extx4vnx1sf */
                  break;

                case 55:
                  if ((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 169 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 673; /* *vlmul_extx2vnx4sf */
                  break;

                case 56:
                  if ((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 182 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 693; /* *vlmul_extx4vnx2sf */
                  break;

                case 57:
                  if ((
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 193 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 707; /* *vlmul_extx8vnx1sf */
                  break;

                case 58:
                  if ((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 674; /* *vlmul_extx2vnx8sf */
                  break;

                case 59:
                  if ((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 183 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 694; /* *vlmul_extx4vnx4sf */
                  break;

                case 60:
                  if ((
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 194 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 708; /* *vlmul_extx8vnx2sf */
                  break;

                case 61:
                  if ((
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 202 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                    return 716; /* *vlmul_extx16vnx1sf */
                  break;

                case 62:
                  if ((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 675; /* *vlmul_extx2vnx1df */
                  break;

                case 63:
                  if ((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 172 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 676; /* *vlmul_extx2vnx2df */
                  break;

                case 64:
                  if ((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 184 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 695; /* *vlmul_extx4vnx1df */
                  break;

                case 65:
                  if ((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 173 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 677; /* *vlmul_extx2vnx4df */
                  break;

                case 66:
                  if ((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 185 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 696; /* *vlmul_extx4vnx2df */
                  break;

                case 67:
                  if ((
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 195 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                    return 709; /* *vlmul_extx8vnx1df */
                  break;

                default:
                  break;
                }
              break;

            case REG:
              if (REGNO (x3) == 66
                  && GET_MODE (x3) == E_SImode
                  && register_operand (operands[0], E_SImode)
                  && 
#line 7251 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                return 6035; /* read_vlsi */
              break;

            default:
              break;
            }
          operands[1] = x3;
          if (register_operand (operands[1], E_VNx2QImode)
              && register_operand (operands[0], E_VNx2QImode)
              && 
#line 616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return 752; /* *movvnx2qi_fract */
          break;

        default:
          break;
        }
      operands[1] = x3;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx4QImode:
          if (reg_or_mem_operand (operands[0], E_VNx4QImode)
              && reg_or_mem_operand (operands[1], E_VNx4QImode)
              && (
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 373 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN == 32)))
            return 723; /* *movvnx4qi_whole */
          if (register_operand (operands[0], E_VNx4QImode)
              && register_operand (operands[1], E_VNx4QImode)
              && (
#line 616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 753; /* *movvnx4qi_fract */
          if (pnum_clobbers == NULL
              || !reg_or_mem_operand (operands[0], E_VNx4QImode)
              || !reg_or_mem_operand (operands[1], E_VNx4QImode))
            return -1;
          if ((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            {
              *pnum_clobbers = 1;
              return 769; /* *movvnx4qisi_lra */
            }
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return -1;
          *pnum_clobbers = 1;
          return 770; /* *movvnx4qidi_lra */

        case E_VNx8QImode:
          if (!reg_or_mem_operand (operands[0], E_VNx8QImode)
              || !reg_or_mem_operand (operands[1], E_VNx8QImode)
              || !
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 724; /* *movvnx8qi_whole */

        case E_VNx16QImode:
          if (!reg_or_mem_operand (operands[0], E_VNx16QImode)
              || !reg_or_mem_operand (operands[1], E_VNx16QImode)
              || !
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 725; /* *movvnx16qi_whole */

        case E_VNx32QImode:
          if (!reg_or_mem_operand (operands[0], E_VNx32QImode)
              || !reg_or_mem_operand (operands[1], E_VNx32QImode)
              || !
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 726; /* *movvnx32qi_whole */

        case E_VNx64QImode:
          if (!reg_or_mem_operand (operands[0], E_VNx64QImode)
              || !reg_or_mem_operand (operands[1], E_VNx64QImode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 373 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 727; /* *movvnx64qi_whole */

        case E_VNx2HImode:
          if (reg_or_mem_operand (operands[0], E_VNx2HImode)
              && reg_or_mem_operand (operands[1], E_VNx2HImode)
              && (
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN == 32)))
            return 728; /* *movvnx2hi_whole */
          if (register_operand (operands[0], E_VNx2HImode)
              && register_operand (operands[1], E_VNx2HImode)
              && (
#line 616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 391 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return 755; /* *movvnx2hi_fract */
          if (pnum_clobbers == NULL
              || !reg_or_mem_operand (operands[0], E_VNx2HImode)
              || !reg_or_mem_operand (operands[1], E_VNx2HImode))
            return -1;
          if ((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 391 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            {
              *pnum_clobbers = 1;
              return 773; /* *movvnx2hisi_lra */
            }
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 391 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return -1;
          *pnum_clobbers = 1;
          return 774; /* *movvnx2hidi_lra */

        case E_VNx4HImode:
          if (!reg_or_mem_operand (operands[0], E_VNx4HImode)
              || !reg_or_mem_operand (operands[1], E_VNx4HImode)
              || !
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 729; /* *movvnx4hi_whole */

        case E_VNx8HImode:
          if (!reg_or_mem_operand (operands[0], E_VNx8HImode)
              || !reg_or_mem_operand (operands[1], E_VNx8HImode)
              || !
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 730; /* *movvnx8hi_whole */

        case E_VNx16HImode:
          if (!reg_or_mem_operand (operands[0], E_VNx16HImode)
              || !reg_or_mem_operand (operands[1], E_VNx16HImode)
              || !
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 731; /* *movvnx16hi_whole */

        case E_VNx32HImode:
          if (!reg_or_mem_operand (operands[0], E_VNx32HImode)
              || !reg_or_mem_operand (operands[1], E_VNx32HImode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 732; /* *movvnx32hi_whole */

        case E_VNx2SImode:
          if (!reg_or_mem_operand (operands[0], E_VNx2SImode)
              || !reg_or_mem_operand (operands[1], E_VNx2SImode)
              || !
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 734; /* *movvnx2si_whole */

        case E_VNx4SImode:
          if (!reg_or_mem_operand (operands[0], E_VNx4SImode)
              || !reg_or_mem_operand (operands[1], E_VNx4SImode)
              || !
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 735; /* *movvnx4si_whole */

        case E_VNx8SImode:
          if (!reg_or_mem_operand (operands[0], E_VNx8SImode)
              || !reg_or_mem_operand (operands[1], E_VNx8SImode)
              || !
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 736; /* *movvnx8si_whole */

        case E_VNx16SImode:
          if (!reg_or_mem_operand (operands[0], E_VNx16SImode)
              || !reg_or_mem_operand (operands[1], E_VNx16SImode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 375 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 737; /* *movvnx16si_whole */

        case E_VNx2DImode:
          if (!reg_or_mem_operand (operands[0], E_VNx2DImode)
              || !reg_or_mem_operand (operands[1], E_VNx2DImode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 376 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 739; /* *movvnx2di_whole */

        case E_VNx4DImode:
          if (!reg_or_mem_operand (operands[0], E_VNx4DImode)
              || !reg_or_mem_operand (operands[1], E_VNx4DImode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 377 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 740; /* *movvnx4di_whole */

        case E_VNx8DImode:
          if (!reg_or_mem_operand (operands[0], E_VNx8DImode)
              || !reg_or_mem_operand (operands[1], E_VNx8DImode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 377 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 741; /* *movvnx8di_whole */

        case E_VNx2SFmode:
          if (!reg_or_mem_operand (operands[0], E_VNx2SFmode)
              || !reg_or_mem_operand (operands[1], E_VNx2SFmode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 379 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 743; /* *movvnx2sf_whole */

        case E_VNx4SFmode:
          if (!reg_or_mem_operand (operands[0], E_VNx4SFmode)
              || !reg_or_mem_operand (operands[1], E_VNx4SFmode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 380 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 744; /* *movvnx4sf_whole */

        case E_VNx8SFmode:
          if (!reg_or_mem_operand (operands[0], E_VNx8SFmode)
              || !reg_or_mem_operand (operands[1], E_VNx8SFmode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 381 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 745; /* *movvnx8sf_whole */

        case E_VNx16SFmode:
          if (!reg_or_mem_operand (operands[0], E_VNx16SFmode)
              || !reg_or_mem_operand (operands[1], E_VNx16SFmode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 382 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 746; /* *movvnx16sf_whole */

        case E_VNx2DFmode:
          if (!reg_or_mem_operand (operands[0], E_VNx2DFmode)
              || !reg_or_mem_operand (operands[1], E_VNx2DFmode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 384 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 748; /* *movvnx2df_whole */

        case E_VNx4DFmode:
          if (!reg_or_mem_operand (operands[0], E_VNx4DFmode)
              || !reg_or_mem_operand (operands[1], E_VNx4DFmode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 749; /* *movvnx4df_whole */

        case E_VNx8DFmode:
          if (!reg_or_mem_operand (operands[0], E_VNx8DFmode)
              || !reg_or_mem_operand (operands[1], E_VNx8DFmode)
              || !(
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 386 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 750; /* *movvnx8df_whole */

        case E_VNx2QImode:
          if (pnum_clobbers == NULL
              || !reg_or_mem_operand (operands[0], E_VNx2QImode)
              || !reg_or_mem_operand (operands[1], E_VNx2QImode))
            return -1;
          if ((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            {
              *pnum_clobbers = 1;
              return 767; /* *movvnx2qisi_lra */
            }
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          *pnum_clobbers = 1;
          return 768; /* *movvnx2qidi_lra */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_133 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  switch (GET_CODE (x3))
    {
    case NE:
    case EQ:
    case GE:
    case GT:
    case LE:
    case LT:
    case GEU:
    case GTU:
    case LEU:
    case LTU:
      if (equality_operator (x3, E_VOIDmode))
        {
          res = recog_20 (x1, insn, pnum_clobbers);
          if (res >= 0)
            return res;
        }
      if (order_operator (x3, E_VOIDmode))
        {
          res = recog_21 (x1, insn, pnum_clobbers);
          if (res >= 0)
            return res;
        }
      if (!equality_operator (x3, E_VOIDmode))
        return -1;
      operands[4] = x3;
      x4 = XEXP (x3, 1);
      if (x4 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
        return -1;
      x5 = XEXP (x1, 0);
      operands[0] = x5;
      x6 = XEXP (x3, 0);
      operands[1] = x6;
      x7 = XEXP (x2, 1);
      operands[2] = x7;
      x8 = XEXP (x2, 2);
      operands[3] = x8;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (!register_operand (operands[0], E_SImode)
              || GET_MODE (x2) != E_SImode
              || !reg_or_0_operand (operands[2], E_SImode)
              || !reg_or_0_operand (operands[3], E_SImode))
            return -1;
          switch (GET_MODE (operands[1]))
            {
            case E_SImode:
              if (!register_operand (operands[1], E_SImode)
                  || !
#line 115 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADCONDMOV))
                return -1;
              return 586; /* *th_cond_movsisi */

            case E_DImode:
              if (!register_operand (operands[1], E_DImode)
                  || !(
#line 115 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADCONDMOV) && 
#line 31 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 588; /* *th_cond_movsidi */

            default:
              return -1;
            }

        case E_DImode:
          if (!register_operand (operands[0], E_DImode)
              || GET_MODE (x2) != E_DImode
              || !register_operand (operands[1], E_DImode)
              || !reg_or_0_operand (operands[2], E_DImode)
              || !reg_or_0_operand (operands[3], E_DImode)
              || !(
#line 115 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADCONDMOV) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 589; /* *th_cond_movdidi */

        default:
          return -1;
        }

    case REG:
    case SUBREG:
      operands[1] = x3;
      x5 = XEXP (x1, 0);
      operands[0] = x5;
      x7 = XEXP (x2, 1);
      operands[2] = x7;
      x8 = XEXP (x2, 2);
      operands[3] = x8;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          switch (pattern90 (x2, E_SImode))
            {
            case 0:
              if (!
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADCONDMOV))
                return -1;
              return 590; /* *th_cond_gpr_movsisi */

            case 1:
              if (!(
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADCONDMOV) && 
#line 31 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 592; /* *th_cond_gpr_movsidi */

            default:
              return -1;
            }

        case E_DImode:
          switch (pattern90 (x2, E_DImode))
            {
            case 0:
              if (!(
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADCONDMOV) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 591; /* *th_cond_gpr_movdisi */

            case 1:
              if (!(
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADCONDMOV) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 593; /* *th_cond_gpr_movdidi */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case UNSPEC:
      if (XINT (x3, 1) != 68)
        return -1;
      x5 = XEXP (x1, 0);
      operands[0] = x5;
      switch (XVECLEN (x3, 0))
        {
        case 7:
          return recog_130 (x1, insn, pnum_clobbers);

        case 4:
          return recog_131 (x1, insn, pnum_clobbers);

        case 5:
          if (pattern81 (x3) != 0)
            return -1;
          x9 = XVECEXP (x3, 0, 2);
          if (!const_int_operand (x9, E_VOIDmode))
            return -1;
          x10 = XVECEXP (x3, 0, 0);
          switch (GET_CODE (x10))
            {
            case CONST_VECTOR:
              operands[1] = x10;
              x11 = XVECEXP (x3, 0, 1);
              if (!vector_length_operand (x11, E_VOIDmode))
                return -1;
              x8 = XEXP (x2, 2);
              operands[2] = x8;
              x7 = XEXP (x2, 1);
              switch (GET_CODE (x7))
                {
                case CONST_VECTOR:
                case REG:
                case SUBREG:
                case MEM:
                  operands[3] = x7;
                  operands[4] = x11;
                  operands[5] = x9;
                  switch (GET_MODE (operands[0]))
                    {
                    case E_VNx1BImode:
                      if (pattern211 (x2, E_VNx1BImode) != 0
                          || !
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 862; /* pred_movvnx1bi */

                    case E_VNx2BImode:
                      if (pattern211 (x2, E_VNx2BImode) != 0
                          || !
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 863; /* pred_movvnx2bi */

                    case E_VNx4BImode:
                      if (pattern211 (x2, E_VNx4BImode) != 0
                          || !
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 864; /* pred_movvnx4bi */

                    case E_VNx8BImode:
                      if (pattern211 (x2, E_VNx8BImode) != 0
                          || !
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 865; /* pred_movvnx8bi */

                    case E_VNx16BImode:
                      if (pattern211 (x2, E_VNx16BImode) != 0
                          || !
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 866; /* pred_movvnx16bi */

                    case E_VNx32BImode:
                      if (pattern211 (x2, E_VNx32BImode) != 0
                          || !
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 867; /* pred_movvnx32bi */

                    case E_VNx64BImode:
                      if (pattern211 (x2, E_VNx64BImode) != 0
                          || !(
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                        return -1;
                      return 868; /* pred_movvnx64bi */

                    default:
                      return -1;
                    }

                case AND:
                  switch (pattern173 (x2))
                    {
                    case 0:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4444; /* pred_andvnx1bi */

                    case 1:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4447; /* pred_andvnx2bi */

                    case 2:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4450; /* pred_andvnx4bi */

                    case 3:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4453; /* pred_andvnx8bi */

                    case 4:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4456; /* pred_andvnx16bi */

                    case 5:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4459; /* pred_andvnx32bi */

                    case 6:
                      if (!(
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                        return -1;
                      return 4462; /* pred_andvnx64bi */

                    case 7:
                      if (!
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4486; /* pred_andnotvnx1bi */

                    case 8:
                      if (!
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4488; /* pred_andnotvnx2bi */

                    case 9:
                      if (!
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4490; /* pred_andnotvnx4bi */

                    case 10:
                      if (!
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4492; /* pred_andnotvnx8bi */

                    case 11:
                      if (!
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4494; /* pred_andnotvnx16bi */

                    case 12:
                      if (!
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4496; /* pred_andnotvnx32bi */

                    case 13:
                      if (!(
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                        return -1;
                      return 4498; /* pred_andnotvnx64bi */

                    default:
                      return -1;
                    }

                case IOR:
                  switch (pattern173 (x2))
                    {
                    case 0:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4445; /* pred_iorvnx1bi */

                    case 1:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4448; /* pred_iorvnx2bi */

                    case 2:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4451; /* pred_iorvnx4bi */

                    case 3:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4454; /* pred_iorvnx8bi */

                    case 4:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4457; /* pred_iorvnx16bi */

                    case 5:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4460; /* pred_iorvnx32bi */

                    case 6:
                      if (!(
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                        return -1;
                      return 4463; /* pred_iorvnx64bi */

                    case 7:
                      if (!
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4487; /* pred_iornotvnx1bi */

                    case 8:
                      if (!
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4489; /* pred_iornotvnx2bi */

                    case 9:
                      if (!
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4491; /* pred_iornotvnx4bi */

                    case 10:
                      if (!
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4493; /* pred_iornotvnx8bi */

                    case 11:
                      if (!
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4495; /* pred_iornotvnx16bi */

                    case 12:
                      if (!
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4497; /* pred_iornotvnx32bi */

                    case 13:
                      if (!(
#line 5247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                        return -1;
                      return 4499; /* pred_iornotvnx64bi */

                    default:
                      return -1;
                    }

                case XOR:
                  operands[5] = x11;
                  operands[6] = x9;
                  x12 = XEXP (x7, 0);
                  operands[3] = x12;
                  switch (pattern171 (x2))
                    {
                    case 0:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4446; /* pred_xorvnx1bi */

                    case 1:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4449; /* pred_xorvnx2bi */

                    case 2:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4452; /* pred_xorvnx4bi */

                    case 3:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4455; /* pred_xorvnx8bi */

                    case 4:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4458; /* pred_xorvnx16bi */

                    case 5:
                      if (!
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                        return -1;
                      return 4461; /* pred_xorvnx32bi */

                    case 6:
                      if (!(
#line 5205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                        return -1;
                      return 4464; /* pred_xorvnx64bi */

                    default:
                      return -1;
                    }

                case NOT:
                  x12 = XEXP (x7, 0);
                  switch (GET_CODE (x12))
                    {
                    case AND:
                      switch (pattern199 (x2))
                        {
                        case 0:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4465; /* pred_nandvnx1bi */

                        case 1:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4468; /* pred_nandvnx2bi */

                        case 2:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4471; /* pred_nandvnx4bi */

                        case 3:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4474; /* pred_nandvnx8bi */

                        case 4:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4477; /* pred_nandvnx16bi */

                        case 5:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4480; /* pred_nandvnx32bi */

                        case 6:
                          if (!(
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                            return -1;
                          return 4483; /* pred_nandvnx64bi */

                        default:
                          return -1;
                        }

                    case IOR:
                      switch (pattern199 (x2))
                        {
                        case 0:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4466; /* pred_niorvnx1bi */

                        case 1:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4469; /* pred_niorvnx2bi */

                        case 2:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4472; /* pred_niorvnx4bi */

                        case 3:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4475; /* pred_niorvnx8bi */

                        case 4:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4478; /* pred_niorvnx16bi */

                        case 5:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4481; /* pred_niorvnx32bi */

                        case 6:
                          if (!(
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                            return -1;
                          return 4484; /* pred_niorvnx64bi */

                        default:
                          return -1;
                        }

                    case XOR:
                      switch (pattern199 (x2))
                        {
                        case 0:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4467; /* pred_nxorvnx1bi */

                        case 1:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4470; /* pred_nxorvnx2bi */

                        case 2:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4473; /* pred_nxorvnx4bi */

                        case 3:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4476; /* pred_nxorvnx8bi */

                        case 4:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4479; /* pred_nxorvnx16bi */

                        case 5:
                          if (!
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4482; /* pred_nxorvnx32bi */

                        case 6:
                          if (!(
#line 5226 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                            return -1;
                          return 4485; /* pred_nxorvnx64bi */

                        default:
                          return -1;
                        }

                    case REG:
                    case SUBREG:
                      operands[3] = x12;
                      operands[4] = x11;
                      operands[5] = x9;
                      switch (GET_MODE (operands[0]))
                        {
                        case E_VNx1BImode:
                          if (pattern233 (x2, E_VNx1BImode) != 0
                              || !
#line 5266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4500; /* pred_notvnx1bi */

                        case E_VNx2BImode:
                          if (pattern233 (x2, E_VNx2BImode) != 0
                              || !
#line 5266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4501; /* pred_notvnx2bi */

                        case E_VNx4BImode:
                          if (pattern233 (x2, E_VNx4BImode) != 0
                              || !
#line 5266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4502; /* pred_notvnx4bi */

                        case E_VNx8BImode:
                          if (pattern233 (x2, E_VNx8BImode) != 0
                              || !
#line 5266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4503; /* pred_notvnx8bi */

                        case E_VNx16BImode:
                          if (pattern233 (x2, E_VNx16BImode) != 0
                              || !
#line 5266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4504; /* pred_notvnx16bi */

                        case E_VNx32BImode:
                          if (pattern233 (x2, E_VNx32BImode) != 0
                              || !
#line 5266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
                            return -1;
                          return 4505; /* pred_notvnx32bi */

                        case E_VNx64BImode:
                          if (pattern233 (x2, E_VNx64BImode) != 0
                              || !(
#line 5266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                            return -1;
                          return 4506; /* pred_notvnx64bi */

                        default:
                          return -1;
                        }

                    default:
                      return -1;
                    }

                default:
                  return -1;
                }

            case CONST_INT:
            case REG:
            case SUBREG:
              return recog_124 (x1, insn, pnum_clobbers);

            default:
              return -1;
            }

        case 6:
          x13 = XVECEXP (x3, 0, 4);
          if (GET_CODE (x13) != REG
              || REGNO (x13) != 66
              || GET_MODE (x13) != E_SImode)
            return -1;
          x14 = XVECEXP (x3, 0, 5);
          if (GET_CODE (x14) != REG
              || REGNO (x14) != 67
              || GET_MODE (x14) != E_SImode)
            return -1;
          x10 = XVECEXP (x3, 0, 0);
          operands[1] = x10;
          x11 = XVECEXP (x3, 0, 1);
          if (!vector_length_operand (x11, E_VOIDmode))
            return -1;
          x9 = XVECEXP (x3, 0, 2);
          if (!const_int_operand (x9, E_VOIDmode))
            return -1;
          return recog_129 (x1, insn, pnum_clobbers);

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_134 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (XVECLEN (x2, 0))
    {
    case 2:
      return recog_15 (x1, insn, pnum_clobbers);

    case 1:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      switch (XINT (x2, 1))
        {
        case 12:
          switch (pattern60 (x2))
            {
            case 0:
              if (!
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
                return -1;
              return 152; /* lrintsfsi2 */

            case 1:
              if (!(
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
                return -1;
              return 156; /* lrintdfsi2 */

            case 2:
              if (!(
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
                return -1;
              return 160; /* lrinthfsi2 */

            case 3:
              if (!(
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))))
                return -1;
              return 154; /* lrintsfdi2 */

            case 4:
              if (!(
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))))
                return -1;
              return 158; /* lrintdfdi2 */

            case 5:
              if (!(
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))))
                return -1;
              return 162; /* lrinthfdi2 */

            default:
              return -1;
            }

        case 13:
          switch (pattern60 (x2))
            {
            case 0:
              if (!
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
                return -1;
              return 153; /* lroundsfsi2 */

            case 1:
              if (!(
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
                return -1;
              return 157; /* lrounddfsi2 */

            case 2:
              if (!(
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
                return -1;
              return 161; /* lroundhfsi2 */

            case 3:
              if (!(
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))))
                return -1;
              return 155; /* lroundsfdi2 */

            case 4:
              if (!(
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))))
                return -1;
              return 159; /* lrounddfdi2 */

            case 5:
              if (!(
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))))
                return -1;
              return 163; /* lroundhfdi2 */

            default:
              return -1;
            }

        case 3:
          switch (pattern61 (x2))
            {
            case 0:
              if (!
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
                return -1;
              return 164; /* got_loadsi */

            case 1:
              if (!
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
                return -1;
              return 165; /* got_loaddi */

            default:
              return -1;
            }

        case 7:
          switch (pattern61 (x2))
            {
            case 0:
              if (!
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
                return -1;
              return 168; /* got_load_tls_gdsi */

            case 1:
              if (!
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
                return -1;
              return 169; /* got_load_tls_gddi */

            default:
              return -1;
            }

        case 6:
          switch (pattern61 (x2))
            {
            case 0:
              if (!
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
                return -1;
              return 170; /* got_load_tls_iesi */

            case 1:
              if (!
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
                return -1;
              return 171; /* got_load_tls_iedi */

            default:
              return -1;
            }

        case 17:
          switch (pattern62 (x2))
            {
            case 0:
              if (!(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 369; /* orcbsi2 */

            case 1:
              if (!(
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 370; /* orcbdi2 */

            default:
              return -1;
            }

        case 18:
          switch (pattern62 (x2))
            {
            case 0:
              if (!(
#line 82 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 421; /* riscv_brev8_si */

            case 1:
              if (!(
#line 82 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 422; /* riscv_brev8_di */

            default:
              return -1;
            }

        case 19:
          switch (pattern63 (x2))
            {
            case 0:
              if (!
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB && !TARGET_64BIT))
                return -1;
              return 423; /* riscv_zip */

            case 1:
              if (!
#line 161 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(!TARGET_64BIT && TARGET_XTHEADFMV))
                return -1;
              return 595; /* th_fmv_x_w */

            default:
              return -1;
            }

        case 20:
          switch (pattern63 (x2))
            {
            case 0:
              if (!
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB && !TARGET_64BIT))
                return -1;
              return 424; /* riscv_unzip */

            case 1:
              if (!
#line 170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(!TARGET_64BIT && TARGET_XTHEADFMV))
                return -1;
              return 596; /* th_fmv_x_hw */

            default:
              return -1;
            }

        case 32:
          if (GET_MODE (x2) != E_DImode
              || !register_operand (operands[0], E_DImode))
            return -1;
          x4 = XVECEXP (x2, 0, 0);
          operands[1] = x4;
          if (!register_operand (operands[1], E_DImode)
              || !
#line 213 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKND && TARGET_64BIT))
            return -1;
          return 444; /* riscv_aes64im */

        case 39:
          switch (pattern62 (x2))
            {
            case 0:
              if (!(
#line 281 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 451; /* riscv_sha256sig0_si */

            case 1:
              if (!(
#line 281 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 452; /* riscv_sha256sig0_di */

            default:
              return -1;
            }

        case 40:
          switch (pattern62 (x2))
            {
            case 0:
              if (!(
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 453; /* riscv_sha256sig1_si */

            case 1:
              if (!(
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 454; /* riscv_sha256sig1_di */

            default:
              return -1;
            }

        case 41:
          switch (pattern62 (x2))
            {
            case 0:
              if (!(
#line 297 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 455; /* riscv_sha256sum0_si */

            case 1:
              if (!(
#line 297 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 456; /* riscv_sha256sum0_di */

            default:
              return -1;
            }

        case 42:
          switch (pattern62 (x2))
            {
            case 0:
              if (!(
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 457; /* riscv_sha256sum1_si */

            case 1:
              if (!(
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 458; /* riscv_sha256sum1_di */

            default:
              return -1;
            }

        case 43:
          if (GET_MODE (x2) != E_DImode
              || !register_operand (operands[0], E_DImode))
            return -1;
          x4 = XVECEXP (x2, 0, 0);
          operands[1] = x4;
          if (!register_operand (operands[1], E_DImode)
              || !
#line 369 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && TARGET_64BIT))
            return -1;
          return 465; /* riscv_sha512sig0 */

        case 46:
          if (GET_MODE (x2) != E_DImode
              || !register_operand (operands[0], E_DImode))
            return -1;
          x4 = XVECEXP (x2, 0, 0);
          operands[1] = x4;
          if (!register_operand (operands[1], E_DImode)
              || !
#line 377 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && TARGET_64BIT))
            return -1;
          return 466; /* riscv_sha512sig1 */

        case 49:
          if (GET_MODE (x2) != E_DImode
              || !register_operand (operands[0], E_DImode))
            return -1;
          x4 = XVECEXP (x2, 0, 0);
          operands[1] = x4;
          if (!register_operand (operands[1], E_DImode)
              || !
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && TARGET_64BIT))
            return -1;
          return 467; /* riscv_sha512sum0 */

        case 51:
          if (GET_MODE (x2) != E_DImode
              || !register_operand (operands[0], E_DImode))
            return -1;
          x4 = XVECEXP (x2, 0, 0);
          operands[1] = x4;
          if (!register_operand (operands[1], E_DImode)
              || !
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && TARGET_64BIT))
            return -1;
          return 468; /* riscv_sha512sum1 */

        case 53:
          switch (pattern62 (x2))
            {
            case 0:
              if (!(
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 469; /* riscv_sm3p0_si */

            case 1:
              if (!(
#line 403 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 470; /* riscv_sm3p0_di */

            default:
              return -1;
            }

        case 54:
          switch (pattern62 (x2))
            {
            case 0:
              if (!(
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 471; /* riscv_sm3p1_si */

            case 1:
              if (!(
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 472; /* riscv_sm3p1_di */

            default:
              return -1;
            }

        case 67:
          return recog_4 (x1, insn, pnum_clobbers);

        case 69:
          x4 = XVECEXP (x2, 0, 0);
          operands[1] = x4;
          switch (GET_MODE (operands[0]))
            {
            case E_SImode:
              if (!register_operand (operands[0], E_SImode)
                  || GET_MODE (x2) != E_SImode
                  || !const_int_operand (operands[1], E_SImode)
                  || !(
#line 528 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 721; /* vlmax_avlsi */

            case E_DImode:
              if (!register_operand (operands[0], E_DImode)
                  || GET_MODE (x2) != E_DImode
                  || !const_int_operand (operands[1], E_DImode)
                  || !(
#line 528 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 722; /* vlmax_avldi */

            default:
              return -1;
            }

        case 71:
          switch (pattern65 (x2))
            {
            case 0:
              if ((
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 5709; /* pred_reduc_plusovnx1sfvnx2sf */
              if (!(
#line 6913 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 269 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5727; /* pred_reduc_plusovnx1sfvnx1sf */

            case 1:
              if ((
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 5711; /* pred_reduc_plusovnx2sfvnx2sf */
              if (!(
#line 6913 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5729; /* pred_reduc_plusovnx2sfvnx1sf */

            case 2:
              if ((
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 5713; /* pred_reduc_plusovnx4sfvnx2sf */
              if (!(
#line 6913 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 271 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5731; /* pred_reduc_plusovnx4sfvnx1sf */

            case 3:
              if ((
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 5715; /* pred_reduc_plusovnx8sfvnx2sf */
              if (!(
#line 6913 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 272 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5733; /* pred_reduc_plusovnx8sfvnx1sf */

            case 4:
              if (!(
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return -1;
              return 5717; /* pred_reduc_plusovnx16sfvnx2sf */

            case 5:
              if (!(
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5719; /* pred_reduc_plusovnx1dfvnx1df */

            case 6:
              if (!(
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5721; /* pred_reduc_plusovnx2dfvnx1df */

            case 7:
              if (!(
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5723; /* pred_reduc_plusovnx4dfvnx1df */

            case 8:
              if (!(
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5725; /* pred_reduc_plusovnx8dfvnx1df */

            case 9:
              if (!
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
                return -1;
              return 5735; /* pred_widen_reduc_plusovnx1sfvnx1df */

            case 10:
              if (!
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
                return -1;
              return 5737; /* pred_widen_reduc_plusovnx2sfvnx1df */

            case 11:
              if (!
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
                return -1;
              return 5739; /* pred_widen_reduc_plusovnx4sfvnx1df */

            case 12:
              if (!
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
                return -1;
              return 5741; /* pred_widen_reduc_plusovnx8sfvnx1df */

            case 13:
              if (!(
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 5743; /* pred_widen_reduc_plusovnx16sfvnx1df */

            default:
              return -1;
            }

        case 72:
          switch (pattern65 (x2))
            {
            case 0:
              if ((
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 5710; /* pred_reduc_plusuvnx1sfvnx2sf */
              if (!(
#line 6913 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 269 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5728; /* pred_reduc_plusuvnx1sfvnx1sf */

            case 1:
              if ((
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 5712; /* pred_reduc_plusuvnx2sfvnx2sf */
              if (!(
#line 6913 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5730; /* pred_reduc_plusuvnx2sfvnx1sf */

            case 2:
              if ((
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 5714; /* pred_reduc_plusuvnx4sfvnx2sf */
              if (!(
#line 6913 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 271 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5732; /* pred_reduc_plusuvnx4sfvnx1sf */

            case 3:
              if ((
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return 5716; /* pred_reduc_plusuvnx8sfvnx2sf */
              if (!(
#line 6913 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 272 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
                return -1;
              return 5734; /* pred_reduc_plusuvnx8sfvnx1sf */

            case 4:
              if (!(
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
                return -1;
              return 5718; /* pred_reduc_plusuvnx16sfvnx2sf */

            case 5:
              if (!(
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5720; /* pred_reduc_plusuvnx1dfvnx1df */

            case 6:
              if (!(
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5722; /* pred_reduc_plusuvnx2dfvnx1df */

            case 7:
              if (!(
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5724; /* pred_reduc_plusuvnx4dfvnx1df */

            case 8:
              if (!(
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
                return -1;
              return 5726; /* pred_reduc_plusuvnx8dfvnx1df */

            case 9:
              if (!
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
                return -1;
              return 5736; /* pred_widen_reduc_plusuvnx1sfvnx1df */

            case 10:
              if (!
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
                return -1;
              return 5738; /* pred_widen_reduc_plusuvnx2sfvnx1df */

            case 11:
              if (!
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
                return -1;
              return 5740; /* pred_widen_reduc_plusuvnx4sfvnx1df */

            case 12:
              if (!
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32))
                return -1;
              return 5742; /* pred_widen_reduc_plusuvnx8sfvnx1df */

            case 13:
              if (!(
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return -1;
              return 5744; /* pred_widen_reduc_plusuvnx16sfvnx1df */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case 3:
      return recog_13 (x1, insn, pnum_clobbers);

    case 4:
      return recog_14 (x1, insn, pnum_clobbers);

    case 5:
      if (XINT (x2, 1) != 66)
        return -1;
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      switch (pattern71 (x2))
        {
        case 0:
          if (!(
#line 890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 798; /* vsetvlsi_no_side_effects */

        case 1:
          if (!(
#line 890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 799; /* vsetvldi_no_side_effects */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_135 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case PLUS:
      if (GET_MODE (x4) != E_SImode
          || !register_operand (operands[0], E_DImode)
          || GET_MODE (x3) != E_DImode)
        return -1;
      x5 = XEXP (x4, 0);
      switch (GET_CODE (x5))
        {
        case REG:
        case SUBREG:
          operands[1] = x5;
          if (!register_operand (operands[1], E_SImode))
            return -1;
          x6 = XEXP (x4, 1);
          operands[2] = x6;
          if (!arith_operand (operands[2], E_SImode)
              || !
#line 568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
            return -1;
          return 6; /* *addsi3_extended */

        case MULT:
          if (GET_MODE (x5) != E_SImode)
            return -1;
          x6 = XEXP (x4, 1);
          operands[3] = x6;
          if (!register_operand (operands[3], E_SImode))
            return -1;
          x7 = XEXP (x5, 0);
          switch (GET_CODE (x7))
            {
            case REG:
            case SUBREG:
              operands[1] = x7;
              if (!register_operand (operands[1], E_SImode))
                return -1;
              x8 = XEXP (x5, 1);
              operands[2] = x8;
              if (!register_operand (operands[2], E_SImode)
                  || !
#line 194 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC && TARGET_64BIT))
                return -1;
              return 599; /* *th_mulawsi */

            case SIGN_EXTEND:
              if (GET_MODE (x7) != E_SImode)
                return -1;
              x8 = XEXP (x5, 1);
              if (GET_CODE (x8) != SIGN_EXTEND
                  || GET_MODE (x8) != E_SImode)
                return -1;
              x9 = XEXP (x7, 0);
              operands[1] = x9;
              if (!register_operand (operands[1], E_HImode))
                return -1;
              x10 = XEXP (x8, 0);
              operands[2] = x10;
              if (!register_operand (operands[2], E_HImode)
                  || !
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC && TARGET_64BIT))
                return -1;
              return 602; /* *th_sextw_maddhisi4 */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case REG:
    case SUBREG:
    case MEM:
    case TRUNCATE:
      switch (GET_CODE (x4))
        {
        case SUBREG:
        case TRUNCATE:
          res = recog_1 (x1, insn, pnum_clobbers);
          if (res >= 0)
            return res;
          break;

        case MEM:
          if (GET_MODE (x4) == E_SImode)
            {
              x5 = XEXP (x4, 0);
              operands[1] = x5;
              if (absolute_symbolic_operand (operands[1], E_VOIDmode))
                {
                  switch (GET_MODE (operands[0]))
                    {
                    case E_HImode:
                      if (register_operand (operands[0], E_HImode)
                          && GET_MODE (x3) == E_HImode
                          && (
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 60 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                        return 519; /* *local_pic_load_ssi */
                      break;

                    case E_SImode:
                      if (register_operand (operands[0], E_SImode)
                          && GET_MODE (x3) == E_SImode
                          && (
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 60 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                        return 520; /* *local_pic_load_ssi */
                      break;

                    default:
                      break;
                    }
                }
            }
          break;

        default:
          break;
        }
      operands[1] = x4;
      res = recog_2 (x1, insn, pnum_clobbers);
      if (res >= 0)
        return res;
      switch (GET_CODE (x4))
        {
        case SUBREG:
          if (pnum_clobbers == NULL
              || maybe_ne (SUBREG_BYTE (x4), 0)
              || GET_MODE (x4) != E_SImode
              || !register_operand (operands[0], E_DImode)
              || GET_MODE (x3) != E_DImode)
            return -1;
          x5 = XEXP (x4, 0);
          if (GET_MODE (x5) != E_DImode)
            return -1;
          switch (GET_CODE (x5))
            {
            case SMIN:
              if (pattern119 (x5) != 0
                  || !
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0))
                return -1;
              *pnum_clobbers = 2;
              return 381; /* *minmax */

            case UMIN:
              if (pattern119 (x5) != 0
                  || !
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0))
                return -1;
              *pnum_clobbers = 2;
              return 382; /* *minmax */

            case SMAX:
              if (pattern119 (x5) != 0
                  || !
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0))
                return -1;
              *pnum_clobbers = 2;
              return 383; /* *minmax */

            case UMAX:
              if (pattern119 (x5) != 0
                  || !
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0))
                return -1;
              *pnum_clobbers = 2;
              return 384; /* *minmax */

            default:
              return -1;
            }

        case MEM:
          x5 = XEXP (x4, 0);
          operands[1] = x5;
          if (!absolute_symbolic_operand (operands[1], E_VOIDmode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_HImode:
              if (!register_operand (operands[0], E_HImode)
                  || GET_MODE (x3) != E_HImode)
                return -1;
              switch (GET_MODE (x4))
                {
                case E_QImode:
                  if (!
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])))
                    return -1;
                  return 513; /* *local_pic_load_sqi */

                case E_HImode:
                  if (!
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])))
                    return -1;
                  return 516; /* *local_pic_load_shi */

                default:
                  return -1;
                }

            case E_SImode:
              if (!register_operand (operands[0], E_SImode)
                  || GET_MODE (x3) != E_SImode)
                return -1;
              switch (GET_MODE (x4))
                {
                case E_QImode:
                  if (!
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])))
                    return -1;
                  return 514; /* *local_pic_load_sqi */

                case E_HImode:
                  if (!
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])))
                    return -1;
                  return 517; /* *local_pic_load_shi */

                default:
                  return -1;
                }

            case E_DImode:
              if (!register_operand (operands[0], E_DImode)
                  || GET_MODE (x3) != E_DImode)
                return -1;
              switch (GET_MODE (x4))
                {
                case E_QImode:
                  if (!(
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 515; /* *local_pic_load_sqi */

                case E_HImode:
                  if (!(
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 518; /* *local_pic_load_shi */

                case E_SImode:
                  if (!(
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 521; /* *local_pic_load_ssi */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        default:
          return -1;
        }

    case MINUS:
      if (GET_MODE (x4) != E_SImode
          || !register_operand (operands[0], E_DImode)
          || GET_MODE (x3) != E_DImode)
        return -1;
      x6 = XEXP (x4, 1);
      switch (GET_CODE (x6))
        {
        case REG:
        case SUBREG:
          operands[2] = x6;
          if (!register_operand (operands[2], E_SImode))
            return -1;
          x5 = XEXP (x4, 0);
          operands[1] = x5;
          if (!reg_or_0_operand (operands[1], E_SImode)
              || !
#line 703 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
            return -1;
          return 13; /* *subsi3_extended */

        case MULT:
          if (GET_MODE (x6) != E_SImode)
            return -1;
          x5 = XEXP (x4, 0);
          operands[3] = x5;
          if (!register_operand (operands[3], E_SImode))
            return -1;
          x11 = XEXP (x6, 0);
          switch (GET_CODE (x11))
            {
            case REG:
            case SUBREG:
              operands[1] = x11;
              if (!register_operand (operands[1], E_SImode))
                return -1;
              x12 = XEXP (x6, 1);
              operands[2] = x12;
              if (!register_operand (operands[2], E_SImode)
                  || !
#line 255 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC && TARGET_64BIT))
                return -1;
              return 605; /* *th_mulswsi */

            case SIGN_EXTEND:
              if (GET_MODE (x11) != E_SImode)
                return -1;
              x12 = XEXP (x6, 1);
              if (GET_CODE (x12) != SIGN_EXTEND
                  || GET_MODE (x12) != E_SImode)
                return -1;
              x13 = XEXP (x11, 0);
              operands[1] = x13;
              if (!register_operand (operands[1], E_HImode))
                return -1;
              x14 = XEXP (x12, 0);
              operands[2] = x14;
              if (!register_operand (operands[2], E_HImode)
                  || !
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC && TARGET_64BIT))
                return -1;
              return 608; /* *th_sextw_msubhisi4 */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case NEG:
      if (pattern19 (x3, E_SImode) != 0
          || !
#line 739 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
        return -1;
      return 17; /* *negsi2_extended */

    case MULT:
      if (pattern20 (x3, E_SImode) != 0
          || !
#line 885 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT))
        return -1;
      return 24; /* *mulsi3_extended */

    case DIV:
      if (pattern20 (x3, E_SImode) != 0
          || !
#line 1064 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV && TARGET_64BIT))
        return -1;
      return 40; /* *divsi3_extended */

    case UDIV:
      if (pattern20 (x3, E_SImode) != 0
          || !
#line 1064 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV && TARGET_64BIT))
        return -1;
      return 41; /* *udivsi3_extended */

    case MOD:
      if (pattern20 (x3, E_SImode) != 0
          || !
#line 1064 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV && TARGET_64BIT))
        return -1;
      return 42; /* *modsi3_extended */

    case UMOD:
      if (pattern20 (x3, E_SImode) != 0
          || !
#line 1064 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV && TARGET_64BIT))
        return -1;
      return 43; /* *umodsi3_extended */

    case ASHIFT:
      if (pattern19 (x3, E_SImode) != 0)
        return -1;
      x6 = XEXP (x4, 1);
      operands[2] = x6;
      if (arith_operand (operands[2], E_QImode)
          && 
#line 2090 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
        return 213; /* *ashlsi3_extend */
      if (!subreg_lowpart_operator (x6, E_VOIDmode))
        return -1;
      switch (pattern106 (x6))
        {
        case 0:
          if (!
#line 2109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1))
            return -1;
          return 216; /* *ashlsi3_extend_mask */

        case 1:
          if (!
#line 2131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1))
            return -1;
          return 219; /* *ashlsi3_extend_mask_1 */

        default:
          return -1;
        }

    case ASHIFTRT:
      if (pattern19 (x3, E_SImode) != 0)
        return -1;
      x6 = XEXP (x4, 1);
      operands[2] = x6;
      if (arith_operand (operands[2], E_QImode)
          && 
#line 2090 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
        return 214; /* *ashrsi3_extend */
      if (!subreg_lowpart_operator (x6, E_VOIDmode))
        return -1;
      switch (pattern106 (x6))
        {
        case 0:
          if (!
#line 2109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1))
            return -1;
          return 217; /* *ashrsi3_extend_mask */

        case 1:
          if (!
#line 2131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1))
            return -1;
          return 220; /* *ashrsi3_extend_mask_1 */

        default:
          return -1;
        }

    case LSHIFTRT:
      if (pattern19 (x3, E_SImode) != 0)
        return -1;
      x6 = XEXP (x4, 1);
      operands[2] = x6;
      if (arith_operand (operands[2], E_QImode)
          && 
#line 2090 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
        return 215; /* *lshrsi3_extend */
      if (!subreg_lowpart_operator (x6, E_VOIDmode))
        return -1;
      switch (pattern106 (x6))
        {
        case 0:
          if (!
#line 2109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1))
            return -1;
          return 218; /* *lshrsi3_extend_mask */

        case 1:
          if (!
#line 2131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1))
            return -1;
          return 221; /* *lshrsi3_extend_mask_1 */

        default:
          return -1;
        }

    case CLZ:
      if (pattern19 (x3, E_SImode) != 0
          || !
#line 253 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB))
        return -1;
      return 347; /* *clzdisi2 */

    case CTZ:
      if (pattern19 (x3, E_SImode) != 0
          || !
#line 253 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB))
        return -1;
      return 348; /* *ctzdisi2 */

    case POPCOUNT:
      if (pattern19 (x3, E_SImode) != 0
          || !
#line 253 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB))
        return -1;
      return 349; /* *popcountdisi2 */

    case ROTATERT:
      if (pattern20 (x3, E_QImode) != 0
          || !
#line 328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)))
        return -1;
      return 365; /* *rotrsi3_sext */

    case ROTATE:
      if (pattern20 (x3, E_QImode) != 0
          || !
#line 352 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)))
        return -1;
      return 368; /* rotlsi3_sext */

    default:
      return -1;
    }
}

static int
recog_136 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15, x16, x17;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      operands[1] = x4;
      x5 = XEXP (x3, 1);
      operands[2] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_SFmode:
          if (pattern0 (x3, E_SFmode) != 0
              || !
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
            return -1;
          return 1; /* addsf3 */

        case E_DFmode:
          if (pattern0 (x3, E_DFmode) != 0
              || !(
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 2; /* adddf3 */

        case E_HFmode:
          if (pattern0 (x3, E_HFmode) != 0
              || !(
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 3; /* addhf3 */

        case E_SImode:
          if (pattern73 (x3, E_SImode) != 0)
            return -1;
          return 4; /* addsi3 */

        case E_DImode:
          if (pattern73 (x3, E_DImode) != 0
              || !
#line 483 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
            return -1;
          return 5; /* adddi3 */

        case E_HImode:
          switch (pattern83 (x3))
            {
            case 0:
              return 182; /* *addhihi3 */

            case 1:
              return 183; /* *addsihi3 */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case ASHIFT:
      x6 = XEXP (x4, 0);
      operands[1] = x6;
      x7 = XEXP (x4, 1);
      operands[2] = x7;
      x5 = XEXP (x3, 1);
      operands[3] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (pattern88 (x3, E_SImode) != 0)
            return -1;
          if (imm123_operand (operands[2], E_QImode)
              && (
#line 37 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBA) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return 332; /* *shNadd */
          if (!const_int_operand (operands[2], E_VOIDmode)
              || !(
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBA
   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 572; /* *th_addslsi4 */

        case E_DImode:
          if (pattern88 (x3, E_DImode) != 0)
            return -1;
          if (imm123_operand (operands[2], E_QImode)
              && (
#line 37 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBA) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return 333; /* *shNadd */
          if (!const_int_operand (operands[2], E_VOIDmode)
              || !(
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBA
   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 573; /* *th_addsldi4 */

        default:
          return -1;
        }

    case AND:
      if (GET_MODE (x4) != E_DImode)
        return -1;
      x6 = XEXP (x4, 0);
      if (GET_CODE (x6) != ASHIFT
          || GET_MODE (x6) != E_DImode
          || !register_operand (operands[0], E_DImode)
          || GET_MODE (x3) != E_DImode)
        return -1;
      x8 = XEXP (x6, 0);
      operands[1] = x8;
      if (!register_operand (operands[1], E_DImode))
        return -1;
      x9 = XEXP (x6, 1);
      operands[2] = x9;
      if (!imm123_operand (operands[2], E_QImode))
        return -1;
      x7 = XEXP (x4, 1);
      operands[3] = x7;
      if (pnum_clobbers != NULL
          && consecutive_bits_operand (operands[3], E_DImode))
        {
          x5 = XEXP (x3, 1);
          operands[4] = x5;
          if (register_operand (operands[4], E_DImode)
              && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2]))))
            {
              *pnum_clobbers = 1;
              return 334; /* *andi_add.uw */
            }
        }
      if (!immediate_operand (operands[3], E_VOIDmode))
        return -1;
      x5 = XEXP (x3, 1);
      operands[4] = x5;
      if (!register_operand (operands[4], E_DImode)
          || !
#line 117 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff))
        return -1;
      return 335; /* *shNadduw */

    case ZERO_EXTEND:
      if (pattern19 (x3, E_DImode) != 0)
        return -1;
      x5 = XEXP (x3, 1);
      operands[2] = x5;
      if (!register_operand (operands[2], E_DImode)
          || !
#line 172 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA))
        return -1;
      return 336; /* *add.uw */

    case MULT:
      x5 = XEXP (x3, 1);
      operands[3] = x5;
      x6 = XEXP (x4, 0);
      switch (GET_CODE (x6))
        {
        case REG:
        case SUBREG:
          operands[1] = x6;
          x7 = XEXP (x4, 1);
          operands[2] = x7;
          switch (GET_MODE (operands[0]))
            {
            case E_SImode:
              if (pattern94 (x3, E_SImode) != 0)
                return -1;
              if ((
#line 182 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return 597; /* *th_mulasi */
              if (!
#line 205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC && TARGET_64BIT))
                return -1;
              return 600; /* *th_mulawsi2 */

            case E_DImode:
              if (pattern94 (x3, E_DImode) != 0
                  || !(
#line 182 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 598; /* *th_muladi */

            default:
              return -1;
            }

        case SIGN_EXTEND:
          if (GET_MODE (x6) != E_SImode)
            return -1;
          x7 = XEXP (x4, 1);
          if (GET_CODE (x7) != SIGN_EXTEND
              || GET_MODE (x7) != E_SImode
              || !register_operand (operands[0], E_SImode)
              || GET_MODE (x3) != E_SImode
              || GET_MODE (x4) != E_SImode)
            return -1;
          x8 = XEXP (x6, 0);
          operands[1] = x8;
          if (!register_operand (operands[1], E_HImode))
            return -1;
          x10 = XEXP (x7, 0);
          operands[2] = x10;
          if (!register_operand (operands[2], E_HImode)
              || !register_operand (operands[3], E_SImode)
              || !
#line 218 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC))
            return -1;
          return 601; /* *th_maddhisi4 */

        default:
          return -1;
        }

    case FFS:
      x6 = XEXP (x4, 0);
      if (GET_CODE (x6) != UNSPEC
          || XVECLEN (x6, 0) != 5
          || XINT (x6, 1) != 68)
        return -1;
      x11 = XVECEXP (x6, 0, 0);
      if (GET_CODE (x11) != AND)
        return -1;
      x12 = XVECEXP (x6, 0, 3);
      if (GET_CODE (x12) != REG
          || REGNO (x12) != 66
          || GET_MODE (x12) != E_SImode)
        return -1;
      x13 = XVECEXP (x6, 0, 4);
      if (GET_CODE (x13) != REG
          || REGNO (x13) != 67
          || GET_MODE (x13) != E_SImode)
        return -1;
      x5 = XEXP (x3, 1);
      if (x5 != const_int_rtx[MAX_SAVED_CONST_INT + -1])
        return -1;
      x14 = XEXP (x11, 0);
      operands[1] = x14;
      x15 = XEXP (x11, 1);
      operands[2] = x15;
      x16 = XVECEXP (x6, 0, 1);
      operands[3] = x16;
      if (!vector_length_operand (operands[3], E_VOIDmode))
        return -1;
      x17 = XVECEXP (x6, 0, 2);
      operands[4] = x17;
      if (!const_int_operand (operands[4], E_VOIDmode))
        return -1;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          switch (pattern215 (x3, E_SImode))
            {
            case 0:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 4521; /* pred_ffsvnx1bisi */

            case 1:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 4522; /* pred_ffsvnx2bisi */

            case 2:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 4523; /* pred_ffsvnx4bisi */

            case 3:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 4524; /* pred_ffsvnx8bisi */

            case 4:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 4525; /* pred_ffsvnx16bisi */

            case 5:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 4526; /* pred_ffsvnx32bisi */

            case 6:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && ((((
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))))
                return -1;
              return 4527; /* pred_ffsvnx64bisi */

            default:
              return -1;
            }

        case E_DImode:
          switch (pattern215 (x3, E_DImode))
            {
            case 0:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 4528; /* pred_ffsvnx1bidi */

            case 1:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 4529; /* pred_ffsvnx2bidi */

            case 2:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 4530; /* pred_ffsvnx4bidi */

            case 3:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 4531; /* pred_ffsvnx8bidi */

            case 4:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 4532; /* pred_ffsvnx16bidi */

            case 5:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 4533; /* pred_ffsvnx32bidi */

            case 6:
              if (!(
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && ((((
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))))
                return -1;
              return 4534; /* pred_ffsvnx64bidi */

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_137 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      operands[1] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_DImode:
          if (!register_operand (operands[0], E_DImode)
              || GET_MODE (x3) != E_DImode
              || !register_operand (operands[1], E_DImode)
              || !
#line 722 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
            return -1;
          return 15; /* negdi2 */

        case E_SImode:
          if (!register_operand (operands[0], E_SImode)
              || GET_MODE (x3) != E_SImode
              || !register_operand (operands[1], E_SImode))
            return -1;
          return 16; /* negsi2 */

        case E_SFmode:
          if (!register_operand (operands[0], E_SFmode)
              || GET_MODE (x3) != E_SFmode
              || !register_operand (operands[1], E_SFmode)
              || !
#line 1223 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
            return -1;
          return 80; /* negsf2 */

        case E_DFmode:
          if (!register_operand (operands[0], E_DFmode)
              || GET_MODE (x3) != E_DFmode
              || !register_operand (operands[1], E_DFmode)
              || !(
#line 1223 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 81; /* negdf2 */

        case E_HFmode:
          if (!register_operand (operands[0], E_HFmode)
              || GET_MODE (x3) != E_HFmode
              || !register_operand (operands[1], E_HFmode)
              || !(
#line 1223 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 82; /* neghf2 */

        default:
          return -1;
        }

    case FMA:
      x5 = XEXP (x4, 1);
      operands[2] = x5;
      x6 = XEXP (x4, 0);
      switch (GET_CODE (x6))
        {
        case NEG:
          x7 = XEXP (x6, 0);
          operands[1] = x7;
          x8 = XEXP (x4, 2);
          switch (GET_CODE (x8))
            {
            case NEG:
              x9 = XEXP (x8, 0);
              operands[3] = x9;
              switch (GET_MODE (operands[0]))
                {
                case E_SFmode:
                  if (pattern107 (x3, E_SFmode) != 0
                      || !(
#line 1151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (SFmode)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
                    return -1;
                  return 62; /* *fmasf4 */

                case E_DFmode:
                  if (pattern107 (x3, E_DFmode) != 0
                      || !(
#line 1151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (DFmode)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
                    return -1;
                  return 63; /* *fmadf4 */

                case E_HFmode:
                  if (pattern107 (x3, E_HFmode) != 0
                      || !(
#line 1151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (HFmode)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
                    return -1;
                  return 64; /* *fmahf4 */

                default:
                  return -1;
                }

            case REG:
            case SUBREG:
              operands[3] = x8;
              switch (GET_MODE (operands[0]))
                {
                case E_SFmode:
                  if (pattern108 (x3, E_SFmode) != 0
                      || !(
#line 1164 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (SFmode)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
                    return -1;
                  return 65; /* *fmssf4 */

                case E_DFmode:
                  if (pattern108 (x3, E_DFmode) != 0
                      || !(
#line 1164 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (DFmode)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
                    return -1;
                  return 66; /* *fmsdf4 */

                case E_HFmode:
                  if (pattern108 (x3, E_HFmode) != 0
                      || !(
#line 1164 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (HFmode)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
                    return -1;
                  return 67; /* *fmshf4 */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        case REG:
        case SUBREG:
          operands[1] = x6;
          x8 = XEXP (x4, 2);
          switch (GET_CODE (x8))
            {
            case REG:
            case SUBREG:
              operands[3] = x8;
              switch (GET_MODE (operands[0]))
                {
                case E_SFmode:
                  if (pattern109 (x3, E_SFmode) != 0
                      || !(
#line 1177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (SFmode)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
                    return -1;
                  return 68; /* *fnmssf4 */

                case E_DFmode:
                  if (pattern109 (x3, E_DFmode) != 0
                      || !(
#line 1177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (DFmode)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
                    return -1;
                  return 69; /* *fnmsdf4 */

                case E_HFmode:
                  if (pattern109 (x3, E_HFmode) != 0
                      || !(
#line 1177 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (HFmode)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
                    return -1;
                  return 70; /* *fnmshf4 */

                default:
                  return -1;
                }

            case NEG:
              x9 = XEXP (x8, 0);
              operands[3] = x9;
              switch (GET_MODE (operands[0]))
                {
                case E_SFmode:
                  if (pattern110 (x3, E_SFmode) != 0
                      || !(
#line 1190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (SFmode)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
                    return -1;
                  return 71; /* *fnmasf4 */

                case E_DFmode:
                  if (pattern110 (x3, E_DFmode) != 0
                      || !(
#line 1190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (DFmode)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
                    return -1;
                  return 72; /* *fnmadf4 */

                case E_HFmode:
                  if (pattern110 (x3, E_HFmode) != 0
                      || !(
#line 1190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (HFmode)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
                    return -1;
                  return 73; /* *fnmahf4 */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_138 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  switch (XVECLEN (x3, 0))
    {
    case 1:
      if (XINT (x3, 1) != 2)
        return -1;
      x4 = XVECEXP (x3, 0, 0);
      if (x4 != const_int_rtx[MAX_SAVED_CONST_INT + 0]
          || !register_operand (operands[0], E_SImode)
          || !
#line 2944 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
        return -1;
      return 306; /* riscv_frflags */

    case 2:
      x5 = XVECEXP (x3, 0, 1);
      operands[2] = x5;
      if (!const_int_operand (operands[2], E_SImode))
        return -1;
      switch (XINT (x3, 1))
        {
        case 63:
          x4 = XVECEXP (x3, 0, 0);
          operands[1] = x4;
          switch (GET_MODE (operands[0]))
            {
            case E_SImode:
              if (!register_operand (operands[0], E_SImode)
                  || GET_MODE (x3) != E_SImode
                  || !memory_operand (operands[1], E_SImode)
                  || !
#line 78 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                return -1;
              return 478; /* atomic_loadsi */

            case E_DImode:
              if (!register_operand (operands[0], E_DImode)
                  || GET_MODE (x3) != E_DImode
                  || !memory_operand (operands[1], E_DImode)
                  || !(
#line 78 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 479; /* atomic_loaddi */

            default:
              return -1;
            }

        case 64:
          x4 = XVECEXP (x3, 0, 0);
          operands[1] = x4;
          switch (GET_MODE (operands[0]))
            {
            case E_SImode:
              if (!memory_operand (operands[0], E_SImode)
                  || GET_MODE (x3) != E_SImode
                  || !reg_or_0_operand (operands[1], E_SImode)
                  || !
#line 104 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                return -1;
              return 480; /* atomic_storesi */

            case E_DImode:
              if (!memory_operand (operands[0], E_DImode)
                  || GET_MODE (x3) != E_DImode
                  || !reg_or_0_operand (operands[1], E_DImode)
                  || !(
#line 104 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 481; /* atomic_storedi */

            default:
              return -1;
            }

        case 59:
          x4 = XVECEXP (x3, 0, 0);
          switch (GET_CODE (x4))
            {
            case PLUS:
              switch (pattern92 (x3))
                {
                case 0:
                  if (!
#line 129 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                    return -1;
                  return 482; /* atomic_addsi */

                case 1:
                  if (!(
#line 129 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 486; /* atomic_adddi */

                default:
                  return -1;
                }

            case IOR:
              switch (pattern92 (x3))
                {
                case 0:
                  if (!
#line 129 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                    return -1;
                  return 483; /* atomic_orsi */

                case 1:
                  if (!(
#line 129 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 487; /* atomic_ordi */

                default:
                  return -1;
                }

            case XOR:
              switch (pattern92 (x3))
                {
                case 0:
                  if (!
#line 129 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                    return -1;
                  return 484; /* atomic_xorsi */

                case 1:
                  if (!(
#line 129 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 488; /* atomic_xordi */

                default:
                  return -1;
                }

            case AND:
              switch (pattern92 (x3))
                {
                case 0:
                  if (!
#line 129 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                    return -1;
                  return 485; /* atomic_andsi */

                case 1:
                  if (!(
#line 129 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 489; /* atomic_anddi */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_139 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      switch (pattern13 (x3))
        {
        case 0:
          if (arith_operand (operands[2], E_SImode))
            {
              if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
                return 96; /* iorsi3 */
              if (
#line 1297 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
                return 102; /* *iorsi3_internal */
            }
          if (single_bit_mask_operand (operands[2], E_SImode)
              && (
#line 475 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return 393; /* *bsetisi */
          if (!uimm_extra_bit_or_twobits (operands[2], E_SImode)
              || !(
#line 628 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 413; /* *iorisi_extrabit */

        case 1:
          if (arith_operand (operands[2], E_DImode)
              && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return 99; /* iordi3 */
          if (single_bit_mask_operand (operands[2], E_DImode)
              && (
#line 475 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return 394; /* *bsetidi */
          if (!uimm_extra_bit_or_twobits (operands[2], E_DImode)
              || !(
#line 628 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 415; /* *ioridi_extrabit */

        default:
          return -1;
        }

    case NOT:
      switch (pattern45 (x3))
        {
        case 0:
          if (!(
#line 214 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 339; /* *ior_notsi */

        case 1:
          if (!(
#line 214 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 341; /* *ior_notdi */

        default:
          return -1;
        }

    case ASHIFT:
      x5 = XEXP (x4, 0);
      if (x5 != const_int_rtx[MAX_SAVED_CONST_INT + 1])
        return -1;
      x6 = XEXP (x4, 1);
      operands[2] = x6;
      switch (pattern47 (x3))
        {
        case 0:
          if ((
#line 438 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return 385; /* *bsetsi */
          break;

        case 1:
          if ((
#line 438 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return 386; /* *bsetdi */
          break;

        default:
          break;
        }
      if (GET_CODE (x6) != SUBREG
          || maybe_ne (SUBREG_BYTE (x6), 0)
          || GET_MODE (x6) != E_QImode)
        return -1;
      x7 = XEXP (x6, 0);
      if (GET_CODE (x7) != AND)
        return -1;
      x8 = XEXP (x7, 0);
      operands[2] = x8;
      x9 = XEXP (x7, 1);
      operands[3] = x9;
      x10 = XEXP (x3, 1);
      operands[1] = x10;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (pattern128 (x3, E_SImode) != 0
              || !const31_operand (operands[3], E_VOIDmode)
              || !register_operand (operands[1], E_SImode)
              || !(
#line 449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 387; /* *bsetsi_mask */

        case E_DImode:
          if (pattern128 (x3, E_DImode) != 0
              || !const63_operand (operands[3], E_VOIDmode)
              || !register_operand (operands[1], E_DImode)
              || !(
#line 449 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 388; /* *bsetdi_mask */

        default:
          return -1;
        }

    case SIGN_EXTEND:
      if (pattern19 (x3, E_DImode) != 0)
        return -1;
      x10 = XEXP (x3, 1);
      operands[2] = x10;
      if (!single_bit_mask_operand (operands[2], E_VOIDmode)
          || !
#line 486 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_64BIT
   && !partial_subreg_p (operands[1])))
        return -1;
      return 395; /* *bsetidisi */

    default:
      return -1;
    }
}

static int
recog_140 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  operands[1] = x4;
  switch (GET_CODE (x3))
    {
    case LT:
      if (GET_MODE (x3) == E_DImode)
        {
          x5 = XEXP (x3, 1);
          if (x5 == const_int_rtx[MAX_SAVED_CONST_INT + 0]
              && register_operand (operands[0], E_DImode)
              && register_operand (operands[1], E_SImode)
              && 
#line 2180 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
            return 224; /* *lshrsi3_zero_extend_3 */
        }
      x5 = XEXP (x3, 1);
      operands[2] = x5;
      switch (pattern74 (x3))
        {
        case 0:
          if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
            return 274; /* *slt_sisi */
          break;

        case 1:
          if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return 276; /* *slt_disi */
          break;

        case 2:
          if (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return 278; /* *slt_didi */
          break;

        default:
          break;
        }
      break;

    case EQ:
      x5 = XEXP (x3, 1);
      if (x5 == const_int_rtx[MAX_SAVED_CONST_INT + 0])
        {
          switch (pattern8 (x3))
            {
            case 0:
              if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
                return 256; /* *seq_zero_sisi */
              break;

            case 1:
              if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
                return 257; /* *seq_zero_disi */
              break;

            case 2:
              if (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
                return 258; /* *seq_zero_didi */
              break;

            default:
              break;
            }
        }
      break;

    case GT:
      switch (pattern49 (x3))
        {
        case 0:
          if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
            return 262; /* *sgt_sisi */
          break;

        case 1:
          if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return 264; /* *sgt_disi */
          break;

        case 2:
          if (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return 266; /* *sgt_didi */
          break;

        default:
          break;
        }
      break;

    case GE:
      x5 = XEXP (x3, 1);
      if (x5 == const_int_rtx[MAX_SAVED_CONST_INT + 1])
        {
          switch (pattern8 (x3))
            {
            case 0:
              if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
                return 268; /* *sge_sisi */
              break;

            case 1:
              if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
                return 270; /* *sge_disi */
              break;

            case 2:
              if (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
                return 272; /* *sge_didi */
              break;

            default:
              break;
            }
        }
      break;

    case LE:
      switch (pattern50 (x3))
        {
        case 0:
          if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
            return 280; /* *sle_sisi */
          break;

        case 1:
          if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return 282; /* *sle_disi */
          break;

        case 2:
          if (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return 284; /* *sle_didi */
          break;

        default:
          break;
        }
      break;

    default:
      break;
    }
  operands[1] = x3;
  operands[2] = x4;
  x5 = XEXP (x3, 1);
  operands[3] = x5;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      switch (pattern87 (E_SImode))
        {
        case 0:
          if (!(
#line 2514 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))))
            return -1;
          return 250; /* *cstoresfsi4 */

        case 1:
          if (!(
#line 2514 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))))
            return -1;
          return 252; /* *cstoredfsi4 */

        case 2:
          if (!(
#line 2514 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))))
            return -1;
          return 254; /* *cstorehfsi4 */

        default:
          return -1;
        }

    case E_DImode:
      switch (pattern87 (E_DImode))
        {
        case 0:
          if (!(
#line 2514 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))))
            return -1;
          return 251; /* *cstoresfdi4 */

        case 1:
          if (!(
#line 2514 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))))
            return -1;
          return 253; /* *cstoredfdi4 */

        case 2:
          if (!(
#line 2514 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))))
            return -1;
          return 255; /* *cstorehfdi4 */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_141 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case LSHIFTRT:
      x5 = XEXP (x4, 0);
      if (GET_CODE (x5) != MULT)
        return -1;
      x6 = XEXP (x4, 1);
      if (GET_CODE (x6) != CONST_INT)
        return -1;
      x7 = XEXP (x5, 0);
      switch (GET_CODE (x7))
        {
        case SIGN_EXTEND:
          x8 = XEXP (x5, 1);
          if (GET_CODE (x8) != SIGN_EXTEND)
            return -1;
          x9 = XEXP (x7, 0);
          operands[1] = x9;
          switch (pattern97 (x3))
            {
            case 0:
              if (!
#line 936 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT))
                return -1;
              return 26; /* smuldi3_highpart */

            case 1:
              if (!
#line 997 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT))
                return -1;
              return 29; /* smulsi3_highpart */

            default:
              return -1;
            }

        case ZERO_EXTEND:
          x9 = XEXP (x7, 0);
          operands[1] = x9;
          x8 = XEXP (x5, 1);
          switch (GET_CODE (x8))
            {
            case ZERO_EXTEND:
              switch (pattern97 (x3))
                {
                case 0:
                  if (!
#line 936 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT))
                    return -1;
                  return 27; /* umuldi3_highpart */

                case 1:
                  if (!
#line 997 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT))
                    return -1;
                  return 30; /* umulsi3_highpart */

                default:
                  return -1;
                }

            case SIGN_EXTEND:
              switch (pattern97 (x3))
                {
                case 0:
                  if (!
#line 967 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT))
                    return -1;
                  return 28; /* usmuldi3_highpart */

                case 1:
                  if (!
#line 1028 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT))
                    return -1;
                  return 31; /* usmulsi3_highpart */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        default:
          return -1;
        }

    case UNSPEC:
      if (XVECLEN (x4, 0) != 2
          || XINT (x4, 1) != 68
          || GET_MODE (x4) != E_DImode)
        return -1;
      x10 = XVECEXP (x4, 0, 0);
      if (GET_CODE (x10) != VEC_SELECT
          || GET_MODE (x10) != E_DImode)
        return -1;
      x11 = XEXP (x10, 1);
      if (GET_CODE (x11) != PARALLEL
          || XVECLEN (x11, 0) != 1)
        return -1;
      x12 = XVECEXP (x11, 0, 0);
      if (x12 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
        return -1;
      x13 = XVECEXP (x4, 0, 1);
      if (GET_CODE (x13) != REG
          || REGNO (x13) != 67
          || GET_MODE (x13) != E_SImode
          || !register_operand (operands[0], E_SImode)
          || GET_MODE (x3) != E_SImode)
        return -1;
      x14 = XEXP (x10, 0);
      operands[1] = x14;
      switch (GET_MODE (operands[1]))
        {
        case E_VNx1DImode:
          if (!register_operand (operands[1], E_VNx1DImode)
              || !(
#line 7006 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5767; /* pred_extract_first_truncvnx1di */

        case E_VNx2DImode:
          if (!register_operand (operands[1], E_VNx2DImode)
              || !(
#line 7006 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5768; /* pred_extract_first_truncvnx2di */

        case E_VNx4DImode:
          if (!register_operand (operands[1], E_VNx4DImode)
              || !(
#line 7006 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5769; /* pred_extract_first_truncvnx4di */

        case E_VNx8DImode:
          if (!register_operand (operands[1], E_VNx8DImode)
              || !(
#line 7006 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 5770; /* pred_extract_first_truncvnx8di */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_142 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 1);
  if (GET_CODE (x3) != CONST_INT)
    return -1;
  operands[2] = x3;
  if (const_int_operand (operands[2], E_VOIDmode))
    {
      x4 = XEXP (x1, 0);
      operands[0] = x4;
      if (register_operand (operands[0], E_DImode)
          && GET_MODE (x2) == E_DImode)
        {
          x5 = XEXP (x2, 0);
          operands[1] = x5;
          if (register_operand (operands[1], E_DImode))
            {
              x6 = XEXP (x2, 2);
              operands[3] = x6;
              if (const_int_operand (operands[3], E_VOIDmode)
                  && 
#line 2166 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_64BIT && (INTVAL (operands[3]) > 0)
    && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))))
                return 223; /* *lshrsi3_zero_extend_2 */
            }
        }
    }
  x4 = XEXP (x1, 0);
  operands[0] = x4;
  x5 = XEXP (x2, 0);
  operands[1] = x5;
  if (XWINT (x3, 0) == 1L)
    {
      x6 = XEXP (x2, 2);
      switch (GET_CODE (x6))
        {
        case ZERO_EXTEND:
          x7 = XEXP (x6, 0);
          operands[2] = x7;
          if (register_operand (operands[2], E_QImode))
            {
              switch (GET_MODE (operands[0]))
                {
                case E_SImode:
                  if (pattern111 (x2, E_SImode) == 0
                      && (
#line 569 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                    return 407; /* *bextsi */
                  break;

                case E_DImode:
                  if (pattern111 (x2, E_DImode) == 0
                      && (
#line 569 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return 408; /* *bextdi */
                  break;

                default:
                  break;
                }
            }
          break;

        case REG:
        case SUBREG:
          operands[2] = x6;
          switch (GET_MODE (operands[0]))
            {
            case E_SImode:
              if (pattern105 (x2, E_SImode) == 0
                  && (
#line 581 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return 409; /* *bextsi */
              break;

            case E_DImode:
              if (pattern105 (x2, E_DImode) == 0
                  && (
#line 581 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return 410; /* *bextdi */
              break;

            default:
              break;
            }
          break;

        case CONST_INT:
        case CONST_WIDE_INT:
        case CONST_POLY_INT:
        case CONST_FIXED:
        case CONST_DOUBLE:
        case CONST_VECTOR:
        case CONST:
        case LABEL_REF:
        case SYMBOL_REF:
        case HIGH:
          operands[2] = x6;
          if (immediate_operand (operands[2], E_VOIDmode))
            {
              switch (pattern12 (x2))
                {
                case 0:
                  if ((
#line 590 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (SImode)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                    return 411; /* *bexti */
                  break;

                case 1:
                  if ((
#line 590 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (DImode)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return 412; /* *bexti */
                  break;

                default:
                  break;
                }
            }
          break;

        default:
          break;
        }
    }
  operands[2] = x3;
  switch (pattern75 (x2))
    {
    case 0:
      if (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB))
        return 578; /* *th_extusi4 */
      break;

    case 1:
      if ((
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
        return 579; /* *th_extudi4 */
      break;

    default:
      break;
    }
  if (XWINT (x3, 0) != 1L)
    return -1;
  x6 = XEXP (x2, 2);
  operands[2] = x6;
  if (!const_int_operand (operands[2], E_VOIDmode))
    return -1;
  switch (pattern12 (x2))
    {
    case 0:
      if (!(
#line 101 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (SImode)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
        return -1;
      return 584; /* *th_tstsi3 */

    case 1:
      if (!(
#line 101 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (DImode)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
        return -1;
      return 585; /* *th_tstdi3 */

    default:
      return -1;
    }
}

static int
recog_143 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      switch (pattern13 (x3))
        {
        case 0:
          if (arith_operand (operands[2], E_SImode))
            {
              if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
                return 95; /* andsi3 */
              if (
#line 1297 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
                return 101; /* *andsi3_internal */
            }
          if (not_single_bit_mask_operand (operands[2], E_SImode)
              && (
#line 504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return 398; /* *bclrisi */
          if (const_nottwobits_operand (operands[2], E_SImode)
              && (
#line 513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return 400; /* *bclrisi_nottwobits */
          if (!not_uimm_extra_bit_or_nottwobits (operands[2], E_SImode)
              || !(
#line 646 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 417; /* *andisi_extrabit */

        case 1:
          if (arith_operand (operands[2], E_DImode)
              && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return 98; /* anddi3 */
          if (not_single_bit_mask_operand (operands[2], E_DImode)
              && (
#line 504 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return 399; /* *bclridi */
          if (const_nottwobits_operand (operands[2], E_DImode))
            {
              if ((
#line 513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return 401; /* *bclridi_nottwobits */
              if (
#line 532 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBS
   && clz_hwi (~UINTVAL (operands[2])) > 33))
                return 402; /* *bclridisi_nottwobits */
            }
          if (!not_uimm_extra_bit_or_nottwobits (operands[2], E_DImode)
              || !(
#line 646 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 418; /* *andidi_extrabit */

        default:
          return -1;
        }

    case ASHIFT:
      if (pattern43 (x3, E_DImode) != 0
          || !immediate_operand (operands[2], E_QImode))
        return -1;
      x5 = XEXP (x3, 1);
      operands[3] = x5;
      if (!immediate_operand (operands[3], E_VOIDmode))
        return -1;
      if (pnum_clobbers != NULL
          && 
#line 2236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)))
        {
          *pnum_clobbers = 1;
          return 225; /* zero_extendsidi2_shifted */
        }
      if (!
#line 182 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff))
        return -1;
      return 337; /* *slliuw */

    case NOT:
      switch (pattern45 (x3))
        {
        case 0:
          if (!(
#line 214 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 338; /* *and_notsi */

        case 1:
          if (!(
#line 214 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 340; /* *and_notdi */

        default:
          return -1;
        }

    case ROTATE:
      switch (pattern48 (x3, -2))
        {
        case 0:
          if (!(
#line 496 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 396; /* *bclrsi */

        case 1:
          if (!(
#line 496 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 397; /* *bclrdi */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_144 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 1);
  operands[2] = x4;
  x5 = XEXP (x3, 0);
  switch (GET_CODE (x5))
    {
    case REG:
    case SUBREG:
      operands[1] = x5;
      x6 = XEXP (x3, 2);
      switch (GET_CODE (x6))
        {
        case REG:
        case SUBREG:
          operands[3] = x6;
          switch (GET_MODE (operands[0]))
            {
            case E_SFmode:
              if (pattern98 (x3, E_SFmode) != 0
                  || !
#line 1103 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
                return -1;
              return 50; /* fmasf4 */

            case E_DFmode:
              if (pattern98 (x3, E_DFmode) != 0
                  || !(
#line 1103 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
                return -1;
              return 51; /* fmadf4 */

            case E_HFmode:
              if (pattern98 (x3, E_HFmode) != 0
                  || !(
#line 1103 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
                return -1;
              return 52; /* fmahf4 */

            default:
              return -1;
            }

        case NEG:
          x7 = XEXP (x6, 0);
          operands[3] = x7;
          switch (GET_MODE (operands[0]))
            {
            case E_SFmode:
              if (pattern99 (x3, E_SFmode) != 0
                  || !(
#line 1114 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
                return -1;
              return 53; /* fmssf4 */

            case E_DFmode:
              if (pattern99 (x3, E_DFmode) != 0
                  || !(
#line 1114 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
                return -1;
              return 54; /* fmsdf4 */

            case E_HFmode:
              if (pattern99 (x3, E_HFmode) != 0
                  || !(
#line 1114 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
                return -1;
              return 55; /* fmshf4 */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case NEG:
      x8 = XEXP (x5, 0);
      operands[1] = x8;
      x6 = XEXP (x3, 2);
      switch (GET_CODE (x6))
        {
        case NEG:
          x7 = XEXP (x6, 0);
          operands[3] = x7;
          switch (GET_MODE (operands[0]))
            {
            case E_SFmode:
              if (pattern100 (x3, E_SFmode) != 0
                  || !(
#line 1126 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
                return -1;
              return 56; /* fnmssf4 */

            case E_DFmode:
              if (pattern100 (x3, E_DFmode) != 0
                  || !(
#line 1126 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
                return -1;
              return 57; /* fnmsdf4 */

            case E_HFmode:
              if (pattern100 (x3, E_HFmode) != 0
                  || !(
#line 1126 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
                return -1;
              return 58; /* fnmshf4 */

            default:
              return -1;
            }

        case REG:
        case SUBREG:
          operands[3] = x6;
          switch (GET_MODE (operands[0]))
            {
            case E_SFmode:
              if (pattern101 (x3, E_SFmode) != 0
                  || !
#line 1138 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
                return -1;
              return 59; /* fnmasf4 */

            case E_DFmode:
              if (pattern101 (x3, E_DFmode) != 0
                  || !(
#line 1138 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
                return -1;
              return 60; /* fnmadf4 */

            case E_HFmode:
              if (pattern101 (x3, E_HFmode) != 0
                  || !(
#line 1138 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
                return -1;
              return 61; /* fnmahf4 */

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_145 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
    case MEM:
      operands[1] = x4;
      res = recog_16 (x1, insn, pnum_clobbers);
      if (res >= 0)
        return res;
      switch (GET_CODE (x4))
        {
        case MEM:
          x5 = XEXP (x4, 0);
          operands[1] = x5;
          if (!absolute_symbolic_operand (operands[1], E_VOIDmode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_HImode:
              if (!register_operand (operands[0], E_HImode)
                  || GET_MODE (x3) != E_HImode)
                return -1;
              switch (GET_MODE (x4))
                {
                case E_QImode:
                  if (!
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])))
                    return -1;
                  return 522; /* *local_pic_load_uqi */

                case E_HImode:
                  if (!
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])))
                    return -1;
                  return 525; /* *local_pic_load_uhi */

                case E_SImode:
                  if (!(
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 60 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 528; /* *local_pic_load_usi */

                default:
                  return -1;
                }

            case E_SImode:
              if (!register_operand (operands[0], E_SImode)
                  || GET_MODE (x3) != E_SImode)
                return -1;
              switch (GET_MODE (x4))
                {
                case E_QImode:
                  if (!
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])))
                    return -1;
                  return 523; /* *local_pic_load_uqi */

                case E_HImode:
                  if (!
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])))
                    return -1;
                  return 526; /* *local_pic_load_uhi */

                case E_SImode:
                  if (!(
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 60 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 529; /* *local_pic_load_usi */

                default:
                  return -1;
                }

            case E_DImode:
              if (!register_operand (operands[0], E_DImode)
                  || GET_MODE (x3) != E_DImode)
                return -1;
              switch (GET_MODE (x4))
                {
                case E_QImode:
                  if (!(
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 524; /* *local_pic_load_uqi */

                case E_HImode:
                  if (!(
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 527; /* *local_pic_load_uhi */

                case E_SImode:
                  if (!(
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 530; /* *local_pic_load_usi */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        case REG:
          if (REGNO (x4) != 66
              || GET_MODE (x4) != E_SImode
              || !register_operand (operands[0], E_DImode)
              || GET_MODE (x3) != E_DImode
              || !
#line 7259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_64BIT))
            return -1;
          return 6036; /* read_vldi_zero_extend */

        default:
          return -1;
        }

    case LSHIFTRT:
      if (pattern43 (x3, E_SImode) != 0
          || !const_int_operand (operands[2], E_VOIDmode)
          || !
#line 2151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && (INTVAL (operands[2]) & 0x1f) > 0))
        return -1;
      return 222; /* *lshrsi3_zero_extend_1 */

    default:
      return -1;
    }
}

static int
recog_146 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 1);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      operands[2] = x4;
      x5 = XEXP (x3, 0);
      operands[1] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_SFmode:
          if (pattern0 (x3, E_SFmode) != 0
              || !
#line 596 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
            return -1;
          return 8; /* subsf3 */

        case E_DFmode:
          if (pattern0 (x3, E_DFmode) != 0
              || !(
#line 596 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 9; /* subdf3 */

        case E_HFmode:
          if (pattern0 (x3, E_HFmode) != 0
              || !(
#line 596 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 10; /* subhf3 */

        case E_DImode:
          if (pattern84 (x3, E_DImode) != 0
              || !
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
            return -1;
          return 11; /* subdi3 */

        case E_SImode:
          if (pattern84 (x3, E_SImode) != 0)
            return -1;
          return 12; /* subsi3 */

        default:
          return -1;
        }

    case MULT:
      x5 = XEXP (x3, 0);
      operands[3] = x5;
      x6 = XEXP (x4, 0);
      switch (GET_CODE (x6))
        {
        case REG:
        case SUBREG:
          operands[1] = x6;
          x7 = XEXP (x4, 1);
          operands[2] = x7;
          switch (GET_MODE (operands[0]))
            {
            case E_SImode:
              if (pattern95 (x3, E_SImode) != 0)
                return -1;
              if ((
#line 243 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return 603; /* *th_mulssi */
              if (!
#line 266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC && TARGET_64BIT))
                return -1;
              return 606; /* *th_mulswsi2 */

            case E_DImode:
              if (pattern95 (x3, E_DImode) != 0
                  || !(
#line 243 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 604; /* *th_mulsdi */

            default:
              return -1;
            }

        case SIGN_EXTEND:
          if (GET_MODE (x6) != E_SImode)
            return -1;
          x7 = XEXP (x4, 1);
          if (GET_CODE (x7) != SIGN_EXTEND
              || GET_MODE (x7) != E_SImode
              || !register_operand (operands[0], E_SImode)
              || GET_MODE (x3) != E_SImode
              || !register_operand (operands[3], E_SImode)
              || GET_MODE (x4) != E_SImode)
            return -1;
          x8 = XEXP (x6, 0);
          operands[1] = x8;
          if (!register_operand (operands[1], E_HImode))
            return -1;
          x9 = XEXP (x7, 0);
          operands[2] = x9;
          if (!register_operand (operands[2], E_HImode)
              || !
#line 277 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC))
            return -1;
          return 607; /* *th_msubhisi4 */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_147 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      operands[1] = x4;
      switch (pattern12 (x3))
        {
        case 0:
          if (!
#line 244 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB))
            return -1;
          return 346; /* *popcountsi2 */

        case 1:
          if (!
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB))
            return -1;
          return 352; /* *popcountdi2 */

        default:
          return -1;
        }

    case UNSPEC:
      if (XVECLEN (x4, 0) != 5
          || XINT (x4, 1) != 68)
        return -1;
      x5 = XVECEXP (x4, 0, 0);
      if (GET_CODE (x5) != AND
          || pattern81 (x4) != 0)
        return -1;
      x6 = XEXP (x5, 0);
      operands[1] = x6;
      x7 = XEXP (x5, 1);
      operands[2] = x7;
      x8 = XVECEXP (x4, 0, 1);
      operands[3] = x8;
      if (!vector_length_operand (operands[3], E_VOIDmode))
        return -1;
      x9 = XVECEXP (x4, 0, 2);
      operands[4] = x9;
      if (!const_int_operand (operands[4], E_VOIDmode))
        return -1;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          switch (pattern209 (x3, E_SImode))
            {
            case 0:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 4507; /* pred_popcountvnx1bisi */

            case 1:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 4508; /* pred_popcountvnx2bisi */

            case 2:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 4509; /* pred_popcountvnx4bisi */

            case 3:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 4510; /* pred_popcountvnx8bisi */

            case 4:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 4511; /* pred_popcountvnx16bisi */

            case 5:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 4512; /* pred_popcountvnx32bisi */

            case 6:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && ((((
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))))
                return -1;
              return 4513; /* pred_popcountvnx64bisi */

            default:
              return -1;
            }

        case E_DImode:
          switch (pattern209 (x3, E_DImode))
            {
            case 0:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 4514; /* pred_popcountvnx1bidi */

            case 1:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 4515; /* pred_popcountvnx2bidi */

            case 2:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 4516; /* pred_popcountvnx4bidi */

            case 3:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 4517; /* pred_popcountvnx8bidi */

            case 4:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 4518; /* pred_popcountvnx16bidi */

            case 5:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 4519; /* pred_popcountvnx32bidi */

            case 6:
              if (!(
#line 5284 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && ((((
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))))
                return -1;
              return 4520; /* pred_popcountvnx64bidi */

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_148 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      operands[1] = x4;
      x5 = XEXP (x3, 1);
      operands[2] = x5;
      if (arith_operand (operands[2], E_QImode))
        {
          switch (pattern12 (x3))
            {
            case 0:
              return 195; /* ashlsi3 */

            case 1:
              if (
#line 2034 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
                return 204; /* ashldi3 */
              break;

            default:
              break;
            }
        }
      if (!subreg_lowpart_operator (x5, E_VOIDmode))
        return -1;
      switch (pattern72 (x3))
        {
        case 0:
          if (!
#line 1998 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
   == GET_MODE_BITSIZE (SImode)-1))
            return -1;
          return 198; /* *ashlsi3_mask */

        case 1:
          if (!
#line 2017 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1))
            return -1;
          return 201; /* *ashlsi3_mask_1 */

        case 2:
          if (!
#line 2053 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1))
            return -1;
          return 207; /* *ashldi3_mask */

        case 3:
          if (!
#line 2073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1))
            return -1;
          return 210; /* *ashldi3_mask_1 */

        default:
          return -1;
        }

    case CONST_INT:
      if (XWINT (x4, 0) != 1L)
        return -1;
      x5 = XEXP (x3, 1);
      operands[1] = x5;
      if (register_operand (operands[1], E_QImode))
        {
          switch (pattern86 (x3))
            {
            case 0:
              if ((
#line 457 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return 389; /* *bsetsi_1 */
              break;

            case 1:
              if ((
#line 457 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return 390; /* *bsetdi_1 */
              break;

            default:
              break;
            }
        }
      if (GET_CODE (x5) != SUBREG
          || maybe_ne (SUBREG_BYTE (x5), 0)
          || GET_MODE (x5) != E_QImode)
        return -1;
      x6 = XEXP (x5, 0);
      if (GET_CODE (x6) != AND)
        return -1;
      x7 = XEXP (x6, 0);
      operands[1] = x7;
      x8 = XEXP (x6, 1);
      operands[2] = x8;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (pattern120 (x3, E_SImode) != 0
              || !const31_operand (operands[2], E_VOIDmode)
              || !(
#line 467 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 391; /* *bsetsi_1_mask */

        case E_DImode:
          if (pattern120 (x3, E_DImode) != 0
              || !const63_operand (operands[2], E_VOIDmode)
              || !(
#line 467 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 392; /* *bsetdi_1_mask */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_149 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = XEXP (x1, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      operands[1] = x4;
      x5 = XEXP (x3, 1);
      operands[2] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (!register_operand (operands[0], E_SImode)
              || GET_MODE (x3) != E_SImode
              || !register_operand (operands[1], E_SImode))
            return -1;
          if (arith_operand (operands[2], E_SImode))
            {
              if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
                return 97; /* xorsi3 */
              if (
#line 1297 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
                return 103; /* *xorsi3_internal */
            }
          if (single_bit_mask_operand (operands[2], E_SImode)
              && (
#line 559 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return 405; /* *binvisi */
          if (!uimm_extra_bit_or_twobits (operands[2], E_SImode)
              || !(
#line 628 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 414; /* *xorisi_extrabit */

        case E_DImode:
          if (!register_operand (operands[0], E_DImode)
              || GET_MODE (x3) != E_DImode
              || !register_operand (operands[1], E_DImode))
            return -1;
          if (arith_operand (operands[2], E_DImode)
              && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return 100; /* xordi3 */
          if (single_bit_mask_operand (operands[2], E_DImode)
              && (
#line 559 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return 406; /* *binvidi */
          if (!uimm_extra_bit_or_twobits (operands[2], E_DImode)
              || !(
#line 628 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 416; /* *xoridi_extrabit */

        case E_HImode:
          switch (pattern83 (x3))
            {
            case 0:
              return 184; /* *xorhihi3 */

            case 1:
              return 185; /* *xorsihi3 */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case ASHIFT:
      switch (pattern48 (x3, 1))
        {
        case 0:
          if (!(
#line 551 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 403; /* *binvsi */

        case 1:
          if (!(
#line 551 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 404; /* *binvdi */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_150 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  int res ATTRIBUTE_UNUSED;
  switch (pattern7 (x1))
    {
    case 0:
      if (reg_or_0_operand (operands[1], E_SImode)
          && 
#line 1568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
        return 146; /* floatunssisf2 */
      if (!reg_or_0_operand (operands[1], E_DImode)
          || !(
#line 1568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))))
        return -1;
      return 147; /* floatunsdisf2 */

    case 1:
      if (reg_or_0_operand (operands[1], E_SImode)
          && (
#line 1568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
        return 148; /* floatunssidf2 */
      if (!reg_or_0_operand (operands[1], E_DImode)
          || !(
#line 1568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))))
        return -1;
      return 149; /* floatunsdidf2 */

    case 2:
      if (reg_or_0_operand (operands[1], E_SImode)
          && (
#line 1568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
        return 150; /* floatunssihf2 */
      if (!reg_or_0_operand (operands[1], E_DImode)
          || !(
#line 1568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))))
        return -1;
      return 151; /* floatunsdihf2 */

    default:
      return -1;
    }
}

static int
recog_151 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 1);
  if (GET_CODE (x2) != USE)
    return -1;
  x3 = XEXP (x2, 0);
  if (GET_CODE (x3) != LABEL_REF)
    return -1;
  x4 = XVECEXP (x1, 0, 0);
  x5 = XEXP (x4, 1);
  operands[0] = x5;
  x6 = XEXP (x3, 0);
  operands[1] = x6;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (!register_operand (operands[0], E_SImode))
        return -1;
      return 289; /* tablejumpsi */

    case E_DImode:
      if (!register_operand (operands[0], E_DImode)
          || !
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
        return -1;
      return 290; /* tablejumpdi */

    default:
      return -1;
    }
}

static int
recog_152 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  x3 = XEXP (x2, 0);
  operands[0] = x3;
  x4 = XVECEXP (x1, 0, 1);
  if (GET_CODE (x4) != SET)
    return -1;
  x5 = XEXP (x4, 1);
  switch (GET_CODE (x5))
    {
    case UNSPEC_VOLATILE:
      x6 = XEXP (x4, 0);
      if (!rtx_equal_p (x6, operands[1]))
        return -1;
      switch (XVECLEN (x5, 0))
        {
        case 2:
          if (XINT (x5, 1) != 59)
            return -1;
          x7 = XVECEXP (x5, 0, 1);
          operands[3] = x7;
          if (!const_int_operand (operands[3], E_SImode))
            return -1;
          x8 = XVECEXP (x5, 0, 0);
          switch (GET_CODE (x8))
            {
            case PLUS:
              switch (pattern137 (x5))
                {
                case 0:
                  if (!
#line 143 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                    return -1;
                  return 490; /* atomic_fetch_addsi */

                case 1:
                  if (!(
#line 143 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 494; /* atomic_fetch_adddi */

                default:
                  return -1;
                }

            case IOR:
              switch (pattern137 (x5))
                {
                case 0:
                  if (!
#line 143 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                    return -1;
                  return 491; /* atomic_fetch_orsi */

                case 1:
                  if (!(
#line 143 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 495; /* atomic_fetch_ordi */

                default:
                  return -1;
                }

            case XOR:
              switch (pattern137 (x5))
                {
                case 0:
                  if (!
#line 143 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                    return -1;
                  return 492; /* atomic_fetch_xorsi */

                case 1:
                  if (!(
#line 143 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 496; /* atomic_fetch_xordi */

                default:
                  return -1;
                }

            case AND:
              switch (pattern137 (x5))
                {
                case 0:
                  if (!
#line 143 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                    return -1;
                  return 493; /* atomic_fetch_andsi */

                case 1:
                  if (!(
#line 143 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 497; /* atomic_fetch_anddi */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        case 4:
          if (pnum_clobbers == NULL
              || XINT (x5, 1) != 57)
            return -1;
          x8 = XVECEXP (x5, 0, 0);
          operands[2] = x8;
          x7 = XVECEXP (x5, 0, 1);
          operands[3] = x7;
          x9 = XVECEXP (x5, 0, 2);
          operands[4] = x9;
          if (!const_int_operand (operands[4], E_SImode))
            return -1;
          x10 = XVECEXP (x5, 0, 3);
          operands[5] = x10;
          if (!const_int_operand (operands[5], E_SImode))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_SImode:
              if (pattern213 (x5, E_SImode) != 0
                  || !
#line 358 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                return -1;
              *pnum_clobbers = 1;
              return 506; /* atomic_cas_value_strongsi */

            case E_DImode:
              if (pattern213 (x5, E_DImode) != 0
                  || !(
#line 358 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              *pnum_clobbers = 1;
              return 507; /* atomic_cas_value_strongdi */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case SUBREG:
    case MEM:
      operands[3] = x5;
      x6 = XEXP (x4, 0);
      operands[2] = x6;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (pattern129 (E_SImode) != 0
              || !
#line 304 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, true, SImode)))
            return -1;
          return 609; /* *th_mempair_load_si2 */

        case E_DImode:
          if (pattern129 (E_DImode) != 0
              || !(
#line 304 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, true, DImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 610; /* *th_mempair_load_di2 */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_153 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 1);
  if (GET_CODE (x2) != CLOBBER)
    return -1;
  x3 = XVECEXP (x1, 0, 0);
  x4 = XEXP (x3, 0);
  x5 = XEXP (x4, 0);
  operands[0] = x5;
  if (!absolute_symbolic_operand (operands[0], E_VOIDmode))
    return -1;
  x6 = XEXP (x2, 0);
  operands[2] = x6;
  switch (GET_MODE (x4))
    {
    case E_QImode:
      switch (pattern121 (E_QImode))
        {
        case 0:
          if (!(
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 546; /* *local_pic_storeqi */

        case 1:
          if (!(
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 550; /* *local_pic_storeqi */

        default:
          return -1;
        }

    case E_HImode:
      switch (pattern121 (E_HImode))
        {
        case 0:
          if (!(
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 547; /* *local_pic_storehi */

        case 1:
          if (!(
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 551; /* *local_pic_storehi */

        default:
          return -1;
        }

    case E_SImode:
      switch (pattern121 (E_SImode))
        {
        case 0:
          if (!(
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 548; /* *local_pic_storesi */

        case 1:
          if (!(
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 552; /* *local_pic_storesi */

        default:
          return -1;
        }

    case E_DImode:
      switch (pattern121 (E_DImode))
        {
        case 0:
          if (!(
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            return -1;
          return 549; /* *local_pic_storedi */

        case 1:
          if (!(
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return -1;
          return 553; /* *local_pic_storedi */

        default:
          return -1;
        }

    case E_SFmode:
      switch (pattern122 (E_SFmode))
        {
        case 0:
          if ((
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            return 554; /* *local_pic_storesf */
          if (!(
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 566; /* *local_pic_store_sfsf */

        case 1:
          if ((
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return 557; /* *local_pic_storesf */
          if (!(
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 569; /* *local_pic_store_sfsf */

        default:
          return -1;
        }

    case E_DFmode:
      switch (pattern122 (E_DFmode))
        {
        case 0:
          if ((
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            return 555; /* *local_pic_storedf */
          if (!(
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            return -1;
          return 567; /* *local_pic_store_sfdf */

        case 1:
          if ((
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return 558; /* *local_pic_storedf */
          if (!(
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return -1;
          return 570; /* *local_pic_store_sfdf */

        default:
          return -1;
        }

    case E_HFmode:
      switch (pattern122 (E_HFmode))
        {
        case 0:
          if ((
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            return 556; /* *local_pic_storehf */
          if (!(
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFHMIN) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            return -1;
          return 568; /* *local_pic_store_sfhf */

        case 1:
          if ((
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return 559; /* *local_pic_storehf */
          if (!(
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFHMIN) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return -1;
          return 571; /* *local_pic_store_sfhf */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_154 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 1);
  x3 = XEXP (x2, 0);
  operands[2] = x3;
  x4 = XEXP (x2, 1);
  operands[3] = x4;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (pattern117 (E_SImode) != 0
          || !
#line 316 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, false, SImode)))
        return -1;
      return 611; /* *th_mempair_store_si2 */

    case E_DImode:
      if (pattern117 (E_DImode) != 0
          || !(
#line 316 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, false, DImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
        return -1;
      return 612; /* *th_mempair_store_di2 */

    default:
      return -1;
    }
}

static int
recog_155 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  x3 = XEXP (x2, 1);
  operands[1] = x3;
  x4 = XEXP (x2, 0);
  switch (GET_CODE (x4))
    {
    case REG:
    case SUBREG:
      res = recog_152 (x1, insn, pnum_clobbers);
      if (res >= 0)
        return res;
      break;

    case MEM:
      res = recog_153 (x1, insn, pnum_clobbers);
      if (res >= 0)
        return res;
      break;

    default:
      break;
    }
  operands[0] = x4;
  x5 = XVECEXP (x1, 0, 1);
  if (GET_CODE (x5) == SET)
    {
      res = recog_154 (x1, insn, pnum_clobbers);
      if (res >= 0)
        return res;
    }
  if (GET_CODE (x5) != CLOBBER)
    return -1;
  x6 = XEXP (x5, 0);
  operands[2] = x6;
  switch (GET_MODE (operands[0]))
    {
    case E_VNx1QImode:
      switch (pattern93 (E_VNx1QImode))
        {
        case 0:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 765; /* *movvnx1qisi_lra */

        case 1:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 766; /* *movvnx1qidi_lra */

        default:
          return -1;
        }

    case E_VNx2QImode:
      switch (pattern93 (E_VNx2QImode))
        {
        case 0:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 767; /* *movvnx2qisi_lra */

        case 1:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 768; /* *movvnx2qidi_lra */

        default:
          return -1;
        }

    case E_VNx4QImode:
      switch (pattern93 (E_VNx4QImode))
        {
        case 0:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            return -1;
          return 769; /* *movvnx4qisi_lra */

        case 1:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return -1;
          return 770; /* *movvnx4qidi_lra */

        default:
          return -1;
        }

    case E_VNx1HImode:
      switch (pattern93 (E_VNx1HImode))
        {
        case 0:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 771; /* *movvnx1hisi_lra */

        case 1:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 772; /* *movvnx1hidi_lra */

        default:
          return -1;
        }

    case E_VNx2HImode:
      switch (pattern93 (E_VNx2HImode))
        {
        case 0:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 391 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            return -1;
          return 773; /* *movvnx2hisi_lra */

        case 1:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 391 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return -1;
          return 774; /* *movvnx2hidi_lra */

        default:
          return -1;
        }

    case E_VNx1SImode:
      switch (pattern93 (E_VNx1SImode))
        {
        case 0:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            return -1;
          return 775; /* *movvnx1sisi_lra */

        case 1:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return -1;
          return 776; /* *movvnx1sidi_lra */

        default:
          return -1;
        }

    case E_VNx1SFmode:
      switch (pattern93 (E_VNx1SFmode))
        {
        case 0:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            return -1;
          return 777; /* *movvnx1sfsi_lra */

        case 1:
          if (!(
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return -1;
          return 778; /* *movvnx1sfdi_lra */

        default:
          return -1;
        }

    case E_VNx1BImode:
      switch (pattern93 (E_VNx1BImode))
        {
        case 0:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 779; /* *movvnx1bisi_lra */

        case 1:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 786; /* *movvnx1bidi_lra */

        default:
          return -1;
        }

    case E_VNx2BImode:
      switch (pattern93 (E_VNx2BImode))
        {
        case 0:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 780; /* *movvnx2bisi_lra */

        case 1:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 787; /* *movvnx2bidi_lra */

        default:
          return -1;
        }

    case E_VNx4BImode:
      switch (pattern93 (E_VNx4BImode))
        {
        case 0:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 781; /* *movvnx4bisi_lra */

        case 1:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 788; /* *movvnx4bidi_lra */

        default:
          return -1;
        }

    case E_VNx8BImode:
      switch (pattern93 (E_VNx8BImode))
        {
        case 0:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 782; /* *movvnx8bisi_lra */

        case 1:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 789; /* *movvnx8bidi_lra */

        default:
          return -1;
        }

    case E_VNx16BImode:
      switch (pattern93 (E_VNx16BImode))
        {
        case 0:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 783; /* *movvnx16bisi_lra */

        case 1:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 790; /* *movvnx16bidi_lra */

        default:
          return -1;
        }

    case E_VNx32BImode:
      switch (pattern93 (E_VNx32BImode))
        {
        case 0:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
            return -1;
          return 784; /* *movvnx32bisi_lra */

        case 1:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
            return -1;
          return 791; /* *movvnx32bidi_lra */

        default:
          return -1;
        }

    case E_VNx64BImode:
      switch (pattern93 (E_VNx64BImode))
        {
        case 0:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
            return -1;
          return 785; /* *movvnx64bisi_lra */

        case 1:
          if (!(
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
            return -1;
          return 792; /* *movvnx64bidi_lra */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_156 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15, x16, x17;
  rtx x18, x19, x20, x21, x22;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  x3 = XEXP (x2, 1);
  x4 = XEXP (x3, 0);
  switch (GET_CODE (x4))
    {
    case NE:
    case EQ:
      if (pattern76 (x2) != 0)
        return -1;
      x5 = XVECEXP (x1, 0, 1);
      if (GET_CODE (x5) != CLOBBER)
        return -1;
      switch (pattern116 (x1))
        {
        case 0:
          if (shifted_const_arith_operand (operands[3], E_VOIDmode))
            {
              switch (GET_MODE (operands[4]))
                {
                case E_SImode:
                  if (scratch_operand (operands[4], E_SImode)
                      && (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                    return 226; /* *branchqi_shiftedarith_equals_zero */
                  break;

                case E_DImode:
                  if (scratch_operand (operands[4], E_DImode)
                      && (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return 229; /* *branchqi_shiftedarith_equals_zero */
                  break;

                default:
                  break;
                }
            }
          if (!consecutive_bits_operand (operands[3], E_VOIDmode))
            return -1;
          switch (GET_MODE (operands[4]))
            {
            case E_SImode:
              if (!scratch_operand (operands[4], E_SImode)
                  || !(
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 233; /* *branchqi_shiftedmask_equals_zero */

            case E_DImode:
              if (!scratch_operand (operands[4], E_DImode)
                  || !(
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 237; /* *branchqi_shiftedmask_equals_zero */

            default:
              return -1;
            }

        case 1:
          if (shifted_const_arith_operand (operands[3], E_VOIDmode))
            {
              switch (GET_MODE (operands[4]))
                {
                case E_SImode:
                  if (scratch_operand (operands[4], E_SImode)
                      && (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                    return 227; /* *branchhi_shiftedarith_equals_zero */
                  break;

                case E_DImode:
                  if (scratch_operand (operands[4], E_DImode)
                      && (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return 230; /* *branchhi_shiftedarith_equals_zero */
                  break;

                default:
                  break;
                }
            }
          if (!consecutive_bits_operand (operands[3], E_VOIDmode))
            return -1;
          switch (GET_MODE (operands[4]))
            {
            case E_SImode:
              if (!scratch_operand (operands[4], E_SImode)
                  || !(
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 234; /* *branchhi_shiftedmask_equals_zero */

            case E_DImode:
              if (!scratch_operand (operands[4], E_DImode)
                  || !(
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 238; /* *branchhi_shiftedmask_equals_zero */

            default:
              return -1;
            }

        case 2:
          if (shifted_const_arith_operand (operands[3], E_VOIDmode))
            {
              switch (GET_MODE (operands[4]))
                {
                case E_SImode:
                  if (scratch_operand (operands[4], E_SImode)
                      && (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                    return 228; /* *branchsi_shiftedarith_equals_zero */
                  break;

                case E_DImode:
                  if (scratch_operand (operands[4], E_DImode)
                      && (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return 231; /* *branchsi_shiftedarith_equals_zero */
                  break;

                default:
                  break;
                }
            }
          if (!consecutive_bits_operand (operands[3], E_VOIDmode))
            return -1;
          switch (GET_MODE (operands[4]))
            {
            case E_SImode:
              if (!scratch_operand (operands[4], E_SImode)
                  || !(
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 235; /* *branchsi_shiftedmask_equals_zero */

            case E_DImode:
              if (!scratch_operand (operands[4], E_DImode)
                  || !(
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 239; /* *branchsi_shiftedmask_equals_zero */

            default:
              return -1;
            }

        case 3:
          if (shifted_const_arith_operand (operands[3], E_VOIDmode)
              && scratch_operand (operands[4], E_DImode)
              && (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return 232; /* *branchdi_shiftedarith_equals_zero */
          if (!consecutive_bits_operand (operands[3], E_VOIDmode))
            return -1;
          switch (GET_MODE (operands[4]))
            {
            case E_SImode:
              if (!scratch_operand (operands[4], E_SImode)
                  || !(
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && ((((
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))))
                return -1;
              return 236; /* *branchdi_shiftedmask_equals_zero */

            case E_DImode:
              if (!scratch_operand (operands[4], E_DImode)
                  || !(
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 240; /* *branchdi_shiftedmask_equals_zero */

            default:
              return -1;
            }

        case 4:
          x6 = XEXP (x4, 0);
          x7 = XEXP (x6, 1);
          if (XWINT (x7, 0) == 1L)
            {
              switch (pattern139 (x6))
                {
                case 0:
                  if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
                    return 246; /* *branch_on_bitsi */
                  break;

                case 1:
                  if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
                    return 247; /* *branch_on_bitdi */
                  break;

                default:
                  break;
                }
            }
          x8 = XEXP (x6, 2);
          if (x8 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
            return -1;
          switch (pattern140 (x6))
            {
            case 0:
              if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
                return -1;
              return 248; /* *branch_on_bit_rangesi */

            case 1:
              if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
                return -1;
              return 249; /* *branch_on_bit_rangedi */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case UNSPEC:
      if (XVECLEN (x4, 0) != 7
          || XINT (x4, 1) != 68)
        return -1;
      x9 = XVECEXP (x4, 0, 5);
      if (GET_CODE (x9) != REG
          || REGNO (x9) != 66
          || GET_MODE (x9) != E_SImode)
        return -1;
      x10 = XVECEXP (x4, 0, 6);
      if (GET_CODE (x10) != REG
          || REGNO (x10) != 67
          || GET_MODE (x10) != E_SImode)
        return -1;
      x11 = XEXP (x3, 1);
      if (GET_CODE (x11) != UNSPEC
          || XVECLEN (x11, 0) != 1
          || XINT (x11, 1) != 115)
        return -1;
      x5 = XVECEXP (x1, 0, 1);
      if (pattern55 (x5, 115, 1, UNSPEC) != 0)
        return -1;
      x12 = XEXP (x5, 0);
      if (GET_CODE (x12) != REG
          || REGNO (x12) != 66
          || GET_MODE (x12) != E_SImode)
        return -1;
      x13 = XEXP (x2, 0);
      operands[0] = x13;
      x14 = XVECEXP (x4, 0, 0);
      operands[1] = x14;
      x15 = XVECEXP (x4, 0, 1);
      operands[4] = x15;
      if (!vector_length_operand (operands[4], E_VOIDmode))
        return -1;
      x16 = XVECEXP (x4, 0, 2);
      operands[5] = x16;
      if (!const_int_operand (operands[5], E_VOIDmode))
        return -1;
      x17 = XVECEXP (x4, 0, 3);
      operands[6] = x17;
      if (!const_int_operand (operands[6], E_VOIDmode))
        return -1;
      x18 = XVECEXP (x4, 0, 4);
      operands[7] = x18;
      if (!const_int_operand (operands[7], E_VOIDmode))
        return -1;
      x19 = XVECEXP (x11, 0, 0);
      operands[3] = x19;
      x20 = XEXP (x3, 2);
      operands[2] = x20;
      x21 = XEXP (x5, 1);
      x22 = XVECEXP (x21, 0, 0);
      if (!rtx_equal_p (x22, operands[0]))
        return -1;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1QImode:
          if (pattern321 (x3, E_VNx1QImode, E_VNx1BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6037; /* pred_fault_loadvnx1qi */

        case E_VNx2QImode:
          if (pattern321 (x3, E_VNx2QImode, E_VNx2BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6038; /* pred_fault_loadvnx2qi */

        case E_VNx4QImode:
          if (pattern321 (x3, E_VNx4QImode, E_VNx4BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6039; /* pred_fault_loadvnx4qi */

        case E_VNx8QImode:
          if (pattern321 (x3, E_VNx8QImode, E_VNx8BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6040; /* pred_fault_loadvnx8qi */

        case E_VNx16QImode:
          if (pattern321 (x3, E_VNx16QImode, E_VNx16BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6041; /* pred_fault_loadvnx16qi */

        case E_VNx32QImode:
          if (pattern321 (x3, E_VNx32QImode, E_VNx32BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6042; /* pred_fault_loadvnx32qi */

        case E_VNx64QImode:
          if (pattern321 (x3, E_VNx64QImode, E_VNx64BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 6043; /* pred_fault_loadvnx64qi */

        case E_VNx1HImode:
          if (pattern321 (x3, E_VNx1HImode, E_VNx1BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6044; /* pred_fault_loadvnx1hi */

        case E_VNx2HImode:
          if (pattern321 (x3, E_VNx2HImode, E_VNx2BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6045; /* pred_fault_loadvnx2hi */

        case E_VNx4HImode:
          if (pattern321 (x3, E_VNx4HImode, E_VNx4BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6046; /* pred_fault_loadvnx4hi */

        case E_VNx8HImode:
          if (pattern321 (x3, E_VNx8HImode, E_VNx8BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6047; /* pred_fault_loadvnx8hi */

        case E_VNx16HImode:
          if (pattern321 (x3, E_VNx16HImode, E_VNx16BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6048; /* pred_fault_loadvnx16hi */

        case E_VNx32HImode:
          if (pattern321 (x3, E_VNx32HImode, E_VNx32BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 6049; /* pred_fault_loadvnx32hi */

        case E_VNx1SImode:
          if (pattern321 (x3, E_VNx1SImode, E_VNx1BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6050; /* pred_fault_loadvnx1si */

        case E_VNx2SImode:
          if (pattern321 (x3, E_VNx2SImode, E_VNx2BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6051; /* pred_fault_loadvnx2si */

        case E_VNx4SImode:
          if (pattern321 (x3, E_VNx4SImode, E_VNx4BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6052; /* pred_fault_loadvnx4si */

        case E_VNx8SImode:
          if (pattern321 (x3, E_VNx8SImode, E_VNx8BImode) != 0
              || !
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR))
            return -1;
          return 6053; /* pred_fault_loadvnx8si */

        case E_VNx16SImode:
          if (pattern321 (x3, E_VNx16SImode, E_VNx16BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
            return -1;
          return 6054; /* pred_fault_loadvnx16si */

        case E_VNx1DImode:
          if (pattern321 (x3, E_VNx1DImode, E_VNx1BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 6055; /* pred_fault_loadvnx1di */

        case E_VNx2DImode:
          if (pattern321 (x3, E_VNx2DImode, E_VNx2BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 6056; /* pred_fault_loadvnx2di */

        case E_VNx4DImode:
          if (pattern321 (x3, E_VNx4DImode, E_VNx4BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 6057; /* pred_fault_loadvnx4di */

        case E_VNx8DImode:
          if (pattern321 (x3, E_VNx8DImode, E_VNx8BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
            return -1;
          return 6058; /* pred_fault_loadvnx8di */

        case E_VNx1SFmode:
          if (pattern321 (x3, E_VNx1SFmode, E_VNx1BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 6059; /* pred_fault_loadvnx1sf */

        case E_VNx2SFmode:
          if (pattern321 (x3, E_VNx2SFmode, E_VNx2BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 6060; /* pred_fault_loadvnx2sf */

        case E_VNx4SFmode:
          if (pattern321 (x3, E_VNx4SFmode, E_VNx4BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 6061; /* pred_fault_loadvnx4sf */

        case E_VNx8SFmode:
          if (pattern321 (x3, E_VNx8SFmode, E_VNx8BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
            return -1;
          return 6062; /* pred_fault_loadvnx8sf */

        case E_VNx16SFmode:
          if (pattern321 (x3, E_VNx16SFmode, E_VNx16BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
            return -1;
          return 6063; /* pred_fault_loadvnx16sf */

        case E_VNx1DFmode:
          if (pattern321 (x3, E_VNx1DFmode, E_VNx1BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 6064; /* pred_fault_loadvnx1df */

        case E_VNx2DFmode:
          if (pattern321 (x3, E_VNx2DFmode, E_VNx2BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 6065; /* pred_fault_loadvnx2df */

        case E_VNx4DFmode:
          if (pattern321 (x3, E_VNx4DFmode, E_VNx4BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 6066; /* pred_fault_loadvnx4df */

        case E_VNx8DFmode:
          if (pattern321 (x3, E_VNx8DFmode, E_VNx8BImode) != 0
              || !(
#line 7279 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
            return -1;
          return 6067; /* pred_fault_loadvnx8df */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_157 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15, x16, x17;
  rtx x18, x19, x20, x21, x22, x23;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  switch (GET_CODE (x2))
    {
    case SET:
      x3 = XEXP (x2, 1);
      switch (GET_CODE (x3))
        {
        case AND:
          if (GET_MODE (x3) != E_DImode)
            return -1;
          x4 = XEXP (x3, 0);
          if (GET_CODE (x4) != ASHIFT
              || GET_MODE (x4) != E_DImode)
            return -1;
          x5 = XVECEXP (x1, 0, 1);
          if (GET_CODE (x5) != CLOBBER)
            return -1;
          x6 = XEXP (x2, 0);
          operands[0] = x6;
          if (!register_operand (operands[0], E_DImode)
              || pattern112 (x1) != 0
              || !
#line 2236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)))
            return -1;
          return 225; /* zero_extendsidi2_shifted */

        case IF_THEN_ELSE:
          return recog_156 (x1, insn, pnum_clobbers);

        case CONST_INT:
        case CONST_WIDE_INT:
        case CONST_VECTOR:
        case REG:
        case SUBREG:
        case MEM:
          x6 = XEXP (x2, 0);
          switch (GET_CODE (x6))
            {
            case PC:
              res = recog_151 (x1, insn, pnum_clobbers);
              if (res >= 0)
                return res;
              break;

            case REG:
            case SUBREG:
            case MEM:
              res = recog_155 (x1, insn, pnum_clobbers);
              if (res >= 0)
                return res;
              break;

            default:
              break;
            }
          if (GET_CODE (x3) != MEM)
            return -1;
          x5 = XVECEXP (x1, 0, 1);
          if (GET_CODE (x5) != CLOBBER)
            return -1;
          operands[0] = x6;
          x4 = XEXP (x3, 0);
          operands[1] = x4;
          if (!absolute_symbolic_operand (operands[1], E_VOIDmode))
            return -1;
          x7 = XEXP (x5, 0);
          operands[2] = x7;
          switch (GET_MODE (operands[0]))
            {
            case E_SFmode:
              switch (pattern118 (x3, E_SFmode))
                {
                case 0:
                  if ((
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
                    return 531; /* *local_pic_loadsf */
                  if (!(
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
                    return -1;
                  return 537; /* *local_pic_load_32dsf */

                case 1:
                  if ((
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
                    return 534; /* *local_pic_loadsf */
                  if (!(
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
                    return -1;
                  return 540; /* *local_pic_load_32dsf */

                default:
                  return -1;
                }

            case E_DFmode:
              switch (pattern118 (x3, E_DFmode))
                {
                case 0:
                  if ((
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
                    return 532; /* *local_pic_loaddf */
                  if (!(
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
                    return -1;
                  return 538; /* *local_pic_load_32ddf */

                case 1:
                  if ((
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
                    return 535; /* *local_pic_loaddf */
                  if (!(
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
                    return -1;
                  return 541; /* *local_pic_load_32ddf */

                default:
                  return -1;
                }

            case E_HFmode:
              switch (pattern118 (x3, E_HFmode))
                {
                case 0:
                  if ((
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
                    return 533; /* *local_pic_loadhf */
                  if (!(
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))))
                    return -1;
                  return 539; /* *local_pic_load_32dhf */

                case 1:
                  if ((
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
                    return 536; /* *local_pic_loadhf */
                  if (!(
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))))
                    return -1;
                  return 542; /* *local_pic_load_32dhf */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        case CALL:
          x4 = XEXP (x3, 0);
          if (GET_CODE (x4) != MEM
              || GET_MODE (x4) != E_SImode)
            return -1;
          x5 = XVECEXP (x1, 0, 1);
          if (GET_CODE (x5) != CLOBBER)
            return -1;
          x7 = XEXP (x5, 0);
          if (GET_CODE (x7) != REG
              || REGNO (x7) != 1
              || GET_MODE (x7) != E_SImode)
            return -1;
          x6 = XEXP (x2, 0);
          operands[0] = x6;
          x8 = XEXP (x4, 0);
          operands[1] = x8;
          if (!call_insn_operand (operands[1], E_VOIDmode))
            return -1;
          x9 = XEXP (x3, 1);
          operands[2] = x9;
          return 300; /* call_value_internal */

        case UNSPEC:
          switch (XVECLEN (x3, 0))
            {
            case 1:
              x6 = XEXP (x2, 0);
              operands[0] = x6;
              switch (XINT (x3, 1))
                {
                case 11:
                  x5 = XVECEXP (x1, 0, 1);
                  if (GET_CODE (x5) != SET)
                    return -1;
                  x10 = XEXP (x5, 1);
                  if (x10 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
                    return -1;
                  x11 = XVECEXP (x3, 0, 0);
                  operands[1] = x11;
                  x7 = XEXP (x5, 0);
                  operands[2] = x7;
                  switch (GET_MODE (operands[0]))
                    {
                    case E_SImode:
                      if (pattern123 (x3, E_SImode) != 0)
                        return -1;
                      return 316; /* stack_protect_set_si */

                    case E_DImode:
                      if (pattern123 (x3, E_DImode) != 0
                          || !
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
                        return -1;
                      return 317; /* stack_protect_set_di */

                    default:
                      return -1;
                    }

                case 65:
                  if (GET_MODE (x3) != E_BLKmode)
                    return -1;
                  x5 = XVECEXP (x1, 0, 1);
                  operands[1] = x5;
                  if (!const_int_operand (operands[1], E_SImode))
                    return -1;
                  x11 = XVECEXP (x3, 0, 0);
                  if (!rtx_equal_p (x11, operands[0]))
                    return -1;
                  return 477; /* mem_thread_fence_1 */

                default:
                  return -1;
                }

            case 2:
              if (XINT (x3, 1) != 12)
                return -1;
              x5 = XVECEXP (x1, 0, 1);
              if (GET_CODE (x5) != CLOBBER)
                return -1;
              x6 = XEXP (x2, 0);
              operands[0] = x6;
              x11 = XVECEXP (x3, 0, 0);
              operands[1] = x11;
              x12 = XVECEXP (x3, 0, 1);
              operands[2] = x12;
              x7 = XEXP (x5, 0);
              operands[3] = x7;
              switch (GET_MODE (operands[0]))
                {
                case E_SImode:
                  if (pattern124 (x3, E_SImode) != 0)
                    return -1;
                  return 318; /* stack_protect_test_si */

                case E_DImode:
                  if (pattern124 (x3, E_DImode) != 0
                      || !
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
                    return -1;
                  return 319; /* stack_protect_test_di */

                default:
                  return -1;
                }

            case 3:
              if (XINT (x3, 1) != 66
                  || GET_MODE (x3) != E_SImode)
                return -1;
              x6 = XEXP (x2, 0);
              if (GET_CODE (x6) != REG
                  || REGNO (x6) != 66
                  || GET_MODE (x6) != E_SImode)
                return -1;
              x5 = XVECEXP (x1, 0, 1);
              if (pattern82 (x5, 67, 4) != 0)
                return -1;
              x11 = XVECEXP (x3, 0, 0);
              operands[0] = x11;
              x12 = XVECEXP (x3, 0, 1);
              operands[1] = x12;
              if (!const_int_operand (operands[1], E_VOIDmode))
                return -1;
              x13 = XVECEXP (x3, 0, 2);
              operands[2] = x13;
              if (!const_int_operand (operands[2], E_VOIDmode))
                return -1;
              x10 = XEXP (x5, 1);
              x14 = XVECEXP (x10, 0, 2);
              operands[3] = x14;
              if (!const_int_operand (operands[3], E_VOIDmode))
                return -1;
              x15 = XVECEXP (x10, 0, 3);
              operands[4] = x15;
              if (!const_int_operand (operands[4], E_VOIDmode))
                return -1;
              x16 = XVECEXP (x10, 0, 0);
              if (!rtx_equal_p (x16, operands[1]))
                return -1;
              x17 = XVECEXP (x10, 0, 1);
              if (!rtx_equal_p (x17, operands[2]))
                return -1;
              if (csr_operand (operands[0], E_SImode)
                  && (
#line 871 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return 796; /* vsetvl_discard_resultsi */
              if (!csr_operand (operands[0], E_DImode)
                  || !(
#line 871 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 797; /* vsetvl_discard_resultdi */

            default:
              return -1;
            }

        case PLUS:
          if (pattern51 (x3, E_DImode, ASHIFT, AND) != 0)
            return -1;
          x5 = XVECEXP (x1, 0, 1);
          if (GET_CODE (x5) != CLOBBER)
            return -1;
          x6 = XEXP (x2, 0);
          operands[0] = x6;
          if (!register_operand (operands[0], E_DImode))
            return -1;
          x4 = XEXP (x3, 0);
          x8 = XEXP (x4, 0);
          x18 = XEXP (x8, 0);
          operands[1] = x18;
          if (!register_operand (operands[1], E_DImode))
            return -1;
          x19 = XEXP (x8, 1);
          operands[2] = x19;
          if (!imm123_operand (operands[2], E_QImode))
            return -1;
          x20 = XEXP (x4, 1);
          operands[3] = x20;
          if (!consecutive_bits_operand (operands[3], E_DImode))
            return -1;
          x9 = XEXP (x3, 1);
          operands[4] = x9;
          if (!register_operand (operands[4], E_DImode))
            return -1;
          x7 = XEXP (x5, 0);
          operands[5] = x7;
          if (!scratch_operand (operands[5], E_DImode)
              || !
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2]))))
            return -1;
          return 334; /* *andi_add.uw */

        case UNSPEC_VOLATILE:
          if (XVECLEN (x3, 0) != 2
              || XINT (x3, 1) != 61)
            return -1;
          x5 = XVECEXP (x1, 0, 1);
          if (GET_CODE (x5) != SET)
            return -1;
          x6 = XEXP (x2, 0);
          operands[0] = x6;
          x11 = XVECEXP (x3, 0, 0);
          operands[1] = x11;
          x12 = XVECEXP (x3, 0, 1);
          operands[3] = x12;
          if (!const_int_operand (operands[3], E_SImode))
            return -1;
          x10 = XEXP (x5, 1);
          operands[2] = x10;
          x7 = XEXP (x5, 0);
          if (!rtx_equal_p (x7, operands[1]))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_SImode:
              if (pattern134 (x3, E_SImode) != 0
                  || !
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                return -1;
              return 503; /* atomic_exchangesi */

            case E_DImode:
              if (pattern134 (x3, E_DImode) != 0
                  || !(
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 504; /* atomic_exchangedi */

            default:
              return -1;
            }

        case SIGN_EXTEND:
          if (pattern52 (x1, SIGN_EXTEND) != 0
              || !
#line 328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
   && th_mempair_operands_p (operands, true, SImode)))
            return -1;
          return 613; /* *th_mempair_load_extendsidi2 */

        case ZERO_EXTEND:
          if (pattern52 (x1, ZERO_EXTEND) != 0
              || !
#line 341 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
   && th_mempair_operands_p (operands, true, SImode)))
            return -1;
          return 614; /* *th_mempair_load_zero_extendsidi2 */

        default:
          return -1;
        }

    case SIMPLE_RETURN:
      x5 = XVECEXP (x1, 0, 1);
      if (GET_CODE (x5) != USE)
        return -1;
      x7 = XEXP (x5, 0);
      operands[0] = x7;
      if (!pmode_register_operand (operands[0], E_VOIDmode))
        return -1;
      return 293; /* simple_return_internal */

    case UNSPEC:
      if (XVECLEN (x2, 0) != 1
          || XINT (x2, 1) != 0)
        return -1;
      x5 = XVECEXP (x1, 0, 1);
      if (GET_CODE (x5) != CLOBBER)
        return -1;
      x21 = XVECEXP (x2, 0, 0);
      operands[0] = x21;
      x7 = XEXP (x5, 0);
      operands[1] = x7;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (!register_operand (operands[0], E_SImode)
              || !scratch_operand (operands[1], E_SImode)
              || !
#line 2757 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(! TARGET_64BIT))
            return -1;
          return 294; /* eh_set_lr_si */

        case E_DImode:
          if (!register_operand (operands[0], E_DImode)
              || !scratch_operand (operands[1], E_DImode)
              || !
#line 2763 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
            return -1;
          return 295; /* eh_set_lr_di */

        default:
          return -1;
        }

    case CALL:
      x6 = XEXP (x2, 0);
      if (GET_CODE (x6) != MEM
          || GET_MODE (x6) != E_SImode)
        return -1;
      x5 = XVECEXP (x1, 0, 1);
      if (GET_CODE (x5) != CLOBBER)
        return -1;
      x7 = XEXP (x5, 0);
      if (GET_CODE (x7) != REG
          || REGNO (x7) != 1
          || GET_MODE (x7) != E_SImode)
        return -1;
      x22 = XEXP (x6, 0);
      operands[0] = x22;
      if (!call_insn_operand (operands[0], E_VOIDmode))
        return -1;
      x3 = XEXP (x2, 1);
      operands[1] = x3;
      return 299; /* call_internal */

    case RETURN:
      x5 = XVECEXP (x1, 0, 1);
      if (GET_CODE (x5) != UNSPEC_VOLATILE
          || XVECLEN (x5, 0) != 1)
        return -1;
      x23 = XVECEXP (x5, 0, 0);
      if (x23 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
        return -1;
      switch (XINT (x5, 1))
        {
        case 5:
          return 311; /* riscv_mret */

        case 6:
          return 312; /* riscv_sret */

        case 7:
          return 313; /* riscv_uret */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_158 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15, x16, x17;
  rtx x18, x19, x20, x21, x22, x23;
  int res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  switch (GET_CODE (x2))
    {
    case RETURN:
      x3 = XVECEXP (x1, 0, 1);
      if (GET_CODE (x3) != USE)
        return -1;
      x4 = XVECEXP (x1, 0, 2);
      if (x4 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
        return -1;
      x5 = XEXP (x3, 0);
      operands[0] = x5;
      if (!pmode_register_operand (operands[0], E_VOIDmode))
        return -1;
      return 305; /* gpr_restore_return */

    case SET:
      x6 = XEXP (x2, 1);
      switch (GET_CODE (x6))
        {
        case SIGN_EXTEND:
          if (pattern53 (x6) != 0)
            return -1;
          x3 = XVECEXP (x1, 0, 1);
          if (GET_CODE (x3) != CLOBBER)
            return -1;
          x4 = XVECEXP (x1, 0, 2);
          if (GET_CODE (x4) != CLOBBER)
            return -1;
          switch (pattern114 (x1))
            {
            case 0:
              if (!
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0))
                return -1;
              return 381; /* *minmax */

            case 1:
              if (!
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0))
                return -1;
              return 382; /* *minmax */

            case 2:
              if (!
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0))
                return -1;
              return 383; /* *minmax */

            case 3:
              if (!
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0))
                return -1;
              return 384; /* *minmax */

            default:
              return -1;
            }

        case IF_THEN_ELSE:
          if (pattern54 (x2) != 0)
            return -1;
          x3 = XVECEXP (x1, 0, 1);
          if (GET_CODE (x3) != CLOBBER)
            return -1;
          x4 = XVECEXP (x1, 0, 2);
          if (GET_CODE (x4) != CLOBBER)
            return -1;
          switch (pattern126 (x1))
            {
            case 0:
              if (!(
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 419; /* *branchsi_mask_twobits_equals_singlebit */

            case 1:
              if (!(
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 420; /* *branchdi_mask_twobits_equals_singlebit */

            default:
              return -1;
            }

        case SUBREG:
        case MEM:
          operands[1] = x6;
          x3 = XVECEXP (x1, 0, 1);
          if (GET_CODE (x3) != SET)
            return -1;
          x7 = XEXP (x3, 1);
          if (GET_CODE (x7) != UNSPEC_VOLATILE)
            return -1;
          x8 = XEXP (x2, 0);
          operands[0] = x8;
          x5 = XEXP (x3, 0);
          if (!rtx_equal_p (x5, operands[1]))
            return -1;
          switch (XVECLEN (x7, 0))
            {
            case 2:
              if (pnum_clobbers == NULL
                  || XINT (x7, 1) != 62
                  || GET_MODE (x7) != E_SImode
                  || !register_operand (operands[0], E_SImode)
                  || !memory_operand (operands[1], E_SImode))
                return -1;
              x9 = XVECEXP (x7, 0, 0);
              operands[2] = x9;
              if (!reg_or_0_operand (operands[2], E_SImode))
                return -1;
              x10 = XVECEXP (x7, 0, 1);
              operands[3] = x10;
              if (!const_int_operand (operands[3], E_SImode))
                return -1;
              x4 = XVECEXP (x1, 0, 2);
              operands[4] = x4;
              if (!reg_or_0_operand (operands[4], E_SImode)
                  || !
#line 337 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
                return -1;
              *pnum_clobbers = 1;
              return 505; /* subword_atomic_exchange_strong */

            case 4:
              if (XINT (x7, 1) != 57)
                return -1;
              x4 = XVECEXP (x1, 0, 2);
              if (GET_CODE (x4) != CLOBBER)
                return -1;
              x9 = XVECEXP (x7, 0, 0);
              operands[2] = x9;
              x10 = XVECEXP (x7, 0, 1);
              operands[3] = x10;
              x11 = XVECEXP (x7, 0, 2);
              operands[4] = x11;
              if (!const_int_operand (operands[4], E_SImode))
                return -1;
              x12 = XVECEXP (x7, 0, 3);
              operands[5] = x12;
              if (!const_int_operand (operands[5], E_SImode))
                return -1;
              x13 = XEXP (x4, 0);
              operands[6] = x13;
              switch (GET_MODE (operands[0]))
                {
                case E_SImode:
                  if (pattern210 (x7, E_SImode) != 0
                      || !
#line 358 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC))
                    return -1;
                  return 506; /* atomic_cas_value_strongsi */

                case E_DImode:
                  if (pattern210 (x7, E_DImode) != 0
                      || !(
#line 358 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 507; /* atomic_cas_value_strongdi */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        case UNSPEC:
          if (XVECLEN (x6, 0) != 5
              || XINT (x6, 1) != 66)
            return -1;
          x3 = XVECEXP (x1, 0, 1);
          if (pattern82 (x3, 66, 3) != 0)
            return -1;
          x4 = XVECEXP (x1, 0, 2);
          if (GET_CODE (x4) != SET)
            return -1;
          x14 = XEXP (x4, 1);
          if (GET_CODE (x14) != UNSPEC
              || XVECLEN (x14, 0) != 4
              || XINT (x14, 1) != 66
              || GET_MODE (x14) != E_SImode)
            return -1;
          x13 = XEXP (x4, 0);
          if (GET_CODE (x13) != REG
              || REGNO (x13) != 67
              || GET_MODE (x13) != E_SImode)
            return -1;
          x8 = XEXP (x2, 0);
          operands[0] = x8;
          x15 = XVECEXP (x6, 0, 0);
          operands[1] = x15;
          x16 = XVECEXP (x6, 0, 1);
          operands[2] = x16;
          if (!const_int_operand (operands[2], E_VOIDmode))
            return -1;
          x17 = XVECEXP (x6, 0, 2);
          operands[3] = x17;
          if (!const_int_operand (operands[3], E_VOIDmode))
            return -1;
          x18 = XVECEXP (x6, 0, 3);
          operands[4] = x18;
          if (!const_int_operand (operands[4], E_VOIDmode))
            return -1;
          x19 = XVECEXP (x6, 0, 4);
          operands[5] = x19;
          if (!const_int_operand (operands[5], E_VOIDmode))
            return -1;
          x7 = XEXP (x3, 1);
          x9 = XVECEXP (x7, 0, 0);
          if (!rtx_equal_p (x9, operands[1]))
            return -1;
          x10 = XVECEXP (x7, 0, 1);
          if (!rtx_equal_p (x10, operands[2]))
            return -1;
          x11 = XVECEXP (x7, 0, 2);
          if (!rtx_equal_p (x11, operands[3]))
            return -1;
          x20 = XVECEXP (x14, 0, 0);
          if (!rtx_equal_p (x20, operands[2]))
            return -1;
          x21 = XVECEXP (x14, 0, 1);
          if (!rtx_equal_p (x21, operands[3]))
            return -1;
          x22 = XVECEXP (x14, 0, 2);
          if (!rtx_equal_p (x22, operands[4]))
            return -1;
          x23 = XVECEXP (x14, 0, 3);
          if (!rtx_equal_p (x23, operands[5]))
            return -1;
          switch (GET_MODE (operands[0]))
            {
            case E_SImode:
              if (!register_operand (operands[0], E_SImode)
                  || GET_MODE (x6) != E_SImode
                  || !csr_operand (operands[1], E_SImode)
                  || !(
#line 835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
                return -1;
              return 793; /* vsetvlsi */

            case E_DImode:
              if (!register_operand (operands[0], E_DImode)
                  || GET_MODE (x6) != E_DImode
                  || !csr_operand (operands[1], E_DImode)
                  || !(
#line 835 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
                return -1;
              return 794; /* vsetvldi */

            default:
              return -1;
            }

        default:
          return -1;
        }

    default:
      return -1;
    }
}

static int
recog_159 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15;
  int res ATTRIBUTE_UNUSED;
  if (pattern11 (x1) != 0)
    return -1;
  x2 = XVECEXP (x1, 0, 5);
  if (GET_CODE (x2) != CLOBBER)
    return -1;
  x3 = XVECEXP (x1, 0, 0);
  x4 = XEXP (x3, 0);
  operands[0] = x4;
  if (!register_operand (operands[0], E_SImode))
    return -1;
  x5 = XEXP (x3, 1);
  operands[1] = x5;
  if (!memory_operand (operands[1], E_SImode))
    return -1;
  x6 = XVECEXP (x1, 0, 1);
  x7 = XEXP (x6, 1);
  if (GET_MODE (x7) != E_SImode)
    return -1;
  x8 = XVECEXP (x7, 0, 1);
  operands[3] = x8;
  x9 = XVECEXP (x1, 0, 2);
  operands[4] = x9;
  x10 = XVECEXP (x1, 0, 3);
  operands[5] = x10;
  if (!register_operand (operands[5], E_SImode))
    return -1;
  x11 = XEXP (x2, 0);
  operands[7] = x11;
  if (!scratch_operand (operands[7], E_SImode))
    return -1;
  x12 = XEXP (x6, 0);
  if (!rtx_equal_p (x12, operands[1]))
    return -1;
  switch (XINT (x7, 1))
    {
    case 60:
      x13 = XVECEXP (x1, 0, 4);
      if (GET_CODE (x13) != CLOBBER)
        return -1;
      x14 = XVECEXP (x7, 0, 0);
      if (GET_MODE (x14) != E_SImode
          || !const_int_operand (operands[3], E_SImode)
          || !register_operand (operands[4], E_SImode))
        return -1;
      x15 = XEXP (x13, 0);
      operands[6] = x15;
      if (!scratch_operand (operands[6], E_SImode))
        return -1;
      switch (pattern214 (x14))
        {
        case 0:
          if (!
#line 161 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
            return -1;
          return 498; /* subword_atomic_fetch_strong_add */

        case 1:
          if (!
#line 161 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
            return -1;
          return 499; /* subword_atomic_fetch_strong_or */

        case 2:
          if (!
#line 161 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
            return -1;
          return 500; /* subword_atomic_fetch_strong_xor */

        case 3:
          if (!
#line 161 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
            return -1;
          return 501; /* subword_atomic_fetch_strong_and */

        case 4:
          if (!
#line 227 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
            return -1;
          return 502; /* subword_atomic_fetch_strong_nand */

        default:
          return -1;
        }

    case 58:
      x14 = XVECEXP (x7, 0, 0);
      operands[2] = x14;
      if (!reg_or_0_operand (operands[2], E_SImode)
          || !reg_or_0_operand (operands[3], E_SImode)
          || !const_int_operand (operands[4], E_SImode))
        return -1;
      x13 = XVECEXP (x1, 0, 4);
      operands[6] = x13;
      if (!register_operand (operands[6], E_SImode)
          || !
#line 530 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
        return -1;
      return 508; /* subword_atomic_cas_strong */

    default:
      return -1;
    }
}

static int
recog_160 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12;
  int res ATTRIBUTE_UNUSED;
  if (pattern11 (x1) != 0)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  x3 = XEXP (x2, 0);
  operands[0] = x3;
  if (!register_operand (operands[0], E_SImode))
    return -1;
  x4 = XEXP (x2, 1);
  operands[1] = x4;
  if (!memory_operand (operands[1], E_SImode))
    return -1;
  x5 = XVECEXP (x1, 0, 1);
  x6 = XEXP (x5, 1);
  if (GET_MODE (x6) != E_SImode)
    return -1;
  x7 = XVECEXP (x6, 0, 1);
  operands[3] = x7;
  if (!const_int_operand (operands[3], E_SImode))
    return -1;
  x8 = XVECEXP (x1, 0, 2);
  operands[4] = x8;
  x9 = XEXP (x5, 0);
  if (!rtx_equal_p (x9, operands[1]))
    return -1;
  switch (XINT (x6, 1))
    {
    case 60:
      if (pnum_clobbers == NULL)
        return -1;
      x10 = XVECEXP (x6, 0, 0);
      if (GET_MODE (x10) != E_SImode
          || !register_operand (operands[4], E_SImode))
        return -1;
      x11 = XVECEXP (x1, 0, 3);
      operands[5] = x11;
      if (!register_operand (operands[5], E_SImode))
        return -1;
      switch (pattern214 (x10))
        {
        case 0:
          if (!
#line 161 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
            return -1;
          *pnum_clobbers = 2;
          return 498; /* subword_atomic_fetch_strong_add */

        case 1:
          if (!
#line 161 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
            return -1;
          *pnum_clobbers = 2;
          return 499; /* subword_atomic_fetch_strong_or */

        case 2:
          if (!
#line 161 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
            return -1;
          *pnum_clobbers = 2;
          return 500; /* subword_atomic_fetch_strong_xor */

        case 3:
          if (!
#line 161 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
            return -1;
          *pnum_clobbers = 2;
          return 501; /* subword_atomic_fetch_strong_and */

        case 4:
          if (!
#line 227 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
            return -1;
          *pnum_clobbers = 2;
          return 502; /* subword_atomic_fetch_strong_nand */

        default:
          return -1;
        }

    case 62:
      x11 = XVECEXP (x1, 0, 3);
      if (GET_CODE (x11) != CLOBBER)
        return -1;
      x10 = XVECEXP (x6, 0, 0);
      operands[2] = x10;
      if (!reg_or_0_operand (operands[2], E_SImode)
          || !reg_or_0_operand (operands[4], E_SImode))
        return -1;
      x12 = XEXP (x11, 0);
      operands[5] = x12;
      if (!scratch_operand (operands[5], E_SImode)
          || !
#line 337 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
        return -1;
      return 505; /* subword_atomic_exchange_strong */

    default:
      return -1;
    }
}

static int
recog_161 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12;
  int res ATTRIBUTE_UNUSED;
  if (pnum_clobbers == NULL)
    return -1;
  x2 = XVECEXP (x1, 0, 0);
  if (GET_CODE (x2) != SET)
    return -1;
  x3 = XVECEXP (x1, 0, 1);
  if (pattern55 (x3, 58, 2, UNSPEC_VOLATILE) != 0)
    return -1;
  x4 = XEXP (x2, 0);
  operands[0] = x4;
  if (!register_operand (operands[0], E_SImode))
    return -1;
  x5 = XEXP (x2, 1);
  operands[1] = x5;
  if (!memory_operand (operands[1], E_SImode))
    return -1;
  x6 = XEXP (x3, 1);
  x7 = XVECEXP (x6, 0, 0);
  operands[2] = x7;
  if (!reg_or_0_operand (operands[2], E_SImode))
    return -1;
  x8 = XVECEXP (x6, 0, 1);
  operands[3] = x8;
  if (!reg_or_0_operand (operands[3], E_SImode))
    return -1;
  x9 = XVECEXP (x1, 0, 2);
  operands[4] = x9;
  if (!const_int_operand (operands[4], E_SImode))
    return -1;
  x10 = XVECEXP (x1, 0, 3);
  operands[5] = x10;
  if (!register_operand (operands[5], E_SImode))
    return -1;
  x11 = XVECEXP (x1, 0, 4);
  operands[6] = x11;
  if (!register_operand (operands[6], E_SImode))
    return -1;
  x12 = XEXP (x3, 0);
  if (!rtx_equal_p (x12, operands[1])
      || !
#line 530 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC))
    return -1;
  *pnum_clobbers = 1;
  return 508; /* subword_atomic_cas_strong */
}

static int
recog_162 (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7;
  int res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  switch (GET_CODE (x2))
    {
    case PLUS:
      return recog_136 (x1, insn, pnum_clobbers);

    case SIGN_EXTEND:
      return recog_135 (x1, insn, pnum_clobbers);

    case MINUS:
      return recog_146 (x1, insn, pnum_clobbers);

    case NEG:
      return recog_137 (x1, insn, pnum_clobbers);

    case MULT:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      x5 = XEXP (x2, 1);
      operands[2] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_SFmode:
          if (pattern0 (x2, E_SFmode) != 0
              || !(
#line 766 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
            return -1;
          return 19; /* mulsf3 */

        case E_DFmode:
          if (pattern0 (x2, E_DFmode) != 0
              || !(
#line 766 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 20; /* muldf3 */

        case E_HFmode:
          if (pattern0 (x2, E_HFmode) != 0
              || !(
#line 766 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 21; /* mulhf3 */

        case E_SImode:
          if (pattern0 (x2, E_SImode) != 0
              || !
#line 775 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZMMUL || TARGET_MUL))
            return -1;
          return 22; /* mulsi3 */

        case E_DImode:
          if (pattern0 (x2, E_DImode) != 0
              || !
#line 784 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT))
            return -1;
          return 23; /* muldi3 */

        default:
          return -1;
        }

    case TRUNCATE:
      return recog_141 (x1, insn, pnum_clobbers);

    case DIV:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      x5 = XEXP (x2, 1);
      operands[2] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (pattern0 (x2, E_SImode) != 0
              || !
#line 1045 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV))
            return -1;
          return 32; /* divsi3 */

        case E_DImode:
          if (pattern0 (x2, E_DImode) != 0
              || !
#line 1054 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV && TARGET_64BIT))
            return -1;
          return 36; /* divdi3 */

        case E_SFmode:
          if (pattern0 (x2, E_SFmode) != 0
              || !(
#line 1073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
            return -1;
          return 44; /* divsf3 */

        case E_DFmode:
          if (pattern0 (x2, E_DFmode) != 0
              || !(
#line 1073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 45; /* divdf3 */

        case E_HFmode:
          if (pattern0 (x2, E_HFmode) != 0
              || !(
#line 1073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 46; /* divhf3 */

        default:
          return -1;
        }

    case UDIV:
      switch (pattern1 (x1))
        {
        case 0:
          if (!
#line 1045 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV))
            return -1;
          return 33; /* udivsi3 */

        case 1:
          if (!
#line 1054 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV && TARGET_64BIT))
            return -1;
          return 37; /* udivdi3 */

        default:
          return -1;
        }

    case MOD:
      switch (pattern1 (x1))
        {
        case 0:
          if (!
#line 1045 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV))
            return -1;
          return 34; /* modsi3 */

        case 1:
          if (!
#line 1054 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV && TARGET_64BIT))
            return -1;
          return 38; /* moddi3 */

        default:
          return -1;
        }

    case UMOD:
      switch (pattern1 (x1))
        {
        case 0:
          if (!
#line 1045 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV))
            return -1;
          return 35; /* umodsi3 */

        case 1:
          if (!
#line 1054 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV && TARGET_64BIT))
            return -1;
          return 39; /* umoddi3 */

        default:
          return -1;
        }

    case SQRT:
      switch (pattern2 (x1))
        {
        case 0:
          if (!(
#line 1088 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
            return -1;
          return 47; /* sqrtsf2 */

        case 1:
          if (!(
#line 1088 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 48; /* sqrtdf2 */

        case 2:
          if (!(
#line 1088 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 49; /* sqrthf2 */

        default:
          return -1;
        }

    case FMA:
      return recog_144 (x1, insn, pnum_clobbers);

    case ABS:
      switch (pattern2 (x1))
        {
        case 0:
          if (!
#line 1205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
            return -1;
          return 74; /* abssf2 */

        case 1:
          if (!(
#line 1205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 75; /* absdf2 */

        case 2:
          if (!(
#line 1205 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 76; /* abshf2 */

        default:
          return -1;
        }

    case UNSPEC:
      return recog_134 (x1, insn, pnum_clobbers);

    case SMIN:
      switch (pattern4 (x1))
        {
        case 0:
          if (!
#line 1259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
            return -1;
          return 89; /* sminsf3 */

        case 1:
          if (!(
#line 1259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 90; /* smindf3 */

        case 2:
          if (!(
#line 1259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 91; /* sminhf3 */

        case 3:
          if (!(
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 373; /* sminsi3 */

        case 4:
          if (!(
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 377; /* smindi3 */

        default:
          return -1;
        }

    case SMAX:
      switch (pattern4 (x1))
        {
        case 0:
          if (!
#line 1268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
            return -1;
          return 92; /* smaxsf3 */

        case 1:
          if (!(
#line 1268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 93; /* smaxdf3 */

        case 2:
          if (!(
#line 1268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 94; /* smaxhf3 */

        case 3:
          if (!(
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 375; /* smaxsi3 */

        case 4:
          if (!(
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 379; /* smaxdi3 */

        default:
          return -1;
        }

    case AND:
      return recog_143 (x1, insn, pnum_clobbers);

    case IOR:
      return recog_139 (x1, insn, pnum_clobbers);

    case XOR:
      return recog_149 (x1, insn, pnum_clobbers);

    case NOT:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      switch (GET_CODE (x4))
        {
        case REG:
        case SUBREG:
          operands[1] = x4;
          switch (pattern12 (x2))
            {
            case 0:
              if (
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
                return 104; /* one_cmplsi2 */
              if (!
#line 1313 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
                return -1;
              return 106; /* *one_cmplsi2_internal */

            case 1:
              if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
                return -1;
              return 105; /* one_cmpldi2 */

            default:
              return -1;
            }

        case XOR:
          x6 = XEXP (x4, 0);
          operands[1] = x6;
          x7 = XEXP (x4, 1);
          operands[2] = x7;
          switch (GET_MODE (operands[0]))
            {
            case E_SImode:
              if (pattern85 (x2, E_SImode) != 0
                  || !(
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                return -1;
              return 342; /* *xor_notsi */

            case E_DImode:
              if (pattern85 (x2, E_DImode) != 0
                  || !(
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return -1;
              return 343; /* *xor_notdi */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case FLOAT_TRUNCATE:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_SFmode:
          if (!register_operand (operands[0], E_SFmode)
              || GET_MODE (x2) != E_SFmode
              || !register_operand (operands[1], E_DFmode)
              || !
#line 1329 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))
            return -1;
          return 107; /* truncdfsf2 */

        case E_HFmode:
          if (!register_operand (operands[0], E_HFmode)
              || GET_MODE (x2) != E_HFmode)
            return -1;
          switch (GET_MODE (operands[1]))
            {
            case E_SFmode:
              if (!register_operand (operands[1], E_SFmode)
                  || !
#line 1338 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZFHMIN || TARGET_ZHINXMIN))
                return -1;
              return 108; /* truncsfhf2 */

            case E_DFmode:
              if (!register_operand (operands[1], E_DFmode)
                  || !
#line 1347 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) ||
   (TARGET_ZHINXMIN && TARGET_ZDINX)))
                return -1;
              return 109; /* truncdfhf2 */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case ZERO_EXTEND:
      return recog_145 (x1, insn, pnum_clobbers);

    case FLOAT_EXTEND:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      switch (GET_MODE (operands[0]))
        {
        case E_SFmode:
          if (!register_operand (operands[0], E_SFmode)
              || GET_MODE (x2) != E_SFmode
              || !register_operand (operands[1], E_HFmode)
              || !
#line 1476 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZFHMIN || TARGET_ZHINXMIN))
            return -1;
          return 123; /* extendhfsf2 */

        case E_DFmode:
          if (!register_operand (operands[0], E_DFmode)
              || GET_MODE (x2) != E_DFmode)
            return -1;
          switch (GET_MODE (operands[1]))
            {
            case E_SFmode:
              if (!register_operand (operands[1], E_SFmode)
                  || !
#line 1485 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))
                return -1;
              return 124; /* extendsfdf2 */

            case E_HFmode:
              if (!register_operand (operands[1], E_HFmode)
                  || !
#line 1494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) ||
   (TARGET_ZHINXMIN && TARGET_ZDINX)))
                return -1;
              return 125; /* extendhfdf2 */

            default:
              return -1;
            }

        default:
          return -1;
        }

    case CONST_INT:
    case CONST_WIDE_INT:
    case CONST_POLY_INT:
    case CONST_FIXED:
    case CONST_DOUBLE:
    case CONST_VECTOR:
    case CONST:
    case REG:
    case SUBREG:
    case MEM:
    case LABEL_REF:
    case SYMBOL_REF:
    case HIGH:
      return recog_132 (x1, insn, pnum_clobbers);

    case FIX:
      switch (pattern6 (x1))
        {
        case 0:
          if (!
#line 1541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
            return -1;
          return 128; /* fix_truncsfsi2 */

        case 1:
          if (!(
#line 1541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 130; /* fix_truncdfsi2 */

        case 2:
          if (!(
#line 1541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 132; /* fix_trunchfsi2 */

        case 3:
          if (!(
#line 1541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))))
            return -1;
          return 129; /* fix_truncsfdi2 */

        case 4:
          if (!(
#line 1541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))))
            return -1;
          return 131; /* fix_truncdfdi2 */

        case 5:
          if (!(
#line 1541 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))))
            return -1;
          return 133; /* fix_trunchfdi2 */

        default:
          return -1;
        }

    case UNSIGNED_FIX:
      switch (pattern6 (x1))
        {
        case 0:
          if (!(
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
            return -1;
          return 134; /* fixuns_truncsfsi2 */

        case 1:
          if (!(
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return -1;
          return 136; /* fixuns_truncdfsi2 */

        case 2:
          if (!(
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return -1;
          return 138; /* fixuns_trunchfsi2 */

        case 3:
          if (!(
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))))
            return -1;
          return 135; /* fixuns_truncsfdi2 */

        case 4:
          if (!(
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))))
            return -1;
          return 137; /* fixuns_truncdfdi2 */

        case 5:
          if (!(
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))))
            return -1;
          return 139; /* fixuns_trunchfdi2 */

        default:
          return -1;
        }

    case FLOAT:
      switch (pattern7 (x1))
        {
        case 0:
          if (reg_or_0_operand (operands[1], E_SImode)
              && 
#line 1559 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
            return 140; /* floatsisf2 */
          if (!reg_or_0_operand (operands[1], E_DImode)
              || !(
#line 1559 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))))
            return -1;
          return 141; /* floatdisf2 */

        case 1:
          if (reg_or_0_operand (operands[1], E_SImode)
              && (
#line 1559 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
            return 142; /* floatsidf2 */
          if (!reg_or_0_operand (operands[1], E_DImode)
              || !(
#line 1559 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))))
            return -1;
          return 143; /* floatdidf2 */

        case 2:
          if (reg_or_0_operand (operands[1], E_SImode)
              && (
#line 1559 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
            return 144; /* floatsihf2 */
          if (!reg_or_0_operand (operands[1], E_DImode)
              || !(
#line 1559 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))))
            return -1;
          return 145; /* floatdihf2 */

        default:
          return -1;
        }

    case UNSIGNED_FLOAT:
      return recog_150 (x1, insn, pnum_clobbers);

    case LO_SUM:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      x5 = XEXP (x2, 1);
      operands[2] = x5;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (pattern79 (x2, E_SImode) != 0
              || !
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
            return -1;
          return 174; /* *lowsi */

        case E_DImode:
          if (pattern79 (x2, E_DImode) != 0
              || !
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
            return -1;
          return 175; /* *lowdi */

        default:
          return -1;
        }

    case ASHIFT:
      return recog_148 (x1, insn, pnum_clobbers);

    case ASHIFTRT:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      x5 = XEXP (x2, 1);
      operands[2] = x5;
      if (arith_operand (operands[2], E_QImode))
        {
          switch (pattern12 (x2))
            {
            case 0:
              return 196; /* ashrsi3 */

            case 1:
              if (
#line 2034 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
                return 205; /* ashrdi3 */
              break;

            default:
              break;
            }
        }
      if (!subreg_lowpart_operator (x5, E_VOIDmode))
        return -1;
      switch (pattern72 (x2))
        {
        case 0:
          if (!
#line 1998 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
   == GET_MODE_BITSIZE (SImode)-1))
            return -1;
          return 199; /* *ashrsi3_mask */

        case 1:
          if (!
#line 2017 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1))
            return -1;
          return 202; /* *ashrsi3_mask_1 */

        case 2:
          if (!
#line 2053 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1))
            return -1;
          return 208; /* *ashrdi3_mask */

        case 3:
          if (!
#line 2073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1))
            return -1;
          return 211; /* *ashrdi3_mask_1 */

        default:
          return -1;
        }

    case LSHIFTRT:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      x5 = XEXP (x2, 1);
      operands[2] = x5;
      if (arith_operand (operands[2], E_QImode))
        {
          switch (pattern12 (x2))
            {
            case 0:
              return 197; /* lshrsi3 */

            case 1:
              if (
#line 2034 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
                return 206; /* lshrdi3 */
              break;

            default:
              break;
            }
        }
      if (!subreg_lowpart_operator (x5, E_VOIDmode))
        return -1;
      switch (pattern72 (x2))
        {
        case 0:
          if (!
#line 1998 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
   == GET_MODE_BITSIZE (SImode)-1))
            return -1;
          return 200; /* *lshrsi3_mask */

        case 1:
          if (!
#line 2017 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1))
            return -1;
          return 203; /* *lshrsi3_mask_1 */

        case 2:
          if (!
#line 2053 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1))
            return -1;
          return 209; /* *lshrdi3_mask */

        case 3:
          if (!
#line 2073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1))
            return -1;
          return 212; /* *lshrdi3_mask_1 */

        default:
          return -1;
        }

    case ZERO_EXTRACT:
      return recog_142 (x1, insn, pnum_clobbers);

    case EQ:
    case GE:
    case GT:
    case LE:
    case LT:
      return recog_140 (x1, insn, pnum_clobbers);

    case IF_THEN_ELSE:
      return recog_133 (x1, insn, pnum_clobbers);

    case NE:
      switch (pattern9 (x1, 0))
        {
        case 0:
          if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
            return -1;
          return 259; /* *sne_zero_sisi */

        case 1:
          if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 260; /* *sne_zero_disi */

        case 2:
          if (!
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 261; /* *sne_zero_didi */

        default:
          return -1;
        }

    case GTU:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      switch (pattern49 (x2))
        {
        case 0:
          if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
            return -1;
          return 263; /* *sgtu_sisi */

        case 1:
          if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 265; /* *sgtu_disi */

        case 2:
          if (!
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 267; /* *sgtu_didi */

        default:
          return -1;
        }

    case GEU:
      switch (pattern9 (x1, 1))
        {
        case 0:
          if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
            return -1;
          return 269; /* *sgeu_sisi */

        case 1:
          if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 271; /* *sgeu_disi */

        case 2:
          if (!
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 273; /* *sgeu_didi */

        default:
          return -1;
        }

    case LTU:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      x5 = XEXP (x2, 1);
      operands[2] = x5;
      switch (pattern74 (x2))
        {
        case 0:
          if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
            return -1;
          return 275; /* *sltu_sisi */

        case 1:
          if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 277; /* *sltu_disi */

        case 2:
          if (!
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 279; /* *sltu_didi */

        default:
          return -1;
        }

    case LEU:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      switch (pattern50 (x2))
        {
        case 0:
          if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
            return -1;
          return 281; /* *sleu_sisi */

        case 1:
          if (!
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 283; /* *sleu_disi */

        case 2:
          if (!
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
            return -1;
          return 285; /* *sleu_didi */

        default:
          return -1;
        }

    case CALL:
      x4 = XEXP (x2, 0);
      if (GET_CODE (x4) != MEM
          || GET_MODE (x4) != E_SImode)
        return -1;
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x6 = XEXP (x4, 0);
      operands[1] = x6;
      if (!call_insn_operand (operands[1], E_VOIDmode))
        return -1;
      x5 = XEXP (x2, 1);
      operands[2] = x5;
      if (
#line 2829 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(SIBLING_CALL_P (insn)))
        return 298; /* sibcall_value_internal */
      if (pnum_clobbers == NULL)
        return -1;
      *pnum_clobbers = 1;
      return 300; /* call_value_internal */

    case UNSPEC_VOLATILE:
      return recog_138 (x1, insn, pnum_clobbers);

    case CLZ:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      switch (pattern12 (x2))
        {
        case 0:
          if (
#line 244 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB))
            return 344; /* *clzsi2 */
          if (!(
#line 78 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 580; /* *th_clzsi2 */

        case 1:
          if (
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB))
            return 350; /* *clzdi2 */
          if (!(
#line 78 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 581; /* *th_clzdi2 */

        default:
          return -1;
        }

    case CTZ:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      switch (pattern12 (x2))
        {
        case 0:
          if (!
#line 244 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB))
            return -1;
          return 345; /* *ctzsi2 */

        case 1:
          if (!
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB))
            return -1;
          return 351; /* *ctzdi2 */

        default:
          return -1;
        }

    case POPCOUNT:
      return recog_147 (x1, insn, pnum_clobbers);

    case ROTATERT:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      switch (pattern13 (x2))
        {
        case 0:
          if (arith_operand (operands[2], E_QImode)
              && 
#line 312 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB))
            return 363; /* *rotrsi3 */
          if (!const_int_operand (operands[2], E_VOIDmode)
              || !
#line 39 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB && (TARGET_64BIT || SImode == SImode)))
            return -1;
          return 574; /* *th_srrisi3 */

        case 1:
          if (arith_operand (operands[2], E_QImode)
              && 
#line 320 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)))
            return 364; /* *rotrdi3 */
          if (!const_int_operand (operands[2], E_VOIDmode)
              || !(
#line 39 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB && (TARGET_64BIT || DImode == SImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 575; /* *th_srridi3 */

        default:
          return -1;
        }

    case ROTATE:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      x5 = XEXP (x2, 1);
      operands[2] = x5;
      if (!register_operand (operands[2], E_QImode))
        return -1;
      switch (pattern12 (x2))
        {
        case 0:
          if (!
#line 336 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB))
            return -1;
          return 366; /* rotlsi3 */

        case 1:
          if (!
#line 344 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)))
            return -1;
          return 367; /* rotldi3 */

        default:
          return -1;
        }

    case BSWAP:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      switch (pattern12 (x2))
        {
        case 0:
          if ((
#line 377 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return 371; /* *bswapsi2 */
          if (!
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB && (TARGET_64BIT || SImode == SImode)))
            return -1;
          return 582; /* *th_revsi2 */

        case 1:
          if ((
#line 377 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return 372; /* *bswapdi2 */
          if (!(
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB && (TARGET_64BIT || DImode == SImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 583; /* *th_revdi2 */

        default:
          return -1;
        }

    case UMIN:
      switch (pattern10 (x1))
        {
        case 0:
          if (!(
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 374; /* uminsi3 */

        case 1:
          if (!(
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 378; /* umindi3 */

        default:
          return -1;
        }

    case UMAX:
      switch (pattern10 (x1))
        {
        case 0:
          if (!(
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
            return -1;
          return 376; /* umaxsi3 */

        case 1:
          if (!(
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 380; /* umaxdi3 */

        default:
          return -1;
        }

    case SIGN_EXTRACT:
      x3 = XEXP (x1, 0);
      operands[0] = x3;
      x4 = XEXP (x2, 0);
      operands[1] = x4;
      x5 = XEXP (x2, 1);
      operands[2] = x5;
      switch (pattern75 (x2))
        {
        case 0:
          if (!
#line 54 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB))
            return -1;
          return 576; /* *th_extsi4 */

        case 1:
          if (!(
#line 54 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return -1;
          return 577; /* *th_extdi4 */

        default:
          return -1;
        }

    default:
      return -1;
    }
}

int
recog (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pnum_clobbers ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8;
  int res ATTRIBUTE_UNUSED;
  recog_data.insn = NULL;
  switch (GET_CODE (x1))
    {
    case SET:
      return recog_162 (x1, insn, pnum_clobbers);

    case UNSPEC_VOLATILE:
      switch (XVECLEN (x1, 0))
        {
        case 1:
          switch (XINT (x1, 1))
            {
            case 9:
              x2 = XVECEXP (x1, 0, 0);
              if (x2 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
                return -1;
              return 192; /* fence */

            case 10:
              x2 = XVECEXP (x1, 0, 0);
              if (x2 != const_int_rtx[MAX_SAVED_CONST_INT + 0]
                  || !
#line 1954 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZIFENCEI))
                return -1;
              return 193; /* fence_i */

            case 18:
              x2 = XVECEXP (x1, 0, 0);
              if (x2 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
                return -1;
              return 194; /* riscv_pause */

            case 8:
              x2 = XVECEXP (x1, 0, 0);
              if (x2 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
                return -1;
              return 291; /* blockage */

            case 1:
              x2 = XVECEXP (x1, 0, 0);
              operands[0] = x2;
              if (!const_int_operand (operands[0], E_VOIDmode))
                return -1;
              return 304; /* gpr_restore */

            case 3:
              x2 = XVECEXP (x1, 0, 0);
              operands[0] = x2;
              if (!csr_operand (operands[0], E_SImode)
                  || !
#line 2949 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
                return -1;
              return 307; /* riscv_fsflags */

            case 13:
              x2 = XVECEXP (x1, 0, 0);
              operands[0] = x2;
              switch (GET_MODE (x1))
                {
                case E_SImode:
                  if (!register_operand (operands[0], E_SImode)
                      || !(
#line 3088 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOM) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                    return -1;
                  return 320; /* riscv_clean_si */

                case E_DImode:
                  if (!register_operand (operands[0], E_DImode)
                      || !(
#line 3088 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOM) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 321; /* riscv_clean_di */

                default:
                  return -1;
                }

            case 14:
              x2 = XVECEXP (x1, 0, 0);
              operands[0] = x2;
              switch (GET_MODE (x1))
                {
                case E_SImode:
                  if (!register_operand (operands[0], E_SImode)
                      || !(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOM) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                    return -1;
                  return 322; /* riscv_flush_si */

                case E_DImode:
                  if (!register_operand (operands[0], E_DImode)
                      || !(
#line 3095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOM) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 323; /* riscv_flush_di */

                default:
                  return -1;
                }

            case 15:
              x2 = XVECEXP (x1, 0, 0);
              operands[0] = x2;
              switch (GET_MODE (x1))
                {
                case E_SImode:
                  if (!register_operand (operands[0], E_SImode)
                      || !(
#line 3102 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOM) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                    return -1;
                  return 324; /* riscv_inval_si */

                case E_DImode:
                  if (!register_operand (operands[0], E_DImode)
                      || !(
#line 3102 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOM) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 325; /* riscv_inval_di */

                default:
                  return -1;
                }

            case 16:
              x2 = XVECEXP (x1, 0, 0);
              operands[0] = x2;
              switch (GET_MODE (x1))
                {
                case E_SImode:
                  if (!register_operand (operands[0], E_SImode)
                      || !(
#line 3109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOZ) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                    return -1;
                  return 326; /* riscv_zero_si */

                case E_DImode:
                  if (!register_operand (operands[0], E_DImode)
                      || !(
#line 3109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOZ) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 327; /* riscv_zero_di */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        case 2:
          x2 = XVECEXP (x1, 0, 0);
          operands[0] = x2;
          x3 = XVECEXP (x1, 0, 1);
          operands[1] = x3;
          switch (XINT (x1, 1))
            {
            case 4:
              switch (GET_MODE (operands[0]))
                {
                case E_SFmode:
                  if (!register_operand (operands[0], E_SFmode)
                      || !register_operand (operands[1], E_SFmode)
                      || !
#line 2956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
                    return -1;
                  return 308; /* *riscv_fsnvsnansf2 */

                case E_DFmode:
                  if (!register_operand (operands[0], E_DFmode)
                      || !register_operand (operands[1], E_DFmode)
                      || !(
#line 2956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
                    return -1;
                  return 309; /* *riscv_fsnvsnandf2 */

                case E_HFmode:
                  if (!register_operand (operands[0], E_HFmode)
                      || !register_operand (operands[1], E_HFmode)
                      || !(
#line 2956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
                    return -1;
                  return 310; /* *riscv_fsnvsnanhf2 */

                default:
                  return -1;
                }

            case 17:
              switch (GET_MODE (x1))
                {
                case E_SImode:
                  if (!address_operand (operands[0], E_SImode)
                      || !imm5_operand (operands[1], E_SImode)
                      || !(
#line 3131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOP) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                    return -1;
                  return 329; /* riscv_prefetchi_si */

                case E_DImode:
                  if (!address_operand (operands[0], E_DImode)
                      || !imm5_operand (operands[1], E_DImode)
                      || !(
#line 3131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOP) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return -1;
                  return 330; /* riscv_prefetchi_di */

                default:
                  return -1;
                }

            default:
              return -1;
            }

        default:
          return -1;
        }

    case PARALLEL:
      switch (XVECLEN (x1, 0))
        {
        case 2:
          res = recog_157 (x1, insn, pnum_clobbers);
          if (res >= 0)
            return res;
          break;

        case 3:
          res = recog_158 (x1, insn, pnum_clobbers);
          if (res >= 0)
            return res;
          break;

        case 6:
          res = recog_159 (x1, insn, pnum_clobbers);
          if (res >= 0)
            return res;
          break;

        case 4:
          res = recog_160 (x1, insn, pnum_clobbers);
          if (res >= 0)
            return res;
          break;

        case 5:
          res = recog_161 (x1, insn, pnum_clobbers);
          if (res >= 0)
            return res;
          break;

        default:
          break;
        }
      if (XVECLEN (x1, 0) < 1)
        return -1;
      operands[1] = x1;
      if (!gpr_save_operation (operands[1], E_VOIDmode))
        return -1;
      x2 = XVECEXP (x1, 0, 0);
      if (GET_CODE (x2) != UNSPEC_VOLATILE
          || XVECLEN (x2, 0) != 1
          || XINT (x2, 1) != 0)
        return -1;
      x4 = XVECEXP (x2, 0, 0);
      operands[0] = x4;
      if (!const_int_operand (operands[0], E_VOIDmode))
        return -1;
      return 303; /* gpr_save */

    case SIMPLE_RETURN:
      return 292; /* simple_return */

    case UNSPEC:
      if (pnum_clobbers == NULL
          || XVECLEN (x1, 0) != 1
          || XINT (x1, 1) != 0)
        return -1;
      x2 = XVECEXP (x1, 0, 0);
      operands[0] = x2;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (!register_operand (operands[0], E_SImode)
              || !
#line 2757 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(! TARGET_64BIT))
            return -1;
          *pnum_clobbers = 1;
          return 294; /* eh_set_lr_si */

        case E_DImode:
          if (!register_operand (operands[0], E_DImode)
              || !
#line 2763 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
            return -1;
          *pnum_clobbers = 1;
          return 295; /* eh_set_lr_di */

        default:
          return -1;
        }

    case EH_RETURN:
      return 296; /* eh_return_internal */

    case CALL:
      x5 = XEXP (x1, 0);
      if (GET_CODE (x5) != MEM
          || GET_MODE (x5) != E_SImode)
        return -1;
      x6 = XEXP (x5, 0);
      operands[0] = x6;
      if (!call_insn_operand (operands[0], E_VOIDmode))
        return -1;
      x7 = XEXP (x1, 1);
      operands[1] = x7;
      if (
#line 2806 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(SIBLING_CALL_P (insn)))
        return 297; /* sibcall_internal */
      if (pnum_clobbers == NULL)
        return -1;
      *pnum_clobbers = 1;
      return 299; /* call_internal */

    case CONST_INT:
      if (XWINT (x1, 0) != 0L)
        return -1;
      return 301; /* nop */

    case TRAP_IF:
      x5 = XEXP (x1, 0);
      if (x5 != const_int_rtx[MAX_SAVED_CONST_INT + 1])
        return -1;
      x7 = XEXP (x1, 1);
      if (x7 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
        return -1;
      return 302; /* trap */

    case PREFETCH:
      x5 = XEXP (x1, 0);
      operands[0] = x5;
      if (!address_operand (operands[0], E_VOIDmode))
        return -1;
      x7 = XEXP (x1, 1);
      operands[1] = x7;
      if (!imm5_operand (operands[1], E_VOIDmode))
        return -1;
      x8 = XEXP (x1, 2);
      operands[2] = x8;
      if (!const_int_operand (operands[2], E_VOIDmode)
          || !
#line 3117 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOP))
        return -1;
      return 328; /* prefetch */

    default:
      return -1;
    }
}

static rtx_insn *
split_1 (rtx x1 ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15;
  rtx_insn *res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[6] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[7] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[8] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[9] = x7;
  x8 = XEXP (x2, 2);
  operands[5] = x8;
  x9 = XEXP (x2, 1);
  x10 = XEXP (x9, 0);
  switch (GET_CODE (x10))
    {
    case CONST_VECTOR:
    case REG:
    case SUBREG:
      operands[4] = x10;
      x11 = XEXP (x9, 1);
      if (GET_CODE (x11) != MULT)
        return NULL;
      switch (pattern212 (x11))
        {
        case 0:
          if (pattern303 (x2, E_VNx1QImode, E_VNx1BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_296 (insn, operands);

        case 1:
          if (pattern303 (x2, E_VNx2QImode, E_VNx2BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_297 (insn, operands);

        case 2:
          if (pattern303 (x2, E_VNx4QImode, E_VNx4BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_298 (insn, operands);

        case 3:
          if (pattern303 (x2, E_VNx8QImode, E_VNx8BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_299 (insn, operands);

        case 4:
          if (pattern303 (x2, E_VNx16QImode, E_VNx16BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_300 (insn, operands);

        case 5:
          if (pattern303 (x2, E_VNx32QImode, E_VNx32BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_301 (insn, operands);

        case 6:
          if (pattern303 (x2, E_VNx64QImode, E_VNx64BImode) != 0
              || !((
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_302 (insn, operands);

        case 7:
          if (pattern303 (x2, E_VNx1HImode, E_VNx1BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_303 (insn, operands);

        case 8:
          if (pattern303 (x2, E_VNx2HImode, E_VNx2BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_304 (insn, operands);

        case 9:
          if (pattern303 (x2, E_VNx4HImode, E_VNx4BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_305 (insn, operands);

        case 10:
          if (pattern303 (x2, E_VNx8HImode, E_VNx8BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_306 (insn, operands);

        case 11:
          if (pattern303 (x2, E_VNx16HImode, E_VNx16BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_307 (insn, operands);

        case 12:
          if (pattern303 (x2, E_VNx32HImode, E_VNx32BImode) != 0
              || !((
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_308 (insn, operands);

        case 13:
          if (pattern303 (x2, E_VNx1SImode, E_VNx1BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_309 (insn, operands);

        case 14:
          if (pattern303 (x2, E_VNx2SImode, E_VNx2BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_310 (insn, operands);

        case 15:
          if (pattern303 (x2, E_VNx4SImode, E_VNx4BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_311 (insn, operands);

        case 16:
          if (pattern303 (x2, E_VNx8SImode, E_VNx8BImode) != 0
              || !(
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_312 (insn, operands);

        case 17:
          if (pattern303 (x2, E_VNx16SImode, E_VNx16BImode) != 0
              || !((
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_313 (insn, operands);

        case 18:
          if (pattern303 (x2, E_VNx1DImode, E_VNx1BImode) != 0
              || !((
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_314 (insn, operands);

        case 19:
          if (pattern303 (x2, E_VNx2DImode, E_VNx2BImode) != 0
              || !((
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_315 (insn, operands);

        case 20:
          if (pattern303 (x2, E_VNx4DImode, E_VNx4BImode) != 0
              || !((
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_316 (insn, operands);

        case 21:
          if (pattern303 (x2, E_VNx8DImode, E_VNx8BImode) != 0
              || !((
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_317 (insn, operands);

        case 22:
          if (pattern315 (x2, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_318 (insn, operands);

        case 23:
          if (pattern315 (x2, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_319 (insn, operands);

        case 24:
          if (pattern315 (x2, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_320 (insn, operands);

        case 25:
          if (pattern315 (x2, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_321 (insn, operands);

        case 26:
          if (pattern315 (x2, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_322 (insn, operands);

        case 27:
          if (pattern315 (x2, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_323 (insn, operands);

        case 28:
          if (pattern315 (x2, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0
              || !((
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_324 (insn, operands);

        case 29:
          if (pattern315 (x2, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_325 (insn, operands);

        case 30:
          if (pattern315 (x2, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_326 (insn, operands);

        case 31:
          if (pattern315 (x2, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_327 (insn, operands);

        case 32:
          if (pattern315 (x2, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_328 (insn, operands);

        case 33:
          if (pattern315 (x2, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_329 (insn, operands);

        case 34:
          if (pattern315 (x2, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0
              || !((
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_330 (insn, operands);

        case 35:
          if (pattern315 (x2, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_331 (insn, operands);

        case 36:
          if (pattern315 (x2, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_332 (insn, operands);

        case 37:
          if (pattern315 (x2, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_333 (insn, operands);

        case 38:
          if (pattern315 (x2, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0
              || !(
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_334 (insn, operands);

        case 39:
          if (pattern315 (x2, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0
              || !((
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_335 (insn, operands);

        case 40:
          if (pattern315 (x2, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0
              || !((
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_336 (insn, operands);

        case 41:
          if (pattern315 (x2, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0
              || !((
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_337 (insn, operands);

        case 42:
          if (pattern315 (x2, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0
              || !((
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_338 (insn, operands);

        case 43:
          if (pattern315 (x2, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0
              || !((
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_339 (insn, operands);

        case 44:
          if (pattern320 (x2, E_VNx1DImode, E_VNx1BImode) != 0
              || !((
#line 5016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 5024 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_340 (insn, operands);

        case 45:
          if (pattern320 (x2, E_VNx2DImode, E_VNx2BImode) != 0
              || !((
#line 5016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 5024 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_341 (insn, operands);

        case 46:
          if (pattern320 (x2, E_VNx4DImode, E_VNx4BImode) != 0
              || !((
#line 5016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 5024 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_342 (insn, operands);

        case 47:
          if (pattern320 (x2, E_VNx8DImode, E_VNx8BImode) != 0
              || !((
#line 5016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 5024 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_343 (insn, operands);

        default:
          return NULL;
        }

    case MULT:
      x12 = XEXP (x10, 1);
      operands[3] = x12;
      x11 = XEXP (x9, 1);
      operands[4] = x11;
      x13 = XEXP (x10, 0);
      switch (GET_CODE (x13))
        {
        case REG:
        case SUBREG:
          operands[2] = x13;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1SFmode:
              if (pattern297 (x2, E_VNx1SFmode, E_VNx1BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_345 (insn, operands);

            case E_VNx2SFmode:
              if (pattern297 (x2, E_VNx2SFmode, E_VNx2BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_347 (insn, operands);

            case E_VNx4SFmode:
              if (pattern297 (x2, E_VNx4SFmode, E_VNx4BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_349 (insn, operands);

            case E_VNx8SFmode:
              if (pattern297 (x2, E_VNx8SFmode, E_VNx8BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_351 (insn, operands);

            case E_VNx16SFmode:
              if (pattern297 (x2, E_VNx16SFmode, E_VNx16BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_353 (insn, operands);

            case E_VNx1DFmode:
              if (pattern297 (x2, E_VNx1DFmode, E_VNx1BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_355 (insn, operands);

            case E_VNx2DFmode:
              if (pattern297 (x2, E_VNx2DFmode, E_VNx2BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_357 (insn, operands);

            case E_VNx4DFmode:
              if (pattern297 (x2, E_VNx4DFmode, E_VNx4BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_359 (insn, operands);

            case E_VNx8DFmode:
              if (pattern297 (x2, E_VNx8DFmode, E_VNx8BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_361 (insn, operands);

            default:
              return NULL;
            }

        case VEC_DUPLICATE:
          x14 = XEXP (x13, 0);
          operands[2] = x14;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1SFmode:
              if (pattern298 (x2, E_VNx1SFmode, E_VNx1BImode, E_SFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_363 (insn, operands);

            case E_VNx2SFmode:
              if (pattern298 (x2, E_VNx2SFmode, E_VNx2BImode, E_SFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_365 (insn, operands);

            case E_VNx4SFmode:
              if (pattern298 (x2, E_VNx4SFmode, E_VNx4BImode, E_SFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_367 (insn, operands);

            case E_VNx8SFmode:
              if (pattern298 (x2, E_VNx8SFmode, E_VNx8BImode, E_SFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_369 (insn, operands);

            case E_VNx16SFmode:
              if (pattern298 (x2, E_VNx16SFmode, E_VNx16BImode, E_SFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_371 (insn, operands);

            case E_VNx1DFmode:
              if (pattern298 (x2, E_VNx1DFmode, E_VNx1BImode, E_DFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_373 (insn, operands);

            case E_VNx2DFmode:
              if (pattern298 (x2, E_VNx2DFmode, E_VNx2BImode, E_DFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_375 (insn, operands);

            case E_VNx4DFmode:
              if (pattern298 (x2, E_VNx4DFmode, E_VNx4BImode, E_DFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_377 (insn, operands);

            case E_VNx8DFmode:
              if (pattern298 (x2, E_VNx8DFmode, E_VNx8BImode, E_DFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_379 (insn, operands);

            default:
              return NULL;
            }

        default:
          return NULL;
        }

    case NEG:
      x13 = XEXP (x10, 0);
      if (GET_CODE (x13) != MULT)
        return NULL;
      x15 = XEXP (x13, 1);
      operands[3] = x15;
      x11 = XEXP (x9, 1);
      operands[4] = x11;
      switch (pattern283 (x2))
        {
        case 0:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_381 (insn, operands);

        case 1:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_383 (insn, operands);

        case 2:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_385 (insn, operands);

        case 3:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_387 (insn, operands);

        case 4:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_389 (insn, operands);

        case 5:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_391 (insn, operands);

        case 6:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_393 (insn, operands);

        case 7:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_395 (insn, operands);

        case 8:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_397 (insn, operands);

        case 9:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_399 (insn, operands);

        case 10:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_401 (insn, operands);

        case 11:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_403 (insn, operands);

        case 12:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_405 (insn, operands);

        case 13:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_407 (insn, operands);

        case 14:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_409 (insn, operands);

        case 15:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_411 (insn, operands);

        case 16:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_413 (insn, operands);

        case 17:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_415 (insn, operands);

        default:
          return NULL;
        }

    default:
      return NULL;
    }
}

static rtx_insn *
split_2 (rtx x1 ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15;
  rtx_insn *res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  x4 = XVECEXP (x3, 0, 1);
  operands[6] = x4;
  x5 = XVECEXP (x3, 0, 2);
  operands[7] = x5;
  x6 = XVECEXP (x3, 0, 3);
  operands[8] = x6;
  x7 = XVECEXP (x3, 0, 4);
  operands[9] = x7;
  x8 = XEXP (x2, 1);
  x9 = XEXP (x8, 1);
  operands[4] = x9;
  x10 = XEXP (x2, 2);
  operands[5] = x10;
  x11 = XEXP (x8, 0);
  switch (GET_CODE (x11))
    {
    case MULT:
      x12 = XEXP (x11, 1);
      operands[3] = x12;
      x13 = XEXP (x11, 0);
      switch (GET_CODE (x13))
        {
        case REG:
        case SUBREG:
          operands[2] = x13;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1QImode:
              if (pattern297 (x2, E_VNx1QImode, E_VNx1BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_248 (insn, operands);

            case E_VNx2QImode:
              if (pattern297 (x2, E_VNx2QImode, E_VNx2BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_249 (insn, operands);

            case E_VNx4QImode:
              if (pattern297 (x2, E_VNx4QImode, E_VNx4BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_250 (insn, operands);

            case E_VNx8QImode:
              if (pattern297 (x2, E_VNx8QImode, E_VNx8BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_251 (insn, operands);

            case E_VNx16QImode:
              if (pattern297 (x2, E_VNx16QImode, E_VNx16BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_252 (insn, operands);

            case E_VNx32QImode:
              if (pattern297 (x2, E_VNx32QImode, E_VNx32BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_253 (insn, operands);

            case E_VNx64QImode:
              if (pattern297 (x2, E_VNx64QImode, E_VNx64BImode) != 0
                  || !((
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_254 (insn, operands);

            case E_VNx1HImode:
              if (pattern297 (x2, E_VNx1HImode, E_VNx1BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_255 (insn, operands);

            case E_VNx2HImode:
              if (pattern297 (x2, E_VNx2HImode, E_VNx2BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_256 (insn, operands);

            case E_VNx4HImode:
              if (pattern297 (x2, E_VNx4HImode, E_VNx4BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_257 (insn, operands);

            case E_VNx8HImode:
              if (pattern297 (x2, E_VNx8HImode, E_VNx8BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_258 (insn, operands);

            case E_VNx16HImode:
              if (pattern297 (x2, E_VNx16HImode, E_VNx16BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_259 (insn, operands);

            case E_VNx32HImode:
              if (pattern297 (x2, E_VNx32HImode, E_VNx32BImode) != 0
                  || !((
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_260 (insn, operands);

            case E_VNx1SImode:
              if (pattern297 (x2, E_VNx1SImode, E_VNx1BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_261 (insn, operands);

            case E_VNx2SImode:
              if (pattern297 (x2, E_VNx2SImode, E_VNx2BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_262 (insn, operands);

            case E_VNx4SImode:
              if (pattern297 (x2, E_VNx4SImode, E_VNx4BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_263 (insn, operands);

            case E_VNx8SImode:
              if (pattern297 (x2, E_VNx8SImode, E_VNx8BImode) != 0
                  || !(
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_264 (insn, operands);

            case E_VNx16SImode:
              if (pattern297 (x2, E_VNx16SImode, E_VNx16BImode) != 0
                  || !((
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_265 (insn, operands);

            case E_VNx1DImode:
              if (pattern297 (x2, E_VNx1DImode, E_VNx1BImode) != 0
                  || !((
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_266 (insn, operands);

            case E_VNx2DImode:
              if (pattern297 (x2, E_VNx2DImode, E_VNx2BImode) != 0
                  || !((
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_267 (insn, operands);

            case E_VNx4DImode:
              if (pattern297 (x2, E_VNx4DImode, E_VNx4BImode) != 0
                  || !((
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_268 (insn, operands);

            case E_VNx8DImode:
              if (pattern297 (x2, E_VNx8DImode, E_VNx8BImode) != 0
                  || !((
#line 4307 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4317 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_269 (insn, operands);

            case E_VNx1SFmode:
              if (pattern297 (x2, E_VNx1SFmode, E_VNx1BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_344 (insn, operands);

            case E_VNx2SFmode:
              if (pattern297 (x2, E_VNx2SFmode, E_VNx2BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_346 (insn, operands);

            case E_VNx4SFmode:
              if (pattern297 (x2, E_VNx4SFmode, E_VNx4BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_348 (insn, operands);

            case E_VNx8SFmode:
              if (pattern297 (x2, E_VNx8SFmode, E_VNx8BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_350 (insn, operands);

            case E_VNx16SFmode:
              if (pattern297 (x2, E_VNx16SFmode, E_VNx16BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_352 (insn, operands);

            case E_VNx1DFmode:
              if (pattern297 (x2, E_VNx1DFmode, E_VNx1BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_354 (insn, operands);

            case E_VNx2DFmode:
              if (pattern297 (x2, E_VNx2DFmode, E_VNx2BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_356 (insn, operands);

            case E_VNx4DFmode:
              if (pattern297 (x2, E_VNx4DFmode, E_VNx4BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_358 (insn, operands);

            case E_VNx8DFmode:
              if (pattern297 (x2, E_VNx8DFmode, E_VNx8BImode) != 0
                  || !((
#line 5607 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_360 (insn, operands);

            default:
              return NULL;
            }

        case VEC_DUPLICATE:
          x14 = XEXP (x13, 0);
          switch (pattern219 (x14))
            {
            case 0:
              if (pattern298 (x2, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_270 (insn, operands);

            case 1:
              if (pattern298 (x2, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_271 (insn, operands);

            case 2:
              if (pattern298 (x2, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_272 (insn, operands);

            case 3:
              if (pattern298 (x2, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_273 (insn, operands);

            case 4:
              if (pattern298 (x2, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_274 (insn, operands);

            case 5:
              if (pattern298 (x2, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_275 (insn, operands);

            case 6:
              if (pattern298 (x2, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0
                  || !((
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_276 (insn, operands);

            case 7:
              if (pattern298 (x2, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_277 (insn, operands);

            case 8:
              if (pattern298 (x2, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_278 (insn, operands);

            case 9:
              if (pattern298 (x2, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_279 (insn, operands);

            case 10:
              if (pattern298 (x2, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_280 (insn, operands);

            case 11:
              if (pattern298 (x2, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_281 (insn, operands);

            case 12:
              if (pattern298 (x2, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0
                  || !((
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_282 (insn, operands);

            case 13:
              if (pattern298 (x2, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_283 (insn, operands);

            case 14:
              if (pattern298 (x2, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_284 (insn, operands);

            case 15:
              if (pattern298 (x2, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_285 (insn, operands);

            case 16:
              if (pattern298 (x2, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0
                  || !(
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_286 (insn, operands);

            case 17:
              if (pattern298 (x2, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0
                  || !((
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_287 (insn, operands);

            case 18:
              if (pattern298 (x2, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0
                  || !((
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_288 (insn, operands);

            case 19:
              if (pattern298 (x2, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0
                  || !((
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_289 (insn, operands);

            case 20:
              if (pattern298 (x2, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0
                  || !((
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_290 (insn, operands);

            case 21:
              if (pattern298 (x2, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0
                  || !((
#line 4446 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_291 (insn, operands);

            case 22:
              if (pattern298 (x2, E_VNx1SFmode, E_VNx1BImode, E_SFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_362 (insn, operands);

            case 23:
              if (pattern298 (x2, E_VNx2SFmode, E_VNx2BImode, E_SFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_364 (insn, operands);

            case 24:
              if (pattern298 (x2, E_VNx4SFmode, E_VNx4BImode, E_SFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_366 (insn, operands);

            case 25:
              if (pattern298 (x2, E_VNx8SFmode, E_VNx8BImode, E_SFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_368 (insn, operands);

            case 26:
              if (pattern298 (x2, E_VNx16SFmode, E_VNx16BImode, E_SFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_370 (insn, operands);

            case 27:
              if (pattern298 (x2, E_VNx1DFmode, E_VNx1BImode, E_DFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_372 (insn, operands);

            case 28:
              if (pattern298 (x2, E_VNx2DFmode, E_VNx2BImode, E_DFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_374 (insn, operands);

            case 29:
              if (pattern298 (x2, E_VNx4DFmode, E_VNx4BImode, E_DFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_376 (insn, operands);

            case 30:
              if (pattern298 (x2, E_VNx8DFmode, E_VNx8BImode, E_DFmode) != 0
                  || !((
#line 5728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5734 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_378 (insn, operands);

            case 31:
              if (pattern319 (x2, E_VNx1DImode, E_VNx1BImode) != 0
                  || !((
#line 4595 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4603 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_292 (insn, operands);

            case 32:
              if (pattern319 (x2, E_VNx2DImode, E_VNx2BImode) != 0
                  || !((
#line 4595 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4603 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_293 (insn, operands);

            case 33:
              if (pattern319 (x2, E_VNx4DImode, E_VNx4BImode) != 0
                  || !((
#line 4595 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4603 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_294 (insn, operands);

            case 34:
              if (pattern319 (x2, E_VNx8DImode, E_VNx8BImode) != 0
                  || !((
#line 4595 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4603 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
                return NULL;
              return gen_split_295 (insn, operands);

            default:
              return NULL;
            }

        default:
          return NULL;
        }

    case NEG:
      x13 = XEXP (x11, 0);
      if (GET_CODE (x13) != MULT)
        return NULL;
      x15 = XEXP (x13, 1);
      operands[3] = x15;
      switch (pattern283 (x2))
        {
        case 0:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_380 (insn, operands);

        case 1:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_382 (insn, operands);

        case 2:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_384 (insn, operands);

        case 3:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_386 (insn, operands);

        case 4:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_388 (insn, operands);

        case 5:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_390 (insn, operands);

        case 6:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_392 (insn, operands);

        case 7:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_394 (insn, operands);

        case 8:
          if (!((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_396 (insn, operands);

        case 9:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_398 (insn, operands);

        case 10:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_400 (insn, operands);

        case 11:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_402 (insn, operands);

        case 12:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_404 (insn, operands);

        case 13:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_406 (insn, operands);

        case 14:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_408 (insn, operands);

        case 15:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_410 (insn, operands);

        case 16:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_412 (insn, operands);

        case 17:
          if (!((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))))
            return NULL;
          return gen_split_414 (insn, operands);

        default:
          return NULL;
        }

    default:
      return NULL;
    }
}

static rtx_insn *
split_3 (rtx x1 ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11;
  rtx_insn *res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  x3 = XEXP (x2, 0);
  if (GET_CODE (x3) != UNSPEC
      || XINT (x3, 1) != 68)
    return NULL;
  switch (XVECLEN (x3, 0))
    {
    case 7:
      if (pattern80 (x3) != 0)
        return NULL;
      x4 = XEXP (x2, 1);
      switch (GET_CODE (x4))
        {
        case CONST_VECTOR:
        case REG:
        case SUBREG:
        case MEM:
          switch (pattern142 (x2))
            {
            case 0:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1QImode)
   && register_operand (operands[3], VNx1QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_188 (insn, operands);

            case 1:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2QImode)
   && register_operand (operands[3], VNx2QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_189 (insn, operands);

            case 2:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4QImode)
   && register_operand (operands[3], VNx4QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_190 (insn, operands);

            case 3:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8QImode)
   && register_operand (operands[3], VNx8QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_191 (insn, operands);

            case 4:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16QImode)
   && register_operand (operands[3], VNx16QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_192 (insn, operands);

            case 5:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx32QImode)
   && register_operand (operands[3], VNx32QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_193 (insn, operands);

            case 6:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx64QImode)
   && register_operand (operands[3], VNx64QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_194 (insn, operands);

            case 7:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1HImode)
   && register_operand (operands[3], VNx1HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_195 (insn, operands);

            case 8:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2HImode)
   && register_operand (operands[3], VNx2HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_196 (insn, operands);

            case 9:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4HImode)
   && register_operand (operands[3], VNx4HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_197 (insn, operands);

            case 10:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8HImode)
   && register_operand (operands[3], VNx8HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_198 (insn, operands);

            case 11:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16HImode)
   && register_operand (operands[3], VNx16HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_199 (insn, operands);

            case 12:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx32HImode)
   && register_operand (operands[3], VNx32HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_200 (insn, operands);

            case 13:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1SImode)
   && register_operand (operands[3], VNx1SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_201 (insn, operands);

            case 14:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2SImode)
   && register_operand (operands[3], VNx2SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_202 (insn, operands);

            case 15:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4SImode)
   && register_operand (operands[3], VNx4SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_203 (insn, operands);

            case 16:
              if (!(
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8SImode)
   && register_operand (operands[3], VNx8SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_204 (insn, operands);

            case 17:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16SImode)
   && register_operand (operands[3], VNx16SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_205 (insn, operands);

            case 18:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1DImode)
   && register_operand (operands[3], VNx1DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_206 (insn, operands);

            case 19:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2DImode)
   && register_operand (operands[3], VNx2DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_207 (insn, operands);

            case 20:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4DImode)
   && register_operand (operands[3], VNx4DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_208 (insn, operands);

            case 21:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8DImode)
   && register_operand (operands[3], VNx8DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_209 (insn, operands);

            case 22:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1SFmode)
   && register_operand (operands[3], VNx1SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_210 (insn, operands);

            case 23:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2SFmode)
   && register_operand (operands[3], VNx2SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_211 (insn, operands);

            case 24:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4SFmode)
   && register_operand (operands[3], VNx4SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_212 (insn, operands);

            case 25:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8SFmode)
   && register_operand (operands[3], VNx8SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_213 (insn, operands);

            case 26:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16SFmode)
   && register_operand (operands[3], VNx16SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_214 (insn, operands);

            case 27:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1DFmode)
   && register_operand (operands[3], VNx1DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_215 (insn, operands);

            case 28:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2DFmode)
   && register_operand (operands[3], VNx2DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_216 (insn, operands);

            case 29:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4DFmode)
   && register_operand (operands[3], VNx4DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_217 (insn, operands);

            case 30:
              if (!((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8DFmode)
   && register_operand (operands[3], VNx8DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)))
                return NULL;
              return gen_split_218 (insn, operands);

            default:
              return NULL;
            }

        case VEC_DUPLICATE:
          x5 = XVECEXP (x3, 0, 1);
          operands[4] = x5;
          x6 = XVECEXP (x3, 0, 2);
          operands[5] = x6;
          x7 = XVECEXP (x3, 0, 3);
          operands[6] = x7;
          x8 = XVECEXP (x3, 0, 4);
          operands[7] = x8;
          x9 = XEXP (x4, 0);
          operands[3] = x9;
          x10 = XEXP (x2, 2);
          operands[2] = x10;
          switch (GET_MODE (operands[0]))
            {
            case E_VNx1QImode:
              if (pattern238 (x2, E_VNx1QImode, E_VNx1BImode, E_QImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_226 (insn, operands);

            case E_VNx2QImode:
              if (pattern238 (x2, E_VNx2QImode, E_VNx2BImode, E_QImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_227 (insn, operands);

            case E_VNx4QImode:
              if (pattern238 (x2, E_VNx4QImode, E_VNx4BImode, E_QImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_228 (insn, operands);

            case E_VNx8QImode:
              if (pattern238 (x2, E_VNx8QImode, E_VNx8BImode, E_QImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_229 (insn, operands);

            case E_VNx16QImode:
              if (pattern238 (x2, E_VNx16QImode, E_VNx16BImode, E_QImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_230 (insn, operands);

            case E_VNx32QImode:
              if (pattern238 (x2, E_VNx32QImode, E_VNx32BImode, E_QImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_231 (insn, operands);

            case E_VNx64QImode:
              if (pattern238 (x2, E_VNx64QImode, E_VNx64BImode, E_QImode) != 0
                  || !(
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return NULL;
              return gen_split_232 (insn, operands);

            case E_VNx1HImode:
              if (pattern238 (x2, E_VNx1HImode, E_VNx1BImode, E_HImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], HImode)
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_233 (insn, operands);

            case E_VNx2HImode:
              if (pattern238 (x2, E_VNx2HImode, E_VNx2BImode, E_HImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], HImode)
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_234 (insn, operands);

            case E_VNx4HImode:
              if (pattern238 (x2, E_VNx4HImode, E_VNx4BImode, E_HImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], HImode)
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_235 (insn, operands);

            case E_VNx8HImode:
              if (pattern238 (x2, E_VNx8HImode, E_VNx8BImode, E_HImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], HImode)
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_236 (insn, operands);

            case E_VNx16HImode:
              if (pattern238 (x2, E_VNx16HImode, E_VNx16BImode, E_HImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], HImode)
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_237 (insn, operands);

            case E_VNx32HImode:
              if (pattern238 (x2, E_VNx32HImode, E_VNx32BImode, E_HImode) != 0
                  || !(
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], HImode)
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return NULL;
              return gen_split_238 (insn, operands);

            case E_VNx1SImode:
              if (pattern238 (x2, E_VNx1SImode, E_VNx1BImode, E_SImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], SImode)
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_239 (insn, operands);

            case E_VNx2SImode:
              if (pattern238 (x2, E_VNx2SImode, E_VNx2BImode, E_SImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], SImode)
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_240 (insn, operands);

            case E_VNx4SImode:
              if (pattern238 (x2, E_VNx4SImode, E_VNx4BImode, E_SImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], SImode)
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_241 (insn, operands);

            case E_VNx8SImode:
              if (pattern238 (x2, E_VNx8SImode, E_VNx8BImode, E_SImode) != 0
                  || !
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], SImode)
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)))
                return NULL;
              return gen_split_242 (insn, operands);

            case E_VNx16SImode:
              if (pattern238 (x2, E_VNx16SImode, E_VNx16BImode, E_SImode) != 0
                  || !(
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], SImode)
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                return NULL;
              return gen_split_243 (insn, operands);

            case E_VNx1DImode:
              if (pattern238 (x2, E_VNx1DImode, E_VNx1BImode, E_DImode) != 0
                  || !(
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], DImode)
  && GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return NULL;
              return gen_split_244 (insn, operands);

            case E_VNx2DImode:
              if (pattern238 (x2, E_VNx2DImode, E_VNx2BImode, E_DImode) != 0
                  || !(
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], DImode)
  && GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return NULL;
              return gen_split_245 (insn, operands);

            case E_VNx4DImode:
              if (pattern238 (x2, E_VNx4DImode, E_VNx4BImode, E_DImode) != 0
                  || !(
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], DImode)
  && GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return NULL;
              return gen_split_246 (insn, operands);

            case E_VNx8DImode:
              if (pattern238 (x2, E_VNx8DImode, E_VNx8BImode, E_DImode) != 0
                  || !(
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], DImode)
  && GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                return NULL;
              return gen_split_247 (insn, operands);

            default:
              return NULL;
            }

        case PLUS:
          return split_2 (x1, insn);

        case MINUS:
          return split_1 (x1, insn);

        default:
          return NULL;
        }

    case 5:
      if (pattern81 (x3) != 0)
        return NULL;
      x11 = XVECEXP (x3, 0, 0);
      operands[1] = x11;
      x5 = XVECEXP (x3, 0, 1);
      operands[4] = x5;
      if (!vector_length_operand (operands[4], E_VOIDmode))
        return NULL;
      x6 = XVECEXP (x3, 0, 2);
      operands[5] = x6;
      if (!const_int_operand (operands[5], E_VOIDmode))
        return NULL;
      x4 = XEXP (x2, 1);
      operands[3] = x4;
      x10 = XEXP (x2, 2);
      operands[2] = x10;
      switch (GET_MODE (operands[0]))
        {
        case E_VNx1BImode:
          if (pattern211 (x2, E_VNx1BImode) != 0
              || !(
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1BImode)
   && register_operand (operands[3], VNx1BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)))
            return NULL;
          return gen_split_219 (insn, operands);

        case E_VNx2BImode:
          if (pattern211 (x2, E_VNx2BImode) != 0
              || !(
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2BImode)
   && register_operand (operands[3], VNx2BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)))
            return NULL;
          return gen_split_220 (insn, operands);

        case E_VNx4BImode:
          if (pattern211 (x2, E_VNx4BImode) != 0
              || !(
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4BImode)
   && register_operand (operands[3], VNx4BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)))
            return NULL;
          return gen_split_221 (insn, operands);

        case E_VNx8BImode:
          if (pattern211 (x2, E_VNx8BImode) != 0
              || !(
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8BImode)
   && register_operand (operands[3], VNx8BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)))
            return NULL;
          return gen_split_222 (insn, operands);

        case E_VNx16BImode:
          if (pattern211 (x2, E_VNx16BImode) != 0
              || !(
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16BImode)
   && register_operand (operands[3], VNx16BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)))
            return NULL;
          return gen_split_223 (insn, operands);

        case E_VNx32BImode:
          if (pattern211 (x2, E_VNx32BImode) != 0
              || !(
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx32BImode)
   && register_operand (operands[3], VNx32BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)))
            return NULL;
          return gen_split_224 (insn, operands);

        case E_VNx64BImode:
          if (pattern211 (x2, E_VNx64BImode) != 0
              || !((
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx64BImode)
   && register_operand (operands[3], VNx64BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)))
            return NULL;
          return gen_split_225 (insn, operands);

        default:
          return NULL;
        }

    default:
      return NULL;
    }
}

static rtx_insn *
split_4 (rtx x1 ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2;
  rtx_insn *res ATTRIBUTE_UNUSED;
  x2 = XEXP (x1, 1);
  operands[1] = x2;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (register_operand (operands[0], E_SImode)
          && splittable_const_int_operand (operands[1], E_SImode)
          && (
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!(p2m1_shift_operand (operands[1], SImode)
     || high_mask_shift_operand (operands[1], SImode))) && 
#line 1697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
        return gen_split_14 (insn, operands);
      break;

    case E_DImode:
      if (register_operand (operands[0], E_DImode)
          && splittable_const_int_operand (operands[1], E_DImode)
          && ((
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!(p2m1_shift_operand (operands[1], DImode)
     || high_mask_shift_operand (operands[1], DImode))) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 1697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
        return gen_split_15 (insn, operands);
      if (nonimmediate_operand (operands[0], E_DImode)
          && move_operand (operands[1], E_DImode)
          && 
#line 1908 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed
   && riscv_split_64bit_move_p (operands[0], operands[1])))
        return gen_split_16 (insn, operands);
      break;

    case E_DFmode:
      if (nonimmediate_operand (operands[0], E_DFmode)
          && move_operand (operands[1], E_DFmode)
          && 
#line 1908 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed
   && riscv_split_64bit_move_p (operands[0], operands[1])))
        return gen_split_17 (insn, operands);
      break;

    default:
      break;
    }
  if (GET_CODE (x2) != SUBREG)
    return NULL;
  switch (pattern58 (x2))
    {
    case 0:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_90 (insn, operands);

    case 1:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_91 (insn, operands);

    case 2:
      if (!(
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_115 (insn, operands);

    case 3:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_92 (insn, operands);

    case 4:
      if (!(
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_116 (insn, operands);

    case 5:
      if (!(
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_134 (insn, operands);

    case 6:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_93 (insn, operands);

    case 7:
      if (!(
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_117 (insn, operands);

    case 8:
      if (!(
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_135 (insn, operands);

    case 9:
      if (!(
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 467 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_147 (insn, operands);

    case 10:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_94 (insn, operands);

    case 11:
      if (!(
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_118 (insn, operands);

    case 12:
      if (!(
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_136 (insn, operands);

    case 13:
      if (!(
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 467 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_148 (insn, operands);

    case 14:
      if (!(
#line 478 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 480 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_154 (insn, operands);

    case 15:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_95 (insn, operands);

    case 16:
      if (!(
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_119 (insn, operands);

    case 17:
      if (!(
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_137 (insn, operands);

    case 18:
      if (!(
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 467 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_149 (insn, operands);

    case 19:
      if (!(
#line 478 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 480 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_155 (insn, operands);

    case 20:
      if (!(
#line 491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 493 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_157 (insn, operands);

    case 21:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_96 (insn, operands);

    case 22:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_97 (insn, operands);

    case 23:
      if (!(
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_120 (insn, operands);

    case 24:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_98 (insn, operands);

    case 25:
      if (!(
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_121 (insn, operands);

    case 26:
      if (!(
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_138 (insn, operands);

    case 27:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_99 (insn, operands);

    case 28:
      if (!(
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_122 (insn, operands);

    case 29:
      if (!(
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_139 (insn, operands);

    case 30:
      if (!(
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 467 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_150 (insn, operands);

    case 31:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_100 (insn, operands);

    case 32:
      if (!(
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_123 (insn, operands);

    case 33:
      if (!(
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_140 (insn, operands);

    case 34:
      if (!(
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 467 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_151 (insn, operands);

    case 35:
      if (!(
#line 478 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 480 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_156 (insn, operands);

    case 36:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_101 (insn, operands);

    case 37:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_102 (insn, operands);

    case 38:
      if (!(
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_124 (insn, operands);

    case 39:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_103 (insn, operands);

    case 40:
      if (!(
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_125 (insn, operands);

    case 41:
      if (!(
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_141 (insn, operands);

    case 42:
      if (!(
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_104 (insn, operands);

    case 43:
      if (!(
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_126 (insn, operands);

    case 44:
      if (!(
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_142 (insn, operands);

    case 45:
      if (!(
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 467 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_152 (insn, operands);

    case 46:
      if (!((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 165 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_105 (insn, operands);

    case 47:
      if (!((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 165 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_106 (insn, operands);

    case 48:
      if (!((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 180 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_127 (insn, operands);

    case 49:
      if (!((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 166 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_107 (insn, operands);

    case 50:
      if (!((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 180 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_128 (insn, operands);

    case 51:
      if (!((
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 192 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_143 (insn, operands);

    case 52:
      if (!((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 167 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_108 (insn, operands);

    case 53:
      if (!((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 168 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_109 (insn, operands);

    case 54:
      if (!((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 181 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_129 (insn, operands);

    case 55:
      if (!((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 169 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_110 (insn, operands);

    case 56:
      if (!((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 182 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_130 (insn, operands);

    case 57:
      if (!((
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 193 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_144 (insn, operands);

    case 58:
      if (!((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_111 (insn, operands);

    case 59:
      if (!((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 183 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_131 (insn, operands);

    case 60:
      if (!((
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 194 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_145 (insn, operands);

    case 61:
      if (!((
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 202 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 467 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_153 (insn, operands);

    case 62:
      if (!((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 171 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_112 (insn, operands);

    case 63:
      if (!((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 172 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_113 (insn, operands);

    case 64:
      if (!((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 184 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_132 (insn, operands);

    case 65:
      if (!((
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 173 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_114 (insn, operands);

    case 66:
      if (!((
#line 439 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 185 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_133 (insn, operands);

    case 67:
      if (!((
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 195 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
        return NULL;
      return gen_split_146 (insn, operands);

    default:
      return NULL;
    }
}

static rtx_insn *
split_5 (rtx x1 ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5;
  rtx_insn *res ATTRIBUTE_UNUSED;
  x2 = XVECEXP (x1, 0, 0);
  x3 = XEXP (x2, 1);
  operands[1] = x3;
  x4 = XVECEXP (x1, 0, 1);
  x5 = XEXP (x4, 0);
  operands[2] = x5;
  switch (GET_MODE (operands[0]))
    {
    case E_SImode:
      if (!register_operand (operands[0], E_SImode)
          || !register_operand (operands[2], E_SImode))
        return NULL;
      if (splittable_const_int_operand (operands[1], E_SImode))
        return gen_split_10 (insn, operands);
      if (!(
#line 1680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
        return NULL;
      return gen_split_12 (insn, operands);

    case E_DImode:
      if (!register_operand (operands[0], E_DImode)
          || !register_operand (operands[2], E_DImode))
        return NULL;
      if (splittable_const_int_operand (operands[1], E_DImode)
          && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
        return gen_split_11 (insn, operands);
      if (!(
#line 1680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
        return NULL;
      return gen_split_13 (insn, operands);

    case E_VNx1QImode:
      switch (pattern93 (E_VNx1QImode))
        {
        case 0:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_158 (insn, operands);

        case 1:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_159 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx2QImode:
      switch (pattern93 (E_VNx2QImode))
        {
        case 0:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_160 (insn, operands);

        case 1:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_161 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx4QImode:
      switch (pattern93 (E_VNx4QImode))
        {
        case 0:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_162 (insn, operands);

        case 1:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 390 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_163 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx1HImode:
      switch (pattern93 (E_VNx1HImode))
        {
        case 0:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_164 (insn, operands);

        case 1:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_165 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx2HImode:
      switch (pattern93 (E_VNx2HImode))
        {
        case 0:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 391 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_166 (insn, operands);

        case 1:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 391 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_167 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx1SImode:
      switch (pattern93 (E_VNx1SImode))
        {
        case 0:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_168 (insn, operands);

        case 1:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_169 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx1SFmode:
      switch (pattern93 (E_VNx1SFmode))
        {
        case 0:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_170 (insn, operands);

        case 1:
          if (!((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_171 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx1BImode:
      switch (pattern93 (E_VNx1BImode))
        {
        case 0:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_172 (insn, operands);

        case 1:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_179 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx2BImode:
      switch (pattern93 (E_VNx2BImode))
        {
        case 0:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_173 (insn, operands);

        case 1:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_180 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx4BImode:
      switch (pattern93 (E_VNx4BImode))
        {
        case 0:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_174 (insn, operands);

        case 1:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_181 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx8BImode:
      switch (pattern93 (E_VNx8BImode))
        {
        case 0:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_175 (insn, operands);

        case 1:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_182 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx16BImode:
      switch (pattern93 (E_VNx16BImode))
        {
        case 0:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_176 (insn, operands);

        case 1:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_183 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx32BImode:
      switch (pattern93 (E_VNx32BImode))
        {
        case 0:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_177 (insn, operands);

        case 1:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_184 (insn, operands);

        default:
          return NULL;
        }

    case E_VNx64BImode:
      switch (pattern93 (E_VNx64BImode))
        {
        case 0:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_178 (insn, operands);

        case 1:
          if (!((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed)))
            return NULL;
          return gen_split_185 (insn, operands);

        default:
          return NULL;
        }

    default:
      return NULL;
    }
}

static rtx_insn *
split_6 (rtx x1 ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15, x16, x17;
  rtx x18, x19, x20, x21;
  rtx_insn *res ATTRIBUTE_UNUSED;
  switch (XVECLEN (x1, 0))
    {
    case 2:
      x2 = XVECEXP (x1, 0, 1);
      if (GET_CODE (x2) != CLOBBER)
        return NULL;
      x3 = XVECEXP (x1, 0, 0);
      switch (GET_CODE (x3))
        {
        case SET:
          x4 = XEXP (x3, 0);
          operands[0] = x4;
          res = split_5 (x1, insn);
          if (res != NULL_RTX)
            return res;
          x5 = XEXP (x3, 1);
          switch (GET_CODE (x5))
            {
            case AND:
              operands[0] = x4;
              x6 = XEXP (x5, 0);
              switch (GET_CODE (x6))
                {
                case REG:
                case SUBREG:
                  operands[1] = x6;
                  x7 = XEXP (x5, 1);
                  operands[2] = x7;
                  x8 = XEXP (x2, 0);
                  operands[3] = x8;
                  switch (GET_MODE (operands[0]))
                    {
                    case E_SImode:
                      if (!register_operand (operands[0], E_SImode)
                          || GET_MODE (x5) != E_SImode
                          || !register_operand (operands[1], E_SImode)
                          || !p2m1_shift_operand (operands[2], E_SImode)
                          || !register_operand (operands[3], E_SImode))
                        return NULL;
                      return gen_split_36 (insn, operands);

                    case E_DImode:
                      if (!register_operand (operands[0], E_DImode)
                          || GET_MODE (x5) != E_DImode
                          || !register_operand (operands[1], E_DImode)
                          || !register_operand (operands[3], E_DImode))
                        return NULL;
                      if (p2m1_shift_operand (operands[2], E_DImode)
                          && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
                        return gen_split_37 (insn, operands);
                      if (!high_mask_shift_operand (operands[2], E_DImode)
                          || !
#line 2217 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT))
                        return NULL;
                      return gen_split_38 (insn, operands);

                    default:
                      return NULL;
                    }

                case ASHIFT:
                  if (GET_MODE (x6) != E_DImode
                      || !register_operand (operands[0], E_DImode)
                      || GET_MODE (x5) != E_DImode
                      || pattern112 (x1) != 0
                      || !(
#line 2236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)) && 
#line 2239 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                    return NULL;
                  return gen_split_39 (insn, operands);

                case SIGN_EXTRACT:
                  x9 = XEXP (x6, 1);
                  if (x9 != const_int_rtx[MAX_SAVED_CONST_INT + 1])
                    return NULL;
                  x10 = XEXP (x6, 0);
                  operands[1] = x10;
                  x11 = XEXP (x6, 2);
                  operands[2] = x11;
                  if (!immediate_operand (operands[2], E_VOIDmode))
                    return NULL;
                  x7 = XEXP (x5, 1);
                  operands[3] = x7;
                  x8 = XEXP (x2, 0);
                  operands[4] = x8;
                  switch (GET_MODE (operands[0]))
                    {
                    case E_SImode:
                      if (pattern135 (x5, E_SImode) != 0)
                        return NULL;
                      if ((
#line 2363 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                        return gen_split_55 (insn, operands);
                      if (!(
#line 2376 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                        return NULL;
                      return gen_split_57 (insn, operands);

                    case E_DImode:
                      if (pattern135 (x5, E_DImode) != 0)
                        return NULL;
                      if ((
#line 2363 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                        return gen_split_56 (insn, operands);
                      if (!(
#line 2376 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                        return NULL;
                      return gen_split_58 (insn, operands);

                    default:
                      return NULL;
                    }

                case NEG:
                  if (GET_MODE (x6) != E_DImode)
                    return NULL;
                  x10 = XEXP (x6, 0);
                  if (GET_CODE (x10) != GE
                      || GET_MODE (x10) != E_DImode)
                    return NULL;
                  x12 = XEXP (x10, 1);
                  if (x12 != const_int_rtx[MAX_SAVED_CONST_INT + 0]
                      || !register_operand (operands[0], E_DImode)
                      || GET_MODE (x5) != E_DImode)
                    return NULL;
                  x13 = XEXP (x10, 0);
                  operands[1] = x13;
                  if (!register_operand (operands[1], E_DImode))
                    return NULL;
                  x7 = XEXP (x5, 1);
                  operands[2] = x7;
                  if (!register_operand (operands[2], E_DImode))
                    return NULL;
                  x8 = XEXP (x2, 0);
                  operands[3] = x8;
                  if (!register_operand (operands[3], E_DImode)
                      || !
#line 228 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB))
                    return NULL;
                  return gen_split_70 (insn, operands);

                default:
                  return NULL;
                }

            case IF_THEN_ELSE:
              if (pattern76 (x3) != 0)
                return NULL;
              switch (pattern116 (x1))
                {
                case 0:
                  if (shifted_const_arith_operand (operands[3], E_VOIDmode))
                    {
                      switch (GET_MODE (operands[4]))
                        {
                        case E_SImode:
                          if (scratch_operand (operands[4], E_SImode)
                              && ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                            return gen_split_40 (insn, operands);
                          break;

                        case E_DImode:
                          if (scratch_operand (operands[4], E_DImode)
                              && ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                            return gen_split_43 (insn, operands);
                          break;

                        default:
                          break;
                        }
                    }
                  if (!consecutive_bits_operand (operands[3], E_VOIDmode))
                    return NULL;
                  switch (GET_MODE (operands[4]))
                    {
                    case E_SImode:
                      if (!scratch_operand (operands[4], E_SImode)
                          || !((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                        return NULL;
                      return gen_split_47 (insn, operands);

                    case E_DImode:
                      if (!scratch_operand (operands[4], E_DImode)
                          || !((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                        return NULL;
                      return gen_split_51 (insn, operands);

                    default:
                      return NULL;
                    }

                case 1:
                  if (shifted_const_arith_operand (operands[3], E_VOIDmode))
                    {
                      switch (GET_MODE (operands[4]))
                        {
                        case E_SImode:
                          if (scratch_operand (operands[4], E_SImode)
                              && ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                            return gen_split_41 (insn, operands);
                          break;

                        case E_DImode:
                          if (scratch_operand (operands[4], E_DImode)
                              && ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                            return gen_split_44 (insn, operands);
                          break;

                        default:
                          break;
                        }
                    }
                  if (!consecutive_bits_operand (operands[3], E_VOIDmode))
                    return NULL;
                  switch (GET_MODE (operands[4]))
                    {
                    case E_SImode:
                      if (!scratch_operand (operands[4], E_SImode)
                          || !((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                        return NULL;
                      return gen_split_48 (insn, operands);

                    case E_DImode:
                      if (!scratch_operand (operands[4], E_DImode)
                          || !((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                        return NULL;
                      return gen_split_52 (insn, operands);

                    default:
                      return NULL;
                    }

                case 2:
                  if (shifted_const_arith_operand (operands[3], E_VOIDmode))
                    {
                      switch (GET_MODE (operands[4]))
                        {
                        case E_SImode:
                          if (scratch_operand (operands[4], E_SImode)
                              && ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                            return gen_split_42 (insn, operands);
                          break;

                        case E_DImode:
                          if (scratch_operand (operands[4], E_DImode)
                              && ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                            return gen_split_45 (insn, operands);
                          break;

                        default:
                          break;
                        }
                    }
                  if (!consecutive_bits_operand (operands[3], E_VOIDmode))
                    return NULL;
                  switch (GET_MODE (operands[4]))
                    {
                    case E_SImode:
                      if (!scratch_operand (operands[4], E_SImode)
                          || !((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                        return NULL;
                      return gen_split_49 (insn, operands);

                    case E_DImode:
                      if (!scratch_operand (operands[4], E_DImode)
                          || !((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                        return NULL;
                      return gen_split_53 (insn, operands);

                    default:
                      return NULL;
                    }

                case 3:
                  if (shifted_const_arith_operand (operands[3], E_VOIDmode)
                      && scratch_operand (operands[4], E_DImode)
                      && ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                    return gen_split_46 (insn, operands);
                  if (!consecutive_bits_operand (operands[3], E_VOIDmode))
                    return NULL;
                  switch (GET_MODE (operands[4]))
                    {
                    case E_SImode:
                      if (!scratch_operand (operands[4], E_SImode)
                          || !((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && ((((
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                        return NULL;
                      return gen_split_50 (insn, operands);

                    case E_DImode:
                      if (!scratch_operand (operands[4], E_DImode)
                          || !((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed)))
                        return NULL;
                      return gen_split_54 (insn, operands);

                    default:
                      return NULL;
                    }

                case 4:
                  x6 = XEXP (x5, 0);
                  x10 = XEXP (x6, 0);
                  x12 = XEXP (x10, 1);
                  if (XWINT (x12, 0) == 1L)
                    {
                      switch (pattern139 (x10))
                        {
                        case 0:
                          if ((
#line 2433 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                            return gen_split_59 (insn, operands);
                          break;

                        case 1:
                          if ((
#line 2433 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                            return gen_split_60 (insn, operands);
                          break;

                        default:
                          break;
                        }
                    }
                  x14 = XEXP (x10, 2);
                  if (x14 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
                    return NULL;
                  switch (pattern140 (x10))
                    {
                    case 0:
                      if (!(
#line 2464 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                        return NULL;
                      return gen_split_61 (insn, operands);

                    case 1:
                      if (!(
#line 2464 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                        return NULL;
                      return gen_split_62 (insn, operands);

                    default:
                      return NULL;
                    }

                default:
                  return NULL;
                }

            case SIGN_EXTEND:
              if (pattern51 (x5, E_SImode, PLUS, DIV) != 0)
                return NULL;
              x6 = XEXP (x5, 0);
              x10 = XEXP (x6, 0);
              x13 = XEXP (x10, 0);
              if (GET_CODE (x13) != SUBREG
                  || maybe_ne (SUBREG_BYTE (x13), 0)
                  || GET_MODE (x13) != E_SImode)
                return NULL;
              x15 = XEXP (x13, 0);
              if (GET_CODE (x15) != ASHIFT
                  || GET_MODE (x15) != E_DImode)
                return NULL;
              x12 = XEXP (x10, 1);
              if (GET_CODE (x12) != SUBREG
                  || maybe_ne (SUBREG_BYTE (x12), 0)
                  || GET_MODE (x12) != E_SImode)
                return NULL;
              x9 = XEXP (x6, 1);
              if (GET_CODE (x9) != SUBREG
                  || maybe_ne (SUBREG_BYTE (x9), 0)
                  || GET_MODE (x9) != E_SImode)
                return NULL;
              operands[0] = x4;
              if (!register_operand (operands[0], E_DImode))
                return NULL;
              x16 = XEXP (x15, 0);
              operands[1] = x16;
              if (!register_operand (operands[1], E_DImode))
                return NULL;
              x17 = XEXP (x15, 1);
              operands[2] = x17;
              if (!imm123_operand (operands[2], E_QImode))
                return NULL;
              x18 = XEXP (x12, 0);
              operands[3] = x18;
              if (!register_operand (operands[3], E_DImode))
                return NULL;
              x19 = XEXP (x9, 0);
              operands[4] = x19;
              if (!register_operand (operands[4], E_DImode))
                return NULL;
              x8 = XEXP (x2, 0);
              operands[5] = x8;
              if (!register_operand (operands[5], E_DImode)
                  || !
#line 55 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA))
                return NULL;
              return gen_split_65 (insn, operands);

            case PLUS:
              if (pattern51 (x5, E_DImode, ASHIFT, AND) != 0)
                return NULL;
              operands[0] = x4;
              if (!register_operand (operands[0], E_DImode))
                return NULL;
              x6 = XEXP (x5, 0);
              x10 = XEXP (x6, 0);
              x13 = XEXP (x10, 0);
              operands[1] = x13;
              if (!register_operand (operands[1], E_DImode))
                return NULL;
              x12 = XEXP (x10, 1);
              operands[2] = x12;
              x9 = XEXP (x6, 1);
              operands[3] = x9;
              if (!consecutive_bits_operand (operands[3], E_DImode))
                return NULL;
              x7 = XEXP (x5, 1);
              operands[4] = x7;
              if (!register_operand (operands[4], E_DImode))
                return NULL;
              x8 = XEXP (x2, 0);
              operands[5] = x8;
              if (scratch_operand (operands[5], E_DImode)
                  && imm123_operand (operands[2], E_QImode)
                  && (
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2]))) && 
#line 102 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                return gen_split_68 (insn, operands);
              if (!register_operand (operands[5], E_DImode)
                  || !immediate_operand (operands[2], E_QImode)
                  || !
#line 137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA))
                return NULL;
              return gen_split_69 (insn, operands);

            default:
              return NULL;
            }

        case UNSPEC:
          if (XVECLEN (x3, 0) != 1
              || XINT (x3, 1) != 0)
            return NULL;
          x20 = XVECEXP (x3, 0, 0);
          operands[0] = x20;
          if (!register_operand (operands[0], E_VOIDmode))
            return NULL;
          x8 = XEXP (x2, 0);
          operands[1] = x8;
          if (!scratch_operand (operands[1], E_VOIDmode)
              || !
#line 2769 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed))
            return NULL;
          return gen_split_63 (insn, operands);

        default:
          return NULL;
        }

    case 3:
      x3 = XVECEXP (x1, 0, 0);
      if (GET_CODE (x3) != SET)
        return NULL;
      x2 = XVECEXP (x1, 0, 1);
      if (GET_CODE (x2) != CLOBBER)
        return NULL;
      x21 = XVECEXP (x1, 0, 2);
      if (GET_CODE (x21) != CLOBBER)
        return NULL;
      x5 = XEXP (x3, 1);
      switch (GET_CODE (x5))
        {
        case SIGN_EXTEND:
          if (pattern53 (x5) != 0)
            return NULL;
          switch (pattern114 (x1))
            {
            case 0:
              if (!(
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0) && 
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                return NULL;
              return gen_split_71 (insn, operands);

            case 1:
              if (!(
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0) && 
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                return NULL;
              return gen_split_72 (insn, operands);

            case 2:
              if (!(
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0) && 
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                return NULL;
              return gen_split_73 (insn, operands);

            case 3:
              if (!(
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0) && 
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                return NULL;
              return gen_split_74 (insn, operands);

            default:
              return NULL;
            }

        case IF_THEN_ELSE:
          if (pattern54 (x3) != 0)
            return NULL;
          switch (pattern126 (x1))
            {
            case 0:
              if (!((
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 673 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                return NULL;
              return gen_split_88 (insn, operands);

            case 1:
              if (!((
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 673 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                return NULL;
              return gen_split_89 (insn, operands);

            default:
              return NULL;
            }

        default:
          return NULL;
        }

    default:
      return NULL;
    }
}

rtx_insn *
split_insns (rtx x1 ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15, x16, x17;
  rtx x18;
  rtx_insn *res ATTRIBUTE_UNUSED;
  recog_data.insn = NULL;
  switch (GET_CODE (x1))
    {
    case SET:
      x2 = XEXP (x1, 0);
      operands[0] = x2;
      x3 = XEXP (x1, 1);
      switch (GET_CODE (x3))
        {
        case ZERO_EXTEND:
          x4 = XEXP (x3, 0);
          switch (GET_CODE (x4))
            {
            case REG:
            case SUBREG:
            case MEM:
              operands[1] = x4;
              switch (GET_MODE (operands[0]))
                {
                case E_DImode:
                  if (!register_operand (operands[0], E_DImode)
                      || GET_MODE (x3) != E_DImode)
                    return NULL;
                  switch (GET_MODE (operands[1]))
                    {
                    case E_SImode:
                      if (!nonimmediate_operand (operands[1], E_SImode)
                          || !(
#line 1371 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && !(register_operand (operands[1], SImode)
        && reg_or_subregno (operands[1]) == VL_REGNUM)) && 
#line 1377 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0]))))
                        return NULL;
                      return gen_split_1 (insn, operands);

                    case E_HImode:
                      if (!nonimmediate_operand (operands[1], E_HImode)
                          || !((
#line 1398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 1402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0]))))
                        return NULL;
                      return gen_split_3 (insn, operands);

                    default:
                      return NULL;
                    }

                case E_SImode:
                  if (!register_operand (operands[0], E_SImode)
                      || GET_MODE (x3) != E_SImode
                      || !nonimmediate_operand (operands[1], E_HImode)
                      || !(
#line 1398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 1402 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0]))))
                    return NULL;
                  return gen_split_2 (insn, operands);

                default:
                  return NULL;
                }

            case PLUS:
              if (GET_MODE (x4) != E_SImode)
                return NULL;
              x5 = XEXP (x4, 1);
              if (GET_CODE (x5) != SUBREG
                  || maybe_ne (SUBREG_BYTE (x5), 0)
                  || GET_MODE (x5) != E_SImode
                  || !register_operand (operands[0], E_DImode)
                  || GET_MODE (x3) != E_DImode)
                return NULL;
              x6 = XEXP (x4, 0);
              if (GET_MODE (x6) != E_SImode)
                return NULL;
              x7 = XEXP (x5, 0);
              if (!register_operand (x7, E_DImode))
                return NULL;
              switch (GET_CODE (x6))
                {
                case ASHIFT:
                  x8 = XEXP (x6, 0);
                  if (GET_CODE (x8) != SUBREG
                      || maybe_ne (SUBREG_BYTE (x8), 0)
                      || GET_MODE (x8) != E_SImode)
                    return NULL;
                  x9 = XEXP (x8, 0);
                  operands[1] = x9;
                  if (!register_operand (operands[1], E_DImode))
                    return NULL;
                  x10 = XEXP (x6, 1);
                  operands[2] = x10;
                  if (!imm123_operand (operands[2], E_QImode))
                    return NULL;
                  operands[3] = x7;
                  if (!
#line 72 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA))
                    return NULL;
                  return gen_split_66 (insn, operands);

                case SUBREG:
                  if (maybe_ne (SUBREG_BYTE (x6), 0))
                    return NULL;
                  x8 = XEXP (x6, 0);
                  if (GET_CODE (x8) != AND
                      || GET_MODE (x8) != E_DImode)
                    return NULL;
                  x9 = XEXP (x8, 0);
                  if (GET_CODE (x9) != ASHIFT
                      || GET_MODE (x9) != E_DImode)
                    return NULL;
                  x11 = XEXP (x9, 0);
                  operands[1] = x11;
                  if (!register_operand (operands[1], E_DImode))
                    return NULL;
                  x12 = XEXP (x9, 1);
                  operands[2] = x12;
                  if (!imm123_operand (operands[2], E_QImode))
                    return NULL;
                  x13 = XEXP (x8, 1);
                  operands[3] = x13;
                  if (!consecutive_bits_operand (operands[3], E_DImode))
                    return NULL;
                  operands[4] = x7;
                  if (!
#line 82 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   /* Ensure the mask includes all the bits in SImode.  */
   && ((INTVAL (operands[3]) & (HOST_WIDE_INT_1U << 31)) != 0)))
                    return NULL;
                  return gen_split_67 (insn, operands);

                default:
                  return NULL;
                }

            default:
              return NULL;
            }

        case SIGN_EXTEND:
          x4 = XEXP (x3, 0);
          switch (GET_CODE (x4))
            {
            case REG:
            case SUBREG:
            case MEM:
              operands[1] = x4;
              switch (GET_MODE (operands[0]))
                {
                case E_HImode:
                  switch (pattern78 (x3, E_HImode))
                    {
                    case 0:
                      if (!(
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 1458 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0]))))
                        return NULL;
                      return gen_split_4 (insn, operands);

                    case 1:
                      if (!(
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 1458 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0]))))
                        return NULL;
                      return gen_split_7 (insn, operands);

                    default:
                      return NULL;
                    }

                case E_SImode:
                  switch (pattern78 (x3, E_SImode))
                    {
                    case 0:
                      if (!(
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 1458 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0]))))
                        return NULL;
                      return gen_split_5 (insn, operands);

                    case 1:
                      if (!(
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 1458 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0]))))
                        return NULL;
                      return gen_split_8 (insn, operands);

                    default:
                      return NULL;
                    }

                case E_DImode:
                  switch (pattern78 (x3, E_DImode))
                    {
                    case 0:
                      if (!((
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 1458 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0]))))
                        return NULL;
                      return gen_split_6 (insn, operands);

                    case 1:
                      if (!((
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 1458 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0]))))
                        return NULL;
                      return gen_split_9 (insn, operands);

                    default:
                      return NULL;
                    }

                default:
                  return NULL;
                }

            case ASHIFT:
              switch (pattern57 (x3))
                {
                case 0:
                  if (!(
#line 2109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1) && 
#line 2113 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                    return NULL;
                  return gen_split_30 (insn, operands);

                case 1:
                  if (!(
#line 2131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1) && 
#line 2135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                    return NULL;
                  return gen_split_33 (insn, operands);

                default:
                  return NULL;
                }

            case ASHIFTRT:
              switch (pattern57 (x3))
                {
                case 0:
                  if (!(
#line 2109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1) && 
#line 2113 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                    return NULL;
                  return gen_split_31 (insn, operands);

                case 1:
                  if (!(
#line 2131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1) && 
#line 2135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                    return NULL;
                  return gen_split_34 (insn, operands);

                default:
                  return NULL;
                }

            case LSHIFTRT:
              switch (pattern57 (x3))
                {
                case 0:
                  if (!(
#line 2109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1) && 
#line 2113 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                    return NULL;
                  return gen_split_32 (insn, operands);

                case 1:
                  if (!(
#line 2131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1) && 
#line 2135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                    return NULL;
                  return gen_split_35 (insn, operands);

                default:
                  return NULL;
                }

            default:
              return NULL;
            }

        case CONST_INT:
        case CONST_WIDE_INT:
        case CONST_POLY_INT:
        case CONST_FIXED:
        case CONST_DOUBLE:
        case CONST_VECTOR:
        case CONST:
        case REG:
        case SUBREG:
        case MEM:
        case LABEL_REF:
        case SYMBOL_REF:
        case HIGH:
          return split_4 (x1, insn);

        case ASHIFT:
          switch (pattern16 (x3))
            {
            case 0:
              if (!(
#line 1998 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
   == GET_MODE_BITSIZE (SImode)-1) && 
#line 2001 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                return NULL;
              return gen_split_18 (insn, operands);

            case 1:
              if (!(
#line 2017 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1) && 
#line 2021 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                return NULL;
              return gen_split_21 (insn, operands);

            case 2:
              if (!(
#line 2053 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1) && 
#line 2057 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                return NULL;
              return gen_split_24 (insn, operands);

            case 3:
              if (!(
#line 2073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1) && 
#line 2077 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                return NULL;
              return gen_split_27 (insn, operands);

            default:
              return NULL;
            }

        case ASHIFTRT:
          switch (pattern16 (x3))
            {
            case 0:
              if (!(
#line 1998 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
   == GET_MODE_BITSIZE (SImode)-1) && 
#line 2001 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                return NULL;
              return gen_split_19 (insn, operands);

            case 1:
              if (!(
#line 2017 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1) && 
#line 2021 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                return NULL;
              return gen_split_22 (insn, operands);

            case 2:
              if (!(
#line 2053 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1) && 
#line 2057 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                return NULL;
              return gen_split_25 (insn, operands);

            case 3:
              if (!(
#line 2073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1) && 
#line 2077 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                return NULL;
              return gen_split_28 (insn, operands);

            default:
              return NULL;
            }

        case LSHIFTRT:
          switch (pattern16 (x3))
            {
            case 0:
              if (!(
#line 1998 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
   == GET_MODE_BITSIZE (SImode)-1) && 
#line 2001 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                return NULL;
              return gen_split_20 (insn, operands);

            case 1:
              if (!(
#line 2017 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1) && 
#line 2021 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                return NULL;
              return gen_split_23 (insn, operands);

            case 2:
              if (!(
#line 2053 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1) && 
#line 2057 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                return NULL;
              return gen_split_26 (insn, operands);

            case 3:
              if (!(
#line 2073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1) && 
#line 2077 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1)))
                return NULL;
              return gen_split_29 (insn, operands);

            default:
              return NULL;
            }

        case AND:
          x4 = XEXP (x3, 0);
          switch (GET_CODE (x4))
            {
            case REG:
            case SUBREG:
              switch (pattern13 (x3))
                {
                case 0:
                  if (const_nottwobits_operand (operands[2], E_SImode)
                      && ((
#line 513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 515 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                    return gen_split_75 (insn, operands);
                  if (!not_uimm_extra_bit_or_nottwobits (operands[2], E_SImode)
                      || !((
#line 646 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                    return NULL;
                  return gen_split_86 (insn, operands);

                case 1:
                  if (const_nottwobits_operand (operands[2], E_DImode))
                    {
                      if (((
#line 513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 515 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                        return gen_split_76 (insn, operands);
                      if ((
#line 532 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBS
   && clz_hwi (~UINTVAL (operands[2])) > 33) && 
#line 535 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                        return gen_split_77 (insn, operands);
                    }
                  if (!not_uimm_extra_bit_or_nottwobits (operands[2], E_DImode)
                      || !((
#line 646 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                    return NULL;
                  return gen_split_87 (insn, operands);

                default:
                  return NULL;
                }

            case NOT:
              x6 = XEXP (x4, 0);
              if (GET_CODE (x6) != LSHIFTRT)
                return NULL;
              x10 = XEXP (x6, 1);
              if (GET_CODE (x10) != SUBREG
                  || maybe_ne (SUBREG_BYTE (x10), 0)
                  || GET_MODE (x10) != E_QImode)
                return NULL;
              x14 = XEXP (x3, 1);
              if (x14 != const_int_rtx[MAX_SAVED_CONST_INT + 1])
                return NULL;
              x8 = XEXP (x6, 0);
              operands[1] = x8;
              x15 = XEXP (x10, 0);
              operands[2] = x15;
              switch (GET_MODE (operands[0]))
                {
                case E_SImode:
                  if (pattern127 (x3, E_SImode) != 0
                      || !(
#line 603 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
                    return NULL;
                  return gen_split_78 (insn, operands);

                case E_DImode:
                  if (pattern127 (x3, E_DImode) != 0
                      || !(
#line 603 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                    return NULL;
                  return gen_split_79 (insn, operands);

                default:
                  return NULL;
                }

            default:
              return NULL;
            }

        case NEG:
          x4 = XEXP (x3, 0);
          if (GET_CODE (x4) != EQ)
            return NULL;
          x6 = XEXP (x4, 0);
          if (GET_CODE (x6) != ZERO_EXTRACT)
            return NULL;
          x10 = XEXP (x6, 1);
          if (x10 != const_int_rtx[MAX_SAVED_CONST_INT + 1])
            return NULL;
          x5 = XEXP (x4, 1);
          if (x5 != const_int_rtx[MAX_SAVED_CONST_INT + 0])
            return NULL;
          x8 = XEXP (x6, 0);
          operands[1] = x8;
          x16 = XEXP (x6, 2);
          operands[2] = x16;
          switch (GET_MODE (operands[0]))
            {
            case E_SImode:
              if (pattern115 (x3, E_SImode) != 0
                  || !
#line 618 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS))
                return NULL;
              return gen_split_80 (insn, operands);

            case E_DImode:
              if (pattern115 (x3, E_DImode) != 0
                  || !(
#line 618 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
                return NULL;
              return gen_split_81 (insn, operands);

            default:
              return NULL;
            }

        case IOR:
          switch (pattern18 (x3))
            {
            case 0:
              if (!((
#line 628 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 630 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                return NULL;
              return gen_split_82 (insn, operands);

            case 1:
              if (!((
#line 628 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 630 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                return NULL;
              return gen_split_84 (insn, operands);

            default:
              return NULL;
            }

        case XOR:
          switch (pattern18 (x3))
            {
            case 0:
              if (!((
#line 628 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 630 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                return NULL;
              return gen_split_83 (insn, operands);

            case 1:
              if (!((
#line 628 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 630 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed)))
                return NULL;
              return gen_split_85 (insn, operands);

            default:
              return NULL;
            }

        case UNSPEC:
          switch (XVECLEN (x3, 0))
            {
            case 5:
              if (XINT (x3, 1) != 66)
                return NULL;
              switch (pattern71 (x3))
                {
                case 0:
                  if (!((
#line 890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 892 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( epilogue_completed)))
                    return NULL;
                  return gen_split_186 (insn, operands);

                case 1:
                  if (!((
#line 890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 892 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( epilogue_completed)))
                    return NULL;
                  return gen_split_187 (insn, operands);

                default:
                  return NULL;
                }

            case 2:
              if (XINT (x3, 1) != 68
                  || pattern27 (x3) != 0)
                return NULL;
              x17 = XVECEXP (x3, 0, 0);
              x18 = XEXP (x17, 0);
              operands[1] = x18;
              switch (GET_MODE (operands[0]))
                {
                case E_QImode:
                  switch (pattern130 (x3))
                    {
                    case 0:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_416 (insn, operands);

                    case 1:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_417 (insn, operands);

                    case 2:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_418 (insn, operands);

                    case 3:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_419 (insn, operands);

                    case 4:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_420 (insn, operands);

                    case 5:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_421 (insn, operands);

                    case 6:
                      if (!(
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                        return NULL;
                      return gen_split_422 (insn, operands);

                    default:
                      return NULL;
                    }

                case E_HImode:
                  switch (pattern131 (x3))
                    {
                    case 0:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_423 (insn, operands);

                    case 1:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_424 (insn, operands);

                    case 2:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_425 (insn, operands);

                    case 3:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_426 (insn, operands);

                    case 4:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_427 (insn, operands);

                    case 5:
                      if (!(
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode))) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                        return NULL;
                      return gen_split_428 (insn, operands);

                    default:
                      return NULL;
                    }

                case E_SImode:
                  switch (pattern132 (x3))
                    {
                    case 0:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_429 (insn, operands);

                    case 1:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_430 (insn, operands);

                    case 2:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_431 (insn, operands);

                    case 3:
                      if (!
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode))))
                        return NULL;
                      return gen_split_432 (insn, operands);

                    case 4:
                      if (!(
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode))) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
                        return NULL;
                      return gen_split_433 (insn, operands);

                    default:
                      return NULL;
                    }

                case E_DImode:
                  switch (pattern133 (x3))
                    {
                    case 0:
                      if (!(
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (DImode), GET_MODE_BITSIZE (Pmode))) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                        return NULL;
                      return gen_split_434 (insn, operands);

                    case 1:
                      if (!(
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (DImode), GET_MODE_BITSIZE (Pmode))) && 
#line 235 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                        return NULL;
                      return gen_split_435 (insn, operands);

                    case 2:
                      if (!(
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (DImode), GET_MODE_BITSIZE (Pmode))) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                        return NULL;
                      return gen_split_436 (insn, operands);

                    case 3:
                      if (!(
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (DImode), GET_MODE_BITSIZE (Pmode))) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
                        return NULL;
                      return gen_split_437 (insn, operands);

                    default:
                      return NULL;
                    }

                default:
                  return NULL;
                }

            default:
              return NULL;
            }

        case IF_THEN_ELSE:
          return split_3 (x1, insn);

        default:
          return NULL;
        }

    case PARALLEL:
      return split_6 (x1, insn);

    case EH_RETURN:
      if (!
#line 2780 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(epilogue_completed))
        return NULL;
      return gen_split_64 (insn, operands);

    default:
      return NULL;
    }
}

rtx_insn *
peephole2_insns (rtx x1 ATTRIBUTE_UNUSED,
	rtx_insn *insn ATTRIBUTE_UNUSED,
	int *pmatch_len_ ATTRIBUTE_UNUSED)
{
  rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0];
  rtx x2, x3, x4, x5, x6, x7, x8, x9;
  rtx x10, x11, x12, x13, x14, x15;
  rtx_insn *res ATTRIBUTE_UNUSED;
  recog_data.insn = NULL;
  if (peep2_current_count < 2
      || GET_CODE (x1) != SET)
    return NULL;
  x2 = XEXP (x1, 0);
  operands[0] = x2;
  x3 = PATTERN (peep2_next_insn (1));
  if (GET_CODE (x3) != SET)
    return NULL;
  x4 = XEXP (x1, 1);
  switch (GET_CODE (x4))
    {
    case ASHIFT:
      if (peep2_current_count < 3
          || GET_MODE (x4) != E_DImode
          || !register_operand (operands[0], E_DImode))
        return NULL;
      x5 = XEXP (x4, 0);
      operands[1] = x5;
      if (!register_operand (operands[1], E_DImode))
        return NULL;
      x6 = XEXP (x4, 1);
      operands[2] = x6;
      if (!const_int_operand (operands[2], E_VOIDmode))
        return NULL;
      x7 = XEXP (x3, 1);
      if (GET_CODE (x7) != LSHIFTRT
          || GET_MODE (x7) != E_DImode)
        return NULL;
      x8 = XEXP (x3, 0);
      operands[3] = x8;
      if (!register_operand (operands[3], E_DImode))
        return NULL;
      x9 = XEXP (x7, 0);
      if (!rtx_equal_p (x9, operands[0]))
        return NULL;
      x10 = XEXP (x7, 1);
      if (!rtx_equal_p (x10, operands[2]))
        return NULL;
      x11 = PATTERN (peep2_next_insn (2));
      if (GET_CODE (x11) != SET)
        return NULL;
      x12 = XEXP (x11, 1);
      if (GET_CODE (x12) != ASHIFT
          || GET_MODE (x12) != E_DImode)
        return NULL;
      x13 = XEXP (x11, 0);
      operands[4] = x13;
      if (!register_operand (operands[4], E_DImode))
        return NULL;
      x14 = XEXP (x12, 1);
      operands[5] = x14;
      if (!const_int_operand (operands[5], E_VOIDmode))
        return NULL;
      x15 = XEXP (x12, 0);
      if (!rtx_equal_p (x15, operands[3])
          || !
#line 30 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_64BIT
   && INTVAL (operands[5]) < INTVAL (operands[2])
   && (REGNO (operands[3]) == REGNO (operands[4])
       || peep2_reg_dead_p (3, operands[3]))))
        return NULL;
      *pmatch_len_ = 2;
      return gen_peephole2_1 (insn, operands);

    case REG:
    case SUBREG:
    case MEM:
      operands[1] = x4;
      x8 = XEXP (x3, 0);
      operands[2] = x8;
      x7 = XEXP (x3, 1);
      operands[3] = x7;
      switch (GET_MODE (operands[0]))
        {
        case E_SImode:
          if (register_operand (operands[0], E_SImode)
              && memory_operand (operands[1], E_SImode)
              && register_operand (operands[2], E_SImode)
              && memory_operand (operands[3], E_SImode)
              && 
#line 48 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, true, SImode)))
            {
              *pmatch_len_ = 1;
              res = gen_peephole2_2 (insn, operands);
              if (res != NULL_RTX)
                return res;
            }
          if (!memory_operand (operands[0], E_SImode)
              || !register_operand (operands[1], E_SImode)
              || !memory_operand (operands[2], E_SImode)
              || !register_operand (operands[3], E_SImode)
              || !
#line 62 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, false, SImode)))
            return NULL;
          *pmatch_len_ = 1;
          return gen_peephole2_4 (insn, operands);

        case E_DImode:
          if (register_operand (operands[0], E_DImode)
              && memory_operand (operands[1], E_DImode)
              && register_operand (operands[2], E_DImode)
              && memory_operand (operands[3], E_DImode)
              && (
#line 48 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, true, DImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            {
              *pmatch_len_ = 1;
              res = gen_peephole2_3 (insn, operands);
              if (res != NULL_RTX)
                return res;
            }
          if (!memory_operand (operands[0], E_DImode)
              || !register_operand (operands[1], E_DImode)
              || !memory_operand (operands[2], E_DImode)
              || !register_operand (operands[3], E_DImode)
              || !(
#line 62 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, false, DImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
            return NULL;
          *pmatch_len_ = 1;
          return gen_peephole2_5 (insn, operands);

        default:
          return NULL;
        }

    case SIGN_EXTEND:
      if (pattern77 (x4, SIGN_EXTEND) != 0
          || !
#line 76 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR && TARGET_64BIT
  && th_mempair_operands_p (operands, true, SImode)))
        return NULL;
      *pmatch_len_ = 1;
      return gen_peephole2_6 (insn, operands);

    case ZERO_EXTEND:
      if (pattern77 (x4, ZERO_EXTEND) != 0
          || !
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR && TARGET_64BIT
  && th_mempair_operands_p (operands, true, SImode)))
        return NULL;
      *pmatch_len_ = 1;
      return gen_peephole2_7 (insn, operands);

    default:
      return NULL;
    }
}
