/* Generated automatically by the program `genconditions' from the target
   machine description file.  */

#define IN_TARGET_CODE 1
#include "bconfig.h"
#define INCLUDE_STRING
#include "system.h"

/* It is necessary, but not entirely safe, to include the headers below
   in a generator program.  As a defensive measure, don't do so when the
   table isn't going to have anything in it.  */
#if GCC_VERSION >= 3001

/* Do not allow checking to confuse the issue.  */
#undef CHECKING_P
#define CHECKING_P 0
#undef ENABLE_TREE_CHECKING
#undef ENABLE_RTL_CHECKING
#undef ENABLE_RTL_FLAG_CHECKING
#undef ENABLE_GC_CHECKING
#undef ENABLE_GC_ALWAYS_COLLECT
#define USE_ENUM_MODES

#include "coretypes.h"
#include "tm.h"
#include "insn-constants.h"
#include "rtl.h"
#include "memmodel.h"
#include "tm_p.h"
#include "hard-reg-set.h"
#include "function.h"
#include "emit-rtl.h"

/* Fake - insn-config.h doesn't exist yet.  */
#define MAX_RECOG_OPERANDS 10
#define MAX_DUP_OPERANDS 10
#define MAX_INSNS_PER_SPLIT 5

#include "regs.h"
#include "recog.h"
#include "output.h"
#include "flags.h"
#include "hard-reg-set.h"
#include "predict.h"
#include "basic-block.h"
#include "bitmap.h"
#include "df.h"
#include "resource.h"
#include "diagnostic-core.h"
#include "reload.h"
#include "tm-constrs.h"

#define HAVE_eh_return 1
#include "except.h"

/* Dummy external declarations.  */
extern rtx_insn *insn;
extern rtx ins1;
extern rtx operands[];

#endif /* gcc >= 3.0.1 */

/* Structure definition duplicated from gensupport.h rather than
   drag in that file and its dependencies.  */
struct c_test
{
  const char *expr;
  int value;
};

/* This table lists each condition found in the machine description.
   Each condition is mapped to its truth value (0 or 1), or -1 if that
   cannot be calculated at compile time.
   If we don't have __builtin_constant_p, or it's not acceptable in array
   initializers, fall back to assuming that all conditions potentially
   vary at run time.  It works in 3.0.1 and later; 3.0 only when not
   optimizing.  */

#if GCC_VERSION >= 3001
static const struct c_test insn_conditions[] = {

  { "(TARGET_VECTOR) && (TARGET_FULL_V)",
    __builtin_constant_p (
#line 2091 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V))
    ? (int) (
#line 2091 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 300 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_FULL_V))
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_VECTOR) && ((TARGET_64BIT && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_FP_32))",
    __builtin_constant_p (
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 327 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
    ? (int) (
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 327 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)))
    : -1 },
  { "(!SMALL_OPERAND (INTVAL (operands[3]))) && (((((TARGET_64BIT) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT))",
    __builtin_constant_p (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && ((((
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
    ? (int) (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && ((((
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
    : -1 },
#line 839 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_ZMMUL || TARGET_MUL",
    __builtin_constant_p 
#line 839 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZMMUL || TARGET_MUL)
    ? (int) 
#line 839 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZMMUL || TARGET_MUL)
    : -1 },
  { "(TARGET_ZKSED) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 433 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSED) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 433 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSED) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(USE_LOAD_ADDRESS_MACRO (operands[0])) && ((TARGET_64BIT) && (Pmode == DImode))",
    __builtin_constant_p (
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])\n\
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && ((TARGET_ZFH || TARGET_ZHINX) && (Pmode == SImode))",
    __builtin_constant_p (
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "(TARGET_VECTOR\n\
   && !rtx_equal_p (operands[2], operands[5])\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx1HImode)\n\
   && register_operand (operands[3], VNx1HImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1HImode)
   && register_operand (operands[3], VNx1HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1HImode)
   && register_operand (operands[3], VNx1HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])\n\
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (Pmode == DImode))",
    __builtin_constant_p (
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
#line 2073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_64BIT\n\
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))\n\
       == GET_MODE_BITSIZE (DImode)-1",
    __builtin_constant_p 
#line 2073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1)
    ? (int) 
#line 2073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1)
    : -1 },
#line 2502 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_HARD_FLOAT || TARGET_ZFINX",
    __builtin_constant_p 
#line 2502 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)
    ? (int) 
#line 2502 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)
    : -1 },
  { "(TARGET_VECTOR\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
  { "(TARGET_VECTOR) && ( register_operand (operands[0], VNx4BImode)\n\
   && register_operand (operands[3], VNx4BImode)\n\
   && INTVAL (operands[5]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4BImode)
   && register_operand (operands[3], VNx4BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    ? (int) (
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4BImode)
   && register_operand (operands[3], VNx4BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (((!TARGET_64BIT) && (TARGET_HARD_FLOAT || TARGET_ZFINX)) && (TARGET_HARD_FLOAT || TARGET_ZFINX))",
    __builtin_constant_p (
#line 2524 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
    ? (int) (
#line 2524 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
  { "(TARGET_VECTOR) && ( reload_completed)",
    __builtin_constant_p (
#line 491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 493 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    ? (int) (
#line 491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 493 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    : -1 },
  { "(TARGET_ZBS && TARGET_ZBB) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_VECTOR\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
  { "((TARGET_VECTOR && (lra_in_progress || reload_completed)) && (Pmode == DImode)) && ( reload_completed)",
    __builtin_constant_p ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    ? (int) ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    : -1 },
  { "((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (SFmode)) && (TARGET_HARD_FLOAT || TARGET_ZFINX)",
    __builtin_constant_p (
#line 1250 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (SFmode)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
    ? (int) (
#line 1250 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (SFmode)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
    : -1 },
  { "(TARGET_HARD_FLOAT  || TARGET_ZFINX) && ((TARGET_64BIT) && (TARGET_HARD_FLOAT || TARGET_ZFINX))",
    __builtin_constant_p (
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
    ? (int) (
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (TARGET_ZFH || TARGET_ZHINX)",
    __builtin_constant_p (
#line 2502 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))
    ? (int) (
#line 2502 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))
    : -1 },
#line 316 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
  { "TARGET_XTHEADMEMPAIR && reload_completed\n\
   && th_mempair_operands_p (operands, false, SImode)",
    __builtin_constant_p 
#line 316 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, false, SImode))
    ? (int) 
#line 316 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, false, SImode))
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_SFB_ALU) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 2363 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 2363 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
#line 2769 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "reload_completed",
    __builtin_constant_p 
#line 2769 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed)
    ? (int) 
#line 2769 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed)
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx8HImode)\n\
   && register_operand (operands[3], VNx8HImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8HImode)
   && register_operand (operands[3], VNx8HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8HImode)
   && register_operand (operands[3], VNx8HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)",
    __builtin_constant_p (
#line 1088 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))
    ? (int) (
#line 1088 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && ((TARGET_64BIT) && (Pmode == SImode))",
    __builtin_constant_p (
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
#line 253 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
  { "TARGET_ZKNE && !TARGET_64BIT",
    __builtin_constant_p 
#line 253 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNE && !TARGET_64BIT)
    ? (int) 
#line 253 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNE && !TARGET_64BIT)
    : -1 },
  { "((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (HFmode)) && (TARGET_ZFH || TARGET_ZHINX)",
    __builtin_constant_p (
#line 1250 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (HFmode)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))
    ? (int) (
#line 1250 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (HFmode)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))
    : -1 },
#line 182 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_64BIT && TARGET_ZBA\n\
   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff",
    __builtin_constant_p 
#line 182 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)
    ? (int) 
#line 182 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)
    : -1 },
  { "(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (TARGET_HARD_FLOAT || TARGET_ZFINX)",
    __builtin_constant_p (
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
    ? (int) (
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
    : -1 },
  { "(TARGET_VECTOR\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && ( reload_completed\n\
   && !rtx_equal_p (operands[0], operands[5]))",
    __builtin_constant_p (
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    ? (int) (
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_64)) && ( register_operand (operands[0], VNx2DImode)\n\
   && register_operand (operands[3], VNx2DImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2DImode)
   && register_operand (operands[3], VNx2DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2DImode)
   && register_operand (operands[3], VNx2DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (SImode)) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 590 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (SImode)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 590 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (SImode)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])\n\
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (Pmode == SImode))",
    __builtin_constant_p (
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "(TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (DImode)) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 590 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (DImode)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 590 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (DImode)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_ZBB) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 208 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 208 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 6913 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 272 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 6913 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && 
#line 272 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
  { "Pmode == DImode",
    __builtin_constant_p 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)
    ? (int) 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)
    : -1 },
  { "((TARGET_ZBS && TARGET_ZBB) && (TARGET_64BIT)) && ( reload_completed)",
    __builtin_constant_p ((
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 673 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    ? (int) ((
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 673 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    : -1 },
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode))",
    __builtin_constant_p 
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode)))
    ? (int) 
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode)))
    : -1 },
#line 1045 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_DIV",
    __builtin_constant_p 
#line 1045 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV)
    ? (int) 
#line 1045 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV)
    : -1 },
  { "((TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_MIN_VLEN > 32) && (Pmode == SImode))) && ( reload_completed)",
    __builtin_constant_p ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    ? (int) ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    : -1 },
  { "(TARGET_SFB_ALU) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 2363 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 2363 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0",
    __builtin_constant_p 
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0)
    ? (int) 
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0)
    : -1 },
#line 486 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_ZBS && TARGET_64BIT\n\
   && !partial_subreg_p (operands[1])",
    __builtin_constant_p 
#line 486 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_64BIT
   && !partial_subreg_p (operands[1]))
    ? (int) 
#line 486 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_64BIT
   && !partial_subreg_p (operands[1]))
    : -1 },
#line 76 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
  { "!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])",
    __builtin_constant_p 
#line 76 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1]))
    ? (int) 
#line 76 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1]))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (((!TARGET_64BIT) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX))",
    __builtin_constant_p (
#line 2524 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
    ? (int) (
#line 2524 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
    : -1 },
#line 302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_ZBB || TARGET_XTHEADBB",
    __builtin_constant_p 
#line 302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_XTHEADBB)
    ? (int) 
#line 302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_XTHEADBB)
    : -1 },
#line 532 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_64BIT && TARGET_ZBS\n\
   && clz_hwi (~UINTVAL (operands[2])) > 33",
    __builtin_constant_p 
#line 532 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBS
   && clz_hwi (~UINTVAL (operands[2])) > 33)
    ? (int) 
#line 532 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBS
   && clz_hwi (~UINTVAL (operands[2])) > 33)
    : -1 },
#line 7259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && TARGET_64BIT",
    __builtin_constant_p 
#line 7259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_64BIT)
    ? (int) 
#line 7259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_64BIT)
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 4052 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 4052 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
#line 352 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)",
    __builtin_constant_p 
#line 352 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB))
    ? (int) 
#line 352 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB))
    : -1 },
  { "(TARGET_VECTOR) && (Pmode == SImode)",
    __builtin_constant_p (
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
    ? (int) (
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_VECTOR) && ( register_operand (operands[0], VNx1BImode)\n\
   && register_operand (operands[3], VNx1BImode)\n\
   && INTVAL (operands[5]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1BImode)
   && register_operand (operands[3], VNx1BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    ? (int) (
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1BImode)
   && register_operand (operands[3], VNx1BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    : -1 },
  { "(reload_completed) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 2464 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 2464 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "((TARGET_ZBS) && (TARGET_64BIT)) && ( reload_completed)",
    __builtin_constant_p ((
#line 646 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    ? (int) ((
#line 646 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    : -1 },
  { "(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)",
    __builtin_constant_p (
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))
    ? (int) (
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32)) && ( register_operand (operands[0], VNx8SFmode)\n\
   && register_operand (operands[3], VNx8SFmode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8SFmode)
   && register_operand (operands[3], VNx8SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8SFmode)
   && register_operand (operands[3], VNx8SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])) && (TARGET_ZFHMIN)",
    __builtin_constant_p (
#line 76 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFHMIN))
    ? (int) (
#line 76 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFHMIN))
    : -1 },
  { "(TARGET_VECTOR\n\
   && !rtx_equal_p (operands[2], operands[5])\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
  { "(TARGET_ZBKC) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (((TARGET_64BIT) && (TARGET_HARD_FLOAT || TARGET_ZFINX)) && (TARGET_HARD_FLOAT || TARGET_ZFINX))",
    __builtin_constant_p (
#line 2524 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
    ? (int) (
#line 2524 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
  { "(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
  { "((TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && (Pmode == DImode))) && ( reload_completed)",
    __builtin_constant_p ((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    ? (int) ((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])\n\
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (Pmode == DImode))",
    __builtin_constant_p (
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
  { "(TARGET_64BIT\n\
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))\n\
       == GET_MODE_BITSIZE (SImode)-1) && ( 1)",
    __builtin_constant_p (
#line 2131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1) && 
#line 2135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1))
    ? (int) (
#line 2131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1) && 
#line 2135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1))
    : -1 },
  { "(TARGET_VECTOR\n\
   && !rtx_equal_p (operands[2], operands[5])\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    ? (int) (
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    : -1 },
  { "(register_operand (operands[3], QImode)\n\
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "(riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)) && (Pmode == DImode)",
    __builtin_constant_p (
#line 1680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
    ? (int) (
#line 1680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
    : -1 },
  { "(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0) && ( reload_completed)",
    __builtin_constant_p (
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0) && 
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    ? (int) (
#line 424 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0) && 
#line 426 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    : -1 },
  { "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && ((TARGET_ZFHMIN) && (Pmode == DImode))",
    __builtin_constant_p (
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFHMIN) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFHMIN) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(reload_completed) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 2464 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 2464 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
#line 2712 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "riscv_can_use_return_insn ()",
    __builtin_constant_p 
#line 2712 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(riscv_can_use_return_insn ())
    ? (int) 
#line 2712 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(riscv_can_use_return_insn ())
    : -1 },
#line 1878 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "!TARGET_64BIT && TARGET_DOUBLE_FLOAT\n\
   && (register_operand (operands[0], DFmode)\n\
       || reg_or_0_operand (operands[1], DFmode))",
    __builtin_constant_p 
#line 1878 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_64BIT && TARGET_DOUBLE_FLOAT
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode)))
    ? (int) 
#line 1878 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_64BIT && TARGET_DOUBLE_FLOAT
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode)))
    : -1 },
  { "(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 276 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (TARGET_64BIT))",
    __builtin_constant_p (
#line 1568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
    ? (int) (
#line 1568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
    : -1 },
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
  { "TARGET_XTHEADCONDMOV",
    __builtin_constant_p 
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADCONDMOV)
    ? (int) 
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADCONDMOV)
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])\n\
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (Pmode == SImode))",
    __builtin_constant_p (
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "(!(p2m1_shift_operand (operands[1], SImode)\n\
     || high_mask_shift_operand (operands[1], SImode))) && ( 1)",
    __builtin_constant_p (
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!(p2m1_shift_operand (operands[1], SImode)
     || high_mask_shift_operand (operands[1], SImode))) && 
#line 1697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1))
    ? (int) (
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!(p2m1_shift_operand (operands[1], SImode)
     || high_mask_shift_operand (operands[1], SImode))) && 
#line 1697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1))
    : -1 },
  { "((TARGET_VECTOR\n\
   && !rtx_equal_p (operands[2], operands[5])\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32)) && ( reload_completed\n\
   && !rtx_equal_p (operands[0], operands[5]))",
    __builtin_constant_p ((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    ? (int) ((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "((!TARGET_ZBB) && (TARGET_64BIT)) && ( reload_completed\n\
   && REG_P (operands[1])\n\
   && !paradoxical_subreg_p (operands[0]))",
    __builtin_constant_p ((
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 1458 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0])))
    ? (int) ((
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 1458 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0])))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
#line 341 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
  { "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed\n\
   && th_mempair_operands_p (operands, true, SImode)",
    __builtin_constant_p 
#line 341 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
   && th_mempair_operands_p (operands, true, SImode))
    ? (int) 
#line 341 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
   && th_mempair_operands_p (operands, true, SImode))
    : -1 },
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])",
    __builtin_constant_p 
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5]))
    ? (int) 
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5]))
    : -1 },
  { "(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
  { "(TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 2376 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 2376 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(TARGET_64BIT && !TARGET_ZBA\n\
   && !(register_operand (operands[1], SImode)\n\
        && reg_or_subregno (operands[1]) == VL_REGNUM)) && ( reload_completed\n\
   && REG_P (operands[1])\n\
   && !paradoxical_subreg_p (operands[0]))",
    __builtin_constant_p (
#line 1371 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && !(register_operand (operands[1], SImode)
        && reg_or_subregno (operands[1]) == VL_REGNUM)) && 
#line 1377 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0])))
    ? (int) (
#line 1371 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && !(register_operand (operands[1], SImode)
        && reg_or_subregno (operands[1]) == VL_REGNUM)) && 
#line 1377 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0])))
    : -1 },
  { "(TARGET_XTHEADBA\n\
   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBA
   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBA
   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32)) && ( register_operand (operands[0], VNx1SFmode)\n\
   && register_operand (operands[3], VNx1SFmode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1SFmode)
   && register_operand (operands[3], VNx1SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 91 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1SFmode)
   && register_operand (operands[3], VNx1SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_ZICBOM) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 3102 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOM) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 3102 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOM) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32)) && ( register_operand (operands[0], VNx2SFmode)\n\
   && register_operand (operands[3], VNx2SFmode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2SFmode)
   && register_operand (operands[3], VNx2SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 92 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2SFmode)
   && register_operand (operands[3], VNx2SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
  { "TARGET_XTHEADMAC && TARGET_64BIT",
    __builtin_constant_p 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC && TARGET_64BIT)
    ? (int) 
#line 290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC && TARGET_64BIT)
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx1QImode)\n\
   && register_operand (operands[3], VNx1QImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1QImode)
   && register_operand (operands[3], VNx1QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1QImode)
   && register_operand (operands[3], VNx1QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_MIN_VLEN > 32) && (Pmode == DImode))",
    __builtin_constant_p (
#line 651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
#line 1844 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_HARD_FLOAT\n\
   && (register_operand (operands[0], SFmode)\n\
       || reg_or_0_operand (operands[1], SFmode))",
    __builtin_constant_p 
#line 1844 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT
   && (register_operand (operands[0], SFmode)
       || reg_or_0_operand (operands[1], SFmode)))
    ? (int) 
#line 1844 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT
   && (register_operand (operands[0], SFmode)
       || reg_or_0_operand (operands[1], SFmode)))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((TARGET_64BIT) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX))",
    __builtin_constant_p (
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
    ? (int) (
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
    : -1 },
  { "(TARGET_XTHEADBA\n\
   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBA
   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBA
   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])\n\
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (Pmode == DImode))",
    __builtin_constant_p (
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
  { "((TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && (TARGET_64BIT)) && ( reload_completed)",
    __builtin_constant_p ((
#line 513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 515 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    ? (int) ((
#line 513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 515 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    : -1 },
#line 1719 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "!TARGET_64BIT\n\
   && (register_operand (operands[0], DImode)\n\
       || reg_or_0_operand (operands[1], DImode))",
    __builtin_constant_p 
#line 1719 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_64BIT
   && (register_operand (operands[0], DImode)
       || reg_or_0_operand (operands[1], DImode)))
    ? (int) 
#line 1719 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_64BIT
   && (register_operand (operands[0], DImode)
       || reg_or_0_operand (operands[1], DImode)))
    : -1 },
#line 82 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_64BIT && TARGET_ZBA\n\
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))\n\
   /* Ensure the mask includes all the bits in SImode.  */\n\
   && ((INTVAL (operands[3]) & (HOST_WIDE_INT_1U << 31)) != 0)",
    __builtin_constant_p 
#line 82 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   /* Ensure the mask includes all the bits in SImode.  */
   && ((INTVAL (operands[3]) & (HOST_WIDE_INT_1U << 31)) != 0))
    ? (int) 
#line 82 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   /* Ensure the mask includes all the bits in SImode.  */
   && ((INTVAL (operands[3]) & (HOST_WIDE_INT_1U << 31)) != 0))
    : -1 },
  { "(TARGET_VECTOR) && (Pmode == DImode)",
    __builtin_constant_p (
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
    ? (int) (
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
    : -1 },
  { "(TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && (Pmode == SImode))",
    __builtin_constant_p (
#line 643 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 643 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "(TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (DImode)) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 101 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (DImode)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 101 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (DImode)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
#line 1752 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "(register_operand (operands[0], SImode)\n\
    || reg_or_0_operand (operands[1], SImode))\n\
    && !(register_operand (operands[1], SImode)\n\
         && reg_or_subregno (operands[1]) == VL_REGNUM)",
    __builtin_constant_p 
#line 1752 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((register_operand (operands[0], SImode)
    || reg_or_0_operand (operands[1], SImode))
    && !(register_operand (operands[1], SImode)
         && reg_or_subregno (operands[1]) == VL_REGNUM))
    ? (int) 
#line 1752 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((register_operand (operands[0], SImode)
    || reg_or_0_operand (operands[1], SImode))
    && !(register_operand (operands[1], SImode)
         && reg_or_subregno (operands[1]) == VL_REGNUM))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])\n\
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_ZFH || TARGET_ZHINX) && (Pmode == DImode))",
    __builtin_constant_p (
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
  { "(USE_LOAD_ADDRESS_MACRO (operands[0])) && ((TARGET_64BIT) && (Pmode == SImode))",
    __builtin_constant_p (
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "(TARGET_ZBS && TARGET_ZBB) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])\n\
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (Pmode == SImode))",
    __builtin_constant_p (
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "(USE_LOAD_ADDRESS_MACRO (operands[0])) && (Pmode == SImode)",
    __builtin_constant_p (
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
    ? (int) (
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
    : -1 },
  { "(TARGET_VECTOR) && ((TARGET_64BIT && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_FP_64))",
    __builtin_constant_p (
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
    ? (int) (
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)))
    : -1 },
  { "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (Pmode == DImode)",
    __builtin_constant_p (
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
    ? (int) (
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
    : -1 },
  { "(TARGET_ZBA) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 37 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBA) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 37 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBA) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
#line 2757 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "! TARGET_64BIT",
    __builtin_constant_p 
#line 2757 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(! TARGET_64BIT)
    ? (int) 
#line 2757 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(! TARGET_64BIT)
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "!TARGET_DOUBLE_FLOAT\n\
   && (register_operand (operands[0], DFmode)\n\
       || reg_or_0_operand (operands[1], DFmode))",
    __builtin_constant_p 
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_DOUBLE_FLOAT
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode)))
    ? (int) 
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_DOUBLE_FLOAT
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode)))
    : -1 },
#line 2328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV",
    __builtin_constant_p 
#line 2328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU || TARGET_XTHEADCONDMOV)
    ? (int) 
#line 2328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU || TARGET_XTHEADCONDMOV)
    : -1 },
#line 1485 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_DOUBLE_FLOAT || TARGET_ZDINX",
    __builtin_constant_p 
#line 1485 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)
    ? (int) 
#line 1485 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)
    : -1 },
  { "((TARGET_VECTOR) && (TARGET_VECTOR_ELEN_FP_32)) && ( reload_completed)",
    __builtin_constant_p ((
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 202 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 467 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    ? (int) ((
#line 465 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 202 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 467 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    : -1 },
  { "(((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))\n\
    && popcount_hwi (INTVAL (operands[3])) > 1\n\
    && !SMALL_OPERAND (INTVAL (operands[3]))) && (((((TARGET_64BIT) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT))) && ( reload_completed)",
    __builtin_constant_p ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && ((((
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    ? (int) ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && ((((
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    : -1 },
#line 1371 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_64BIT && !TARGET_ZBA\n\
   && !(register_operand (operands[1], SImode)\n\
        && reg_or_subregno (operands[1]) == VL_REGNUM)",
    __builtin_constant_p 
#line 1371 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && !(register_operand (operands[1], SImode)
        && reg_or_subregno (operands[1]) == VL_REGNUM))
    ? (int) 
#line 1371 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && !(register_operand (operands[1], SImode)
        && reg_or_subregno (operands[1]) == VL_REGNUM))
    : -1 },
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
  { "TARGET_XTHEADMEMPAIR && TARGET_64BIT\n\
  && th_mempair_operands_p (operands, true, SImode)",
    __builtin_constant_p 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR && TARGET_64BIT
  && th_mempair_operands_p (operands, true, SImode))
    ? (int) 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR && TARGET_64BIT
  && th_mempair_operands_p (operands, true, SImode))
    : -1 },
  { "(TARGET_ZBS) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 603 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 603 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(TARGET_VECTOR) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 7018 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    ? (int) (
#line 7018 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    : -1 },
  { "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && ((TARGET_64BIT) && (Pmode == DImode))",
    __builtin_constant_p (
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
#line 1954 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_ZIFENCEI",
    __builtin_constant_p 
#line 1954 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZIFENCEI)
    ? (int) 
#line 1954 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZIFENCEI)
    : -1 },
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))",
    __builtin_constant_p 
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1])))
    ? (int) 
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1])))
    : -1 },
  { "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 76 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 76 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_VECTOR\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
  { "(TARGET_VECTOR) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 6955 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 6955 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
#line 213 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
  { "TARGET_ZKND && TARGET_64BIT",
    __builtin_constant_p 
#line 213 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKND && TARGET_64BIT)
    ? (int) 
#line 213 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKND && TARGET_64BIT)
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
#line 231 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
  { "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT",
    __builtin_constant_p 
#line 231 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
((TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT)
    ? (int) 
#line 231 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
((TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT)
    : -1 },
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "register_operand (operands[3], SImode)\n\
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)",
    __builtin_constant_p 
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], SImode)
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode))
    ? (int) 
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], SImode)
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode))
    : -1 },
  { "(TARGET_XTHEADMEMPAIR && reload_completed\n\
   && th_mempair_operands_p (operands, true, DImode)) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 304 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, true, DImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 304 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, true, DImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (((TARGET_64BIT) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX))",
    __builtin_constant_p (
#line 2524 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
    ? (int) (
#line 2524 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
    : -1 },
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "!(p2m1_shift_operand (operands[1], SImode)\n\
     || high_mask_shift_operand (operands[1], SImode))",
    __builtin_constant_p 
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!(p2m1_shift_operand (operands[1], SImode)
     || high_mask_shift_operand (operands[1], SImode)))
    ? (int) 
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!(p2m1_shift_operand (operands[1], SImode)
     || high_mask_shift_operand (operands[1], SImode)))
    : -1 },
  { "(TARGET_ZKSED) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 433 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSED) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 433 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSED) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (((TARGET_64BIT) && (TARGET_ZFH || TARGET_ZHINX)) && (TARGET_ZFH || TARGET_ZHINX))",
    __builtin_constant_p (
#line 2524 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
    ? (int) (
#line 2524 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 258 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
  { "(TARGET_XTHEADBB && (TARGET_64BIT || DImode == SImode)) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB && (TARGET_64BIT || DImode == SImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB && (TARGET_64BIT || DImode == SImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_64)) && ( register_operand (operands[0], VNx8DImode)\n\
   && register_operand (operands[3], VNx8DImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8DImode)
   && register_operand (operands[3], VNx8DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8DImode)
   && register_operand (operands[3], VNx8DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "((TARGET_ZBS) && (!TARGET_64BIT)) && ( reload_completed)",
    __builtin_constant_p ((
#line 646 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    ? (int) ((
#line 646 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 648 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    : -1 },
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
  { "TARGET_ZBKB && !TARGET_64BIT",
    __builtin_constant_p 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB && !TARGET_64BIT)
    ? (int) 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB && !TARGET_64BIT)
    : -1 },
  { "((!SMALL_OPERAND (INTVAL (operands[3]))) && (((((TARGET_64BIT) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT))) && ( reload_completed)",
    __builtin_constant_p ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && ((((
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    ? (int) ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && ((((
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    : -1 },
  { "((TARGET_VECTOR && (lra_in_progress || reload_completed)) && (Pmode == SImode)) && ( reload_completed)",
    __builtin_constant_p ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    ? (int) ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    : -1 },
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "!TARGET_ZBB",
    __builtin_constant_p 
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB)
    ? (int) 
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB)
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && 
#line 289 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
#line 6955 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR",
    __builtin_constant_p 
#line 6955 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR)
    ? (int) 
#line 6955 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR)
    : -1 },
  { "(TARGET_ZBB || TARGET_XTHEADBB) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_XTHEADBB) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_XTHEADBB) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (((!TARGET_64BIT) && (TARGET_ZFH || TARGET_ZHINX)) && (TARGET_ZFH || TARGET_ZHINX))",
    __builtin_constant_p (
#line 2524 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
    ? (int) (
#line 2524 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
    : -1 },
  { "(TARGET_ZBB || TARGET_ZBKB) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 377 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 377 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])\n\
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (Pmode == SImode))",
    __builtin_constant_p (
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "(TARGET_VECTOR) && ((TARGET_64BIT && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_64))",
    __builtin_constant_p (
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 326 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    ? (int) (
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32) && 
#line 326 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)))
    : -1 },
  { "(TARGET_VECTOR) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN == 32)",
    __builtin_constant_p (
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 378 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN == 32))
    ? (int) (
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 378 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN == 32))
    : -1 },
  { "(TARGET_VECTOR) && ((TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))",
    __builtin_constant_p (
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 365 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 333 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
    ? (int) (
#line 1631 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && (
#line 365 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 333 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)))
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 264 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_ZKSH) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 263 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 4073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 4073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
#line 137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_64BIT && TARGET_ZBA",
    __builtin_constant_p 
#line 137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA)
    ? (int) 
#line 137 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA)
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])\n\
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (Pmode == DImode))",
    __builtin_constant_p (
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_64)) && ( register_operand (operands[0], VNx1DImode)\n\
   && register_operand (operands[3], VNx1DImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1DImode)
   && register_operand (operands[3], VNx1DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 89 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1DImode)
   && register_operand (operands[3], VNx1DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 4052 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 4052 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
  { "((!(p2m1_shift_operand (operands[1], DImode)\n\
     || high_mask_shift_operand (operands[1], DImode))) && (TARGET_64BIT)) && ( 1)",
    __builtin_constant_p ((
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!(p2m1_shift_operand (operands[1], DImode)
     || high_mask_shift_operand (operands[1], DImode))) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 1697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1))
    ? (int) ((
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!(p2m1_shift_operand (operands[1], DImode)
     || high_mask_shift_operand (operands[1], DImode))) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 1697 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])\n\
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (Pmode == DImode))",
    __builtin_constant_p (
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (DFmode)) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)",
    __builtin_constant_p (
#line 1190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (DFmode)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))
    ? (int) (
#line 1190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (DFmode)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx32QImode)\n\
   && register_operand (operands[3], VNx32QImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx32QImode)
   && register_operand (operands[3], VNx32QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx32QImode)
   && register_operand (operands[3], VNx32QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 4073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 4073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
  { "((TARGET_VECTOR) && (Pmode == SImode)) && ( epilogue_completed)",
    __builtin_constant_p ((
#line 890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 892 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( epilogue_completed))
    ? (int) ((
#line 890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)) && 
#line 892 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( epilogue_completed))
    : -1 },
  { "(TARGET_64BIT\n\
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))\n\
       == GET_MODE_BITSIZE (DImode)-1) && ( 1)",
    __builtin_constant_p (
#line 2073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1) && 
#line 2077 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1))
    ? (int) (
#line 2073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1) && 
#line 2077 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1))
    : -1 },
  { "(TARGET_ZBKB) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_ZBS) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 618 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 618 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "((TARGET_VECTOR\n\
   && !rtx_equal_p (operands[2], operands[5])\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_64)) && ( reload_completed\n\
   && !rtx_equal_p (operands[0], operands[5]))",
    __builtin_constant_p ((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    ? (int) ((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])\n\
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (Pmode == SImode))",
    __builtin_constant_p (
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "((TARGET_VECTOR) && (TARGET_VECTOR_ELEN_64)) && ( reload_completed)",
    __builtin_constant_p ((
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 192 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    ? (int) ((
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 192 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    : -1 },
#line 1730 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_64BIT\n\
   && (register_operand (operands[0], DImode)\n\
       || reg_or_0_operand (operands[1], DImode))",
    __builtin_constant_p 
#line 1730 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (register_operand (operands[0], DImode)
       || reg_or_0_operand (operands[1], DImode)))
    ? (int) 
#line 1730 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (register_operand (operands[0], DImode)
       || reg_or_0_operand (operands[1], DImode)))
    : -1 },
  { "((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))\n\
    && popcount_hwi (INTVAL (operands[3])) > 1\n\
    && !SMALL_OPERAND (INTVAL (operands[3]))) && (((((TARGET_64BIT) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT))",
    __builtin_constant_p (
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && ((((
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
    ? (int) (
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && ((((
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)))
    : -1 },
  { "(TARGET_VECTOR) && (TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 6688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 419 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 6688 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 419 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32))
    : -1 },
  { "(TARGET_ZICBOZ) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 3109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOZ) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 3109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOZ) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT  || TARGET_ZFINX) && ((TARGET_64BIT) && (TARGET_ZFH || TARGET_ZHINX))",
    __builtin_constant_p (
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
    ? (int) (
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
    : -1 },
#line 170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
  { "!TARGET_64BIT && TARGET_XTHEADFMV",
    __builtin_constant_p 
#line 170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(!TARGET_64BIT && TARGET_XTHEADFMV)
    ? (int) 
#line 170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(!TARGET_64BIT && TARGET_XTHEADFMV)
    : -1 },
  { "(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 6765 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
  { "(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    ? (int) (
#line 6890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_HARD_FLOAT  || TARGET_ZFINX) && ((TARGET_64BIT) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX))",
    __builtin_constant_p (
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
    ? (int) (
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX)))
    : -1 },
#line 2131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_64BIT\n\
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))\n\
       == GET_MODE_BITSIZE (SImode)-1",
    __builtin_constant_p 
#line 2131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1)
    ? (int) 
#line 2131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1)
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_MIN_VLEN > 32)) && ( register_operand (operands[0], VNx64QImode)\n\
   && register_operand (operands[3], VNx64QImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx64QImode)
   && register_operand (operands[3], VNx64QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx64QImode)
   && register_operand (operands[3], VNx64QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
#line 367 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB)",
    __builtin_constant_p 
#line 367 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB))
    ? (int) 
#line 367 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB))
    : -1 },
#line 1908 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "reload_completed\n\
   && riscv_split_64bit_move_p (operands[0], operands[1])",
    __builtin_constant_p 
#line 1908 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed
   && riscv_split_64bit_move_p (operands[0], operands[1]))
    ? (int) 
#line 1908 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(reload_completed
   && riscv_split_64bit_move_p (operands[0], operands[1]))
    : -1 },
  { "(!SMALL_OPERAND (INTVAL (operands[3]))) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
#line 228 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_ZBB || TARGET_ZBKB",
    __builtin_constant_p 
#line 228 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB)
    ? (int) 
#line 228 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB)
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))) && 
#line 232 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && ( register_operand (operands[0], VNx16SFmode)\n\
   && register_operand (operands[3], VNx16SFmode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16SFmode)
   && register_operand (operands[3], VNx16SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16SFmode)
   && register_operand (operands[3], VNx16SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_VECTOR) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 7018 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 7018 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((TARGET_64BIT) && (TARGET_HARD_FLOAT || TARGET_ZFINX))",
    __builtin_constant_p (
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
    ? (int) (
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX)))
    : -1 },
  { "((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (HFmode)) && (TARGET_ZFH || TARGET_ZHINX)",
    __builtin_constant_p (
#line 1190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (HFmode)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))
    ? (int) (
#line 1190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (HFmode)) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))
    : -1 },
  { "(TARGET_VECTOR\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 5016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 5016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
  { "((TARGET_VECTOR\n\
   && !rtx_equal_p (operands[2], operands[5])\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && ( reload_completed\n\
   && !rtx_equal_p (operands[0], operands[5]))",
    __builtin_constant_p ((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    ? (int) ((
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 5860 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    : -1 },
  { "(TARGET_VECTOR\n\
   && !rtx_equal_p (operands[2], operands[5])\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 5853 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
  { "((TARGET_VECTOR\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_MIN_VLEN > 32)) && ( reload_completed\n\
   && !rtx_equal_p (operands[0], operands[5]))",
    __builtin_constant_p ((
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    ? (int) ((
#line 4867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4875 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_64)) && ( register_operand (operands[0], VNx4DFmode)\n\
   && register_operand (operands[3], VNx4DFmode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4DFmode)
   && register_operand (operands[3], VNx4DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4DFmode)
   && register_operand (operands[3], VNx4DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx4SImode)\n\
   && register_operand (operands[3], VNx4SImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4SImode)
   && register_operand (operands[3], VNx4SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4SImode)
   && register_operand (operands[3], VNx4SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))\n\
    && popcount_hwi (INTVAL (operands[3])) > 1\n\
    && !SMALL_OPERAND (INTVAL (operands[3]))) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_VECTOR\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    ? (int) (
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    : -1 },
#line 30 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
  { "TARGET_64BIT\n\
   && INTVAL (operands[5]) < INTVAL (operands[2])\n\
   && (REGNO (operands[3]) == REGNO (operands[4])\n\
       || peep2_reg_dead_p (3, operands[3]))",
    __builtin_constant_p 
#line 30 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_64BIT
   && INTVAL (operands[5]) < INTVAL (operands[2])
   && (REGNO (operands[3]) == REGNO (operands[4])
       || peep2_reg_dead_p (3, operands[3])))
    ? (int) 
#line 30 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_64BIT
   && INTVAL (operands[5]) < INTVAL (operands[2])
   && (REGNO (operands[3]) == REGNO (operands[4])
       || peep2_reg_dead_p (3, operands[3])))
    : -1 },
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
  { "TARGET_64BIT",
    __builtin_constant_p 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)
    ? (int) 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)
    : -1 },
  { "(TARGET_VECTOR\n\
   && !rtx_equal_p (operands[2], operands[5])\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && ( reload_completed\n\
   && !rtx_equal_p (operands[0], operands[5]))",
    __builtin_constant_p (
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    ? (int) (
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    : -1 },
  { "(register_operand (operands[3], DImode)\n\
  && GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode)) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], DImode)
  && GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], DImode)
  && GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
  { "(TARGET_ZICBOP) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 3131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOP) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 3131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOP) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (Pmode == SImode)",
    __builtin_constant_p (
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
    ? (int) (
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
#line 1064 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_DIV && TARGET_64BIT",
    __builtin_constant_p 
#line 1064 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV && TARGET_64BIT)
    ? (int) 
#line 1064 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_DIV && TARGET_64BIT)
    : -1 },
  { "(TARGET_ZICBOM) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 3102 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOM) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 3102 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOM) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
#line 304 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
  { "TARGET_XTHEADMEMPAIR && reload_completed\n\
   && th_mempair_operands_p (operands, true, SImode)",
    __builtin_constant_p 
#line 304 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, true, SImode))
    ? (int) 
#line 304 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, true, SImode))
    : -1 },
#line 1888 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_64BIT && TARGET_DOUBLE_FLOAT\n\
   && (register_operand (operands[0], DFmode)\n\
       || reg_or_0_operand (operands[1], DFmode))",
    __builtin_constant_p 
#line 1888 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && TARGET_DOUBLE_FLOAT
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode)))
    ? (int) 
#line 1888 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && TARGET_DOUBLE_FLOAT
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode)))
    : -1 },
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "register_operand (operands[3], HImode)\n\
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)",
    __builtin_constant_p 
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], HImode)
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode))
    ? (int) 
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], HImode)
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_64)) && ( register_operand (operands[0], VNx1DFmode)\n\
   && register_operand (operands[3], VNx1DFmode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1DFmode)
   && register_operand (operands[3], VNx1DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 96 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1DFmode)
   && register_operand (operands[3], VNx1DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode))) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode))) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode))) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx1SImode)\n\
   && register_operand (operands[3], VNx1SImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1SImode)
   && register_operand (operands[3], VNx1SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx1SImode)
   && register_operand (operands[3], VNx1SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
#line 2780 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "epilogue_completed",
    __builtin_constant_p 
#line 2780 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(epilogue_completed)
    ? (int) 
#line 2780 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(epilogue_completed)
    : -1 },
  { "(TARGET_XTHEADMEMPAIR\n\
  && th_mempair_operands_p (operands, false, DImode)) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 62 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, false, DImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 62 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, false, DImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_SFB_ALU) && (((((TARGET_64BIT) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (TARGET_64BIT)) && (TARGET_64BIT))",
    __builtin_constant_p (
#line 2345 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU) && ((((
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
    ? (int) (
#line 2345 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU) && ((((
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
    : -1 },
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
  { "TARGET_ZKNH && !TARGET_64BIT",
    __builtin_constant_p 
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && !TARGET_64BIT)
    ? (int) 
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && !TARGET_64BIT)
    : -1 },
#line 48 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
  { "TARGET_XTHEADMEMPAIR\n\
  && th_mempair_operands_p (operands, true, SImode)",
    __builtin_constant_p 
#line 48 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, true, SImode))
    ? (int) 
#line 48 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, true, SImode))
    : -1 },
  { "(TARGET_64BIT && !TARGET_ZBA\n\
   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)) && ( reload_completed)",
    __builtin_constant_p (
#line 2236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)) && 
#line 2239 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    ? (int) (
#line 2236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)) && 
#line 2239 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    : -1 },
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "register_operand (operands[3], QImode)\n\
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)",
    __builtin_constant_p 
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode))
    ? (int) 
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx16QImode)\n\
   && register_operand (operands[3], VNx16QImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16QImode)
   && register_operand (operands[3], VNx16QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16QImode)
   && register_operand (operands[3], VNx16QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_VECTOR) && (((((Pmode == SImode) && (TARGET_MIN_VLEN > 32)) && (TARGET_MIN_VLEN > 32)) && (TARGET_MIN_VLEN > 32)) && (TARGET_MIN_VLEN > 32))",
    __builtin_constant_p (
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && ((((
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
    ? (int) (
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && ((((
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
    : -1 },
  { "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && ((TARGET_ZFHMIN) && (Pmode == SImode))",
    __builtin_constant_p (
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFHMIN) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 119 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (
#line 71 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFHMIN) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "(!TARGET_ZBB) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))\n\
    && popcount_hwi (INTVAL (operands[3])) > 1\n\
    && !SMALL_OPERAND (INTVAL (operands[3]))) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(TARGET_ZBKX) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 165 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKX) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 165 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKX) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])\n\
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (Pmode == SImode))",
    __builtin_constant_p (
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
  { "(TARGET_VECTOR) && (((((Pmode == DImode) && (TARGET_MIN_VLEN > 32)) && (TARGET_MIN_VLEN > 32)) && (TARGET_MIN_VLEN > 32)) && (TARGET_MIN_VLEN > 32))",
    __builtin_constant_p (
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && ((((
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
    ? (int) (
#line 5302 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && ((((
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)))
    : -1 },
#line 2236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_64BIT && !TARGET_ZBA\n\
   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)",
    __builtin_constant_p 
#line 2236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff))
    ? (int) 
#line 2236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && !TARGET_ZBA
   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff))
    : -1 },
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && TARGET_MIN_VLEN == 32",
    __builtin_constant_p 
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32)
    ? (int) 
#line 6823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN == 32)
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])\n\
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_ZFH || TARGET_ZHINX) && (Pmode == DImode))",
    __builtin_constant_p (
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)",
    __builtin_constant_p (
#line 2502 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))
    ? (int) (
#line 2502 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 4052 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 4052 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
#line 3170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_XTHEADMAC",
    __builtin_constant_p 
#line 3170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_XTHEADMAC)
    ? (int) 
#line 3170 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_XTHEADMAC)
    : -1 },
  { "(TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (SImode)) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 101 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (SImode)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 101 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (SImode)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "!TARGET_HARD_FLOAT\n\
   && (register_operand (operands[0], SFmode)\n\
       || reg_or_0_operand (operands[1], SFmode))",
    __builtin_constant_p 
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_HARD_FLOAT
   && (register_operand (operands[0], SFmode)
       || reg_or_0_operand (operands[1], SFmode)))
    ? (int) 
#line 1854 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_HARD_FLOAT
   && (register_operand (operands[0], SFmode)
       || reg_or_0_operand (operands[1], SFmode)))
    : -1 },
  { "(riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)) && (Pmode == SImode)",
    __builtin_constant_p (
#line 1680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
    ? (int) (
#line 1680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
    : -1 },
#line 388 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_ZBB",
    __builtin_constant_p 
#line 388 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB)
    ? (int) 
#line 388 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB)
    : -1 },
  { "(TARGET_SFB_ALU || TARGET_XTHEADCONDMOV) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 2328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU || TARGET_XTHEADCONDMOV) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 2328 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU || TARGET_XTHEADCONDMOV) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "((TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && (Pmode == SImode))) && ( reload_completed)",
    __builtin_constant_p ((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    ? (int) ((
#line 658 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))) && 
#line 660 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    : -1 },
  { "(TARGET_VECTOR) && ( register_operand (operands[0], VNx32BImode)\n\
   && register_operand (operands[3], VNx32BImode)\n\
   && INTVAL (operands[5]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx32BImode)
   && register_operand (operands[3], VNx32BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    ? (int) (
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx32BImode)
   && register_operand (operands[3], VNx32BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    : -1 },
#line 548 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
  { "TARGET_ATOMIC",
    __builtin_constant_p 
#line 548 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC)
    ? (int) 
#line 548 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC)
    : -1 },
  { "(TARGET_ZKSH) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKSH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx2SImode)\n\
   && register_operand (operands[3], VNx2SImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2SImode)
   && register_operand (operands[3], VNx2SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2SImode)
   && register_operand (operands[3], VNx2SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_64BIT && TARGET_ZBA\n\
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))\n\
   && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2]))",
    __builtin_constant_p 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2])))
    ? (int) 
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2])))
    : -1 },
  { "(known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode))) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode))) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode))) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_MIN_VLEN > 32) && (Pmode == SImode))",
    __builtin_constant_p (
#line 651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "(TARGET_ZMMUL || TARGET_MUL) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 839 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZMMUL || TARGET_MUL) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 839 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZMMUL || TARGET_MUL) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (TARGET_64BIT))",
    __builtin_constant_p (
#line 1568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
    ? (int) (
#line 1568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
    : -1 },
  { "((TARGET_VECTOR\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && ( reload_completed\n\
   && !rtx_equal_p (operands[0], operands[5]))",
    __builtin_constant_p ((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    ? (int) ((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 4073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 4073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
  { "(TARGET_VECTOR) && (TARGET_MIN_VLEN == 32)",
    __builtin_constant_p (
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 375 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN == 32))
    ? (int) (
#line 605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 375 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN == 32))
    : -1 },
  { "(TARGET_ZBA) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 37 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBA) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 37 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBA) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
#line 2151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_64BIT && (INTVAL (operands[2]) & 0x1f) > 0",
    __builtin_constant_p 
#line 2151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && (INTVAL (operands[2]) & 0x1f) > 0)
    ? (int) 
#line 2151 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_64BIT && (INTVAL (operands[2]) & 0x1f) > 0)
    : -1 },
  { "(TARGET_VECTOR) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 7018 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 7018 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
  { "((TARGET_64BIT) && (!TARGET_64BIT)) && (!TARGET_64BIT)",
    __builtin_constant_p ((
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) ((
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (Pmode == SImode)",
    __builtin_constant_p (
#line 651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
    ? (int) (
#line 651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode))
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((TARGET_64BIT) && (TARGET_ZFH || TARGET_ZHINX))",
    __builtin_constant_p (
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
    ? (int) (
#line 1578 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX)))
    : -1 },
  { "(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(TARGET_VECTOR) && ( register_operand (operands[0], VNx16BImode)\n\
   && register_operand (operands[3], VNx16BImode)\n\
   && INTVAL (operands[5]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16BImode)
   && register_operand (operands[3], VNx16BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    ? (int) (
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16BImode)
   && register_operand (operands[3], VNx16BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    : -1 },
  { "((!SMALL_OPERAND (INTVAL (operands[3]))) && (TARGET_64BIT)) && ( reload_completed)",
    __builtin_constant_p ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    ? (int) ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    : -1 },
  { "((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (DFmode)) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)",
    __builtin_constant_p (
#line 1250 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (DFmode)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))
    ? (int) (
#line 1250 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (DFmode)) && 
#line 67 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX))
    : -1 },
  { "((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (SFmode)) && (TARGET_HARD_FLOAT || TARGET_ZFINX)",
    __builtin_constant_p (
#line 1190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (SFmode)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
    ? (int) (
#line 1190 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (SFmode)) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
    : -1 },
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_64BIT && TARGET_ZBB",
    __builtin_constant_p 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB)
    ? (int) 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBB)
    : -1 },
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
  { "USE_LOAD_ADDRESS_MACRO (operands[1])",
    __builtin_constant_p 
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1]))
    ? (int) 
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1]))
    : -1 },
#line 198 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_ZBB || (!TARGET_64BIT && TARGET_XTHEADBB)",
    __builtin_constant_p 
#line 198 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || (!TARGET_64BIT && TARGET_XTHEADBB))
    ? (int) 
#line 198 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || (!TARGET_64BIT && TARGET_XTHEADBB))
    : -1 },
  { "(TARGET_VECTOR) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 7094 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 7094 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode))",
    __builtin_constant_p 
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode)))
    ? (int) 
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode)))
    : -1 },
#line 372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "(!TARGET_64BIT && TARGET_ZBB) || TARGET_XTHEADBB",
    __builtin_constant_p 
#line 372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
((!TARGET_64BIT && TARGET_ZBB) || TARGET_XTHEADBB)
    ? (int) 
#line 372 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
((!TARGET_64BIT && TARGET_ZBB) || TARGET_XTHEADBB)
    : -1 },
#line 618 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
  { "TARGET_ZBS",
    __builtin_constant_p 
#line 618 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS)
    ? (int) 
#line 618 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS)
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_MIN_VLEN > 32)) && ( register_operand (operands[0], VNx16SImode)\n\
   && register_operand (operands[3], VNx16SImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16SImode)
   && register_operand (operands[3], VNx16SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 88 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16SImode)
   && register_operand (operands[3], VNx16SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(USE_LOAD_ADDRESS_MACRO (operands[1])) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 42 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[1])) && 
#line 57 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "((TARGET_VECTOR\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_64)) && ( reload_completed\n\
   && !rtx_equal_p (operands[0], operands[5]))",
    __builtin_constant_p ((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    ? (int) ((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 265 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    : -1 },
  { "(TARGET_64BIT) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])\n\
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && ((TARGET_ZFH || TARGET_ZHINX) && (Pmode == DImode))",
    __builtin_constant_p (
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 110 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
  { "(!(p2m1_shift_operand (operands[1], DImode)\n\
     || high_mask_shift_operand (operands[1], DImode))) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!(p2m1_shift_operand (operands[1], DImode)
     || high_mask_shift_operand (operands[1], DImode))) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 1694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!(p2m1_shift_operand (operands[1], DImode)
     || high_mask_shift_operand (operands[1], DImode))) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_64BIT && TARGET_ZBA\n\
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))\n\
   && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2]))) && ( reload_completed)",
    __builtin_constant_p (
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2]))) && 
#line 102 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    ? (int) (
#line 98 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2]))) && 
#line 102 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    : -1 },
  { "(TARGET_64BIT && TARGET_ZBS\n\
   && clz_hwi (~UINTVAL (operands[2])) > 33) && ( reload_completed)",
    __builtin_constant_p (
#line 532 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBS
   && clz_hwi (~UINTVAL (operands[2])) > 33) && 
#line 535 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    ? (int) (
#line 532 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_64BIT && TARGET_ZBS
   && clz_hwi (~UINTVAL (operands[2])) > 33) && 
#line 535 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    : -1 },
  { "(TARGET_XTHEADBB) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 3148 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_XTHEADBB) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 3148 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_XTHEADBB) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_64)) && ( register_operand (operands[0], VNx8DFmode)\n\
   && register_operand (operands[3], VNx8DFmode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8DFmode)
   && register_operand (operands[3], VNx8DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 99 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8DFmode)
   && register_operand (operands[3], VNx8DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx4QImode)\n\
   && register_operand (operands[3], VNx4QImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4QImode)
   && register_operand (operands[3], VNx4QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4QImode)
   && register_operand (operands[3], VNx4QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
#line 125 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
  { "TARGET_ZBKB && TARGET_64BIT",
    __builtin_constant_p 
#line 125 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB && TARGET_64BIT)
    ? (int) 
#line 125 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB && TARGET_64BIT)
    : -1 },
  { "(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
  { "Pmode == SImode",
    __builtin_constant_p 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)
    ? (int) 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)
    : -1 },
#line 945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT",
    __builtin_constant_p 
#line 945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT)
    ? (int) 
#line 945 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT)
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_ZKNH) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])\n\
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (Pmode == DImode))",
    __builtin_constant_p (
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
  { "((!SMALL_OPERAND (INTVAL (operands[3]))) && (!TARGET_64BIT)) && ( reload_completed)",
    __builtin_constant_p ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    ? (int) ((
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 2268 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && 
#line 288 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "((TARGET_VECTOR\n\
   && !rtx_equal_p (operands[2], operands[5])\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_64)) && ( reload_completed\n\
   && !rtx_equal_p (operands[0], operands[5]))",
    __builtin_constant_p ((
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    ? (int) ((
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx2QImode)\n\
   && register_operand (operands[3], VNx2QImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2QImode)
   && register_operand (operands[3], VNx2QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2QImode)
   && register_operand (operands[3], VNx2QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "((TARGET_ZBS && TARGET_ZBB) && (!TARGET_64BIT)) && ( reload_completed)",
    __builtin_constant_p ((
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 673 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    ? (int) ((
#line 671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 673 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    : -1 },
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR\n\
   && !rtx_equal_p (operands[2], operands[5])\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])",
    __builtin_constant_p 
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5]))
    ? (int) 
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5]))
    : -1 },
#line 2829 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "SIBLING_CALL_P (insn)",
    __builtin_constant_p 
#line 2829 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(SIBLING_CALL_P (insn))
    ? (int) 
#line 2829 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(SIBLING_CALL_P (insn))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    ? (int) (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx16HImode)\n\
   && register_operand (operands[3], VNx16HImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16HImode)
   && register_operand (operands[3], VNx16HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx16HImode)
   && register_operand (operands[3], VNx16HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (Pmode == DImode)",
    __builtin_constant_p (
#line 651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
    ? (int) (
#line 651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
    : -1 },
#line 472 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
  { "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC",
    __builtin_constant_p 
#line 472 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC)
    ? (int) 
#line 472 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC)
    : -1 },
#line 1476 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_ZFHMIN || TARGET_ZHINXMIN",
    __builtin_constant_p 
#line 1476 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZFHMIN || TARGET_ZHINXMIN)
    ? (int) 
#line 1476 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZFHMIN || TARGET_ZHINXMIN)
    : -1 },
#line 62 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
  { "TARGET_XTHEADMEMPAIR\n\
  && th_mempair_operands_p (operands, false, SImode)",
    __builtin_constant_p 
#line 62 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, false, SImode))
    ? (int) 
#line 62 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, false, SImode))
    : -1 },
  { "(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (TARGET_ZFH || TARGET_ZHINX)",
    __builtin_constant_p (
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))
    ? (int) (
#line 1550 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT  || TARGET_ZFINX) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))
    : -1 },
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))",
    __builtin_constant_p 
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode)))
    ? (int) 
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode)))
    : -1 },
  { "((TARGET_VECTOR\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32)) && ( reload_completed\n\
   && !rtx_equal_p (operands[0], operands[5]))",
    __builtin_constant_p ((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    ? (int) ((
#line 5978 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 5984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    : -1 },
  { "(TARGET_VECTOR) && (TARGET_64BIT && TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32))
    ? (int) (
#line 1614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 361 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_64BIT && TARGET_MIN_VLEN > 32))
    : -1 },
#line 1513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_ZFHMIN\n\
   && (register_operand (operands[0], HFmode)\n\
       || reg_or_0_operand (operands[1], HFmode))",
    __builtin_constant_p 
#line 1513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZFHMIN
   && (register_operand (operands[0], HFmode)
       || reg_or_0_operand (operands[1], HFmode)))
    ? (int) 
#line 1513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZFHMIN
   && (register_operand (operands[0], HFmode)
       || reg_or_0_operand (operands[1], HFmode)))
    : -1 },
#line 2166 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "(TARGET_64BIT && (INTVAL (operands[3]) > 0)\n\
    && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))",
    __builtin_constant_p 
#line 2166 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_64BIT && (INTVAL (operands[3]) > 0)
    && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32)))
    ? (int) 
#line 2166 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_64BIT && (INTVAL (operands[3]) > 0)
    && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32)))
    : -1 },
  { "(TARGET_ZBKC) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 145 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
#line 1009 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT",
    __builtin_constant_p 
#line 1009 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT)
    ? (int) 
#line 1009 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT)
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
#line 1998 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "(INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))\n\
   == GET_MODE_BITSIZE (SImode)-1",
    __builtin_constant_p 
#line 1998 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
   == GET_MODE_BITSIZE (SImode)-1)
    ? (int) 
#line 1998 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
   == GET_MODE_BITSIZE (SImode)-1)
    : -1 },
  { "(TARGET_XTHEADCONDMOV) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADCONDMOV) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 135 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADCONDMOV) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
#line 271 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
  { "TARGET_ZKNE && TARGET_64BIT",
    __builtin_constant_p 
#line 271 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNE && TARGET_64BIT)
    ? (int) 
#line 271 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNE && TARGET_64BIT)
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 4073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 4073 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
  { "(TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && (Pmode == DImode))",
    __builtin_constant_p (
#line 643 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    ? (int) (
#line 643 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)))
    : -1 },
  { "(known_gt (GET_MODE_BITSIZE (DImode), GET_MODE_BITSIZE (Pmode))) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (DImode), GET_MODE_BITSIZE (Pmode))) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 6974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(known_gt (GET_MODE_BITSIZE (DImode), GET_MODE_BITSIZE (Pmode))) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
  { "!TARGET_64BIT",
    __builtin_constant_p 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)
    ? (int) 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32)) && ( register_operand (operands[0], VNx4SFmode)\n\
   && register_operand (operands[3], VNx4SFmode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4SFmode)
   && register_operand (operands[3], VNx4SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 93 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4SFmode)
   && register_operand (operands[3], VNx4SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "((TARGET_VECTOR) && (Pmode == DImode)) && ( epilogue_completed)",
    __builtin_constant_p ((
#line 890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 892 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( epilogue_completed))
    ? (int) ((
#line 890 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode)) && 
#line 892 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( epilogue_completed))
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(register_operand (operands[3], SImode)\n\
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], SImode)
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], SImode)
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "(!SMALL_OPERAND (INTVAL (operands[3]))) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 2266 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3807 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])\n\
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_ZFH || TARGET_ZHINX) && (Pmode == SImode))",
    __builtin_constant_p (
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 53 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx8QImode)\n\
   && register_operand (operands[3], VNx8QImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8QImode)
   && register_operand (operands[3], VNx8QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8QImode)
   && register_operand (operands[3], VNx8QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "((INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))\n\
   == GET_MODE_BITSIZE (SImode)-1) && ( 1)",
    __builtin_constant_p (
#line 1998 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
   == GET_MODE_BITSIZE (SImode)-1) && 
#line 2001 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1))
    ? (int) (
#line 1998 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
   == GET_MODE_BITSIZE (SImode)-1) && 
#line 2001 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( 1))
    : -1 },
  { "(!TARGET_ZBB) && ( reload_completed\n\
   && REG_P (operands[1])\n\
   && !paradoxical_subreg_p (operands[0]))",
    __builtin_constant_p (
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 1458 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0])))
    ? (int) (
#line 1454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZBB) && 
#line 1458 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0])))
    : -1 },
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && TARGET_MIN_VLEN > 32",
    __builtin_constant_p 
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32)
    ? (int) 
#line 6932 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && TARGET_MIN_VLEN > 32)
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx8SImode)\n\
   && register_operand (operands[3], VNx8SImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8SImode)
   && register_operand (operands[3], VNx8SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8SImode)
   && register_operand (operands[3], VNx8SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_MIN_VLEN > 32)) && ( register_operand (operands[0], VNx32HImode)\n\
   && register_operand (operands[3], VNx32HImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx32HImode)
   && register_operand (operands[3], VNx32HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx32HImode)
   && register_operand (operands[3], VNx32HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx4HImode)\n\
   && register_operand (operands[3], VNx4HImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4HImode)
   && register_operand (operands[3], VNx4HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4HImode)
   && register_operand (operands[3], VNx4HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_64)) && ( register_operand (operands[0], VNx2DFmode)\n\
   && register_operand (operands[3], VNx2DFmode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2DFmode)
   && register_operand (operands[3], VNx2DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 97 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2DFmode)
   && register_operand (operands[3], VNx2DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(register_operand (operands[3], HImode)\n\
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)) && (TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], HImode)
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    ? (int) (
#line 1270 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(register_operand (operands[3], HImode)
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)) && 
#line 233 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_VECTOR) && ( register_operand (operands[0], VNx8BImode)\n\
   && register_operand (operands[3], VNx8BImode)\n\
   && INTVAL (operands[5]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8BImode)
   && register_operand (operands[3], VNx8BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    ? (int) (
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx8BImode)
   && register_operand (operands[3], VNx8BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)",
    __builtin_constant_p (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    ? (int) (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 261 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))
    : -1 },
  { "(TARGET_ZBB) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "((TARGET_VECTOR\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_64)) && ( reload_completed\n\
   && !rtx_equal_p (operands[0], operands[5]))",
    __builtin_constant_p ((
#line 5016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 5024 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    ? (int) ((
#line 5016 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 5024 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    : -1 },
  { "((TARGET_VECTOR) && (TARGET_VECTOR_ELEN_FP_64)) && ( reload_completed)",
    __builtin_constant_p ((
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 195 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    ? (int) ((
#line 452 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 195 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64)) && 
#line 454 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    : -1 },
  { "((TARGET_VECTOR\n\
   && !rtx_equal_p (operands[2], operands[5])\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_MIN_VLEN > 32)) && ( reload_completed\n\
   && !rtx_equal_p (operands[0], operands[5]))",
    __builtin_constant_p ((
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    ? (int) ((
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 234 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 4738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed
   && !rtx_equal_p (operands[0], operands[5])))
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx2HImode)\n\
   && register_operand (operands[3], VNx2HImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2HImode)
   && register_operand (operands[3], VNx2HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) (
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2HImode)
   && register_operand (operands[3], VNx2HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
  { "(TARGET_ZBKX) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 165 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKX) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 165 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKX) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(USE_LOAD_ADDRESS_MACRO (operands[0])) && (Pmode == DImode)",
    __builtin_constant_p (
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
    ? (int) (
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(USE_LOAD_ADDRESS_MACRO (operands[0])) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))
    : -1 },
  { "(TARGET_VECTOR) && ( register_operand (operands[0], VNx2BImode)\n\
   && register_operand (operands[3], VNx2BImode)\n\
   && INTVAL (operands[5]) == riscv_vector::VLMAX)",
    __builtin_constant_p (
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2BImode)
   && register_operand (operands[3], VNx2BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    ? (int) (
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx2BImode)
   && register_operand (operands[3], VNx2BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    : -1 },
  { "((TARGET_VECTOR) && (TARGET_MIN_VLEN > 32)) && ( register_operand (operands[0], VNx64BImode)\n\
   && register_operand (operands[3], VNx64BImode)\n\
   && INTVAL (operands[5]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx64BImode)
   && register_operand (operands[3], VNx64BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    ? (int) ((
#line 1039 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR) && 
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32)) && 
#line 1046 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx64BImode)
   && register_operand (operands[3], VNx64BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX))
    : -1 },
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
  { "TARGET_XTHEADBB && (TARGET_64BIT || SImode == SImode)",
    __builtin_constant_p 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB && (TARGET_64BIT || SImode == SImode))
    ? (int) 
#line 86 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB && (TARGET_64BIT || SImode == SImode))
    : -1 },
  { "(TARGET_ZBKB) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
#line 1494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "(TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) ||\n\
   (TARGET_ZHINXMIN && TARGET_ZDINX)",
    __builtin_constant_p 
#line 1494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) ||
   (TARGET_ZHINXMIN && TARGET_ZDINX))
    ? (int) 
#line 1494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) ||
   (TARGET_ZHINXMIN && TARGET_ZDINX))
    : -1 },
  { "(TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 2376 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 2376 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
#line 1780 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "(register_operand (operands[0], HImode)\n\
    || reg_or_0_operand (operands[1], HImode))",
    __builtin_constant_p 
#line 1780 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((register_operand (operands[0], HImode)
    || reg_or_0_operand (operands[1], HImode)))
    ? (int) 
#line 1780 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((register_operand (operands[0], HImode)
    || reg_or_0_operand (operands[1], HImode)))
    : -1 },
  { "(((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))\n\
    && popcount_hwi (INTVAL (operands[3])) > 1\n\
    && !SMALL_OPERAND (INTVAL (operands[3]))) && (TARGET_64BIT)) && ( reload_completed)",
    __builtin_constant_p ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    ? (int) ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 63 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 259 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
  { "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])\n\
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_ZFH || TARGET_ZHINX) && (Pmode == SImode))",
    __builtin_constant_p (
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    ? (int) (
#line 95 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md"
(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == SImode)))
    : -1 },
  { "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])\n\
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_64)) && ( register_operand (operands[0], VNx4DImode)\n\
   && register_operand (operands[3], VNx4DImode)\n\
   && satisfies_constraint_vu (operands[2])\n\
   && INTVAL (operands[7]) == riscv_vector::VLMAX)",
    __builtin_constant_p ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4DImode)
   && register_operand (operands[3], VNx4DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    ? (int) ((
#line 984 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && 
#line 90 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64)) && 
#line 995 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( register_operand (operands[0], VNx4DImode)
   && register_operand (operands[3], VNx4DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX))
    : -1 },
#line 3148 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_XTHEADBB",
    __builtin_constant_p 
#line 3148 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_XTHEADBB)
    ? (int) 
#line 3148 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_XTHEADBB)
    : -1 },
  { "(TARGET_XTHEADMEMPAIR && reload_completed\n\
   && th_mempair_operands_p (operands, false, DImode)) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 316 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, false, DImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 316 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, false, DImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_ZICBOZ) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 3109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOZ) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 3109 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOZ) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "((TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_MIN_VLEN > 32) && (Pmode == DImode))) && ( reload_completed)",
    __builtin_constant_p ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    ? (int) ((
#line 678 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (
#line 398 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_MIN_VLEN > 32) && 
#line 35 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(Pmode == DImode))) && 
#line 680 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
( reload_completed))
    : -1 },
  { "(TARGET_ZICBOP) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 3131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOP) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 3131 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOP) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_XTHEADMEMPAIR\n\
  && th_mempair_operands_p (operands, true, DImode)) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 48 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, true, DImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 48 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, true, DImode)) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
  { "(TARGET_ZBB || TARGET_ZBKB) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 377 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 377 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBB || TARGET_ZBKB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))\n\
    && popcount_hwi (INTVAL (operands[3])) > 1\n\
    && !SMALL_OPERAND (INTVAL (operands[3]))) && (!TARGET_64BIT)) && ( reload_completed)",
    __builtin_constant_p ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    ? (int) ((
#line 2290 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 2294 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
( reload_completed))
    : -1 },
  { "(TARGET_VECTOR\n\
   && !rtx_equal_p (operands[2], operands[5])\n\
   && !rtx_equal_p (operands[3], operands[5])\n\
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 4728 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && 
#line 236 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
  { "((TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && (!TARGET_64BIT)) && ( reload_completed)",
    __builtin_constant_p ((
#line 513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 515 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    ? (int) ((
#line 513 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT)) && 
#line 515 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
( reload_completed))
    : -1 },
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
  { "TARGET_ZKNH && TARGET_64BIT",
    __builtin_constant_p 
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && TARGET_64BIT)
    ? (int) 
#line 393 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH && TARGET_64BIT)
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
#line 1823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "(register_operand (operands[0], QImode)\n\
    || reg_or_0_operand (operands[1], QImode))",
    __builtin_constant_p 
#line 1823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((register_operand (operands[0], QImode)
    || reg_or_0_operand (operands[1], QImode)))
    ? (int) 
#line 1823 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((register_operand (operands[0], QImode)
    || reg_or_0_operand (operands[1], QImode)))
    : -1 },
#line 1523 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "!TARGET_ZFHMIN\n\
   && (register_operand (operands[0], HFmode)\n\
       || reg_or_0_operand (operands[1], HFmode))",
    __builtin_constant_p 
#line 1523 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZFHMIN
   && (register_operand (operands[0], HFmode)
       || reg_or_0_operand (operands[1], HFmode)))
    ? (int) 
#line 1523 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(!TARGET_ZFHMIN
   && (register_operand (operands[0], HFmode)
       || reg_or_0_operand (operands[1], HFmode)))
    : -1 },
  { "(TARGET_XTHEADMAC) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 243 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 243 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
  { "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((TARGET_ZFH || TARGET_ZHINX) && (TARGET_64BIT))",
    __builtin_constant_p (
#line 1568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
    ? (int) (
#line 1568 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX) && (
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT)))
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)",
    __builtin_constant_p (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    ? (int) (
#line 6429 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 262 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_64))
    : -1 },
  { "(TARGET_ATOMIC) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 384 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 384 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
(TARGET_ATOMIC) && 
#line 27 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && (TARGET_HARD_FLOAT || TARGET_ZFINX)",
    __builtin_constant_p (
#line 1088 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
    ? (int) (
#line 1088 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && 
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_HARD_FLOAT || TARGET_ZFINX))
    : -1 },
  { "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)",
    __builtin_constant_p (
#line 4052 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    ? (int) (
#line 4052 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && 
#line 295 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_64))
    : -1 },
  { "((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && (TARGET_ZFH || TARGET_ZHINX)",
    __builtin_constant_p (
#line 1088 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))
    ? (int) (
#line 1088 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && 
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_ZFH || TARGET_ZHINX))
    : -1 },
  { "(TARGET_XTHEADBB) && (!TARGET_64BIT)",
    __builtin_constant_p (
#line 78 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    ? (int) (
#line 78 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADBB) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(!TARGET_64BIT))
    : -1 },
#line 187 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
  { "TARGET_ZKND && !TARGET_64BIT",
    __builtin_constant_p 
#line 187 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKND && !TARGET_64BIT)
    ? (int) 
#line 187 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKND && !TARGET_64BIT)
    : -1 },
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
  { "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR)",
    __builtin_constant_p 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR))
    ? (int) 
#line 3828 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR))
    : -1 },
#line 3117 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
  { "TARGET_ZICBOP",
    __builtin_constant_p 
#line 3117 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOP)
    ? (int) 
#line 3117 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
(TARGET_ZICBOP)
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 257 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
  { "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)",
    __builtin_constant_p (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    ? (int) (
#line 6450 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && 
#line 260 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector-iterators.md"
(TARGET_VECTOR_ELEN_FP_32))
    : -1 },
  { "(TARGET_XTHEADMAC) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 243 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 243 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
(TARGET_XTHEADMAC) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { "(TARGET_ZKNH) && (TARGET_64BIT)",
    __builtin_constant_p (
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    ? (int) (
#line 305 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md"
(TARGET_ZKNH) && 
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/iterators.md"
(TARGET_64BIT))
    : -1 },
  { nullptr, -1 }
};
#endif /* gcc >= 3.0.1 */

int
main(void)
{
  unsigned int i;
  const char *p;
  puts ("(define_conditions [");
#if GCC_VERSION >= 3001
  for (i = 0; i < ARRAY_SIZE (insn_conditions) - 1; i++)
    {
      printf ("  (%d \"", insn_conditions[i].value);
      for (p = insn_conditions[i].expr; *p; p++)
        {
          switch (*p)
	     {
	     case '\\':
	     case '\"': putchar ('\\'); break;
	     default: break;
	     }
          putchar (*p);
        }
      puts ("\")");
    }
#endif /* gcc >= 3.0.1 */
  puts ("])");
  fflush (stdout);
return ferror (stdout) != 0 ? FATAL_EXIT_CODE : SUCCESS_EXIT_CODE;
}
