/* Generated automatically by the program `genemit'
from the machine description file `md'.  */

#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "backend.h"
#include "predict.h"
#include "tree.h"
#include "rtl.h"
#include "alias.h"
#include "varasm.h"
#include "stor-layout.h"
#include "calls.h"
#include "memmodel.h"
#include "tm_p.h"
#include "flags.h"
#include "insn-config.h"
#include "expmed.h"
#include "dojump.h"
#include "explow.h"
#include "emit-rtl.h"
#include "stmt.h"
#include "expr.h"
#include "insn-codes.h"
#include "optabs.h"
#include "dfp.h"
#include "output.h"
#include "recog.h"
#include "df.h"
#include "resource.h"
#include "reload.h"
#include "diagnostic-core.h"
#include "regs.h"
#include "tm-constrs.h"
#include "ggc.h"
#include "target.h"

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:461 */
rtx
gen_addsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:461 */
rtx
gen_adddf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:461 */
rtx
gen_addhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:470 */
rtx
gen_addsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:479 */
rtx
gen_adddi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:592 */
rtx
gen_subsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:592 */
rtx
gen_subdf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:592 */
rtx
gen_subhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:601 */
rtx
gen_subdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:610 */
rtx
gen_subsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:719 */
rtx
gen_negdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:727 */
rtx
gen_negsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:762 */
rtx
gen_mulsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:762 */
rtx
gen_muldf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:762 */
rtx
gen_mulhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:771 */
rtx
gen_mulsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:780 */
rtx
gen_muldi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:927 */
rtx
gen_smuldi3_highpart (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (DImode,
	gen_rtx_LSHIFTRT (TImode,
	gen_rtx_MULT (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	operand1),
	gen_rtx_SIGN_EXTEND (TImode,
	operand2)),
	const_int_rtx[MAX_SAVED_CONST_INT + (64)])));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:927 */
rtx
gen_umuldi3_highpart (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (DImode,
	gen_rtx_LSHIFTRT (TImode,
	gen_rtx_MULT (TImode,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1),
	gen_rtx_ZERO_EXTEND (TImode,
	operand2)),
	const_int_rtx[MAX_SAVED_CONST_INT + (64)])));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:958 */
rtx
gen_usmuldi3_highpart (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (DImode,
	gen_rtx_LSHIFTRT (TImode,
	gen_rtx_MULT (TImode,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1),
	gen_rtx_SIGN_EXTEND (TImode,
	operand2)),
	const_int_rtx[MAX_SAVED_CONST_INT + (64)])));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:988 */
rtx
gen_smulsi3_highpart (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (SImode,
	gen_rtx_LSHIFTRT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	const_int_rtx[MAX_SAVED_CONST_INT + (32)])));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:988 */
rtx
gen_umulsi3_highpart (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (SImode,
	gen_rtx_LSHIFTRT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (DImode,
	operand2)),
	const_int_rtx[MAX_SAVED_CONST_INT + (32)])));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1019 */
rtx
gen_usmulsi3_highpart (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (SImode,
	gen_rtx_LSHIFTRT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	const_int_rtx[MAX_SAVED_CONST_INT + (32)])));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1041 */
rtx
gen_divsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_DIV (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1041 */
rtx
gen_udivsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UDIV (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1041 */
rtx
gen_modsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MOD (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1041 */
rtx
gen_umodsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMOD (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1050 */
rtx
gen_divdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_DIV (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1050 */
rtx
gen_udivdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UDIV (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1050 */
rtx
gen_moddi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MOD (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1050 */
rtx
gen_umoddi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMOD (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1069 */
rtx
gen_divsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_DIV (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1069 */
rtx
gen_divdf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_DIV (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1069 */
rtx
gen_divhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_DIV (HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1085 */
rtx
gen_sqrtsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SQRT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1085 */
rtx
gen_sqrtdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SQRT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1085 */
rtx
gen_sqrthf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SQRT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1098 */
rtx
gen_fmasf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (SFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1098 */
rtx
gen_fmadf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (DFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1098 */
rtx
gen_fmahf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (HFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1109 */
rtx
gen_fmssf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (SFmode,
	operand1,
	operand2,
	gen_rtx_NEG (SFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1109 */
rtx
gen_fmsdf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (DFmode,
	operand1,
	operand2,
	gen_rtx_NEG (DFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1109 */
rtx
gen_fmshf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (HFmode,
	operand1,
	operand2,
	gen_rtx_NEG (HFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1120 */
rtx
gen_fnmssf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (SFmode,
	gen_rtx_NEG (SFmode,
	operand1),
	operand2,
	gen_rtx_NEG (SFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1120 */
rtx
gen_fnmsdf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (DFmode,
	gen_rtx_NEG (DFmode,
	operand1),
	operand2,
	gen_rtx_NEG (DFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1120 */
rtx
gen_fnmshf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (HFmode,
	gen_rtx_NEG (HFmode,
	operand1),
	operand2,
	gen_rtx_NEG (HFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1132 */
rtx
gen_fnmasf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (SFmode,
	gen_rtx_NEG (SFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1132 */
rtx
gen_fnmadf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (DFmode,
	gen_rtx_NEG (DFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1132 */
rtx
gen_fnmahf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (HFmode,
	gen_rtx_NEG (HFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1202 */
rtx
gen_abssf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1202 */
rtx
gen_absdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1202 */
rtx
gen_abshf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1210 */
rtx
gen_copysignsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1210 */
rtx
gen_copysigndf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1210 */
rtx
gen_copysignhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1220 */
rtx
gen_negsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1220 */
rtx
gen_negdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1220 */
rtx
gen_neghf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1235 */
rtx
gen_fminsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		gen_rtx_USE (VOIDmode,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2)),
	14));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1235 */
rtx
gen_fmindf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		gen_rtx_USE (VOIDmode,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2)),
	14));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1235 */
rtx
gen_fminhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		gen_rtx_USE (VOIDmode,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2)),
	14));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1245 */
rtx
gen_fmaxsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		gen_rtx_USE (VOIDmode,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2)),
	15));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1245 */
rtx
gen_fmaxdf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		gen_rtx_USE (VOIDmode,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2)),
	15));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1245 */
rtx
gen_fmaxhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		gen_rtx_USE (VOIDmode,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2)),
	15));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1255 */
rtx
gen_sminsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1255 */
rtx
gen_smindf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1255 */
rtx
gen_sminhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1264 */
rtx
gen_smaxsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1264 */
rtx
gen_smaxdf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1264 */
rtx
gen_smaxhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1284 */
rtx
gen_andsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1284 */
rtx
gen_iorsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1284 */
rtx
gen_xorsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1284 */
rtx
gen_anddi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1284 */
rtx
gen_iordi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1284 */
rtx
gen_xordi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1302 */
rtx
gen_one_cmplsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1302 */
rtx
gen_one_cmpldi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1325 */
rtx
gen_truncdfsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1334 */
rtx
gen_truncsfhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1343 */
rtx
gen_truncdfhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1416 */
rtx
gen_zero_extendqihi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1416 */
rtx
gen_zero_extendqisi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1416 */
rtx
gen_zero_extendqidi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1434 */
rtx
gen_extendsidi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1472 */
rtx
gen_extendhfsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1481 */
rtx
gen_extendsfdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1490 */
rtx
gen_extendhfdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1537 */
rtx
gen_fix_truncsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1537 */
rtx
gen_fix_truncsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1537 */
rtx
gen_fix_truncdfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1537 */
rtx
gen_fix_truncdfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1537 */
rtx
gen_fix_trunchfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1537 */
rtx
gen_fix_trunchfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1546 */
rtx
gen_fixuns_truncsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1546 */
rtx
gen_fixuns_truncsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1546 */
rtx
gen_fixuns_truncdfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1546 */
rtx
gen_fixuns_truncdfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1546 */
rtx
gen_fixuns_trunchfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1546 */
rtx
gen_fixuns_trunchfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1555 */
rtx
gen_floatsisf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1555 */
rtx
gen_floatdisf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1555 */
rtx
gen_floatsidf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1555 */
rtx
gen_floatdidf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1555 */
rtx
gen_floatsihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1555 */
rtx
gen_floatdihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1564 */
rtx
gen_floatunssisf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1564 */
rtx
gen_floatunsdisf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1564 */
rtx
gen_floatunssidf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1564 */
rtx
gen_floatunsdidf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1564 */
rtx
gen_floatunssihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1564 */
rtx
gen_floatunsdihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
rtx
gen_lrintsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
rtx
gen_lroundsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	13));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
rtx
gen_lrintsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
rtx
gen_lroundsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	13));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
rtx
gen_lrintdfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
rtx
gen_lrounddfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	13));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
rtx
gen_lrintdfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
rtx
gen_lrounddfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	13));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
rtx
gen_lrinthfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
rtx
gen_lroundhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	13));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
rtx
gen_lrinthfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
rtx
gen_lroundhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	13));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1594 */
rtx
gen_got_loadsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	3));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1594 */
rtx
gen_got_loaddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	3));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1604 */
rtx
gen_tls_add_tp_lesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	5));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1604 */
rtx
gen_tls_add_tp_ledi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	5));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1616 */
rtx
gen_got_load_tls_gdsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	7));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1616 */
rtx
gen_got_load_tls_gddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	7));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1626 */
rtx
gen_got_load_tls_iesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	6));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1626 */
rtx
gen_got_load_tls_iedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	6));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1636 */
rtx
gen_auipcsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		pc_rtx),
	8));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1636 */
rtx
gen_auipcdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		pc_rtx),
	8));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1947 */
rtx
gen_fence (void)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	9);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1952 */
rtx
gen_fence_i (void)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	10);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1957 */
rtx
gen_riscv_pause (void)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	18);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1974 */
rtx
gen_ashlsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1974 */
rtx
gen_ashrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1974 */
rtx
gen_lshrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2029 */
rtx
gen_ashldi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2029 */
rtx
gen_ashrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2029 */
rtx
gen_lshrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2230 */
rtx
gen_zero_extendsidi2_shifted (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2),
	operand3)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2612 */
rtx
gen_jump (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (pc_rtx,
	gen_rtx_LABEL_REF (VOIDmode,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2632 */
rtx
gen_indirect_jumpsi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (pc_rtx,
	operand0);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2632 */
rtx
gen_indirect_jumpdi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (pc_rtx,
	operand0);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2656 */
rtx
gen_tablejumpsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (pc_rtx,
	operand0),
		gen_rtx_USE (VOIDmode,
	gen_rtx_LABEL_REF (VOIDmode,
	operand1))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2656 */
rtx
gen_tablejumpdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (pc_rtx,
	operand0),
		gen_rtx_USE (VOIDmode,
	gen_rtx_LABEL_REF (VOIDmode,
	operand1))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2684 */
rtx
gen_blockage (void)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	8);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2715 */
rtx
gen_simple_return (void)
{
  return simple_return_rtx;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2726 */
rtx
gen_simple_return_internal (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		simple_return_rtx,
		gen_rtx_USE (VOIDmode,
	operand0)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2754 */
rtx
gen_eh_set_lr_si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_UNSPEC (VOIDmode,
	gen_rtvec (1,
		operand0),
	0),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2760 */
rtx
gen_eh_set_lr_di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_UNSPEC (VOIDmode,
	gen_rtvec (1,
		operand0),
	0),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2776 */
rtx
gen_eh_return_internal (void)
{
  return gen_rtx_EH_RETURN (VOIDmode);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2803 */
rtx
gen_sibcall_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_CALL (VOIDmode,
	gen_rtx_MEM (SImode,
	operand0),
	operand1);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2825 */
rtx
gen_sibcall_value_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	gen_rtx_MEM (SImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2848 */
rtx
gen_call_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_CALL (VOIDmode,
	gen_rtx_MEM (SImode,
	operand0),
	operand1),
		gen_hard_reg_clobber (SImode, 1)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2871 */
rtx
gen_call_value_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	gen_rtx_MEM (SImode,
	operand1),
	operand2)),
		gen_hard_reg_clobber (SImode, 1)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2906 */
rtx
gen_nop (void)
{
  return const0_rtx;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2913 */
rtx
gen_trap (void)
{
  return gen_rtx_TRAP_IF (VOIDmode,
	const1_rtx,
	const0_rtx);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2922 */
rtx
gen_gpr_save (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return operand1;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2929 */
rtx
gen_gpr_restore (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		operand0),
	1);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2934 */
rtx
gen_gpr_restore_return (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		ret_rtx,
		gen_rtx_USE (VOIDmode,
	operand0),
		const0_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2941 */
rtx
gen_riscv_frflags (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2947 */
rtx
gen_riscv_fsflags (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		operand0),
	3);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2961 */
rtx
gen_riscv_mret (void)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		ret_rtx,
		gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	5)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2967 */
rtx
gen_riscv_sret (void)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		ret_rtx,
		gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	6)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2973 */
rtx
gen_riscv_uret (void)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		ret_rtx,
		gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	7)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2979 */
rtx
gen_stack_tiesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand0,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2979 */
rtx
gen_stack_tiedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand0,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3037 */
rtx
gen_stack_protect_set_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	11)),
		gen_rtx_SET (gen_rtx_SCRATCH (SImode),
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3037 */
rtx
gen_stack_protect_set_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	11)),
		gen_rtx_SET (gen_rtx_SCRATCH (DImode),
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3075 */
rtx
gen_stack_protect_test_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3075 */
rtx
gen_stack_protect_test_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3085 */
rtx
gen_riscv_clean_si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		operand0),
	13);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3085 */
rtx
gen_riscv_clean_di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (1,
		operand0),
	13);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3092 */
rtx
gen_riscv_flush_si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		operand0),
	14);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3092 */
rtx
gen_riscv_flush_di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (1,
		operand0),
	14);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3099 */
rtx
gen_riscv_inval_si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		operand0),
	15);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3099 */
rtx
gen_riscv_inval_di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (1,
		operand0),
	15);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3106 */
rtx
gen_riscv_zero_si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		operand0),
	16);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3106 */
rtx
gen_riscv_zero_di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (1,
		operand0),
	16);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3113 */
rtx
gen_prefetch (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PREFETCH (VOIDmode,
	operand0,
	operand1,
	operand2);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3127 */
rtx
gen_riscv_prefetchi_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand0,
		operand1),
	17);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3127 */
rtx
gen_riscv_prefetchi_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand0,
		operand1),
	17);
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:332 */
rtx
gen_rotlsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ROTATE (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:340 */
rtx
gen_rotldi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ROTATE (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:348 */
rtx
gen_rotlsi3_sext (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_ROTATE (SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:358 */
rtx
gen_orcbsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:358 */
rtx
gen_orcbdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
rtx
gen_sminsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
rtx
gen_uminsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
rtx
gen_smaxsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
rtx
gen_umaxsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
rtx
gen_smindi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
rtx
gen_umindi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
rtx
gen_smaxdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
rtx
gen_umaxdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:78 */
rtx
gen_riscv_brev8_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:78 */
rtx
gen_riscv_brev8_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:86 */
rtx
gen_riscv_zip (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:94 */
rtx
gen_riscv_unzip (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:102 */
rtx
gen_riscv_pack_sihi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	21));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:102 */
rtx
gen_riscv_pack_sisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	21));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:102 */
rtx
gen_riscv_pack_dihi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	21));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:102 */
rtx
gen_riscv_pack_disi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	21));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:111 */
rtx
gen_riscv_packh_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	22));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:111 */
rtx
gen_riscv_packh_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	22));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:120 */
rtx
gen_riscv_packw (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	23));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:131 */
rtx
gen_riscv_clmul_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	24));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:131 */
rtx
gen_riscv_clmul_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	24));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:140 */
rtx
gen_riscv_clmulh_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	25));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:140 */
rtx
gen_riscv_clmulh_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	25));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:151 */
rtx
gen_riscv_xperm4_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	27));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:151 */
rtx
gen_riscv_xperm4_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	27));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:160 */
rtx
gen_riscv_xperm8_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	26));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:160 */
rtx
gen_riscv_xperm8_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	26));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:171 */
rtx
gen_riscv_aes32dsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	28));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:181 */
rtx
gen_riscv_aes32dsmi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	29));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:191 */
rtx
gen_riscv_aes64ds (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	30));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:200 */
rtx
gen_riscv_aes64dsm (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	31));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:209 */
rtx
gen_riscv_aes64im (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	32));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:217 */
rtx
gen_riscv_aes64ks1i (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	33));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:226 */
rtx
gen_riscv_aes64ks2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	34));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:237 */
rtx
gen_riscv_aes32esi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	37));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:247 */
rtx
gen_riscv_aes32esmi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	38));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:257 */
rtx
gen_riscv_aes64es (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	35));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:266 */
rtx
gen_riscv_aes64esm (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	36));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:277 */
rtx
gen_riscv_sha256sig0_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	39));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:277 */
rtx
gen_riscv_sha256sig0_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	39));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:285 */
rtx
gen_riscv_sha256sig1_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	40));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:285 */
rtx
gen_riscv_sha256sig1_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	40));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:293 */
rtx
gen_riscv_sha256sum0_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	41));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:293 */
rtx
gen_riscv_sha256sum0_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	41));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:301 */
rtx
gen_riscv_sha256sum1_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	42));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:301 */
rtx
gen_riscv_sha256sum1_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	42));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:311 */
rtx
gen_riscv_sha512sig0h (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	44));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:320 */
rtx
gen_riscv_sha512sig0l (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	45));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:329 */
rtx
gen_riscv_sha512sig1h (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	47));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:338 */
rtx
gen_riscv_sha512sig1l (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	48));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:347 */
rtx
gen_riscv_sha512sum0r (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:356 */
rtx
gen_riscv_sha512sum1r (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:365 */
rtx
gen_riscv_sha512sig0 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	43));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:373 */
rtx
gen_riscv_sha512sig1 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:381 */
rtx
gen_riscv_sha512sum0 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	49));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:389 */
rtx
gen_riscv_sha512sum1 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	51));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:399 */
rtx
gen_riscv_sm3p0_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	53));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:399 */
rtx
gen_riscv_sm3p0_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	53));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:407 */
rtx
gen_riscv_sm3p1_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	54));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:407 */
rtx
gen_riscv_sm3p1_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	54));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:417 */
rtx
gen_riscv_sm4ed_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	55));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:417 */
rtx
gen_riscv_sm4ed_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	55));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:427 */
rtx
gen_riscv_sm4ks_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	56));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:427 */
rtx
gen_riscv_sm4ks_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	56));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:49 */
rtx
gen_mem_thread_fence_1 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	65)),
		operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:72 */
rtx
gen_atomic_loadsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:72 */
rtx
gen_atomic_loaddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:98 */
rtx
gen_atomic_storesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	64));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:98 */
rtx
gen_atomic_storedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	64));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
rtx
gen_atomic_addsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (SImode,
	operand0,
	operand1),
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
rtx
gen_atomic_orsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_IOR (SImode,
	operand0,
	operand1),
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
rtx
gen_atomic_xorsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_XOR (SImode,
	operand0,
	operand1),
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
rtx
gen_atomic_andsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_AND (SImode,
	operand0,
	operand1),
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
rtx
gen_atomic_adddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (DImode,
	operand0,
	operand1),
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
rtx
gen_atomic_ordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_IOR (DImode,
	operand0,
	operand1),
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
rtx
gen_atomic_xordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_XOR (DImode,
	operand0,
	operand1),
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
rtx
gen_atomic_anddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_AND (DImode,
	operand0,
	operand1),
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
rtx
gen_atomic_fetch_addsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	59))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
rtx
gen_atomic_fetch_orsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_IOR (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	59))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
rtx
gen_atomic_fetch_xorsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_XOR (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	59))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
rtx
gen_atomic_fetch_andsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_AND (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	59))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
rtx
gen_atomic_fetch_adddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	59))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
rtx
gen_atomic_fetch_ordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_IOR (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	59))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
rtx
gen_atomic_fetch_xordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_XOR (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	59))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
rtx
gen_atomic_fetch_anddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_AND (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	59))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:148 */
rtx
gen_subword_atomic_fetch_strong_add (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (6,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	60)),
		operand4,
		operand5,
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:148 */
rtx
gen_subword_atomic_fetch_strong_or (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (6,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_IOR (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	60)),
		operand4,
		operand5,
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:148 */
rtx
gen_subword_atomic_fetch_strong_xor (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (6,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_XOR (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	60)),
		operand4,
		operand5,
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:148 */
rtx
gen_subword_atomic_fetch_strong_and (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (6,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_AND (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	60)),
		operand4,
		operand5,
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:214 */
rtx
gen_subword_atomic_fetch_strong_nand (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (6,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_NOT (SImode,
	gen_rtx_AND (SImode,
	copy_rtx (operand1),
	operand2)),
		operand3),
	60)),
		operand4,
		operand5,
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:282 */
rtx
gen_atomic_exchangesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand1,
		operand3),
	61)),
		gen_rtx_SET (copy_rtx (operand1),
	operand2)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:282 */
rtx
gen_atomic_exchangedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand1,
		operand3),
	61)),
		gen_rtx_SET (copy_rtx (operand1),
	operand2)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:327 */
rtx
gen_subword_atomic_exchange_strong (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	62)),
		operand4,
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:348 */
rtx
gen_atomic_cas_value_strongsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (4,
		operand2,
		operand3,
		operand4,
		operand5),
	57)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:348 */
rtx
gen_atomic_cas_value_strongdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (4,
		operand2,
		operand3,
		operand4,
		operand5),
	57)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:519 */
rtx
gen_subword_atomic_cas_strong (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (6,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	58)),
		operand4,
		operand5,
		operand6,
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:147 */
rtx
gen_th_fmv_hw_w_x (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	19));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:157 */
rtx
gen_th_fmv_x_w (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:166 */
rtx
gen_th_fmv_x_hw (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx1qi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx2qi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx4qi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx8qi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx16qi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx32qi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx64qi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx1hi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx2hi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx4hi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx8hi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx16hi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx32hi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx1si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx2si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx4si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx8si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx16si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx1di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx2di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx4di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx8di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx1sf (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx2sf (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx4sf (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx8sf (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx16sf (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx1df (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx2df (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx4df (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
rtx
gen_vundefinedvnx8df (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
rtx
gen_vundefinedvnx1bi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
rtx
gen_vundefinedvnx2bi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
rtx
gen_vundefinedvnx4bi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
rtx
gen_vundefinedvnx8bi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
rtx
gen_vundefinedvnx16bi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
rtx
gen_vundefinedvnx32bi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
rtx
gen_vundefinedvnx64bi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (1,
		gen_rtx_REG (SImode,
	0)),
	67));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:525 */
rtx
gen_vlmax_avlsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	69));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:525 */
rtx
gen_vlmax_avldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	69));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:819 */
rtx
gen_vsetvlsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (5,
		operand1,
		operand2,
		operand3,
		operand4,
		operand5),
	66)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		copy_rtx (operand3)),
	66)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	67),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (4,
		copy_rtx (operand2),
		copy_rtx (operand3),
		copy_rtx (operand4),
		copy_rtx (operand5)),
	66))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:819 */
rtx
gen_vsetvldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (5,
		operand1,
		operand2,
		operand3,
		operand4,
		operand5),
	66)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		copy_rtx (operand3)),
	66)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	67),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (4,
		copy_rtx (operand2),
		copy_rtx (operand3),
		copy_rtx (operand4),
		copy_rtx (operand5)),
	66))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:846 */
rtx
gen_vsetvl_vtype_change_only (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (SImode,
	67),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (4,
		operand0,
		operand1,
		operand2,
		operand3),
	66));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:861 */
rtx
gen_vsetvl_discard_resultsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand0,
		operand1,
		operand2),
	66)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	67),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (4,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3,
		operand4),
	66))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:861 */
rtx
gen_vsetvl_discard_resultdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand0,
		operand1,
		operand2),
	66)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	67),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (4,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3,
		operand4),
	66))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:883 */
rtx
gen_vsetvlsi_no_side_effects (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (5,
		operand1,
		operand2,
		operand3,
		operand4,
		operand5),
	66));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:883 */
rtx
gen_vsetvldi_no_side_effects (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (5,
		operand1,
		operand2,
		operand3,
		operand4,
		operand5),
	66));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
rtx
gen_pred_movvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
rtx
gen_pred_storevnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
rtx
gen_pred_movvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
rtx
gen_pred_movvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
rtx
gen_pred_movvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
rtx
gen_pred_movvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
rtx
gen_pred_movvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
rtx
gen_pred_movvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
rtx
gen_pred_movvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
rtx
gen_pred_storevnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
rtx
gen_pred_storevnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
rtx
gen_pred_storevnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
rtx
gen_pred_storevnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
rtx
gen_pred_storevnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
rtx
gen_pred_storevnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
rtx
gen_pred_storevnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (4,
		operand1,
		operand3,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	operand2,
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx1QImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx2QImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx4QImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx8QImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx16QImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx32QImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx64QImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx1HImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx2HImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx4HImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx8HImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx16HImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx32HImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx1SImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx2SImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx4SImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx8SImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx16SImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx1DImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx2DImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx4DImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx8DImode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx1SFmode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx2SFmode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx4SFmode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx8SFmode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx16SFmode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx1DFmode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx2DFmode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx4DFmode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
rtx
gen_pred_mergevnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx8DFmode,
	operand3,
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
rtx
gen_pred_mergevnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
rtx
gen_pred_strided_loadvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	70),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
rtx
gen_pred_strided_storevnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand1,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	70),
	operand0));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx1qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx1qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx2qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx2qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx4qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx4qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx8qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx8qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx16qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx16qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx32qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx32qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx64qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx64qi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx1hi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx1hi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx2hi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx2hi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx4hi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx4hi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx8hi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx8hi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx16hi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx16hi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx32hi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx32hi_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx1si_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx1si_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx2si_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx2si_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx4si_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx4si_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx8si_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx8si_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx16si_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx16si_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx1di_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx1di_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx2di_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx2di_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx4di_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx4di_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx8di_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx8di_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx1sf_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx1sf_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx2sf_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx2sf_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx4sf_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx4sf_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx8sf_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx8sf_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx16sf_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx16sf_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx1df_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx1df_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx2df_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx2df_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx4df_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx4df_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_oloadvnx8df_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
rtx
gen_pred_indexed_uloadvnx8df_same_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx1hi_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx1hi_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx2hi_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx2hi_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx4hi_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx4hi_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx8hi_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx8hi_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx16hi_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx16hi_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx32hi_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx32hi_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx1si_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx1si_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx2si_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx2si_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx4si_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx4si_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx8si_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx8si_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx16si_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx16si_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx1di_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx1di_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx2di_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx2di_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx4di_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx4di_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx8di_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx8di_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx1sf_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx1sf_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx2sf_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx2sf_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx4sf_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx4sf_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx8sf_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx8sf_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx16sf_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx16sf_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx1df_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx1df_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx2df_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx2df_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx4df_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx4df_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_oloadvnx8df_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
rtx
gen_pred_indexed_uloadvnx8df_x2_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx1si_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx1si_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx2si_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx2si_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx4si_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx4si_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx8si_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx8si_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx16si_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx16si_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx1di_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx1di_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx2di_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx2di_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx4di_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx4di_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx8di_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx8di_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx1sf_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx1sf_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx2sf_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx2sf_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx4sf_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx4sf_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx8sf_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx8sf_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx16sf_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx16sf_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx1df_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx1df_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx2df_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx2df_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx4df_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx4df_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_oloadvnx8df_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
rtx
gen_pred_indexed_uloadvnx8df_x4_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_oloadvnx1di_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_uloadvnx1di_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_oloadvnx2di_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_uloadvnx2di_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_oloadvnx4di_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_uloadvnx4di_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_oloadvnx8di_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_uloadvnx8di_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_oloadvnx1df_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_uloadvnx1df_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_oloadvnx2df_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_uloadvnx2df_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_oloadvnx4df_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_uloadvnx4df_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_oloadvnx8df_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
rtx
gen_pred_indexed_uloadvnx8df_x8_greater_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx1qi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx1qi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx2qi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx2qi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx4qi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx4qi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx8qi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx8qi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx16qi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx16qi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx32qi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx32qi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx1hi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx1hi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx2hi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx2hi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx4hi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx4hi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx8hi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx8hi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx16hi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx16hi_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx1si_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx1si_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx2si_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx2si_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx4si_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx4si_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx8si_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx8si_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx1sf_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx1sf_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx2sf_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx2sf_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx4sf_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx4sf_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_oloadvnx8sf_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
rtx
gen_pred_indexed_uloadvnx8sf_x2_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_oloadvnx1qi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_uloadvnx1qi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_oloadvnx2qi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_uloadvnx2qi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_oloadvnx4qi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_uloadvnx4qi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_oloadvnx8qi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_uloadvnx8qi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_oloadvnx16qi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_uloadvnx16qi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_oloadvnx1hi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_uloadvnx1hi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_oloadvnx2hi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_uloadvnx2hi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_oloadvnx4hi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_uloadvnx4hi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_oloadvnx8hi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
rtx
gen_pred_indexed_uloadvnx8hi_x4_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
rtx
gen_pred_indexed_oloadvnx1qi_x8_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
rtx
gen_pred_indexed_uloadvnx1qi_x8_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
rtx
gen_pred_indexed_oloadvnx2qi_x8_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
rtx
gen_pred_indexed_uloadvnx2qi_x8_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
rtx
gen_pred_indexed_oloadvnx4qi_x8_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
rtx
gen_pred_indexed_uloadvnx4qi_x8_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
rtx
gen_pred_indexed_oloadvnx8qi_x8_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	71),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
rtx
gen_pred_indexed_uloadvnx8qi_x8_smaller_eew (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		operand3,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
		operand4),
	72),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1qivnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1qivnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1qivnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1qivnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1qivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1qivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1qivnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1qivnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1hivnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1hivnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1hivnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1hivnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1hivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1hivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1hivnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1hivnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1sivnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1sivnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1sivnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1sivnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1sivnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1sivnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1divnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1divnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1divnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1divnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1divnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1divnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1divnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1divnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1sfvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1sfvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1sfvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1sfvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1sfvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1sfvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1sfvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1sfvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1dfvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1dfvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1dfvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1dfvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1dfvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1dfvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ostorevnx1dfvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
rtx
gen_pred_indexed_ustorevnx1dfvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2qivnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2qivnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2hivnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2hivnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2sivnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2sivnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2divnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2divnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2sfvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2sfvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2dfvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2dfvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2sivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2sivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2divnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2divnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2sfvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2sfvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2dfvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2dfvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2qivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2qivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2divnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2divnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2sfvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2sfvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2dfvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2dfvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2qivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2qivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2hivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2hivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2sivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2sivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2divnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2divnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2sfvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2sfvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ostorevnx2dfvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
rtx
gen_pred_indexed_ustorevnx2dfvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4hivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4hivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4sivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4sivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4divnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4divnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4sfvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4sfvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4dfvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4dfvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4sivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4sivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4divnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4divnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4sfvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4sfvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4dfvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4dfvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4qivnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4qivnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4hivnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4hivnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4sivnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4sivnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4divnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4divnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4sfvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4sfvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4dfvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4dfvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4qivnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4qivnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4hivnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4hivnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4sivnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4sivnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4divnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4divnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4sfvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4sfvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ostorevnx4dfvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
rtx
gen_pred_indexed_ustorevnx4dfvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8hivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8hivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8sivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8sivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8divnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8divnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8sfvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8sfvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8dfvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8dfvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8qivnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8qivnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8hivnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8hivnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8sivnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8sivnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8divnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8divnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8sfvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8sfvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8dfvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8dfvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8qivnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8qivnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8hivnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8hivnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8sivnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8sivnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8divnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8divnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8sfvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8sfvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8dfvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8dfvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8qivnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8qivnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8hivnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8hivnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8sivnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8sivnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8divnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8divnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8sfvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8sfvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ostorevnx8dfvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
rtx
gen_pred_indexed_ustorevnx8dfvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ostorevnx16qivnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ustorevnx16qivnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ostorevnx16hivnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ustorevnx16hivnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ostorevnx16sivnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ustorevnx16sivnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ostorevnx16sfvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ustorevnx16sfvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ostorevnx16qivnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ustorevnx16qivnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ostorevnx16hivnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ustorevnx16hivnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ostorevnx16sivnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ustorevnx16sivnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ostorevnx16sfvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ustorevnx16sfvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ostorevnx16qivnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ustorevnx16qivnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ostorevnx16hivnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ustorevnx16hivnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ostorevnx16sivnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ustorevnx16sivnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ostorevnx16sfvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
rtx
gen_pred_indexed_ustorevnx16sfvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
rtx
gen_pred_indexed_ostorevnx32qivnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
rtx
gen_pred_indexed_ustorevnx32qivnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
rtx
gen_pred_indexed_ostorevnx32qivnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
rtx
gen_pred_indexed_ustorevnx32qivnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
rtx
gen_pred_indexed_ostorevnx32hivnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
rtx
gen_pred_indexed_ustorevnx32hivnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
rtx
gen_pred_indexed_ostorevnx32hivnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
rtx
gen_pred_indexed_ustorevnx32hivnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1653 */
rtx
gen_pred_indexed_ostorevnx64qivnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1653 */
rtx
gen_pred_indexed_ustorevnx64qivnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand0,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand1,
		operand2,
		operand3),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_addvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_subvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_andvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_iorvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_xorvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashlvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_ashrvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_lshrvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_smaxvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umaxvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_sminvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_uminvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_mulvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_divvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_udivvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_modvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
rtx
gen_pred_umodvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashlvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFT (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_ashrvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ASHIFTRT (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
rtx
gen_pred_lshrvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_LSHIFTRT (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_addvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_andvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_iorvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_xorvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_smaxvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_umaxvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_sminvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_uminvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
rtx
gen_pred_mulvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx1QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx1QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx1QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx2QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx2QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx2QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx4QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx4QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx4QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx8QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx8QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx8QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx16QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx16QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx16QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx16QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx32QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx32QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx32QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx32QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx64QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx64QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx64QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx64QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx64QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx1HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx1HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx1HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx2HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx2HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx2HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx4HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx4HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx4HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx8HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx8HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx8HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx16HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx16HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx16HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx16HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx32HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx32HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx32HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx32HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx1SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx1SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx1SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx2SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx2SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx2SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx4SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx4SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx4SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx8SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx8SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx8SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_subvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_divvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx16SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_udivvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx16SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_modvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx16SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
rtx
gen_pred_umodvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx16SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx1qi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx2qi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx4qi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx8qi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx16qi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx32qi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx64qi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx1hi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx2hi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx4hi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx8hi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx16hi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx32hi_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx1si_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx2si_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx4si_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx8si_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
rtx
gen_pred_subvnx16si_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhuvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
rtx
gen_pred_mulhsuvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
		operand3),
	73),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhuvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
		operand3),
	74),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
rtx
gen_pred_mulhsuvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
		operand3),
	75),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1QImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2QImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4QImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8QImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx16QImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx32QImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx64QImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1HImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2HImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4HImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8HImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx16HImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx32HImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1SImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2SImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4SImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8SImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx16SImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1DImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2DImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4DImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
rtx
gen_pred_adcvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8DImode,
	operand2,
	operand3),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1QImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2QImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4QImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8QImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx16QImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx32QImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx64QImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1HImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2HImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4HImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8HImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx16HImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx32HImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1SImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2SImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4SImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8SImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx16SImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1DImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2DImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4DImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
rtx
gen_pred_sbcvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8DImode,
	operand2,
	operand3),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
rtx
gen_pred_adcvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1QImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2QImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4QImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8QImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx16QImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx32QImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx64QImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1HImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2HImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4HImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8HImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx16HImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx32HImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1SImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2SImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4SImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8SImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
rtx
gen_pred_sbcvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx16SImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand3)),
		operand4),
	77),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx1QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx2QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx4QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx8QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx16QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx32QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx64QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx1HImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx2HImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx4HImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx8HImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx16HImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx32HImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx1SImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx2SImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx4SImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx8SImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx16SImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx1DImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx2DImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx4DImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
rtx
gen_pred_madcvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx8DImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx1QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx2QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx4QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx8QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx16QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx32QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx64QImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx1HImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx2HImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx4HImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx8HImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx16HImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx32HImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx1SImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx2SImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx4SImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx8SImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx16SImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx1DImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx2DImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx4DImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
rtx
gen_pred_msbcvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx8DImode,
	operand1,
	operand2),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
rtx
gen_pred_madcvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
rtx
gen_pred_msbcvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx1qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx2qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx4qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx8qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx16qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx16QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx32qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx32QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx64qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx64QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx1hi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1HImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx2hi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2HImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx4hi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4HImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx8hi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8HImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx16hi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx16HImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx32hi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx32HImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx1si_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1SImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx2si_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2SImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx4si_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4SImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx8si_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8SImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx16si_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx16SImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx1di_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1DImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx2di_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2DImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx4di_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4DImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
rtx
gen_pred_madcvnx8di_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8DImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx1qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx2qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx4qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx8qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx16qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx16QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx32qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx32QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx64qi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx64QImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx1hi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1HImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx2hi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2HImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx4hi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4HImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx8hi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8HImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx16hi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx16HImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx32hi_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx32HImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx1si_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1SImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx2si_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2SImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx4si_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4SImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx8si_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8SImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx16si_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx16SImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx1di_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1DImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx2di_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2DImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx4di_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4DImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
rtx
gen_pred_msbcvnx8di_overflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8DImode,
	operand1,
	operand2),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx1qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx2qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx4qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx8qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx16qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx32qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx64qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx1hi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx2hi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx4hi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx8hi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx16hi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx32hi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx1si_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx2si_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx4si_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx8si_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
rtx
gen_pred_madcvnx16si_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx1qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx2qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx4qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx8qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx16qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx32qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx64qi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx1hi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx2hi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx4hi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx8hi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx16hi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx32hi_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx1si_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx2si_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx4si_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx8si_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
rtx
gen_pred_msbcvnx16si_overflow_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx1QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx1QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx2QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx2QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx4QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx4QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx8QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx8QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx16QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx16QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx32QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx32QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx64QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx64QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx1HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx1HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx2HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx2HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx4HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx4HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx8HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx8HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx16HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx16HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx32HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx32HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx1SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx1SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx2SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx2SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx4SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx4SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx8SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx8SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx16SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx16SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx1DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx1DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx2DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx2DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx4DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx4DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_negvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx8DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
rtx
gen_pred_one_cmplvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx8DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx1hi_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx1hi_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx2hi_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx2hi_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx4hi_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx4hi_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx8hi_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx8hi_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx16hi_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx16hi_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx32hi_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx32hi_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx1si_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx1si_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx2si_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx2si_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx4si_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx4si_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx8si_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx8si_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx16si_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx16si_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx1di_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx1di_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx2di_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx2di_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx4di_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx4di_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_extendvnx8di_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
rtx
gen_pred_zero_extendvnx8di_vf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_extendvnx1si_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_zero_extendvnx1si_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_extendvnx2si_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_zero_extendvnx2si_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_extendvnx4si_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_zero_extendvnx4si_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_extendvnx8si_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_zero_extendvnx8si_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_extendvnx16si_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_zero_extendvnx16si_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_extendvnx1di_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_zero_extendvnx1di_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_extendvnx2di_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_zero_extendvnx2di_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_extendvnx4di_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_zero_extendvnx4di_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_extendvnx8di_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
rtx
gen_pred_zero_extendvnx8di_vf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
rtx
gen_pred_extendvnx1di_vf8 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
rtx
gen_pred_zero_extendvnx1di_vf8 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
rtx
gen_pred_extendvnx2di_vf8 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
rtx
gen_pred_zero_extendvnx2di_vf8 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
rtx
gen_pred_extendvnx4di_vf8 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
rtx
gen_pred_zero_extendvnx4di_vf8 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
rtx
gen_pred_extendvnx8di_vf8 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
rtx
gen_pred_zero_extendvnx8di_vf8 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_addsvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subsvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_mulsvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_adduvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_subuvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
rtx
gen_pred_dual_widen_muluvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_addsvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subsvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_mulsvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_adduvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_subuvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
rtx
gen_pred_dual_widen_muluvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_addsvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subsvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_adduvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
rtx
gen_pred_single_widen_subuvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_addsvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subsvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_adduvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
rtx
gen_pred_single_widen_subuvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	operand3,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
rtx
gen_pred_widen_mulsuvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
rtx
gen_pred_widen_mulsuvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_REG (HImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_REG (HImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_REG (HImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_REG (HImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_REG (HImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_REG (HImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_REG (HImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_REG (HImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_REG (HImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_REG (HImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	gen_rtx_REG (HImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	gen_rtx_REG (HImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_REG (SImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_REG (SImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_REG (SImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_REG (SImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_REG (SImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_REG (SImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_REG (SImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_REG (SImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	gen_rtx_REG (SImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	gen_rtx_REG (SImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	gen_rtx_REG (DImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	gen_rtx_REG (DImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	gen_rtx_REG (DImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	gen_rtx_REG (DImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	gen_rtx_REG (DImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	gen_rtx_REG (DImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_extendvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	gen_rtx_REG (DImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
rtx
gen_pred_zero_extendvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	gen_rtx_REG (DImode,
	0))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1QImode,
	gen_rtx_ASHIFTRT (VNx1HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1QImode,
	gen_rtx_LSHIFTRT (VNx1HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2QImode,
	gen_rtx_ASHIFTRT (VNx2HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2QImode,
	gen_rtx_LSHIFTRT (VNx2HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4QImode,
	gen_rtx_ASHIFTRT (VNx4HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4QImode,
	gen_rtx_LSHIFTRT (VNx4HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8QImode,
	gen_rtx_ASHIFTRT (VNx8HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8QImode,
	gen_rtx_LSHIFTRT (VNx8HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx16QImode,
	gen_rtx_ASHIFTRT (VNx16HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx16QImode,
	gen_rtx_LSHIFTRT (VNx16HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx32QImode,
	gen_rtx_ASHIFTRT (VNx32HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx32QImode,
	gen_rtx_LSHIFTRT (VNx32HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1HImode,
	gen_rtx_ASHIFTRT (VNx1SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1HImode,
	gen_rtx_LSHIFTRT (VNx1SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2HImode,
	gen_rtx_ASHIFTRT (VNx2SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2HImode,
	gen_rtx_LSHIFTRT (VNx2SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4HImode,
	gen_rtx_ASHIFTRT (VNx4SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4HImode,
	gen_rtx_LSHIFTRT (VNx4SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8HImode,
	gen_rtx_ASHIFTRT (VNx8SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8HImode,
	gen_rtx_LSHIFTRT (VNx8SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx16HImode,
	gen_rtx_ASHIFTRT (VNx16SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx16HImode,
	gen_rtx_LSHIFTRT (VNx16SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1SImode,
	gen_rtx_ASHIFTRT (VNx1DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1SImode,
	gen_rtx_LSHIFTRT (VNx1DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2SImode,
	gen_rtx_ASHIFTRT (VNx2DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2SImode,
	gen_rtx_LSHIFTRT (VNx2DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4SImode,
	gen_rtx_ASHIFTRT (VNx4DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4SImode,
	gen_rtx_LSHIFTRT (VNx4DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_ashrvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8SImode,
	gen_rtx_ASHIFTRT (VNx8DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
rtx
gen_pred_narrow_lshrvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8SImode,
	gen_rtx_LSHIFTRT (VNx8DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1QImode,
	gen_rtx_ASHIFTRT (VNx1HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1QImode,
	gen_rtx_LSHIFTRT (VNx1HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2QImode,
	gen_rtx_ASHIFTRT (VNx2HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2QImode,
	gen_rtx_LSHIFTRT (VNx2HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4QImode,
	gen_rtx_ASHIFTRT (VNx4HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4QImode,
	gen_rtx_LSHIFTRT (VNx4HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8QImode,
	gen_rtx_ASHIFTRT (VNx8HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8QImode,
	gen_rtx_LSHIFTRT (VNx8HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx16QImode,
	gen_rtx_ASHIFTRT (VNx16HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx16QImode,
	gen_rtx_LSHIFTRT (VNx16HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx32QImode,
	gen_rtx_ASHIFTRT (VNx32HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx32QImode,
	gen_rtx_LSHIFTRT (VNx32HImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1HImode,
	gen_rtx_ASHIFTRT (VNx1SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1HImode,
	gen_rtx_LSHIFTRT (VNx1SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2HImode,
	gen_rtx_ASHIFTRT (VNx2SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2HImode,
	gen_rtx_LSHIFTRT (VNx2SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4HImode,
	gen_rtx_ASHIFTRT (VNx4SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4HImode,
	gen_rtx_LSHIFTRT (VNx4SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8HImode,
	gen_rtx_ASHIFTRT (VNx8SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8HImode,
	gen_rtx_LSHIFTRT (VNx8SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx16HImode,
	gen_rtx_ASHIFTRT (VNx16SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx16HImode,
	gen_rtx_LSHIFTRT (VNx16SImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1SImode,
	gen_rtx_ASHIFTRT (VNx1DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1SImode,
	gen_rtx_LSHIFTRT (VNx1DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2SImode,
	gen_rtx_ASHIFTRT (VNx2DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2SImode,
	gen_rtx_LSHIFTRT (VNx2DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4SImode,
	gen_rtx_ASHIFTRT (VNx4DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4SImode,
	gen_rtx_LSHIFTRT (VNx4DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_ashrvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8SImode,
	gen_rtx_ASHIFTRT (VNx8DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
rtx
gen_pred_narrow_lshrvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8SImode,
	gen_rtx_LSHIFTRT (VNx8DImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx16QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx32QImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx16HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx1SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx2SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx4SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
rtx
gen_pred_truncvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_TRUNCATE (VNx8SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx1QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx2QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx4QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx8QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx16QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx32QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx64QImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx1HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx2HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx4HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx8HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx16HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx32HImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx1SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx2SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx4SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx8SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx16SImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx1DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx2DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx4DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ssaddvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_sssubvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_usaddvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
rtx
gen_pred_ussubvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx8DImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_ssaddvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
rtx
gen_pred_usaddvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx1QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx1QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx2QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx2QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx4QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx4QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx8QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx8QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx16QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx16QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx32QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx32QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx64QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx64QImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx1HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx1HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx2HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx2HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx4HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx4HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx8HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx8HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx16HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx16HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx32HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx32HImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx1SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx1SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx2SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx2SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx4SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx4SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx8SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx8SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_sssubvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx16SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
rtx
gen_pred_ussubvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx16SImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aadduvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_aaddvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubuvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_asubvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_smulvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssrlvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
rtx
gen_pred_ssravnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aadduvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_aaddvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubuvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_asubvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
rtx
gen_pred_smulvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssrlvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	83),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
rtx
gen_pred_ssravnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	84),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
rtx
gen_pred_narrow_clipuvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	81),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
rtx
gen_pred_narrow_clipuvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	82),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plussvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
rtx
gen_pred_widen_mul_plusuvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plussvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
rtx
gen_pred_widen_mul_plusuvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
rtx
gen_pred_widen_mul_plussuvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand3),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
rtx
gen_pred_widen_mul_plussuvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand3)),
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_ZERO_EXTEND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx1HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_ZERO_EXTEND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx2HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_ZERO_EXTEND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx4HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_ZERO_EXTEND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx8HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_ZERO_EXTEND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx16HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_ZERO_EXTEND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx32HImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_ZERO_EXTEND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx1SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_ZERO_EXTEND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx2SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_ZERO_EXTEND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx4SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_ZERO_EXTEND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx8SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_ZERO_EXTEND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx16SImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_ZERO_EXTEND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx1DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_ZERO_EXTEND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx2DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_ZERO_EXTEND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx4DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
rtx
gen_pred_widen_mul_plususvnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_ZERO_EXTEND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand3)),
	gen_rtx_SIGN_EXTEND (VNx8DImode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_andvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx1BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_iorvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx1BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_xorvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx1BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_andvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx2BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_iorvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx2BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_xorvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx2BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_andvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx4BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_iorvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx4BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_xorvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx4BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_andvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx8BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_iorvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx8BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_xorvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx8BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_andvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx16BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_iorvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx16BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_xorvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx16BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_andvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx32BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_iorvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx32BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_xorvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx32BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_andvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx64BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_iorvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx64BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
rtx
gen_pred_xorvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx64BImode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nandvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx1BImode,
	gen_rtx_AND (VNx1BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_niorvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx1BImode,
	gen_rtx_IOR (VNx1BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nxorvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx1BImode,
	gen_rtx_XOR (VNx1BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nandvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx2BImode,
	gen_rtx_AND (VNx2BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_niorvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx2BImode,
	gen_rtx_IOR (VNx2BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nxorvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx2BImode,
	gen_rtx_XOR (VNx2BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nandvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx4BImode,
	gen_rtx_AND (VNx4BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_niorvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx4BImode,
	gen_rtx_IOR (VNx4BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nxorvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx4BImode,
	gen_rtx_XOR (VNx4BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nandvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx8BImode,
	gen_rtx_AND (VNx8BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_niorvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx8BImode,
	gen_rtx_IOR (VNx8BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nxorvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx8BImode,
	gen_rtx_XOR (VNx8BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nandvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx16BImode,
	gen_rtx_AND (VNx16BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_niorvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx16BImode,
	gen_rtx_IOR (VNx16BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nxorvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx16BImode,
	gen_rtx_XOR (VNx16BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nandvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx32BImode,
	gen_rtx_AND (VNx32BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_niorvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx32BImode,
	gen_rtx_IOR (VNx32BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nxorvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx32BImode,
	gen_rtx_XOR (VNx32BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nandvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx64BImode,
	gen_rtx_AND (VNx64BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_niorvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx64BImode,
	gen_rtx_IOR (VNx64BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
rtx
gen_pred_nxorvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx64BImode,
	gen_rtx_XOR (VNx64BImode,
	operand3,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_andnotvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx1BImode,
	operand3,
	gen_rtx_NOT (VNx1BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_iornotvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx1BImode,
	operand3,
	gen_rtx_NOT (VNx1BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_andnotvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx2BImode,
	operand3,
	gen_rtx_NOT (VNx2BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_iornotvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx2BImode,
	operand3,
	gen_rtx_NOT (VNx2BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_andnotvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx4BImode,
	operand3,
	gen_rtx_NOT (VNx4BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_iornotvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx4BImode,
	operand3,
	gen_rtx_NOT (VNx4BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_andnotvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx8BImode,
	operand3,
	gen_rtx_NOT (VNx8BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_iornotvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx8BImode,
	operand3,
	gen_rtx_NOT (VNx8BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_andnotvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx16BImode,
	operand3,
	gen_rtx_NOT (VNx16BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_iornotvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx16BImode,
	operand3,
	gen_rtx_NOT (VNx16BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_andnotvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx32BImode,
	operand3,
	gen_rtx_NOT (VNx32BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_iornotvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx32BImode,
	operand3,
	gen_rtx_NOT (VNx32BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_andnotvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx64BImode,
	operand3,
	gen_rtx_NOT (VNx64BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
rtx
gen_pred_iornotvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand1,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx64BImode,
	operand3,
	gen_rtx_NOT (VNx64BImode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
rtx
gen_pred_notvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx1BImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
rtx
gen_pred_notvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx2BImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
rtx
gen_pred_notvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx4BImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
rtx
gen_pred_notvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx8BImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
rtx
gen_pred_notvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx16BImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
rtx
gen_pred_notvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx32BImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
rtx
gen_pred_notvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		operand1,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NOT (VNx64BImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx1bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx1BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx2bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx2BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx4bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx4BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx8bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx8BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx16bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx16BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx32bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (SImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx32BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx64bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (SImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx64BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx1bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx1BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx2bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx2BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx4bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx4BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx8bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx8BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx16bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (DImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx16BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx32bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (DImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx32BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
rtx
gen_pred_popcountvnx64bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (DImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx64BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx1bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_FFS (SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx1BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx2bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_FFS (SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx2BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx4bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_FFS (SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx4BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx8bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_FFS (SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx8BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx16bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_FFS (SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx16BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx32bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_FFS (SImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx32BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx64bisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_FFS (SImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx64BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx1bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_FFS (DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx1BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx2bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_FFS (DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx2BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx4bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_FFS (DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx4BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx8bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_FFS (DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx8BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx16bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_FFS (DImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx16BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx32bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_FFS (DImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx32BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
rtx
gen_pred_ffsvnx64bidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_FFS (DImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (5,
		gen_rtx_AND (VNx64BImode,
	operand1,
	operand2),
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	constm1_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sbfvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (1,
		operand3),
	90),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sifvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (1,
		operand3),
	91),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sofvnx1bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (1,
		operand3),
	92),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sbfvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (1,
		operand3),
	90),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sifvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (1,
		operand3),
	91),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sofvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (1,
		operand3),
	92),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sbfvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (1,
		operand3),
	90),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sifvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (1,
		operand3),
	91),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sofvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (1,
		operand3),
	92),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sbfvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (1,
		operand3),
	90),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sifvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (1,
		operand3),
	91),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sofvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (1,
		operand3),
	92),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sbfvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (1,
		operand3),
	90),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sifvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (1,
		operand3),
	91),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sofvnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (1,
		operand3),
	92),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sbfvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (1,
		operand3),
	90),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sifvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (1,
		operand3),
	91),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sofvnx32bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (1,
		operand3),
	92),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sbfvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (1,
		operand3),
	90),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sifvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (1,
		operand3),
	91),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
rtx
gen_pred_sofvnx64bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (1,
		operand3),
	92),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
rtx
gen_pred_iotavnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (1,
		operand3),
	93),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx1QImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx2QImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx4QImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx8QImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx16QImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx32QImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx64QImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx1HImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx2HImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx4HImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx8HImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx16HImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx32HImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx1SImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx2SImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx4SImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx8SImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx16SImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx1DImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx2DImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx4DImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
rtx
gen_pred_seriesvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_SERIES (VNx8DImode,
	const0_rtx,
	const1_rtx),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_addvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_mulvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_smaxvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx1SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_sminvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx1SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_subvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_divvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_addvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_mulvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_smaxvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx2SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_sminvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx2SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_subvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_divvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_addvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_mulvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_smaxvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx4SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_sminvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx4SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_subvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_divvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_addvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_mulvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_smaxvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx8SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_sminvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx8SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_subvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_divvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_addvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_mulvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_smaxvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx16SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_sminvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx16SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_subvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_divvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx16SFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_addvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_mulvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_smaxvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx1DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_sminvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx1DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_subvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_divvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_addvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_mulvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_smaxvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx2DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_sminvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx2DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_subvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_divvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_addvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_mulvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_smaxvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx4DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_sminvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx4DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_subvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_divvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_addvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_mulvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_smaxvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx8DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_sminvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx8DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_subvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
rtx
gen_pred_divvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8DFmode,
	operand3,
	operand4),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_addvnx1sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_mulvnx1sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_smaxvnx1sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_sminvnx1sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_addvnx2sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_mulvnx2sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_smaxvnx2sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_sminvnx2sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_addvnx4sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_mulvnx4sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_smaxvnx4sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_sminvnx4sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_addvnx8sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_mulvnx8sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_smaxvnx8sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_sminvnx8sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_addvnx16sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_mulvnx16sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_smaxvnx16sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_sminvnx16sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_addvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_mulvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_smaxvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_sminvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_addvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_mulvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_smaxvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_sminvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_addvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_mulvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_smaxvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_sminvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_addvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_mulvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_smaxvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
rtx
gen_pred_sminvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_subvnx1sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_divvnx1sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1SFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_subvnx2sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_divvnx2sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2SFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_subvnx4sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_divvnx4sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4SFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_subvnx8sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_divvnx8sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8SFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_subvnx16sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_divvnx16sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx16SFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_subvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_divvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1DFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_subvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_divvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2DFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_subvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_divvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4DFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_subvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
rtx
gen_pred_divvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8DFmode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_subvnx1sf_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_divvnx1sf_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_subvnx2sf_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_divvnx2sf_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_subvnx4sf_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_divvnx4sf_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_subvnx8sf_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_divvnx8sf_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_subvnx16sf_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_divvnx16sf_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_subvnx1df_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_divvnx1df_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_subvnx2df_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_divvnx2df_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_subvnx4df_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_divvnx4df_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_subvnx8df_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
rtx
gen_pred_divvnx8df_reverse_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand4),
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_copysignvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_ncopysignvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_xorsignvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_copysignvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_ncopysignvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_xorsignvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_copysignvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_ncopysignvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_xorsignvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_copysignvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_ncopysignvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_xorsignvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_copysignvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_ncopysignvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_xorsignvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_copysignvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_ncopysignvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_xorsignvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_copysignvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_ncopysignvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_xorsignvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_copysignvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_ncopysignvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_xorsignvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_copysignvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_ncopysignvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
rtx
gen_pred_xorsignvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_copysignvnx1sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4)),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_ncopysignvnx1sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4)),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_xorsignvnx1sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4)),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_copysignvnx2sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4)),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_ncopysignvnx2sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4)),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_xorsignvnx2sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4)),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_copysignvnx4sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4)),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_ncopysignvnx4sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4)),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_xorsignvnx4sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4)),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_copysignvnx8sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4)),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_ncopysignvnx8sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4)),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_xorsignvnx8sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4)),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_copysignvnx16sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand4)),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_ncopysignvnx16sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand4)),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_xorsignvnx16sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand4)),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_copysignvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand4)),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_ncopysignvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand4)),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_xorsignvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand4)),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_copysignvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand4)),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_ncopysignvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand4)),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_xorsignvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand4)),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_copysignvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand4)),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_ncopysignvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand4)),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_xorsignvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand4)),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_copysignvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand4)),
	97),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_ncopysignvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand4)),
	98),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
rtx
gen_pred_xorsignvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand4)),
	99),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_negvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx1SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_absvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ABS (VNx1SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_sqrtvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SQRT (VNx1SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_negvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx2SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_absvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ABS (VNx2SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_sqrtvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SQRT (VNx2SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_negvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx4SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_absvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ABS (VNx4SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_sqrtvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SQRT (VNx4SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_negvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx8SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_absvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ABS (VNx8SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_sqrtvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SQRT (VNx8SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_negvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx16SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_absvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ABS (VNx16SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_sqrtvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SQRT (VNx16SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_negvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx1DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_absvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ABS (VNx1DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_sqrtvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SQRT (VNx1DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_negvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx2DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_absvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ABS (VNx2DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_sqrtvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SQRT (VNx2DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_negvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx4DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_absvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ABS (VNx4DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_sqrtvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SQRT (VNx4DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_negvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_NEG (VNx8DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_absvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_ABS (VNx8DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
rtx
gen_pred_sqrtvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SQRT (VNx8DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rsqrt7vnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (1,
		operand3),
	94),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rec7vnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (1,
		operand3),
	95),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rsqrt7vnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		operand3),
	94),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rec7vnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		operand3),
	95),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rsqrt7vnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand3),
	94),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rec7vnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand3),
	95),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rsqrt7vnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (1,
		operand3),
	94),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rec7vnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (1,
		operand3),
	95),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rsqrt7vnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (1,
		operand3),
	94),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rec7vnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (1,
		operand3),
	95),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rsqrt7vnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		operand3),
	94),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rec7vnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		operand3),
	95),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rsqrt7vnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (1,
		operand3),
	94),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rec7vnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (1,
		operand3),
	95),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rsqrt7vnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (1,
		operand3),
	94),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rec7vnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (1,
		operand3),
	95),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rsqrt7vnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (1,
		operand3),
	94),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
rtx
gen_pred_rec7vnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (1,
		operand3),
	95),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
rtx
gen_pred_classvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (1,
		operand3),
	96),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
rtx
gen_pred_classvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (1,
		operand3),
	96),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
rtx
gen_pred_classvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand3),
	96),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
rtx
gen_pred_classvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (1,
		operand3),
	96),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
rtx
gen_pred_classvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (1,
		operand3),
	96),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
rtx
gen_pred_classvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (1,
		operand3),
	96),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
rtx
gen_pred_classvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand3),
	96),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
rtx
gen_pred_classvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (1,
		operand3),
	96),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
rtx
gen_pred_classvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (1,
		operand3),
	96),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
rtx
gen_pred_dual_widen_addvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
rtx
gen_pred_dual_widen_subvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
rtx
gen_pred_dual_widen_mulvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
rtx
gen_pred_dual_widen_addvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
rtx
gen_pred_dual_widen_subvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
rtx
gen_pred_dual_widen_mulvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
rtx
gen_pred_dual_widen_addvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
rtx
gen_pred_dual_widen_subvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
rtx
gen_pred_dual_widen_mulvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
rtx
gen_pred_dual_widen_addvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
rtx
gen_pred_dual_widen_subvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
rtx
gen_pred_dual_widen_mulvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
rtx
gen_pred_dual_widen_addvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
rtx
gen_pred_dual_widen_subvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
rtx
gen_pred_dual_widen_mulvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
rtx
gen_pred_dual_widen_addvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
rtx
gen_pred_dual_widen_subvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
rtx
gen_pred_dual_widen_mulvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
rtx
gen_pred_dual_widen_addvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
rtx
gen_pred_dual_widen_subvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
rtx
gen_pred_dual_widen_mulvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
rtx
gen_pred_dual_widen_addvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
rtx
gen_pred_dual_widen_subvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
rtx
gen_pred_dual_widen_mulvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
rtx
gen_pred_single_widen_addvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
rtx
gen_pred_single_widen_subvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
rtx
gen_pred_single_widen_addvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
rtx
gen_pred_single_widen_subvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
rtx
gen_pred_single_widen_addvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
rtx
gen_pred_single_widen_subvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
rtx
gen_pred_single_widen_addvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
rtx
gen_pred_single_widen_subvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4)),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
rtx
gen_pred_single_widen_addvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
rtx
gen_pred_single_widen_subvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
rtx
gen_pred_single_widen_addvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
rtx
gen_pred_single_widen_subvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
rtx
gen_pred_single_widen_addvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
rtx
gen_pred_single_widen_subvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
rtx
gen_pred_single_widen_addvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
rtx
gen_pred_single_widen_subvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	operand3,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand4))),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
rtx
gen_pred_widen_mul_addvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
rtx
gen_pred_widen_mul_subvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
rtx
gen_pred_widen_mul_addvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
rtx
gen_pred_widen_mul_subvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
rtx
gen_pred_widen_mul_addvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
rtx
gen_pred_widen_mul_subvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
rtx
gen_pred_widen_mul_addvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
rtx
gen_pred_widen_mul_subvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
rtx
gen_pred_widen_mul_addvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
rtx
gen_pred_widen_mul_subvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
rtx
gen_pred_widen_mul_addvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
rtx
gen_pred_widen_mul_subvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
rtx
gen_pred_widen_mul_addvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
rtx
gen_pred_widen_mul_subvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
rtx
gen_pred_widen_mul_addvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
rtx
gen_pred_widen_mul_subvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4)),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
rtx
gen_pred_widen_mul_neg_addvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_NEG (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
rtx
gen_pred_widen_mul_neg_subvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_NEG (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
rtx
gen_pred_widen_mul_neg_addvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
rtx
gen_pred_widen_mul_neg_subvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
rtx
gen_pred_widen_mul_neg_addvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_NEG (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
rtx
gen_pred_widen_mul_neg_subvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_NEG (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
rtx
gen_pred_widen_mul_neg_addvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_NEG (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
rtx
gen_pred_widen_mul_neg_subvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_NEG (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand3),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
rtx
gen_pred_widen_mul_neg_addvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_NEG (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
rtx
gen_pred_widen_mul_neg_subvnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_NEG (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
rtx
gen_pred_widen_mul_neg_addvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
rtx
gen_pred_widen_mul_neg_subvnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
rtx
gen_pred_widen_mul_neg_addvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_NEG (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
rtx
gen_pred_widen_mul_neg_subvnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_NEG (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
rtx
gen_pred_widen_mul_neg_addvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_NEG (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
rtx
gen_pred_widen_mul_neg_subvnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_NEG (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand3)),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand4))),
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
rtx
gen_pred_mergevnx1sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
rtx
gen_pred_mergevnx2sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
rtx
gen_pred_mergevnx4sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
rtx
gen_pred_mergevnx8sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
rtx
gen_pred_mergevnx16sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
rtx
gen_pred_mergevnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
rtx
gen_pred_mergevnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
rtx
gen_pred_mergevnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
rtx
gen_pred_mergevnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand3),
	operand2,
	operand4),
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_x_fvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_xu_fvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_x_fvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_xu_fvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_x_fvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_xu_fvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_x_fvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_xu_fvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_x_fvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_xu_fvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_x_fvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_xu_fvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_x_fvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_xu_fvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_x_fvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_xu_fvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_x_fvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
rtx
gen_pred_fcvt_xu_fvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fix_truncvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx1SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fixuns_truncvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx1SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fix_truncvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx2SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fixuns_truncvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx2SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fix_truncvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx4SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fixuns_truncvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx4SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fix_truncvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx8SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fixuns_truncvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx8SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fix_truncvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx16SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fixuns_truncvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx16SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fix_truncvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx1DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fixuns_truncvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx1DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fix_truncvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx2DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fixuns_truncvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx2DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fix_truncvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx4DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fixuns_truncvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx4DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fix_truncvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx8DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
rtx
gen_pred_fixuns_truncvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx8DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx1SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatunsvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx1SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx2SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatunsvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx2SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx4SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatunsvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx4SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx8SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatunsvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx8SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx16SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatunsvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx16SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx1DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatunsvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx1DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx2DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatunsvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx2DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx4DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatunsvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx4DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx8DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
rtx
gen_pred_floatunsvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx8DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
rtx
gen_pred_widen_fcvt_x_fvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
rtx
gen_pred_widen_fcvt_xu_fvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
rtx
gen_pred_widen_fcvt_x_fvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
rtx
gen_pred_widen_fcvt_xu_fvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
rtx
gen_pred_widen_fcvt_x_fvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
rtx
gen_pred_widen_fcvt_xu_fvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
rtx
gen_pred_widen_fcvt_x_fvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
rtx
gen_pred_widen_fcvt_xu_fvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
rtx
gen_pred_widen_fix_truncvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx1DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
rtx
gen_pred_widen_fixuns_truncvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx1DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
rtx
gen_pred_widen_fix_truncvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx2DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
rtx
gen_pred_widen_fixuns_truncvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx2DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
rtx
gen_pred_widen_fix_truncvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx4DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
rtx
gen_pred_widen_fixuns_truncvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx4DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
rtx
gen_pred_widen_fix_truncvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx8DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
rtx
gen_pred_widen_fixuns_truncvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx8DImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx1SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatunsvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx1SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx2SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatunsvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx2SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx4SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatunsvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx4SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx8SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatunsvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx8SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx16SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatunsvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx16SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx1DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatunsvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx1DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx2DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatunsvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx2DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx4DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatunsvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx4DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx8DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
rtx
gen_pred_widen_floatunsvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx8DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6610 */
rtx
gen_pred_extendvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT_EXTEND (VNx1DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6610 */
rtx
gen_pred_extendvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT_EXTEND (VNx2DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6610 */
rtx
gen_pred_extendvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT_EXTEND (VNx4DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6610 */
rtx
gen_pred_extendvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT_EXTEND (VNx8DFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_x_fvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_xu_fvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_x_fvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_xu_fvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_x_fvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_xu_fvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_x_fvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_xu_fvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_x_fvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_xu_fvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_x_fvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_xu_fvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_x_fvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_xu_fvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_x_fvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_xu_fvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_x_fvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (1,
		operand3),
	100),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
rtx
gen_pred_narrow_fcvt_xu_fvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (1,
		operand3),
	101),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fix_truncvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx1HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fixuns_truncvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx1HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fix_truncvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx2HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fixuns_truncvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx2HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fix_truncvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx4HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fixuns_truncvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx4HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fix_truncvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx8HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fixuns_truncvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx8HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fix_truncvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx16HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fixuns_truncvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx16HImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fix_truncvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx1SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fixuns_truncvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx1SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fix_truncvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx2SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fixuns_truncvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx2SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fix_truncvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx4SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fixuns_truncvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx4SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fix_truncvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FIX (VNx8SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
rtx
gen_pred_narrow_fixuns_truncvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FIX (VNx8SImode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
rtx
gen_pred_narrow_floatvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx1SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
rtx
gen_pred_narrow_floatunsvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx1SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
rtx
gen_pred_narrow_floatvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx2SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
rtx
gen_pred_narrow_floatunsvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx2SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
rtx
gen_pred_narrow_floatvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx4SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
rtx
gen_pred_narrow_floatunsvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx4SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
rtx
gen_pred_narrow_floatvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT (VNx8SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
rtx
gen_pred_narrow_floatunsvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSIGNED_FLOAT (VNx8SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6693 */
rtx
gen_pred_truncvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT_TRUNCATE (VNx1SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6693 */
rtx
gen_pred_truncvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT_TRUNCATE (VNx2SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6693 */
rtx
gen_pred_truncvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT_TRUNCATE (VNx4SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6693 */
rtx
gen_pred_truncvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_FLOAT_TRUNCATE (VNx8SFmode,
	operand3),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6712 */
rtx
gen_pred_rod_truncvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (1,
		gen_rtx_FLOAT_TRUNCATE (VNx1SFmode,
	operand3)),
	102),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6712 */
rtx
gen_pred_rod_truncvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_FLOAT_TRUNCATE (VNx2SFmode,
	operand3)),
	102),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6712 */
rtx
gen_pred_rod_truncvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		gen_rtx_FLOAT_TRUNCATE (VNx4SFmode,
	operand3)),
	102),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6712 */
rtx
gen_pred_rod_truncvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (1,
		gen_rtx_FLOAT_TRUNCATE (VNx8SFmode,
	operand3)),
	102),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx1qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx1qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx1qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx1qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx1qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx1qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx1qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx1qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx2qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx2qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx2qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx2qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx2qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx2qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx2qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx2qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx4qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx4qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx4qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx4qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx4qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx4qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx4qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx4qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx8qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx8qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx8qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx8qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx8qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx8qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx8qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx8qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx16qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx16qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx16qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx16qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx16qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx16qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx16qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx16qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx32qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx32qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx32qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx32qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx32qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx32qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx32qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx32qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx64qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx64qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx64qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx64qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx64qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx64qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx64qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx64qivnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx1hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx1hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx1hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx1hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx1hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx1hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx1hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx1hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx2hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx2hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx2hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx2hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx2hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx2hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx2hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx2hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx4hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx4hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx4hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx4hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx4hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx4hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx4hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx4hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx8hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx8hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx8hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx8hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx8hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx8hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx8hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx8hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx16hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx16hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx16hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx16hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx16hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx16hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx16hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx16hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx32hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx32hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx32hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx32hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx32hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx32hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx32hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx32hivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx1sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx1sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx1sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx1sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx1sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx1sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx1sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx1sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx2sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx2sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx2sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx2sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx2sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx2sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx2sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx2sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx4sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx4sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx4sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx4sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx4sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx4sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx4sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx4sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx8sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx8sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx8sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx8sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx8sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx8sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx8sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx8sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx16sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx16sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx16sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx16sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx16sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx16sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx16sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx16sivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx1divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx1divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx1divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx1divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx1divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx1divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx1divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx1divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx2divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx2divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx2divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx2divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx2divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx2divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx2divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx2divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx4divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx4divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx4divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx4divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx4divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx4divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx4divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx4divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_sumvnx8divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxuvnx8divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_maxvnx8divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minuvnx8divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_minvnx8divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_andvnx8divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_orvnx8divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
rtx
gen_pred_reduc_xorvnx8divnx1DI (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx1qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx1qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx1qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx1qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx1qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx1qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx1qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx1qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx2qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx2qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx2qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx2qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx2qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx2qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx2qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx2qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx4qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx4qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx4qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx4qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx4qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx4qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx4qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx4qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx8qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx8qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx8qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx8qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx8qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx8qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx8qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx8qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx16qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx16qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx16qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx16qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx16qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx16qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx16qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx16qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx32qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx32qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx32qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx32qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx32qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx32qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx32qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx32qivnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx1hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx1hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx1hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx1hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx1hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx1hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx1hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx1hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx2hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx2hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx2hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx2hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx2hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx2hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx2hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx2hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx4hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx4hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx4hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx4hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx4hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx4hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx4hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx4hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx8hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx8hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx8hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx8hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx8hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx8hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx8hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx8hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx16hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx16hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx16hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx16hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx16hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx16hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx16hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx16hivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx1sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx1sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx1sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx1sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx1sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx1sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx1sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx1sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx2sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx2sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx2sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx2sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx2sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx2sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx2sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx2sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx4sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx4sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx4sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx4sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx4sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx4sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx4sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx4sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_sumvnx8sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxuvnx8sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMAX (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_maxvnx8sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minuvnx8sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_UMIN (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_minvnx8sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_andvnx8sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_AND (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_orvnx8sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_IOR (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
rtx
gen_pred_reduc_xorvnx8sivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_XOR (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx1qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx1qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx2qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx2qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx4qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx4qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx8qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx8qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx16qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx16qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx32qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx32qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx64qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx64qivnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx1hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx1hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx2hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx2hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx4hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx4hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx8hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx8hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx16hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx16hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx32hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx32hivnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx1sivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx1sivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx2sivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx2sivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx4sivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx4sivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx8sivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx8sivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusvnx16sivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
rtx
gen_pred_widen_reduc_plusuvnx16sivnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusvnx1qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusuvnx1qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusvnx2qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusuvnx2qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusvnx4qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusuvnx4qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusvnx8qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusuvnx8qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusvnx16qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusuvnx16qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusvnx32qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusuvnx32qivnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusvnx1hivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusuvnx1hivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusvnx2hivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusuvnx2hivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusvnx4hivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusuvnx4hivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusvnx8hivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusuvnx8hivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusvnx16hivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
rtx
gen_pred_widen_reduc_plusuvnx16hivnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	105));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_maxvnx1sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_minvnx1sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_maxvnx2sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_minvnx2sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_maxvnx4sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_minvnx4sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_maxvnx8sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_minvnx8sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_maxvnx16sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_minvnx16sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_maxvnx1dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_minvnx1dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_maxvnx2dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_minvnx2dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_maxvnx4dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_minvnx4dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_maxvnx8dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
rtx
gen_pred_reduc_minvnx8dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
rtx
gen_pred_reduc_maxvnx1sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
rtx
gen_pred_reduc_minvnx1sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
rtx
gen_pred_reduc_maxvnx2sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
rtx
gen_pred_reduc_minvnx2sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
rtx
gen_pred_reduc_maxvnx4sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
rtx
gen_pred_reduc_minvnx4sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
rtx
gen_pred_reduc_maxvnx8sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMAX (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
rtx
gen_pred_reduc_minvnx8sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_SMIN (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusovnx1sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusuvnx1sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusovnx2sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusuvnx2sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusovnx4sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusuvnx4sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusovnx8sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusuvnx8sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusovnx16sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusuvnx16sfvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusovnx1dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusuvnx1dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusovnx2dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusuvnx2dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusovnx4dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusuvnx4dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusovnx8dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
rtx
gen_pred_reduc_plusuvnx8dfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
rtx
gen_pred_reduc_plusovnx1sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
rtx
gen_pred_reduc_plusuvnx1sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
rtx
gen_pred_reduc_plusovnx2sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
rtx
gen_pred_reduc_plusuvnx2sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
rtx
gen_pred_reduc_plusovnx4sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
rtx
gen_pred_reduc_plusuvnx4sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
rtx
gen_pred_reduc_plusovnx8sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
rtx
gen_pred_reduc_plusuvnx8sfvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand4,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	operand3),
		operand2),
	103)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
rtx
gen_pred_widen_reduc_plusovnx1sfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
rtx
gen_pred_widen_reduc_plusuvnx1sfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
rtx
gen_pred_widen_reduc_plusovnx2sfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
rtx
gen_pred_widen_reduc_plusuvnx2sfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
rtx
gen_pred_widen_reduc_plusovnx4sfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
rtx
gen_pred_widen_reduc_plusuvnx4sfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
rtx
gen_pred_widen_reduc_plusovnx8sfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
rtx
gen_pred_widen_reduc_plusuvnx8sfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
rtx
gen_pred_widen_reduc_plusovnx16sfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104)),
	71));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
rtx
gen_pred_widen_reduc_plusuvnx16sfvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand3,
		operand4,
		operand2),
	104)),
	72));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6998 */
rtx
gen_pred_extract_first_truncvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (SImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6998 */
rtx
gen_pred_extract_first_truncvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (SImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6998 */
rtx
gen_pred_extract_first_truncvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (SImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6998 */
rtx
gen_pred_extract_first_truncvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (SImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slideupvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	106));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
rtx
gen_pred_slidedownvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	107));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1upvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
rtx
gen_pred_slide1downvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1upvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	110));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1downvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	111));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1upvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	110));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1downvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	111));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1upvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	110));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1downvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	111));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1upvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	110));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1downvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	111));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1upvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	110));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1downvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	111));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1upvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	110));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1downvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	111));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1upvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	110));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1downvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	111));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1upvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	110));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1downvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	111));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1upvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	110));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
rtx
gen_pred_slide1downvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	111));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
rtx
gen_pred_gathervnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx1qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx2qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx4qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx8qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx16qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx32qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx64qi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx1hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx2hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx4hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx8hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx16hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx32hi_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx1si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx2si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx4si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx8si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx16si_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx1di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx2di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx4di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx8di_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx1sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx2sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx4sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx8sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx16sf_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx1df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx2df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx4df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
rtx
gen_pred_gathervnx8df_scalar (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	112),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
rtx
gen_pred_gatherei16vnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED,
	rtx operand8 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand3,
		operand4),
	113),
	operand2));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
rtx
gen_pred_compressvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand3,
		operand4,
		operand5,
		operand6,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7248 */
rtx
gen_read_vlsi (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_REG (SImode,
	66));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7256 */
rtx
gen_read_vldi_zero_extend (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_REG (SImode,
	66)));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx1qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1QImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx2qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2QImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx4qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4QImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8QImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx1hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1HImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx2hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2HImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4HImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx1si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx1sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1SFmode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2SFmode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx1df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DFmode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
rtx
gen_pred_fault_loadvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED,
	rtx operand7 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (1,
		operand3),
	115),
	operand2)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		copy_rtx (operand0)),
	115))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:488 */
rtx
gen_addvsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_64BIT && SImode == SImode)
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);
      rtx t5 = gen_reg_rtx (DImode);
      rtx t6 = gen_reg_rtx (DImode);

      emit_insn (gen_addsi3 (operands[0], operands[1], operands[2]));
      if (GET_CODE (operands[1]) != CONST_INT)
	emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0));
      else
	t4 = operands[1];
      if (GET_CODE (operands[2]) != CONST_INT)
	emit_insn (gen_extend_insn (t5, operands[2], DImode, SImode, 0));
      else
	t5 = operands[2];
      emit_insn (gen_adddi3 (t3, t4, t5));
      emit_insn (gen_extend_insn (t6, operands[0], DImode, SImode, 0));

      riscv_expand_conditional_branch (operands[3], NE, t6, t3);
    }
  else
    {
      rtx t3 = gen_reg_rtx (SImode);
      rtx t4 = gen_reg_rtx (SImode);

      emit_insn (gen_add3_insn (operands[0], operands[1], operands[2]));
      rtx cmp1 = gen_rtx_LT (SImode, operands[2], const0_rtx);
      emit_insn (gen_cstoresi4 (t3, cmp1, operands[2], const0_rtx));
      rtx cmp2 = gen_rtx_LT (SImode, operands[0], operands[1]);

      emit_insn (gen_cstoresi4 (t4, cmp2, operands[0], operands[1]));
      riscv_expand_conditional_branch (operands[3], NE, t3, t4);
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:488 */
rtx
gen_addvdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_64BIT && DImode == SImode)
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);
      rtx t5 = gen_reg_rtx (DImode);
      rtx t6 = gen_reg_rtx (DImode);

      emit_insn (gen_addsi3 (operands[0], operands[1], operands[2]));
      if (GET_CODE (operands[1]) != CONST_INT)
	emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0));
      else
	t4 = operands[1];
      if (GET_CODE (operands[2]) != CONST_INT)
	emit_insn (gen_extend_insn (t5, operands[2], DImode, SImode, 0));
      else
	t5 = operands[2];
      emit_insn (gen_adddi3 (t3, t4, t5));
      emit_insn (gen_extend_insn (t6, operands[0], DImode, SImode, 0));

      riscv_expand_conditional_branch (operands[3], NE, t6, t3);
    }
  else
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);

      emit_insn (gen_add3_insn (operands[0], operands[1], operands[2]));
      rtx cmp1 = gen_rtx_LT (DImode, operands[2], const0_rtx);
      emit_insn (gen_cstoredi4 (t3, cmp1, operands[2], const0_rtx));
      rtx cmp2 = gen_rtx_LT (DImode, operands[0], operands[1]);

      emit_insn (gen_cstoredi4 (t4, cmp2, operands[0], operands[1]));
      riscv_expand_conditional_branch (operands[3], NE, t3, t4);
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:532 */
rtx
gen_uaddvsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 538 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_64BIT && SImode == SImode)
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);

      if (GET_CODE (operands[1]) != CONST_INT)
	emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0));
      else
	t3 = operands[1];
      emit_insn (gen_addsi3 (operands[0], operands[1], operands[2]));
      emit_insn (gen_extend_insn (t4, operands[0], DImode, SImode, 0));

      riscv_expand_conditional_branch (operands[3], LTU, t4, t3);
    }
  else
    {
      emit_insn (gen_add3_insn (operands[0], operands[1], operands[2]));
      riscv_expand_conditional_branch (operands[3], LTU, operands[0],
				       operands[1]);
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:532 */
rtx
gen_uaddvdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 538 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_64BIT && DImode == SImode)
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);

      if (GET_CODE (operands[1]) != CONST_INT)
	emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0));
      else
	t3 = operands[1];
      emit_insn (gen_addsi3 (operands[0], operands[1], operands[2]));
      emit_insn (gen_extend_insn (t4, operands[0], DImode, SImode, 0));

      riscv_expand_conditional_branch (operands[3], LTU, t4, t3);
    }
  else
    {
      emit_insn (gen_add3_insn (operands[0], operands[1], operands[2]));
      riscv_expand_conditional_branch (operands[3], LTU, operands[0],
				       operands[1]);
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:619 */
rtx
gen_subvsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 625 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_64BIT && SImode == SImode)
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);
      rtx t5 = gen_reg_rtx (DImode);
      rtx t6 = gen_reg_rtx (DImode);

      emit_insn (gen_subsi3 (operands[0], operands[1], operands[2]));
      if (GET_CODE (operands[1]) != CONST_INT)
	emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0));
      else
	t4 = operands[1];
      if (GET_CODE (operands[2]) != CONST_INT)
	emit_insn (gen_extend_insn (t5, operands[2], DImode, SImode, 0));
      else
	t5 = operands[2];
      emit_insn (gen_subdi3 (t3, t4, t5));
      emit_insn (gen_extend_insn (t6, operands[0], DImode, SImode, 0));

      riscv_expand_conditional_branch (operands[3], NE, t6, t3);
    }
  else
    {
      rtx t3 = gen_reg_rtx (SImode);
      rtx t4 = gen_reg_rtx (SImode);

      emit_insn (gen_sub3_insn (operands[0], operands[1], operands[2]));

      rtx cmp1 = gen_rtx_LT (SImode, operands[2], const0_rtx);
      emit_insn (gen_cstoresi4 (t3, cmp1, operands[2], const0_rtx));

      rtx cmp2 = gen_rtx_LT (SImode, operands[1], operands[0]);
      emit_insn (gen_cstoresi4 (t4, cmp2, operands[1], operands[0]));

      riscv_expand_conditional_branch (operands[3], NE, t3, t4);
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:619 */
rtx
gen_subvdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 625 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_64BIT && DImode == SImode)
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);
      rtx t5 = gen_reg_rtx (DImode);
      rtx t6 = gen_reg_rtx (DImode);

      emit_insn (gen_subsi3 (operands[0], operands[1], operands[2]));
      if (GET_CODE (operands[1]) != CONST_INT)
	emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0));
      else
	t4 = operands[1];
      if (GET_CODE (operands[2]) != CONST_INT)
	emit_insn (gen_extend_insn (t5, operands[2], DImode, SImode, 0));
      else
	t5 = operands[2];
      emit_insn (gen_subdi3 (t3, t4, t5));
      emit_insn (gen_extend_insn (t6, operands[0], DImode, SImode, 0));

      riscv_expand_conditional_branch (operands[3], NE, t6, t3);
    }
  else
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);

      emit_insn (gen_sub3_insn (operands[0], operands[1], operands[2]));

      rtx cmp1 = gen_rtx_LT (DImode, operands[2], const0_rtx);
      emit_insn (gen_cstoredi4 (t3, cmp1, operands[2], const0_rtx));

      rtx cmp2 = gen_rtx_LT (DImode, operands[1], operands[0]);
      emit_insn (gen_cstoredi4 (t4, cmp2, operands[1], operands[0]));

      riscv_expand_conditional_branch (operands[3], NE, t3, t4);
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:666 */
rtx
gen_usubvsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 672 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_64BIT && SImode == SImode)
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);

      if (GET_CODE (operands[1]) != CONST_INT)
	emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0));
      else
	t3 = operands[1];
      emit_insn (gen_subsi3 (operands[0], operands[1], operands[2]));
      emit_insn (gen_extend_insn (t4, operands[0], DImode, SImode, 0));

      riscv_expand_conditional_branch (operands[3], LTU, t3, t4);
    }
  else
    {
      emit_insn (gen_sub3_insn (operands[0], operands[1], operands[2]));
      riscv_expand_conditional_branch (operands[3], LTU, operands[1],
				       operands[0]);
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:666 */
rtx
gen_usubvdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 672 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_64BIT && DImode == SImode)
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);

      if (GET_CODE (operands[1]) != CONST_INT)
	emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0));
      else
	t3 = operands[1];
      emit_insn (gen_subsi3 (operands[0], operands[1], operands[2]));
      emit_insn (gen_extend_insn (t4, operands[0], DImode, SImode, 0));

      riscv_expand_conditional_branch (operands[3], LTU, t3, t4);
    }
  else
    {
      emit_insn (gen_sub3_insn (operands[0], operands[1], operands[2]));
      riscv_expand_conditional_branch (operands[3], LTU, operands[1],
				       operands[0]);
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:789 */
rtx
gen_mulvsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 795 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_64BIT && SImode == SImode)
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);
      rtx t5 = gen_reg_rtx (DImode);
      rtx t6 = gen_reg_rtx (DImode);

      if (GET_CODE (operands[1]) != CONST_INT)
	emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0));
      else
	t4 = operands[1];
      if (GET_CODE (operands[2]) != CONST_INT)
	emit_insn (gen_extend_insn (t5, operands[2], DImode, SImode, 0));
      else
	t5 = operands[2];
      emit_insn (gen_muldi3 (t3, t4, t5));

      emit_move_insn (operands[0], gen_lowpart (SImode, t3));
      emit_insn (gen_extend_insn (t6, operands[0], DImode, SImode, 0));

      riscv_expand_conditional_branch (operands[3], NE, t6, t3);
    }
  else
    {
      rtx hp = gen_reg_rtx (SImode);
      rtx lp = gen_reg_rtx (SImode);

      emit_insn (gen_smulsi3_highpart (hp, operands[1], operands[2]));
      emit_insn (gen_mulsi3 (operands[0], operands[1], operands[2]));
      emit_insn (gen_ashrsi3 (lp, operands[0],
				  GEN_INT (BITS_PER_WORD - 1)));

      riscv_expand_conditional_branch (operands[3], NE, hp, lp);
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:789 */
rtx
gen_mulvdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 795 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_64BIT && DImode == SImode)
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);
      rtx t5 = gen_reg_rtx (DImode);
      rtx t6 = gen_reg_rtx (DImode);

      if (GET_CODE (operands[1]) != CONST_INT)
	emit_insn (gen_extend_insn (t4, operands[1], DImode, SImode, 0));
      else
	t4 = operands[1];
      if (GET_CODE (operands[2]) != CONST_INT)
	emit_insn (gen_extend_insn (t5, operands[2], DImode, SImode, 0));
      else
	t5 = operands[2];
      emit_insn (gen_muldi3 (t3, t4, t5));

      emit_move_insn (operands[0], gen_lowpart (SImode, t3));
      emit_insn (gen_extend_insn (t6, operands[0], DImode, SImode, 0));

      riscv_expand_conditional_branch (operands[3], NE, t6, t3);
    }
  else
    {
      rtx hp = gen_reg_rtx (DImode);
      rtx lp = gen_reg_rtx (DImode);

      emit_insn (gen_smuldi3_highpart (hp, operands[1], operands[2]));
      emit_insn (gen_muldi3 (operands[0], operands[1], operands[2]));
      emit_insn (gen_ashrdi3 (lp, operands[0],
				  GEN_INT (BITS_PER_WORD - 1)));

      riscv_expand_conditional_branch (operands[3], NE, hp, lp);
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:834 */
rtx
gen_umulvsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 840 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_64BIT && SImode == SImode)
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);
      rtx t5 = gen_reg_rtx (DImode);
      rtx t6 = gen_reg_rtx (DImode);
      rtx t7 = gen_reg_rtx (DImode);
      rtx t8 = gen_reg_rtx (DImode);

      if (GET_CODE (operands[1]) != CONST_INT)
	emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0));
      else
	t3 = operands[1];
      if (GET_CODE (operands[2]) != CONST_INT)
	emit_insn (gen_extend_insn (t4, operands[2], DImode, SImode, 0));
      else
	t4 = operands[2];

      emit_insn (gen_ashldi3 (t5, t3, GEN_INT (32)));
      emit_insn (gen_ashldi3 (t6, t4, GEN_INT (32)));
      emit_insn (gen_umuldi3_highpart (t7, t5, t6));
      emit_move_insn (operands[0], gen_lowpart (SImode, t7));
      emit_insn (gen_lshrdi3 (t8, t7, GEN_INT (32)));

      riscv_expand_conditional_branch (operands[3], NE, t8, const0_rtx);
    }
  else
    {
      rtx hp = gen_reg_rtx (SImode);

      emit_insn (gen_umulsi3_highpart (hp, operands[1], operands[2]));
      emit_insn (gen_mulsi3 (operands[0], operands[1], operands[2]));

      riscv_expand_conditional_branch (operands[3], NE, hp, const0_rtx);
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:834 */
rtx
gen_umulvdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 840 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_64BIT && DImode == SImode)
    {
      rtx t3 = gen_reg_rtx (DImode);
      rtx t4 = gen_reg_rtx (DImode);
      rtx t5 = gen_reg_rtx (DImode);
      rtx t6 = gen_reg_rtx (DImode);
      rtx t7 = gen_reg_rtx (DImode);
      rtx t8 = gen_reg_rtx (DImode);

      if (GET_CODE (operands[1]) != CONST_INT)
	emit_insn (gen_extend_insn (t3, operands[1], DImode, SImode, 0));
      else
	t3 = operands[1];
      if (GET_CODE (operands[2]) != CONST_INT)
	emit_insn (gen_extend_insn (t4, operands[2], DImode, SImode, 0));
      else
	t4 = operands[2];

      emit_insn (gen_ashldi3 (t5, t3, GEN_INT (32)));
      emit_insn (gen_ashldi3 (t6, t4, GEN_INT (32)));
      emit_insn (gen_umuldi3_highpart (t7, t5, t6));
      emit_move_insn (operands[0], gen_lowpart (SImode, t7));
      emit_insn (gen_lshrdi3 (t8, t7, GEN_INT (32)));

      riscv_expand_conditional_branch (operands[3], NE, t8, const0_rtx);
    }
  else
    {
      rtx hp = gen_reg_rtx (DImode);

      emit_insn (gen_umuldi3_highpart (hp, operands[1], operands[2]));
      emit_insn (gen_muldi3 (operands[0], operands[1], operands[2]));

      riscv_expand_conditional_branch (operands[3], NE, hp, const0_rtx);
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:910 */
rtx
gen_mulditi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 915 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx low = gen_reg_rtx (DImode);
  emit_insn (gen_muldi3 (low, operands[1], operands[2]));

  rtx high = gen_reg_rtx (DImode);
  emit_insn (gen_smuldi3_highpart (high, operands[1], operands[2]));

  emit_move_insn (gen_lowpart (DImode, operands[0]), low);
  emit_move_insn (gen_highpart (DImode, operands[0]), high);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	operand1),
	gen_rtx_SIGN_EXTEND (TImode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:910 */
rtx
gen_umulditi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 915 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx low = gen_reg_rtx (DImode);
  emit_insn (gen_muldi3 (low, operands[1], operands[2]));

  rtx high = gen_reg_rtx (DImode);
  emit_insn (gen_umuldi3_highpart (high, operands[1], operands[2]));

  emit_move_insn (gen_lowpart (DImode, operands[0]), low);
  emit_move_insn (gen_highpart (DImode, operands[0]), high);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (TImode,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1),
	gen_rtx_ZERO_EXTEND (TImode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:941 */
rtx
gen_usmulditi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 946 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx low = gen_reg_rtx (DImode);
  emit_insn (gen_muldi3 (low, operands[1], operands[2]));

  rtx high = gen_reg_rtx (DImode);
  emit_insn (gen_usmuldi3_highpart (high, operands[1], operands[2]));

  emit_move_insn (gen_lowpart (DImode, operands[0]), low);
  emit_move_insn (gen_highpart (DImode, operands[0]), high);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (TImode,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1),
	gen_rtx_SIGN_EXTEND (TImode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:972 */
rtx
gen_mulsidi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 979 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx temp = gen_reg_rtx (SImode);
  emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
  emit_insn (gen_smulsi3_highpart (riscv_subword (operands[0], true),
				     operands[1], operands[2]));
  emit_insn (gen_movsi (riscv_subword (operands[0], false), temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:972 */
rtx
gen_umulsidi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 979 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx temp = gen_reg_rtx (SImode);
  emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
  emit_insn (gen_umulsi3_highpart (riscv_subword (operands[0], true),
				     operands[1], operands[2]));
  emit_insn (gen_movsi (riscv_subword (operands[0], false), temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (DImode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (DImode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1003 */
rtx
gen_usmulsidi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1010 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx temp = gen_reg_rtx (SImode);
  emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
  emit_insn (gen_usmulsi3_highpart (riscv_subword (operands[0], true),
				     operands[1], operands[2]));
  emit_insn (gen_movsi (riscv_subword (operands[0], false), temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (DImode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1362 */
rtx
gen_zero_extendsidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1367 */
extern rtx_insn *gen_split_1 (rtx_insn *, rtx *);
rtx_insn *
gen_split_1 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_1 (riscv.md:1367)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1384 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ operands[1] = gen_lowpart (DImode, operands[1]); }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (32)])));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_LSHIFTRT (DImode,
	copy_rtx (operand0),
	const_int_rtx[MAX_SAVED_CONST_INT + (32)])));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1388 */
rtx
gen_zero_extendhisi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1388 */
rtx
gen_zero_extendhidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1394 */
extern rtx_insn *gen_split_2 (rtx_insn *, rtx *);
rtx_insn *
gen_split_2 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_2 (riscv.md:1394)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
    operands[1] = gen_lowpart (SImode, operands[1]);
    operands[2] = GEN_INT(GET_MODE_BITSIZE(SImode) - 16);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_LSHIFTRT (SImode,
	copy_rtx (operand0),
	copy_rtx (operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1394 */
extern rtx_insn *gen_split_3 (rtx_insn *, rtx *);
rtx_insn *
gen_split_3 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_3 (riscv.md:1394)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1409 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
    operands[1] = gen_lowpart (DImode, operands[1]);
    operands[2] = GEN_INT(GET_MODE_BITSIZE(DImode) - 16);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_LSHIFTRT (DImode,
	copy_rtx (operand0),
	copy_rtx (operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1445 */
rtx
gen_extendqihi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1445 */
rtx
gen_extendqisi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1445 */
rtx
gen_extendqidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1445 */
rtx
gen_extendhihi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1445 */
rtx
gen_extendhisi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1445 */
rtx
gen_extendhidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1450 */
extern rtx_insn *gen_split_4 (rtx_insn *, rtx *);
rtx_insn *
gen_split_4 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_4 (riscv.md:1450)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1463 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[0] = gen_lowpart (SImode, operands[0]);
  operands[1] = gen_lowpart (SImode, operands[1]);
  operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
			 - GET_MODE_BITSIZE (QImode));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_ASHIFTRT (SImode,
	copy_rtx (operand0),
	copy_rtx (operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1450 */
extern rtx_insn *gen_split_5 (rtx_insn *, rtx *);
rtx_insn *
gen_split_5 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_5 (riscv.md:1450)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1463 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[0] = gen_lowpart (SImode, operands[0]);
  operands[1] = gen_lowpart (SImode, operands[1]);
  operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
			 - GET_MODE_BITSIZE (QImode));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_ASHIFTRT (SImode,
	copy_rtx (operand0),
	copy_rtx (operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1450 */
extern rtx_insn *gen_split_6 (rtx_insn *, rtx *);
rtx_insn *
gen_split_6 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_6 (riscv.md:1450)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1463 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[0] = gen_lowpart (SImode, operands[0]);
  operands[1] = gen_lowpart (SImode, operands[1]);
  operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
			 - GET_MODE_BITSIZE (QImode));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_ASHIFTRT (SImode,
	copy_rtx (operand0),
	copy_rtx (operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1450 */
extern rtx_insn *gen_split_7 (rtx_insn *, rtx *);
rtx_insn *
gen_split_7 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_7 (riscv.md:1450)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1463 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[0] = gen_lowpart (SImode, operands[0]);
  operands[1] = gen_lowpart (SImode, operands[1]);
  operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
			 - GET_MODE_BITSIZE (HImode));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_ASHIFTRT (SImode,
	copy_rtx (operand0),
	copy_rtx (operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1450 */
extern rtx_insn *gen_split_8 (rtx_insn *, rtx *);
rtx_insn *
gen_split_8 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_8 (riscv.md:1450)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1463 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[0] = gen_lowpart (SImode, operands[0]);
  operands[1] = gen_lowpart (SImode, operands[1]);
  operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
			 - GET_MODE_BITSIZE (HImode));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_ASHIFTRT (SImode,
	copy_rtx (operand0),
	copy_rtx (operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1450 */
extern rtx_insn *gen_split_9 (rtx_insn *, rtx *);
rtx_insn *
gen_split_9 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_9 (riscv.md:1450)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1463 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[0] = gen_lowpart (SImode, operands[0]);
  operands[1] = gen_lowpart (SImode, operands[1]);
  operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
			 - GET_MODE_BITSIZE (HImode));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_ASHIFTRT (SImode,
	copy_rtx (operand0),
	copy_rtx (operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1501 */
rtx
gen_movhf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1505 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (riscv_legitimize_move (HFmode, operands[0], operands[1]))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1663 */
extern rtx_insn *gen_split_10 (rtx_insn *, rtx *);
rtx_insn *
gen_split_10 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_10 (riscv.md:1663)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]),
		      SImode, TRUE);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1663 */
extern rtx_insn *gen_split_11 (rtx_insn *, rtx *);
rtx_insn *
gen_split_11 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_11 (riscv.md:1663)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1669 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]),
		      DImode, TRUE);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1676 */
extern rtx_insn *gen_split_12 (rtx_insn *, rtx *);
rtx_insn *
gen_split_12 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_12 (riscv.md:1676)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_split_symbol (operands[2], operands[1],
		      MAX_MACHINE_MODE, &operands[3], TRUE);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1676 */
extern rtx_insn *gen_split_13 (rtx_insn *, rtx *);
rtx_insn *
gen_split_13 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_13 (riscv.md:1676)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_split_symbol (operands[2], operands[1],
		      MAX_MACHINE_MODE, &operands[3], TRUE);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1691 */
extern rtx_insn *gen_split_14 (rtx_insn *, rtx *);
rtx_insn *
gen_split_14 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_14 (riscv.md:1691)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1699 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]),
                      SImode, TRUE);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1691 */
extern rtx_insn *gen_split_15 (rtx_insn *, rtx *);
rtx_insn *
gen_split_15 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_15 (riscv.md:1691)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1699 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]),
                      DImode, TRUE);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1707 */
rtx
gen_movdi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1711 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (riscv_legitimize_move (DImode, operands[0], operands[1]))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1740 */
rtx
gen_movsi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1744 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (riscv_legitimize_move (SImode, operands[0], operands[1]))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1768 */
rtx
gen_movhi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1772 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (riscv_legitimize_move (HImode, operands[0], operands[1]))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1811 */
rtx
gen_movqi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1815 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (riscv_legitimize_move (QImode, operands[0], operands[1]))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1832 */
rtx
gen_movsf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1836 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (riscv_legitimize_move (SFmode, operands[0], operands[1]))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1863 */
rtx
gen_movdf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1867 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (riscv_legitimize_move (DFmode, operands[0], operands[1]))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1905 */
extern rtx_insn *gen_split_16 (rtx_insn *, rtx *);
rtx_insn *
gen_split_16 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_16 (riscv.md:1905)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1911 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_split_doubleword_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1905 */
extern rtx_insn *gen_split_17 (rtx_insn *, rtx *);
rtx_insn *
gen_split_17 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_17 (riscv.md:1905)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1911 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_split_doubleword_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1916 */
rtx
gen_cpymemsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1922 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (riscv_expand_block_move (operands[0], operands[1], operands[2]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2),
		gen_rtx_USE (VOIDmode,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1931 */
rtx
gen_clear_cache (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1935 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
#ifdef ICACHE_FLUSH_FUNC
  emit_library_call (gen_rtx_SYMBOL_REF (Pmode, ICACHE_FLUSH_FUNC),
		     LCT_NORMAL, VOIDmode, operands[0], Pmode,
		     operands[1], Pmode, const0_rtx, Pmode);
#else
  if (TARGET_ZIFENCEI)
    emit_insn (gen_fence_i ());
#endif
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1990 */
extern rtx_insn *gen_split_18 (rtx_insn *, rtx *);
rtx_insn *
gen_split_18 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_18 (riscv.md:1990)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1990 */
extern rtx_insn *gen_split_19 (rtx_insn *, rtx *);
rtx_insn *
gen_split_19 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_19 (riscv.md:1990)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1990 */
extern rtx_insn *gen_split_20 (rtx_insn *, rtx *);
rtx_insn *
gen_split_20 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_20 (riscv.md:1990)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2005 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2009 */
extern rtx_insn *gen_split_21 (rtx_insn *, rtx *);
rtx_insn *
gen_split_21 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_21 (riscv.md:2009)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2025 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2009 */
extern rtx_insn *gen_split_22 (rtx_insn *, rtx *);
rtx_insn *
gen_split_22 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_22 (riscv.md:2009)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2025 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2009 */
extern rtx_insn *gen_split_23 (rtx_insn *, rtx *);
rtx_insn *
gen_split_23 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_23 (riscv.md:2009)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2025 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2045 */
extern rtx_insn *gen_split_24 (rtx_insn *, rtx *);
rtx_insn *
gen_split_24 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_24 (riscv.md:2045)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2061 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2045 */
extern rtx_insn *gen_split_25 (rtx_insn *, rtx *);
rtx_insn *
gen_split_25 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_25 (riscv.md:2045)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2061 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2045 */
extern rtx_insn *gen_split_26 (rtx_insn *, rtx *);
rtx_insn *
gen_split_26 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_26 (riscv.md:2045)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2061 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2065 */
extern rtx_insn *gen_split_27 (rtx_insn *, rtx *);
rtx_insn *
gen_split_27 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_27 (riscv.md:2065)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2081 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2065 */
extern rtx_insn *gen_split_28 (rtx_insn *, rtx *);
rtx_insn *
gen_split_28 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_28 (riscv.md:2065)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2081 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2065 */
extern rtx_insn *gen_split_29 (rtx_insn *, rtx *);
rtx_insn *
gen_split_29 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_29 (riscv.md:2065)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2081 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2100 */
extern rtx_insn *gen_split_30 (rtx_insn *, rtx *);
rtx_insn *
gen_split_30 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_30 (riscv.md:2100)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2118 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2100 */
extern rtx_insn *gen_split_31 (rtx_insn *, rtx *);
rtx_insn *
gen_split_31 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_31 (riscv.md:2100)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2118 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2100 */
extern rtx_insn *gen_split_32 (rtx_insn *, rtx *);
rtx_insn *
gen_split_32 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_32 (riscv.md:2100)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2118 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2122 */
extern rtx_insn *gen_split_33 (rtx_insn *, rtx *);
rtx_insn *
gen_split_33 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_33 (riscv.md:2122)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2140 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2122 */
extern rtx_insn *gen_split_34 (rtx_insn *, rtx *);
rtx_insn *
gen_split_34 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_34 (riscv.md:2122)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2140 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2122 */
extern rtx_insn *gen_split_35 (rtx_insn *, rtx *);
rtx_insn *
gen_split_35 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_35 (riscv.md:2122)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2140 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[2] = gen_lowpart (QImode, operands[2]);
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2194 */
extern rtx_insn *gen_split_36 (rtx_insn *, rtx *);
rtx_insn *
gen_split_36 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_36 (riscv.md:2194)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2204 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  /* Op2 is a VOIDmode constant, so get the mode size from op1.  */
  operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[1])).to_constant ()
			 - exact_log2 (INTVAL (operands[2]) + 1));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (SImode,
	copy_rtx (operand3),
	copy_rtx (operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2194 */
extern rtx_insn *gen_split_37 (rtx_insn *, rtx *);
rtx_insn *
gen_split_37 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_37 (riscv.md:2194)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2204 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  /* Op2 is a VOIDmode constant, so get the mode size from op1.  */
  operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[1])).to_constant ()
			 - exact_log2 (INTVAL (operands[2]) + 1));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (DImode,
	copy_rtx (operand3),
	copy_rtx (operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2212 */
extern rtx_insn *gen_split_38 (rtx_insn *, rtx *);
rtx_insn *
gen_split_38 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_38 (riscv.md:2212)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2222 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[2] = GEN_INT (ctz_hwi (INTVAL (operands[2])));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (DImode,
	copy_rtx (operand3),
	copy_rtx (operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2230 */
extern rtx_insn *gen_split_39 (rtx_insn *, rtx *);
rtx_insn *
gen_split_39 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_39 (riscv.md:2230)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2244 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
operands[5] = GEN_INT (32 - (INTVAL (operands [2])));
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (32)])));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (DImode,
	copy_rtx (operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
extern rtx_insn *gen_split_40 (rtx_insn *, rtx *);
rtx_insn *
gen_split_40 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_40 (riscv.md:2257)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2273 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	HOST_WIDE_INT mask = INTVAL (operands[3]);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (trailing);
	operands[7] = GEN_INT (mask >> trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_LSHIFTRT (SImode,
	gen_rtx_SUBREG (SImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_AND (SImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
extern rtx_insn *gen_split_41 (rtx_insn *, rtx *);
rtx_insn *
gen_split_41 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_41 (riscv.md:2257)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2273 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	HOST_WIDE_INT mask = INTVAL (operands[3]);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (trailing);
	operands[7] = GEN_INT (mask >> trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_LSHIFTRT (SImode,
	gen_rtx_SUBREG (SImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_AND (SImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
extern rtx_insn *gen_split_42 (rtx_insn *, rtx *);
rtx_insn *
gen_split_42 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_42 (riscv.md:2257)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2273 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	HOST_WIDE_INT mask = INTVAL (operands[3]);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (trailing);
	operands[7] = GEN_INT (mask >> trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_LSHIFTRT (SImode,
	gen_rtx_SUBREG (SImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_AND (SImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
extern rtx_insn *gen_split_43 (rtx_insn *, rtx *);
rtx_insn *
gen_split_43 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_43 (riscv.md:2257)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2273 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	HOST_WIDE_INT mask = INTVAL (operands[3]);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (trailing);
	operands[7] = GEN_INT (mask >> trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_LSHIFTRT (DImode,
	gen_rtx_SUBREG (DImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_AND (DImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
extern rtx_insn *gen_split_44 (rtx_insn *, rtx *);
rtx_insn *
gen_split_44 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_44 (riscv.md:2257)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2273 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	HOST_WIDE_INT mask = INTVAL (operands[3]);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (trailing);
	operands[7] = GEN_INT (mask >> trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_LSHIFTRT (DImode,
	gen_rtx_SUBREG (DImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_AND (DImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
extern rtx_insn *gen_split_45 (rtx_insn *, rtx *);
rtx_insn *
gen_split_45 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_45 (riscv.md:2257)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2273 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	HOST_WIDE_INT mask = INTVAL (operands[3]);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (trailing);
	operands[7] = GEN_INT (mask >> trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_LSHIFTRT (DImode,
	gen_rtx_SUBREG (DImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_AND (DImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
extern rtx_insn *gen_split_46 (rtx_insn *, rtx *);
rtx_insn *
gen_split_46 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_46 (riscv.md:2257)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2273 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	HOST_WIDE_INT mask = INTVAL (operands[3]);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (trailing);
	operands[7] = GEN_INT (mask >> trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_LSHIFTRT (DImode,
	gen_rtx_SUBREG (DImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_AND (DImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
extern rtx_insn *gen_split_47 (rtx_insn *, rtx *);
rtx_insn *
gen_split_47 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_47 (riscv.md:2281)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	unsigned HOST_WIDE_INT mask = INTVAL (operands[3]);
	int leading  = clz_hwi (mask);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (leading);
	operands[7] = GEN_INT (leading + trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (SImode,
	gen_rtx_SUBREG (SImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_LSHIFTRT (SImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
extern rtx_insn *gen_split_48 (rtx_insn *, rtx *);
rtx_insn *
gen_split_48 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_48 (riscv.md:2281)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	unsigned HOST_WIDE_INT mask = INTVAL (operands[3]);
	int leading  = clz_hwi (mask);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (leading);
	operands[7] = GEN_INT (leading + trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (SImode,
	gen_rtx_SUBREG (SImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_LSHIFTRT (SImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
extern rtx_insn *gen_split_49 (rtx_insn *, rtx *);
rtx_insn *
gen_split_49 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_49 (riscv.md:2281)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	unsigned HOST_WIDE_INT mask = INTVAL (operands[3]);
	int leading  = clz_hwi (mask);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (leading);
	operands[7] = GEN_INT (leading + trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (SImode,
	gen_rtx_SUBREG (SImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_LSHIFTRT (SImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
extern rtx_insn *gen_split_50 (rtx_insn *, rtx *);
rtx_insn *
gen_split_50 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_50 (riscv.md:2281)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	unsigned HOST_WIDE_INT mask = INTVAL (operands[3]);
	int leading  = clz_hwi (mask);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (leading);
	operands[7] = GEN_INT (leading + trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (SImode,
	gen_rtx_SUBREG (SImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_LSHIFTRT (SImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
extern rtx_insn *gen_split_51 (rtx_insn *, rtx *);
rtx_insn *
gen_split_51 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_51 (riscv.md:2281)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	unsigned HOST_WIDE_INT mask = INTVAL (operands[3]);
	int leading  = clz_hwi (mask);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (leading);
	operands[7] = GEN_INT (leading + trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (DImode,
	gen_rtx_SUBREG (DImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_LSHIFTRT (DImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
extern rtx_insn *gen_split_52 (rtx_insn *, rtx *);
rtx_insn *
gen_split_52 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_52 (riscv.md:2281)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	unsigned HOST_WIDE_INT mask = INTVAL (operands[3]);
	int leading  = clz_hwi (mask);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (leading);
	operands[7] = GEN_INT (leading + trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (DImode,
	gen_rtx_SUBREG (DImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_LSHIFTRT (DImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
extern rtx_insn *gen_split_53 (rtx_insn *, rtx *);
rtx_insn *
gen_split_53 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_53 (riscv.md:2281)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	unsigned HOST_WIDE_INT mask = INTVAL (operands[3]);
	int leading  = clz_hwi (mask);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (leading);
	operands[7] = GEN_INT (leading + trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (DImode,
	gen_rtx_SUBREG (DImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_LSHIFTRT (DImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
extern rtx_insn *gen_split_54 (rtx_insn *, rtx *);
rtx_insn *
gen_split_54 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_54 (riscv.md:2281)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2299 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
	unsigned HOST_WIDE_INT mask = INTVAL (operands[3]);
	int leading  = clz_hwi (mask);
	int trailing = ctz_hwi (mask);

	operands[6] = GEN_INT (leading);
	operands[7] = GEN_INT (leading + trailing);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (DImode,
	gen_rtx_SUBREG (DImode,
	operand2,
	0),
	operand6)));
  emit_insn (gen_rtx_SET (copy_rtx (operand4),
	gen_rtx_LSHIFTRT (DImode,
	copy_rtx (operand4),
	operand7)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2323 */
rtx
gen_movsicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2329 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (riscv_expand_conditional_move (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2323 */
rtx
gen_movdicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2329 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (riscv_expand_conditional_move (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2356 */
extern rtx_insn *gen_split_55 (rtx_insn *, rtx *);
rtx_insn *
gen_split_55 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_55 (riscv.md:2356)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ZERO_EXTRACT (SImode,
	operand1,
	const1_rtx,
	operand2)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	gen_rtx_NE (VOIDmode,
	copy_rtx (operand4),
	const0_rtx),
	operand3,
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2356 */
extern rtx_insn *gen_split_56 (rtx_insn *, rtx *);
rtx_insn *
gen_split_56 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_56 (riscv.md:2356)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	const1_rtx,
	operand2)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	gen_rtx_NE (VOIDmode,
	copy_rtx (operand4),
	const0_rtx),
	operand3,
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2369 */
extern rtx_insn *gen_split_57 (rtx_insn *, rtx *);
rtx_insn *
gen_split_57 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_57 (riscv.md:2369)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2381 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[2] = GEN_INT (1 << UINTVAL(operands[2]));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_AND (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	gen_rtx_NE (VOIDmode,
	copy_rtx (operand4),
	const0_rtx),
	operand3,
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2369 */
extern rtx_insn *gen_split_58 (rtx_insn *, rtx *);
rtx_insn *
gen_split_58 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_58 (riscv.md:2369)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2381 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[2] = GEN_INT (1 << UINTVAL(operands[2]));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_AND (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	gen_rtx_NE (VOIDmode,
	copy_rtx (operand4),
	const0_rtx),
	operand3,
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2386 */
rtx
gen_condjump (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	operand0,
	gen_rtx_LABEL_REF (VOIDmode,
	operand1),
	pc_rtx));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2392 */
rtx
gen_cbranchqi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2400 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]),
				   operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2392 */
rtx
gen_cbranchsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2400 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]),
				   operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2392 */
rtx
gen_cbranchdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2400 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]),
				   operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2406 */
rtx
gen_cbranchsf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]),
				   operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2406 */
rtx
gen_cbranchdf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]),
				   operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2406 */
rtx
gen_cbranchhf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2414 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]),
				   operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2420 */
extern rtx_insn *gen_split_59 (rtx_insn *, rtx *);
rtx_insn *
gen_split_59 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_59 (riscv.md:2420)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  int shift = GET_MODE_BITSIZE (SImode) - 1 - INTVAL (operands[3]);
  operands[3] = GEN_INT (shift);

  if (GET_CODE (operands[0]) == EQ)
    operands[0] = gen_rtx_GE (SImode, operands[4], const0_rtx);
  else
    operands[0] = gen_rtx_LT (SImode, operands[4], const0_rtx);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (SImode,
	operand2,
	operand3)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), GET_MODE (operand0),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand1),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2420 */
extern rtx_insn *gen_split_60 (rtx_insn *, rtx *);
rtx_insn *
gen_split_60 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_60 (riscv.md:2420)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2441 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  int shift = GET_MODE_BITSIZE (DImode) - 1 - INTVAL (operands[3]);
  operands[3] = GEN_INT (shift);

  if (GET_CODE (operands[0]) == EQ)
    operands[0] = gen_rtx_GE (DImode, operands[4], const0_rtx);
  else
    operands[0] = gen_rtx_LT (DImode, operands[4], const0_rtx);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (DImode,
	operand2,
	operand3)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), GET_MODE (operand0),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand1),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2451 */
extern rtx_insn *gen_split_61 (rtx_insn *, rtx *);
rtx_insn *
gen_split_61 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_61 (riscv.md:2451)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2472 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[3] = GEN_INT (GET_MODE_BITSIZE (SImode) - INTVAL (operands[3]));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (SImode,
	operand2,
	operand3)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), GET_MODE (operand0),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand1),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2451 */
extern rtx_insn *gen_split_62 (rtx_insn *, rtx *);
rtx_insn *
gen_split_62 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_62 (riscv.md:2451)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2472 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[3] = GEN_INT (GET_MODE_BITSIZE (DImode) - INTVAL (operands[3]));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_ASHIFT (DImode,
	operand2,
	operand3)));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), GET_MODE (operand0),
		copy_rtx (operand4),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand1),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2485 */
rtx
gen_cstoresi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_int_scc (operands[0], GET_CODE (operands[1]), operands[2],
			operands[3]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2485 */
rtx
gen_cstoredi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2491 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_int_scc (operands[0], GET_CODE (operands[1]), operands[2],
			operands[3]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2497 */
rtx
gen_cstoresf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_float_scc (operands[0], GET_CODE (operands[1]), operands[2],
			  operands[3]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2497 */
rtx
gen_cstoredf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_float_scc (operands[0], GET_CODE (operands[1]), operands[2],
			  operands[3]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2497 */
rtx
gen_cstorehf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2503 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_float_scc (operands[0], GET_CODE (operands[1]), operands[2],
			  operands[3]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
rtx
gen_flt_quietsfsi4 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx tmp = gen_reg_rtx (SImode);
  rtx cmp = gen_rtx_LT (SImode, op1, op2);
  rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx),
					 UNSPECV_FRFLAGS);
  rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp),
					 UNSPECV_FSFLAGS);

  emit_insn (gen_rtx_SET (tmp, frflags));
  emit_insn (gen_rtx_SET (op0, cmp));
  emit_insn (fsflags);
  if (HONOR_SNANS (SFmode))
    emit_insn (gen_rtx_UNSPEC_VOLATILE (SFmode,
					gen_rtvec (2, op1, op2),
					UNSPECV_FSNVSNAN));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
rtx
gen_fle_quietsfsi4 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx tmp = gen_reg_rtx (SImode);
  rtx cmp = gen_rtx_LE (SImode, op1, op2);
  rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx),
					 UNSPECV_FRFLAGS);
  rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp),
					 UNSPECV_FSFLAGS);

  emit_insn (gen_rtx_SET (tmp, frflags));
  emit_insn (gen_rtx_SET (op0, cmp));
  emit_insn (fsflags);
  if (HONOR_SNANS (SFmode))
    emit_insn (gen_rtx_UNSPEC_VOLATILE (SFmode,
					gen_rtvec (2, op1, op2),
					UNSPECV_FSNVSNAN));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
rtx
gen_flt_quietsfdi4 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx tmp = gen_reg_rtx (SImode);
  rtx cmp = gen_rtx_LT (DImode, op1, op2);
  rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx),
					 UNSPECV_FRFLAGS);
  rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp),
					 UNSPECV_FSFLAGS);

  emit_insn (gen_rtx_SET (tmp, frflags));
  emit_insn (gen_rtx_SET (op0, cmp));
  emit_insn (fsflags);
  if (HONOR_SNANS (SFmode))
    emit_insn (gen_rtx_UNSPEC_VOLATILE (SFmode,
					gen_rtvec (2, op1, op2),
					UNSPECV_FSNVSNAN));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
rtx
gen_fle_quietsfdi4 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx tmp = gen_reg_rtx (SImode);
  rtx cmp = gen_rtx_LE (DImode, op1, op2);
  rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx),
					 UNSPECV_FRFLAGS);
  rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp),
					 UNSPECV_FSFLAGS);

  emit_insn (gen_rtx_SET (tmp, frflags));
  emit_insn (gen_rtx_SET (op0, cmp));
  emit_insn (fsflags);
  if (HONOR_SNANS (SFmode))
    emit_insn (gen_rtx_UNSPEC_VOLATILE (SFmode,
					gen_rtvec (2, op1, op2),
					UNSPECV_FSNVSNAN));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
rtx
gen_flt_quietdfsi4 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx tmp = gen_reg_rtx (SImode);
  rtx cmp = gen_rtx_LT (SImode, op1, op2);
  rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx),
					 UNSPECV_FRFLAGS);
  rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp),
					 UNSPECV_FSFLAGS);

  emit_insn (gen_rtx_SET (tmp, frflags));
  emit_insn (gen_rtx_SET (op0, cmp));
  emit_insn (fsflags);
  if (HONOR_SNANS (DFmode))
    emit_insn (gen_rtx_UNSPEC_VOLATILE (DFmode,
					gen_rtvec (2, op1, op2),
					UNSPECV_FSNVSNAN));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
rtx
gen_fle_quietdfsi4 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx tmp = gen_reg_rtx (SImode);
  rtx cmp = gen_rtx_LE (SImode, op1, op2);
  rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx),
					 UNSPECV_FRFLAGS);
  rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp),
					 UNSPECV_FSFLAGS);

  emit_insn (gen_rtx_SET (tmp, frflags));
  emit_insn (gen_rtx_SET (op0, cmp));
  emit_insn (fsflags);
  if (HONOR_SNANS (DFmode))
    emit_insn (gen_rtx_UNSPEC_VOLATILE (DFmode,
					gen_rtvec (2, op1, op2),
					UNSPECV_FSNVSNAN));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
rtx
gen_flt_quietdfdi4 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx tmp = gen_reg_rtx (SImode);
  rtx cmp = gen_rtx_LT (DImode, op1, op2);
  rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx),
					 UNSPECV_FRFLAGS);
  rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp),
					 UNSPECV_FSFLAGS);

  emit_insn (gen_rtx_SET (tmp, frflags));
  emit_insn (gen_rtx_SET (op0, cmp));
  emit_insn (fsflags);
  if (HONOR_SNANS (DFmode))
    emit_insn (gen_rtx_UNSPEC_VOLATILE (DFmode,
					gen_rtvec (2, op1, op2),
					UNSPECV_FSNVSNAN));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
rtx
gen_fle_quietdfdi4 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx tmp = gen_reg_rtx (SImode);
  rtx cmp = gen_rtx_LE (DImode, op1, op2);
  rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx),
					 UNSPECV_FRFLAGS);
  rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp),
					 UNSPECV_FSFLAGS);

  emit_insn (gen_rtx_SET (tmp, frflags));
  emit_insn (gen_rtx_SET (op0, cmp));
  emit_insn (fsflags);
  if (HONOR_SNANS (DFmode))
    emit_insn (gen_rtx_UNSPEC_VOLATILE (DFmode,
					gen_rtvec (2, op1, op2),
					UNSPECV_FSNVSNAN));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
rtx
gen_flt_quiethfsi4 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx tmp = gen_reg_rtx (SImode);
  rtx cmp = gen_rtx_LT (SImode, op1, op2);
  rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx),
					 UNSPECV_FRFLAGS);
  rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp),
					 UNSPECV_FSFLAGS);

  emit_insn (gen_rtx_SET (tmp, frflags));
  emit_insn (gen_rtx_SET (op0, cmp));
  emit_insn (fsflags);
  if (HONOR_SNANS (HFmode))
    emit_insn (gen_rtx_UNSPEC_VOLATILE (HFmode,
					gen_rtvec (2, op1, op2),
					UNSPECV_FSNVSNAN));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
rtx
gen_fle_quiethfsi4 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx tmp = gen_reg_rtx (SImode);
  rtx cmp = gen_rtx_LE (SImode, op1, op2);
  rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx),
					 UNSPECV_FRFLAGS);
  rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp),
					 UNSPECV_FSFLAGS);

  emit_insn (gen_rtx_SET (tmp, frflags));
  emit_insn (gen_rtx_SET (op0, cmp));
  emit_insn (fsflags);
  if (HONOR_SNANS (HFmode))
    emit_insn (gen_rtx_UNSPEC_VOLATILE (HFmode,
					gen_rtvec (2, op1, op2),
					UNSPECV_FSNVSNAN));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
rtx
gen_flt_quiethfdi4 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx tmp = gen_reg_rtx (SImode);
  rtx cmp = gen_rtx_LT (DImode, op1, op2);
  rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx),
					 UNSPECV_FRFLAGS);
  rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp),
					 UNSPECV_FSFLAGS);

  emit_insn (gen_rtx_SET (tmp, frflags));
  emit_insn (gen_rtx_SET (op0, cmp));
  emit_insn (fsflags);
  if (HONOR_SNANS (HFmode))
    emit_insn (gen_rtx_UNSPEC_VOLATILE (HFmode,
					gen_rtvec (2, op1, op2),
					UNSPECV_FSNVSNAN));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
rtx
gen_fle_quiethfdi4 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2525 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx tmp = gen_reg_rtx (SImode);
  rtx cmp = gen_rtx_LE (DImode, op1, op2);
  rtx frflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, const0_rtx),
					 UNSPECV_FRFLAGS);
  rtx fsflags = gen_rtx_UNSPEC_VOLATILE (SImode, gen_rtvec (1, tmp),
					 UNSPECV_FSFLAGS);

  emit_insn (gen_rtx_SET (tmp, frflags));
  emit_insn (gen_rtx_SET (op0, cmp));
  emit_insn (fsflags);
  if (HONOR_SNANS (HFmode))
    emit_insn (gen_rtx_UNSPEC_VOLATILE (HFmode,
					gen_rtvec (2, op1, op2),
					UNSPECV_FSNVSNAN));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2620 */
rtx
gen_indirect_jump (rtx operand0)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[1];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2623 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[0] = force_reg (Pmode, operands[0]);
  if (Pmode == SImode)
    emit_jump_insn (gen_indirect_jumpsi (operands[0]));
  else
    emit_jump_insn (gen_indirect_jumpdi (operands[0]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	operand0));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2639 */
rtx
gen_tablejump (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2643 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (CASE_VECTOR_PC_RELATIVE)
      operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
					 gen_rtx_LABEL_REF (Pmode, operands[1]),
					 NULL_RTX, 0, OPTAB_DIRECT);

  if (CASE_VECTOR_PC_RELATIVE && Pmode == DImode)
    emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
  else
    emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	operand0));
  emit_insn (gen_rtx_USE (VOIDmode,
	gen_rtx_LABEL_REF (VOIDmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2672 */
rtx
gen_prologue (void)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2675 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_prologue ();
  DONE;
}
#undef DONE
#undef FAIL
  }
  emit_insn (const1_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2691 */
rtx
gen_epilogue (void)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2694 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_epilogue (NORMAL_RETURN);
  DONE;
}
#undef DONE
#undef FAIL
  }
  emit_insn (const_int_rtx[MAX_SAVED_CONST_INT + (2)]);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2699 */
rtx
gen_sibcall_epilogue (void)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2702 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_expand_epilogue (SIBCALL_RETURN);
  DONE;
}
#undef DONE
#undef FAIL
  }
  emit_insn (const_int_rtx[MAX_SAVED_CONST_INT + (2)]);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2710 */
rtx
gen_return (void)
{
  return simple_return_rtx;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2735 */
rtx
gen_eh_return (rtx operand0)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[1];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2738 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (GET_MODE (operands[0]) != word_mode)
    operands[0] = convert_to_mode (word_mode, operands[0], 0);
  if (TARGET_64BIT)
    emit_insn (gen_eh_set_lr_di (operands[0]));
  else
    emit_insn (gen_eh_set_lr_si (operands[0]));

  emit_jump_insn (gen_eh_return_internal ());
  emit_barrier ();
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
  }
  emit_insn (gen_rtx_USE (VOIDmode,
	operand0));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2766 */
extern rtx_insn *gen_split_63 (rtx_insn *, rtx *);
rtx_insn *
gen_split_63 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_63 (riscv.md:2766)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2771 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  riscv_set_return_address (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2776 */
extern rtx_insn *gen_split_64 (rtx_insn *, rtx *);
rtx_insn *
gen_split_64 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_64 (riscv.md:2776)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2782 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
riscv_expand_epilogue (EXCEPTION_RETURN); DONE;
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2791 */
rtx
gen_sibcall (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2797 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx target = riscv_legitimize_call_address (XEXP (operands[0], 0));
  emit_call_insn (gen_sibcall_internal (target, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_CALL (VOIDmode,
	operand0,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2),
		gen_rtx_USE (VOIDmode,
	operand3))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2813 */
rtx
gen_sibcall_value (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2819 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx target = riscv_legitimize_call_address (XEXP (operands[1], 0));
  emit_call_insn (gen_sibcall_value_internal (operands[0], target, operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	operand1,
	operand2)),
		gen_rtx_USE (VOIDmode,
	operand3))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2836 */
rtx
gen_call (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2842 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx target = riscv_legitimize_call_address (XEXP (operands[0], 0));
  emit_call_insn (gen_call_internal (target, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_CALL (VOIDmode,
	operand0,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2),
		gen_rtx_USE (VOIDmode,
	operand3))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2859 */
rtx
gen_call_value (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2865 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx target = riscv_legitimize_call_address (XEXP (operands[1], 0));
  emit_call_insn (gen_call_value_internal (operands[0], target, operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	operand1,
	operand2)),
		gen_rtx_USE (VOIDmode,
	operand3))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2885 */
rtx
gen_untyped_call (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  int i;

  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));

  for (i = 0; i < XVECLEN (operands[2], 0); i++)
    {
      rtx set = XVECEXP (operands[2], 0, i);
      riscv_emit_move (SET_DEST (set), SET_SRC (set));
    }

  emit_insn (gen_blockage ());
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_CALL (VOIDmode,
	operand0,
	const0_rtx),
		operand1,
		operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2994 */
rtx
gen_restore_stack_nonlocal (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2998 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  emit_move_insn (operands[0], operands[1]);
  /* Prevent the following hard fp restore from being moved before the move
     insn above which uses a copy of the soft fp reg.  */
  emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3007 */
rtx
gen_get_thread_pointersi (rtx operand0)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[1];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3011 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_REG (SImode,
	4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3007 */
rtx
gen_get_thread_pointerdi (rtx operand0)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[1];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3011 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_REG (DImode,
	4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3015 */
rtx
gen_stack_protect_set (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3019 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  machine_mode mode = GET_MODE (operands[0]);
  if (riscv_stack_protector_guard == SSP_TLS)
  {
    rtx reg = gen_rtx_REG (Pmode, riscv_stack_protector_guard_reg);
    rtx offset = GEN_INT (riscv_stack_protector_guard_offset);
    rtx addr = gen_rtx_PLUS (Pmode, reg, offset);
    operands[1] = gen_rtx_MEM (Pmode, addr);
  }

  emit_insn ((mode == DImode
	      ? gen_stack_protect_set_di
	      : gen_stack_protect_set_si) (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3046 */
rtx
gen_stack_protect_test (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3051 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  rtx result;
  machine_mode mode = GET_MODE (operands[0]);

  result = gen_reg_rtx(mode);
  if (riscv_stack_protector_guard == SSP_TLS)
  {
      rtx reg = gen_rtx_REG (Pmode, riscv_stack_protector_guard_reg);
      rtx offset = GEN_INT (riscv_stack_protector_guard_offset);
      rtx addr = gen_rtx_PLUS (Pmode, reg, offset);
      operands[1] = gen_rtx_MEM (Pmode, addr);
  }
  emit_insn ((mode == DImode
		  ? gen_stack_protect_test_di
		  : gen_stack_protect_test_si) (result,
					        operands[0],
					        operands[1]));

  rtx cond = gen_rtx_EQ (VOIDmode, result, const0_rtx);
  emit_jump_insn (gen_cbranch4 (mode, cond, result, const0_rtx, operands[2]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3135 */
rtx
gen_extvsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTRACT (SImode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3135 */
rtx
gen_extvdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTRACT (DImode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3143 */
rtx
gen_extzvsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3149 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_XTHEADBB
      && (INTVAL (operands[2]) < 8) && (INTVAL (operands[3]) == 0))
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (SImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3143 */
rtx
gen_extzvdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3149 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (TARGET_XTHEADBB
      && (INTVAL (operands[2]) < 8) && (INTVAL (operands[3]) == 0))
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3155 */
rtx
gen_maddhisi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (SImode,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3164 */
rtx
gen_msubhisi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	operand3,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (SImode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:48 */
extern rtx_insn *gen_split_65 (rtx_insn *, rtx *);
rtx_insn *
gen_split_65 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_65 (bitmanip.md:48)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand5,
	gen_rtx_PLUS (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2),
	operand3)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_DIV (SImode,
	gen_rtx_SUBREG (SImode,
	copy_rtx (operand5),
	0),
	gen_rtx_SUBREG (SImode,
	operand4,
	0)))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:67 */
extern rtx_insn *gen_split_66 (rtx_insn *, rtx *);
rtx_insn *
gen_split_66 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_66 (bitmanip.md:67)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2),
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_SUBREG (SImode,
	copy_rtx (operand0),
	0))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:76 */
extern rtx_insn *gen_split_67 (rtx_insn *, rtx *);
rtx_insn *
gen_split_67 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_67 (bitmanip.md:76)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2),
	operand4)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_SUBREG (SImode,
	copy_rtx (operand0),
	0))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:91 */
extern rtx_insn *gen_split_68 (rtx_insn *, rtx *);
rtx_insn *
gen_split_68 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_68 (bitmanip.md:91)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 106 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
	operands[3] = GEN_INT (INTVAL (operands[3]) >> INTVAL (operands[2]));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand5,
	gen_rtx_AND (DImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_ASHIFT (DImode,
	copy_rtx (operand5),
	operand2),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:130 */
extern rtx_insn *gen_split_69 (rtx_insn *, rtx *);
rtx_insn *
gen_split_69 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_69 (bitmanip.md:130)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 143 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
	unsigned HOST_WIDE_INT mask = UINTVAL (operands[3]);
	/* scale: shift within the sh[123]add.uw */
	unsigned HOST_WIDE_INT scale = 32 - clz_hwi (mask);
	/* bias:  pre-scale amount (i.e. the prior shift amount) */
	int bias = ctz_hwi (mask) - scale;

	/* If the bias + scale don't add up to operand[2], reject. */
	if ((scale + bias) != UINTVAL (operands[2]))
	   FAIL;

	/* If the shift-amount is out-of-range for sh[123]add.uw, reject. */
	if ((scale < 1) || (scale > 3))
	   FAIL;

	/* If there's no bias, the '*shNadduw' pattern should have matched. */
	if (bias == 0)
	   FAIL;

	operands[6] = GEN_INT (bias);
	operands[7] = GEN_INT (scale);
	operands[8] = GEN_INT (0xffffffffULL << scale);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  emit_insn (gen_rtx_SET (operand5,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand6)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_AND (DImode,
	gen_rtx_ASHIFT (DImode,
	copy_rtx (operand5),
	operand7),
	operand8),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:190 */
rtx
gen_clzdi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:195 */
rtx
gen_clzsi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:200 */
rtx
gen_ctzsi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CTZ (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:200 */
rtx
gen_ctzdi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CTZ (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:205 */
rtx
gen_popcountsi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:205 */
rtx
gen_popcountdi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:222 */
extern rtx_insn *gen_split_70 (rtx_insn *, rtx *);
rtx_insn *
gen_split_70 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_70 (bitmanip.md:222)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_ASHIFTRT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (63)])));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	gen_rtx_NOT (DImode,
	copy_rtx (operand3)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:298 */
rtx
gen_rotrsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 303 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
  if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode))
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ROTATERT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:298 */
rtx
gen_rotrdi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 303 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
  if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode))
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ROTATERT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:364 */
rtx
gen_bswapdi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:369 */
rtx
gen_bswapsi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:385 */
rtx
gen_bswaphi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 389 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
  rtx tmp = gen_reg_rtx (word_mode);
  rtx newop1 = gen_lowpart (word_mode, operands[1]);
  if (TARGET_64BIT)
    emit_insn (gen_bswapdi2 (tmp, newop1));
  else
    emit_insn (gen_bswapsi2 (tmp, newop1));
  rtx tmp1 = gen_reg_rtx (word_mode);
  if (TARGET_64BIT)
    emit_insn (gen_lshrdi3 (tmp1, tmp, GEN_INT (64 - 16)));
  else
    emit_insn (gen_lshrsi3 (tmp1, tmp, GEN_INT (32 - 16)));
  emit_move_insn (operands[0], gen_lowpart (HImode, tmp1));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_BSWAP (HImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:415 */
extern rtx_insn *gen_split_71 (rtx_insn *, rtx *);
rtx_insn *
gen_split_71 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_71 (bitmanip.md:415)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1)));
  emit_insn (gen_rtx_SET (operand4,
	operand2));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SMIN (DImode,
	copy_rtx (operand3),
	copy_rtx (operand4))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:415 */
extern rtx_insn *gen_split_72 (rtx_insn *, rtx *);
rtx_insn *
gen_split_72 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_72 (bitmanip.md:415)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1)));
  emit_insn (gen_rtx_SET (operand4,
	operand2));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UMIN (DImode,
	copy_rtx (operand3),
	copy_rtx (operand4))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:415 */
extern rtx_insn *gen_split_73 (rtx_insn *, rtx *);
rtx_insn *
gen_split_73 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_73 (bitmanip.md:415)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1)));
  emit_insn (gen_rtx_SET (operand4,
	operand2));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SMAX (DImode,
	copy_rtx (operand3),
	copy_rtx (operand4))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:415 */
extern rtx_insn *gen_split_74 (rtx_insn *, rtx *);
rtx_insn *
gen_split_74 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_74 (bitmanip.md:415)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1)));
  emit_insn (gen_rtx_SET (operand4,
	operand2));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UMAX (DImode,
	copy_rtx (operand3),
	copy_rtx (operand4))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:509 */
extern rtx_insn *gen_split_75 (rtx_insn *, rtx *);
rtx_insn *
gen_split_75 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_75 (bitmanip.md:509)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 518 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
	unsigned HOST_WIDE_INT bits = ~UINTVAL (operands[2]);
	unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);

	operands[3] = GEN_INT (~bits | topbit);
	operands[4] = GEN_INT (~topbit);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_AND (SImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:509 */
extern rtx_insn *gen_split_76 (rtx_insn *, rtx *);
rtx_insn *
gen_split_76 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_76 (bitmanip.md:509)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 518 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
	unsigned HOST_WIDE_INT bits = ~UINTVAL (operands[2]);
	unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);

	operands[3] = GEN_INT (~bits | topbit);
	operands[4] = GEN_INT (~topbit);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_AND (DImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:528 */
extern rtx_insn *gen_split_77 (rtx_insn *, rtx *);
rtx_insn *
gen_split_77 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_77 (bitmanip.md:528)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 538 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
	unsigned HOST_WIDE_INT bits = ~UINTVAL (operands[2]);
	unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);

	operands[3] = GEN_INT (~bits | topbit);
	operands[4] = GEN_INT (~topbit);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_AND (DImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:598 */
extern rtx_insn *gen_split_78 (rtx_insn *, rtx *);
rtx_insn *
gen_split_78 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_78 (bitmanip.md:598)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (SImode,
	operand1,
	const1_rtx,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_XOR (SImode,
	copy_rtx (operand0),
	const1_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:598 */
extern rtx_insn *gen_split_79 (rtx_insn *, rtx *);
rtx_insn *
gen_split_79 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_79 (bitmanip.md:598)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	const1_rtx,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_XOR (DImode,
	copy_rtx (operand0),
	const1_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:612 */
extern rtx_insn *gen_split_80 (rtx_insn *, rtx *);
rtx_insn *
gen_split_80 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_80 (bitmanip.md:612)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (SImode,
	operand1,
	const1_rtx,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_PLUS (SImode,
	copy_rtx (operand0),
	constm1_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:612 */
extern rtx_insn *gen_split_81 (rtx_insn *, rtx *);
rtx_insn *
gen_split_81 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_81 (bitmanip.md:612)\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	const1_rtx,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_PLUS (DImode,
	copy_rtx (operand0),
	constm1_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:624 */
extern rtx_insn *gen_split_82 (rtx_insn *, rtx *);
rtx_insn *
gen_split_82 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_82 (bitmanip.md:624)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 633 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
	unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]);
	unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);

	operands[3] = GEN_INT (bits &~ topbit);
	operands[4] = GEN_INT (topbit);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_IOR (SImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:624 */
extern rtx_insn *gen_split_83 (rtx_insn *, rtx *);
rtx_insn *
gen_split_83 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_83 (bitmanip.md:624)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 633 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
	unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]);
	unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);

	operands[3] = GEN_INT (bits &~ topbit);
	operands[4] = GEN_INT (topbit);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_XOR (SImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:624 */
extern rtx_insn *gen_split_84 (rtx_insn *, rtx *);
rtx_insn *
gen_split_84 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_84 (bitmanip.md:624)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 633 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
	unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]);
	unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);

	operands[3] = GEN_INT (bits &~ topbit);
	operands[4] = GEN_INT (topbit);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_IOR (DImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:624 */
extern rtx_insn *gen_split_85 (rtx_insn *, rtx *);
rtx_insn *
gen_split_85 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_85 (bitmanip.md:624)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 633 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
	unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]);
	unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);

	operands[3] = GEN_INT (bits &~ topbit);
	operands[4] = GEN_INT (topbit);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_XOR (DImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:642 */
extern rtx_insn *gen_split_86 (rtx_insn *, rtx *);
rtx_insn *
gen_split_86 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_86 (bitmanip.md:642)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
	unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]);
	unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (~bits);

	operands[3] = GEN_INT (bits | topbit);
	operands[4] = GEN_INT (~topbit);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_AND (SImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:642 */
extern rtx_insn *gen_split_87 (rtx_insn *, rtx *);
rtx_insn *
gen_split_87 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_87 (bitmanip.md:642)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 651 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
	unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]);
	unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (~bits);

	operands[3] = GEN_INT (bits | topbit);
	operands[4] = GEN_INT (~topbit);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_AND (DImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:660 */
extern rtx_insn *gen_split_88 (rtx_insn *, rtx *);
rtx_insn *
gen_split_88 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_88 (bitmanip.md:660)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
   unsigned HOST_WIDE_INT twobits_mask = UINTVAL (operands[3]);
   unsigned HOST_WIDE_INT singlebit_mask = UINTVAL (operands[4]);

   /* We should never see an unsatisfiable condition.  */
   gcc_assert (twobits_mask & singlebit_mask);

   int setbit = ctz_hwi (singlebit_mask);
   int clearbit = ctz_hwi (twobits_mask & ~singlebit_mask);

   operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == NE ? EQ : NE,
				 SImode, operands[6], GEN_INT(0));

   operands[8] = GEN_INT (setbit);
   operands[9] = GEN_INT (clearbit);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand5,
	gen_rtx_ZERO_EXTRACT (SImode,
	operand2,
	const1_rtx,
	operand8)));
  emit_insn (gen_rtx_SET (operand6,
	gen_rtx_ZERO_EXTRACT (SImode,
	copy_rtx (operand2),
	const1_rtx,
	operand9)));
  emit_insn (gen_rtx_SET (copy_rtx (operand6),
	gen_rtx_AND (SImode,
	gen_rtx_NOT (SImode,
	copy_rtx (operand6)),
	copy_rtx (operand5))));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand6),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:660 */
extern rtx_insn *gen_split_89 (rtx_insn *, rtx *);
rtx_insn *
gen_split_89 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_89 (bitmanip.md:660)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 684 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md"
{
   unsigned HOST_WIDE_INT twobits_mask = UINTVAL (operands[3]);
   unsigned HOST_WIDE_INT singlebit_mask = UINTVAL (operands[4]);

   /* We should never see an unsatisfiable condition.  */
   gcc_assert (twobits_mask & singlebit_mask);

   int setbit = ctz_hwi (singlebit_mask);
   int clearbit = ctz_hwi (twobits_mask & ~singlebit_mask);

   operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == NE ? EQ : NE,
				 DImode, operands[6], GEN_INT(0));

   operands[8] = GEN_INT (setbit);
   operands[9] = GEN_INT (clearbit);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand5,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand2,
	const1_rtx,
	operand8)));
  emit_insn (gen_rtx_SET (operand6,
	gen_rtx_ZERO_EXTRACT (DImode,
	copy_rtx (operand2),
	const1_rtx,
	operand9)));
  emit_insn (gen_rtx_SET (copy_rtx (operand6),
	gen_rtx_AND (DImode,
	gen_rtx_NOT (DImode,
	copy_rtx (operand6)),
	copy_rtx (operand5))));
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), GET_MODE (operand1),
		copy_rtx (operand6),
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand0),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:36 */
rtx
gen_mem_thread_fence (rtx operand0)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[1];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 39 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  if (INTVAL (operands[0]) != MEMMODEL_RELAXED)
    {
      rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
      MEM_VOLATILE_P (mem) = 1;
      emit_insn (gen_mem_thread_fence_1 (mem, operands[0]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
  }
  emit (operand0, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:174 */
rtx
gen_atomic_fetch_nandqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 180 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode/HImode atomics, so form a mask, then use
     subword_atomic_fetch_strong_nand to implement a LR/SC version of the
     operation.  */

  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
     is disabled.  */

  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx value = operands[2];
  rtx model = operands[3];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx shifted_value = gen_reg_rtx (SImode);
  riscv_lshift_subword (QImode, value, shift, &shifted_value);

  emit_insn (gen_subword_atomic_fetch_strong_nand (old, aligned_mem,
						   shifted_value, model,
						   mask, not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (QImode, old));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_NOT (QImode,
	gen_rtx_AND (QImode,
	operand1,
	operand2)));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:174 */
rtx
gen_atomic_fetch_nandhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 180 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode/HImode atomics, so form a mask, then use
     subword_atomic_fetch_strong_nand to implement a LR/SC version of the
     operation.  */

  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
     is disabled.  */

  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx value = operands[2];
  rtx model = operands[3];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx shifted_value = gen_reg_rtx (SImode);
  riscv_lshift_subword (HImode, value, shift, &shifted_value);

  emit_insn (gen_subword_atomic_fetch_strong_nand (old, aligned_mem,
						   shifted_value, model,
						   mask, not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (HImode, old));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_NOT (HImode,
	gen_rtx_AND (HImode,
	operand1,
	operand2)));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
rtx
gen_atomic_fetch_addqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode/HImode atomics, so form a mask, then use
     subword_atomic_fetch_strong_qi to implement a LR/SC version of the
     operation.  */

  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
     is disabled.  */

  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx value = operands[2];
  rtx model = operands[3];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx shifted_value = gen_reg_rtx (SImode);
  riscv_lshift_subword (QImode, value, shift, &shifted_value);

  emit_insn (gen_subword_atomic_fetch_strong_add (old, aligned_mem,
							     shifted_value,
							     model, mask,
							     not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (QImode, old));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
rtx
gen_atomic_fetch_orqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode/HImode atomics, so form a mask, then use
     subword_atomic_fetch_strong_qi to implement a LR/SC version of the
     operation.  */

  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
     is disabled.  */

  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx value = operands[2];
  rtx model = operands[3];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx shifted_value = gen_reg_rtx (SImode);
  riscv_lshift_subword (QImode, value, shift, &shifted_value);

  emit_insn (gen_subword_atomic_fetch_strong_or (old, aligned_mem,
							     shifted_value,
							     model, mask,
							     not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (QImode, old));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
rtx
gen_atomic_fetch_xorqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode/HImode atomics, so form a mask, then use
     subword_atomic_fetch_strong_qi to implement a LR/SC version of the
     operation.  */

  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
     is disabled.  */

  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx value = operands[2];
  rtx model = operands[3];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx shifted_value = gen_reg_rtx (SImode);
  riscv_lshift_subword (QImode, value, shift, &shifted_value);

  emit_insn (gen_subword_atomic_fetch_strong_xor (old, aligned_mem,
							     shifted_value,
							     model, mask,
							     not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (QImode, old));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
rtx
gen_atomic_fetch_andqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode/HImode atomics, so form a mask, then use
     subword_atomic_fetch_strong_qi to implement a LR/SC version of the
     operation.  */

  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
     is disabled.  */

  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx value = operands[2];
  rtx model = operands[3];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx shifted_value = gen_reg_rtx (SImode);
  riscv_lshift_subword (QImode, value, shift, &shifted_value);

  emit_insn (gen_subword_atomic_fetch_strong_and (old, aligned_mem,
							     shifted_value,
							     model, mask,
							     not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (QImode, old));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
rtx
gen_atomic_fetch_addhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode/HImode atomics, so form a mask, then use
     subword_atomic_fetch_strong_hi to implement a LR/SC version of the
     operation.  */

  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
     is disabled.  */

  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx value = operands[2];
  rtx model = operands[3];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx shifted_value = gen_reg_rtx (SImode);
  riscv_lshift_subword (HImode, value, shift, &shifted_value);

  emit_insn (gen_subword_atomic_fetch_strong_add (old, aligned_mem,
							     shifted_value,
							     model, mask,
							     not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (HImode, old));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
rtx
gen_atomic_fetch_orhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode/HImode atomics, so form a mask, then use
     subword_atomic_fetch_strong_hi to implement a LR/SC version of the
     operation.  */

  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
     is disabled.  */

  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx value = operands[2];
  rtx model = operands[3];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx shifted_value = gen_reg_rtx (SImode);
  riscv_lshift_subword (HImode, value, shift, &shifted_value);

  emit_insn (gen_subword_atomic_fetch_strong_or (old, aligned_mem,
							     shifted_value,
							     model, mask,
							     not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (HImode, old));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
rtx
gen_atomic_fetch_xorhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode/HImode atomics, so form a mask, then use
     subword_atomic_fetch_strong_hi to implement a LR/SC version of the
     operation.  */

  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
     is disabled.  */

  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx value = operands[2];
  rtx model = operands[3];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx shifted_value = gen_reg_rtx (SImode);
  riscv_lshift_subword (HImode, value, shift, &shifted_value);

  emit_insn (gen_subword_atomic_fetch_strong_xor (old, aligned_mem,
							     shifted_value,
							     model, mask,
							     not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (HImode, old));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
rtx
gen_atomic_fetch_andhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 247 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode/HImode atomics, so form a mask, then use
     subword_atomic_fetch_strong_hi to implement a LR/SC version of the
     operation.  */

  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
     is disabled.  */

  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx value = operands[2];
  rtx model = operands[3];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx shifted_value = gen_reg_rtx (SImode);
  riscv_lshift_subword (HImode, value, shift, &shifted_value);

  emit_insn (gen_subword_atomic_fetch_strong_and (old, aligned_mem,
							     shifted_value,
							     model, mask,
							     not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (HImode, old));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:295 */
rtx
gen_atomic_exchangeqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 301 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx value = operands[2];
  rtx model = operands[3];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx shifted_value = gen_reg_rtx (SImode);
  riscv_lshift_subword (QImode, value, shift, &shifted_value);

  emit_insn (gen_subword_atomic_exchange_strong (old, aligned_mem,
						 shifted_value, model,
						 not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (QImode, old));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:295 */
rtx
gen_atomic_exchangehi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 301 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx value = operands[2];
  rtx model = operands[3];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx shifted_value = gen_reg_rtx (SImode);
  riscv_lshift_subword (HImode, value, shift, &shifted_value);

  emit_insn (gen_subword_atomic_exchange_strong (old, aligned_mem,
						 shifted_value, model,
						 not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (HImode, old));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:375 */
rtx
gen_atomic_compare_and_swapsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  if (word_mode != SImode && operands[3] != const0_rtx)
    {
      /* We don't have SI mode compare on RV64, so we need to make sure expected
	 value is sign-extended.  */
      rtx tmp0 = gen_reg_rtx (word_mode);
      emit_insn (gen_extend_insn (tmp0, operands[3], word_mode, SImode, 0));
      operands[3] = simplify_gen_subreg (SImode, tmp0, word_mode, 0);
    }

  emit_insn (gen_atomic_cas_value_strongsi (operands[1], operands[2],
						operands[3], operands[4],
						operands[6], operands[7]));

  rtx compare = operands[1];
  if (operands[3] != const0_rtx)
    {
      rtx difference = gen_rtx_MINUS (SImode, operands[1], operands[3]);
      compare = gen_reg_rtx (SImode);
      emit_insn (gen_rtx_SET (compare, difference));
    }

  if (word_mode != SImode)
    {
      rtx reg = gen_reg_rtx (word_mode);
      emit_insn (gen_rtx_SET (reg, gen_rtx_SIGN_EXTEND (word_mode, compare)));
      compare = reg;
    }

  emit_insn (gen_rtx_SET (operands[0], gen_rtx_EQ (SImode, compare, const0_rtx)));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit (operand6, true);
  emit (operand7, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:375 */
rtx
gen_atomic_compare_and_swapdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  if (word_mode != DImode && operands[3] != const0_rtx)
    {
      /* We don't have SI mode compare on RV64, so we need to make sure expected
	 value is sign-extended.  */
      rtx tmp0 = gen_reg_rtx (word_mode);
      emit_insn (gen_extend_insn (tmp0, operands[3], word_mode, DImode, 0));
      operands[3] = simplify_gen_subreg (DImode, tmp0, word_mode, 0);
    }

  emit_insn (gen_atomic_cas_value_strongdi (operands[1], operands[2],
						operands[3], operands[4],
						operands[6], operands[7]));

  rtx compare = operands[1];
  if (operands[3] != const0_rtx)
    {
      rtx difference = gen_rtx_MINUS (DImode, operands[1], operands[3]);
      compare = gen_reg_rtx (DImode);
      emit_insn (gen_rtx_SET (compare, difference));
    }

  if (word_mode != DImode)
    {
      rtx reg = gen_reg_rtx (word_mode);
      emit_insn (gen_rtx_SET (reg, gen_rtx_SIGN_EXTEND (word_mode, compare)));
      compare = reg;
    }

  emit_insn (gen_rtx_SET (operands[0], gen_rtx_EQ (SImode, compare, const0_rtx)));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit (operand6, true);
  emit (operand7, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:418 */
rtx
gen_atomic_compare_and_swapqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  emit_insn (gen_atomic_cas_value_strongqi (operands[1], operands[2],
						operands[3], operands[4],
						operands[6], operands[7]));

  rtx val = gen_reg_rtx (SImode);
  if (operands[1] != const0_rtx)
    emit_move_insn (val, gen_rtx_SIGN_EXTEND (SImode, operands[1]));
  else
    emit_move_insn (val, const0_rtx);

  rtx exp = gen_reg_rtx (SImode);
  if (operands[3] != const0_rtx)
    emit_move_insn (exp, gen_rtx_SIGN_EXTEND (SImode, operands[3]));
  else
    emit_move_insn (exp, const0_rtx);

  rtx compare = val;
  if (exp != const0_rtx)
    {
      rtx difference = gen_rtx_MINUS (SImode, val, exp);
      compare = gen_reg_rtx (SImode);
      emit_move_insn (compare, difference);
    }

  if (word_mode != SImode)
    {
      rtx reg = gen_reg_rtx (word_mode);
      emit_move_insn (reg, gen_rtx_SIGN_EXTEND (word_mode, compare));
      compare = reg;
    }

  emit_move_insn (operands[0], gen_rtx_EQ (SImode, compare, const0_rtx));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit (operand6, true);
  emit (operand7, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:418 */
rtx
gen_atomic_compare_and_swaphi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 428 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  emit_insn (gen_atomic_cas_value_stronghi (operands[1], operands[2],
						operands[3], operands[4],
						operands[6], operands[7]));

  rtx val = gen_reg_rtx (SImode);
  if (operands[1] != const0_rtx)
    emit_move_insn (val, gen_rtx_SIGN_EXTEND (SImode, operands[1]));
  else
    emit_move_insn (val, const0_rtx);

  rtx exp = gen_reg_rtx (SImode);
  if (operands[3] != const0_rtx)
    emit_move_insn (exp, gen_rtx_SIGN_EXTEND (SImode, operands[3]));
  else
    emit_move_insn (exp, const0_rtx);

  rtx compare = val;
  if (exp != const0_rtx)
    {
      rtx difference = gen_rtx_MINUS (SImode, val, exp);
      compare = gen_reg_rtx (SImode);
      emit_move_insn (compare, difference);
    }

  if (word_mode != SImode)
    {
      rtx reg = gen_reg_rtx (word_mode);
      emit_move_insn (reg, gen_rtx_SIGN_EXTEND (word_mode, compare));
      compare = reg;
    }

  emit_move_insn (operands[0], gen_rtx_EQ (SImode, compare, const0_rtx));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit (operand6, true);
  emit (operand7, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:464 */
rtx
gen_atomic_cas_value_strongqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[7];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 473 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode/HImode atomics, so form a mask, then use
     subword_atomic_cas_strongqi to implement a LR/SC version of the
     operation.  */

  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
     is disabled.  */

  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx o = operands[2];
  rtx n = operands[3];
  rtx shifted_o = gen_reg_rtx (SImode);
  rtx shifted_n = gen_reg_rtx (SImode);

  riscv_lshift_subword (QImode, o, shift, &shifted_o);
  riscv_lshift_subword (QImode, n, shift, &shifted_n);

  emit_move_insn (shifted_o, gen_rtx_AND (SImode, shifted_o, mask));
  emit_move_insn (shifted_n, gen_rtx_AND (SImode, shifted_n, mask));

  enum memmodel model_success = (enum memmodel) INTVAL (operands[4]);
  enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]);
  /* Find the union of the two memory models so we can satisfy both success
     and failure memory models.  */
  rtx model = GEN_INT (riscv_union_memmodels (model_success, model_failure));

  emit_insn (gen_subword_atomic_cas_strong (old, aligned_mem,
					    shifted_o, shifted_n,
					    model, mask, not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (QImode, old));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit_insn (gen_rtx_SCRATCH (QImode));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:464 */
rtx
gen_atomic_cas_value_stronghi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[7];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 473 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode/HImode atomics, so form a mask, then use
     subword_atomic_cas_stronghi to implement a LR/SC version of the
     operation.  */

  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
     is disabled.  */

  rtx old = gen_reg_rtx (SImode);
  rtx mem = operands[1];
  rtx aligned_mem = gen_reg_rtx (SImode);
  rtx shift = gen_reg_rtx (SImode);
  rtx mask = gen_reg_rtx (SImode);
  rtx not_mask = gen_reg_rtx (SImode);

  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);

  rtx o = operands[2];
  rtx n = operands[3];
  rtx shifted_o = gen_reg_rtx (SImode);
  rtx shifted_n = gen_reg_rtx (SImode);

  riscv_lshift_subword (HImode, o, shift, &shifted_o);
  riscv_lshift_subword (HImode, n, shift, &shifted_n);

  emit_move_insn (shifted_o, gen_rtx_AND (SImode, shifted_o, mask));
  emit_move_insn (shifted_n, gen_rtx_AND (SImode, shifted_n, mask));

  enum memmodel model_success = (enum memmodel) INTVAL (operands[4]);
  enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]);
  /* Find the union of the two memory models so we can satisfy both success
     and failure memory models.  */
  rtx model = GEN_INT (riscv_union_memmodels (model_success, model_failure));

  emit_insn (gen_subword_atomic_cas_strong (old, aligned_mem,
					    shifted_o, shifted_n,
					    model, mask, not_mask));

  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
					 gen_lowpart (QImode, shift)));

  emit_move_insn (operands[0], gen_lowpart (HImode, old));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit_insn (gen_rtx_SCRATCH (HImode));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:544 */
rtx
gen_atomic_test_and_set (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 549 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
  /* We have no QImode atomics, so use the address LSBs to form a mask,
     then use an aligned SImode atomic.  */
  rtx result = operands[0];
  rtx mem = operands[1];
  rtx model = operands[2];
  rtx addr = force_reg (Pmode, XEXP (mem, 0));

  rtx aligned_addr = gen_reg_rtx (Pmode);
  emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, GEN_INT (-4)));

  rtx aligned_mem = change_address (mem, SImode, aligned_addr);
  set_mem_alias_set (aligned_mem, 0);

  rtx offset = gen_reg_rtx (SImode);
  emit_move_insn (offset, gen_rtx_AND (SImode, gen_lowpart (SImode, addr),
				       GEN_INT (3)));

  rtx tmp = gen_reg_rtx (SImode);
  emit_move_insn (tmp, GEN_INT (1));

  rtx shmt = gen_reg_rtx (SImode);
  emit_move_insn (shmt, gen_rtx_ASHIFT (SImode, offset, GEN_INT (3)));

  rtx word = gen_reg_rtx (SImode);
  emit_move_insn (word, gen_rtx_ASHIFT (SImode, tmp,
					gen_lowpart (QImode, shmt)));

  tmp = gen_reg_rtx (SImode);
  emit_insn (gen_atomic_fetch_orsi (tmp, aligned_mem, word, model));

  emit_move_insn (gen_lowpart (SImode, result),
		  gen_rtx_LSHIFTRT (SImode, tmp,
				    gen_lowpart (QImode, shmt)));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md:22 */
extern rtx_insn *gen_peephole2_1 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_1 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_1 (peephole.md:22)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 38 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
{
  operands[5] = GEN_INT (INTVAL (operands[2]) - INTVAL (operands[5]));
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_LSHIFTRT (DImode,
	copy_rtx (operand0),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md:43 */
extern rtx_insn *gen_peephole2_2 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_2 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_2 (peephole.md:43)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 52 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
{
  th_mempair_order_operands (operands, true, SImode);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md:43 */
extern rtx_insn *gen_peephole2_3 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_3 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_3 (peephole.md:43)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 52 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
{
  th_mempair_order_operands (operands, true, DImode);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md:57 */
extern rtx_insn *gen_peephole2_4 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_4 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_4 (peephole.md:57)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
{
  th_mempair_order_operands (operands, false, SImode);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md:57 */
extern rtx_insn *gen_peephole2_5 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_5 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_5 (peephole.md:57)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 66 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
{
  th_mempair_order_operands (operands, false, DImode);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md:71 */
extern rtx_insn *gen_peephole2_6 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_6 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_6 (peephole.md:71)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 80 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
{
  th_mempair_order_operands (operands, true, SImode);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1)),
		gen_rtx_SET (operand2,
	gen_rtx_SIGN_EXTEND (DImode,
	operand3)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md:85 */
extern rtx_insn *gen_peephole2_7 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_7 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_7 (peephole.md:85)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 94 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/peephole.md"
{
  th_mempair_order_operands (operands, true, SImode);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1)),
		gen_rtx_SET (operand2,
	gen_rtx_ZERO_EXTEND (DImode,
	operand3)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx1qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx1QImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx2qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx2QImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx4qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx4QImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx8QImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx16QImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx32qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx32QImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx64qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx64QImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx1hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx1HImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx2hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx2HImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx4HImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx8HImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx16hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx16HImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx32hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx32HImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx1si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx1SImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx2SImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx4SImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx8si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx8SImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx16si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx16SImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx1di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx1DImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx2DImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx4di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx4DImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx8di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx8DImode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx1sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx1SFmode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx2SFmode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx4SFmode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx8sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx8SFmode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx16sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx16SFmode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx1df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx1DFmode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx2DFmode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx4df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx4DFmode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
rtx
gen_vreinterpretvnx8df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 374 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_move_insn (operands[0], gen_lowpart (VNx8DFmode, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx1qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx2QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx2qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx4QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx4qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx32QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx32qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx64QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx1hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx2HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx2hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx4HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx16hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx32HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx1si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx2SImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx4SImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8SImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx8si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16SImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx1di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx2DImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx4DImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx4di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8DImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx1sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx2SFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx4SFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8SFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx8sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16SFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx1df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx2DFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx4DFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
rtx
gen_vlmul_extx2vnx4df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8DFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx1qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx4QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx2qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx4qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx32QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx64QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx1hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx4HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx2hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx32HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx1si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx4SImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8SImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16SImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx1di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx4DImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8DImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx1sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx4SFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8SFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16SFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx1df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx4DFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
rtx
gen_vlmul_extx4vnx2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 392 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8DFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx1qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx2qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx4qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx32QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx64QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx1hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx2hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx32HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx1si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8SImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16SImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx1di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8DImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx1sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8SFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16SFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
rtx
gen_vlmul_extx8vnx1df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 399 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx8DFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
rtx
gen_vlmul_extx16vnx1qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 406 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
rtx
gen_vlmul_extx16vnx2qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 406 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx32QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
rtx
gen_vlmul_extx16vnx4qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 406 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx64QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
rtx
gen_vlmul_extx16vnx1hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 406 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
rtx
gen_vlmul_extx16vnx2hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 406 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx32HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
rtx
gen_vlmul_extx16vnx1si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 406 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16SImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
rtx
gen_vlmul_extx16vnx1sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 406 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx16SFmode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:408 */
rtx
gen_vlmul_extx32vnx1qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx32QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:408 */
rtx
gen_vlmul_extx32vnx2qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx64QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:408 */
rtx
gen_vlmul_extx32vnx1hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx32HImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:415 */
rtx
gen_vlmul_extx64vnx1qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 420 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SUBREG (VNx64QImode,
	operand1,
	0)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_90 (rtx_insn *, rtx *);
rtx_insn *
gen_split_90 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_90 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_91 (rtx_insn *, rtx *);
rtx_insn *
gen_split_91 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_91 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_92 (rtx_insn *, rtx *);
rtx_insn *
gen_split_92 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_92 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_93 (rtx_insn *, rtx *);
rtx_insn *
gen_split_93 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_93 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx8QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_94 (rtx_insn *, rtx *);
rtx_insn *
gen_split_94 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_94 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx16QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_95 (rtx_insn *, rtx *);
rtx_insn *
gen_split_95 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_95 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx32QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_96 (rtx_insn *, rtx *);
rtx_insn *
gen_split_96 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_96 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_97 (rtx_insn *, rtx *);
rtx_insn *
gen_split_97 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_97 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_98 (rtx_insn *, rtx *);
rtx_insn *
gen_split_98 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_98 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_99 (rtx_insn *, rtx *);
rtx_insn *
gen_split_99 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_99 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx8HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_100 (rtx_insn *, rtx *);
rtx_insn *
gen_split_100 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_100 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx16HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_101 (rtx_insn *, rtx *);
rtx_insn *
gen_split_101 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_101 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_102 (rtx_insn *, rtx *);
rtx_insn *
gen_split_102 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_102 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_103 (rtx_insn *, rtx *);
rtx_insn *
gen_split_103 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_103 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_104 (rtx_insn *, rtx *);
rtx_insn *
gen_split_104 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_104 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx8SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_105 (rtx_insn *, rtx *);
rtx_insn *
gen_split_105 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_105 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1DImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_106 (rtx_insn *, rtx *);
rtx_insn *
gen_split_106 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_106 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2DImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_107 (rtx_insn *, rtx *);
rtx_insn *
gen_split_107 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_107 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4DImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_108 (rtx_insn *, rtx *);
rtx_insn *
gen_split_108 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_108 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1SFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_109 (rtx_insn *, rtx *);
rtx_insn *
gen_split_109 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_109 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2SFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_110 (rtx_insn *, rtx *);
rtx_insn *
gen_split_110 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_110 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4SFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_111 (rtx_insn *, rtx *);
rtx_insn *
gen_split_111 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_111 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx8SFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_112 (rtx_insn *, rtx *);
rtx_insn *
gen_split_112 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_112 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1DFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_113 (rtx_insn *, rtx *);
rtx_insn *
gen_split_113 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_113 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2DFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
extern rtx_insn *gen_split_114 (rtx_insn *, rtx *);
rtx_insn *
gen_split_114 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_114 (vector.md:422)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4DFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_115 (rtx_insn *, rtx *);
rtx_insn *
gen_split_115 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_115 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_116 (rtx_insn *, rtx *);
rtx_insn *
gen_split_116 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_116 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_117 (rtx_insn *, rtx *);
rtx_insn *
gen_split_117 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_117 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_118 (rtx_insn *, rtx *);
rtx_insn *
gen_split_118 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_118 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx8QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_119 (rtx_insn *, rtx *);
rtx_insn *
gen_split_119 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_119 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx16QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_120 (rtx_insn *, rtx *);
rtx_insn *
gen_split_120 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_120 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_121 (rtx_insn *, rtx *);
rtx_insn *
gen_split_121 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_121 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_122 (rtx_insn *, rtx *);
rtx_insn *
gen_split_122 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_122 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_123 (rtx_insn *, rtx *);
rtx_insn *
gen_split_123 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_123 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx8HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_124 (rtx_insn *, rtx *);
rtx_insn *
gen_split_124 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_124 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_125 (rtx_insn *, rtx *);
rtx_insn *
gen_split_125 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_125 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_126 (rtx_insn *, rtx *);
rtx_insn *
gen_split_126 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_126 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_127 (rtx_insn *, rtx *);
rtx_insn *
gen_split_127 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_127 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1DImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_128 (rtx_insn *, rtx *);
rtx_insn *
gen_split_128 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_128 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2DImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_129 (rtx_insn *, rtx *);
rtx_insn *
gen_split_129 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_129 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1SFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_130 (rtx_insn *, rtx *);
rtx_insn *
gen_split_130 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_130 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2SFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_131 (rtx_insn *, rtx *);
rtx_insn *
gen_split_131 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_131 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4SFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_132 (rtx_insn *, rtx *);
rtx_insn *
gen_split_132 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_132 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1DFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
extern rtx_insn *gen_split_133 (rtx_insn *, rtx *);
rtx_insn *
gen_split_133 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_133 (vector.md:435)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 443 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2DFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_134 (rtx_insn *, rtx *);
rtx_insn *
gen_split_134 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_134 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_135 (rtx_insn *, rtx *);
rtx_insn *
gen_split_135 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_135 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_136 (rtx_insn *, rtx *);
rtx_insn *
gen_split_136 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_136 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_137 (rtx_insn *, rtx *);
rtx_insn *
gen_split_137 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_137 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx8QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_138 (rtx_insn *, rtx *);
rtx_insn *
gen_split_138 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_138 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_139 (rtx_insn *, rtx *);
rtx_insn *
gen_split_139 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_139 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_140 (rtx_insn *, rtx *);
rtx_insn *
gen_split_140 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_140 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_141 (rtx_insn *, rtx *);
rtx_insn *
gen_split_141 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_141 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_142 (rtx_insn *, rtx *);
rtx_insn *
gen_split_142 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_142 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_143 (rtx_insn *, rtx *);
rtx_insn *
gen_split_143 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_143 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1DImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_144 (rtx_insn *, rtx *);
rtx_insn *
gen_split_144 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_144 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1SFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_145 (rtx_insn *, rtx *);
rtx_insn *
gen_split_145 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_145 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2SFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
extern rtx_insn *gen_split_146 (rtx_insn *, rtx *);
rtx_insn *
gen_split_146 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_146 (vector.md:448)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1DFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
extern rtx_insn *gen_split_147 (rtx_insn *, rtx *);
rtx_insn *
gen_split_147 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_147 (vector.md:461)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
extern rtx_insn *gen_split_148 (rtx_insn *, rtx *);
rtx_insn *
gen_split_148 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_148 (vector.md:461)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
extern rtx_insn *gen_split_149 (rtx_insn *, rtx *);
rtx_insn *
gen_split_149 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_149 (vector.md:461)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx4QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
extern rtx_insn *gen_split_150 (rtx_insn *, rtx *);
rtx_insn *
gen_split_150 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_150 (vector.md:461)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
extern rtx_insn *gen_split_151 (rtx_insn *, rtx *);
rtx_insn *
gen_split_151 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_151 (vector.md:461)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
extern rtx_insn *gen_split_152 (rtx_insn *, rtx *);
rtx_insn *
gen_split_152 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_152 (vector.md:461)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
extern rtx_insn *gen_split_153 (rtx_insn *, rtx *);
rtx_insn *
gen_split_153 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_153 (vector.md:461)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 469 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1SFmode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:474 */
extern rtx_insn *gen_split_154 (rtx_insn *, rtx *);
rtx_insn *
gen_split_154 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_154 (vector.md:474)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:474 */
extern rtx_insn *gen_split_155 (rtx_insn *, rtx *);
rtx_insn *
gen_split_155 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_155 (vector.md:474)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx2QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:474 */
extern rtx_insn *gen_split_156 (rtx_insn *, rtx *);
rtx_insn *
gen_split_156 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_156 (vector.md:474)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 482 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1HImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:487 */
extern rtx_insn *gen_split_157 (rtx_insn *, rtx *);
rtx_insn *
gen_split_157 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_157 (vector.md:487)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 495 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  emit_insn (gen_rtx_SET (gen_lowpart (VNx1QImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx1qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx1qi.

       - Classify the machine_mode mode = VNx1QImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx1BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx2qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx2qi.

       - Classify the machine_mode mode = VNx2QImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx2BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx4qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx4qi.

       - Classify the machine_mode mode = VNx4QImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx4BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx8qi.

       - Classify the machine_mode mode = VNx8QImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx8BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx16qi.

       - Classify the machine_mode mode = VNx16QImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx16BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx32qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx32qi.

       - Classify the machine_mode mode = VNx32QImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx32BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx64qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx64qi.

       - Classify the machine_mode mode = VNx64QImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx64BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx1hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx1hi.

       - Classify the machine_mode mode = VNx1HImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx1BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx2hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx2hi.

       - Classify the machine_mode mode = VNx2HImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx2BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx4hi.

       - Classify the machine_mode mode = VNx4HImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx4BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx8hi.

       - Classify the machine_mode mode = VNx8HImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx8BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx16hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx16hi.

       - Classify the machine_mode mode = VNx16HImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx16BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx32hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx32hi.

       - Classify the machine_mode mode = VNx32HImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx32BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx1si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx1si.

       - Classify the machine_mode mode = VNx1SImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx1BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx2si.

       - Classify the machine_mode mode = VNx2SImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx2BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx4si.

       - Classify the machine_mode mode = VNx4SImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx4BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx8si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx8si.

       - Classify the machine_mode mode = VNx8SImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx8BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx16si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx16si.

       - Classify the machine_mode mode = VNx16SImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx16BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx1di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx1di.

       - Classify the machine_mode mode = VNx1DImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx1BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx2di.

       - Classify the machine_mode mode = VNx2DImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx2BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx4di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx4di.

       - Classify the machine_mode mode = VNx4DImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx4BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx8di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx8di.

       - Classify the machine_mode mode = VNx8DImode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx8BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx1sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx1sf.

       - Classify the machine_mode mode = VNx1SFmode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx1BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx2sf.

       - Classify the machine_mode mode = VNx2SFmode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx2BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx4sf.

       - Classify the machine_mode mode = VNx4SFmode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx4BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx8sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx8sf.

       - Classify the machine_mode mode = VNx8SFmode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx8BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx16sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx16sf.

       - Classify the machine_mode mode = VNx16SFmode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx16BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx1df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx1df.

       - Classify the machine_mode mode = VNx1DFmode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx1BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx2df.

       - Classify the machine_mode mode = VNx2DFmode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx2BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx4df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx4df.

       - Classify the machine_mode mode = VNx4DFmode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx4BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
rtx
gen_movvnx8df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 539 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* For whole register move, we transform the pattern into the format
     that excludes the clobber of scratch register.

     We include clobber of a scalar scratch register which is going to be
     used for emit of vsetvl instruction after reload_completed since we
     need vsetvl instruction to set VL/VTYPE global status for fractional
     vector load/store.

     For example:
       [(set (match_operand:VNx1QI v24)
	     (match_operand:VNx1QI (mem: a4)))
	     (clobber (scratch:SI a5))]
     ====>> vsetvl a5,zero,e8,mf8
     ====>> vle8.v v24,(a4)

     Philosophy:

       - Clobber a scalar scratch register for each movvnx8df.

       - Classify the machine_mode mode = VNx8DFmode into 2 class:
	 Whole register move and fractional register move.

       - Transform and remove scratch clobber register for whole
	 register move so that we can avoid occupying the scalar
	 registers.

       - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
	 before spilling. The clobber scratch is used by spilling fractional
	 registers in IRA/LRA so it's too early.  */

  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx8BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
rtx
gen_movvnx1bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 625 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx1BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
rtx
gen_movvnx2bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 625 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx2BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
rtx
gen_movvnx4bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 625 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx4BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
rtx
gen_movvnx8bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 625 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx8BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
rtx
gen_movvnx16bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 625 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx16BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
rtx
gen_movvnx32bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 625 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx32BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
rtx
gen_movvnx64bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 625 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::legitimize_move (operands[0], operands[1], VNx64BImode))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx1qisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx1qidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx2qisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx2qidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx4qisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx4qidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx1hisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx1hidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx2hisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx2hidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx1sisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx1sidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx1sfsi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
rtx
gen_movvnx1sfdi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx1bisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx2bisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx4bisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx8bisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx16bisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx32bisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx64bisi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx1bidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx2bidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx4bidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx8bidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx16bidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx32bidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
rtx
gen_movvnx64bidi_lra (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 652 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_158 (rtx_insn *, rtx *);
rtx_insn *
gen_split_158 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_158 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx1QImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx1QImode),
      		operands[0], operands[1], operands[2], VNx1BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_159 (rtx_insn *, rtx *);
rtx_insn *
gen_split_159 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_159 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx1QImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx1QImode),
      		operands[0], operands[1], operands[2], VNx1BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_160 (rtx_insn *, rtx *);
rtx_insn *
gen_split_160 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_160 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx2QImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx2QImode),
      		operands[0], operands[1], operands[2], VNx2BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_161 (rtx_insn *, rtx *);
rtx_insn *
gen_split_161 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_161 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx2QImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx2QImode),
      		operands[0], operands[1], operands[2], VNx2BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_162 (rtx_insn *, rtx *);
rtx_insn *
gen_split_162 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_162 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx4QImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx4QImode),
      		operands[0], operands[1], operands[2], VNx4BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_163 (rtx_insn *, rtx *);
rtx_insn *
gen_split_163 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_163 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx4QImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx4QImode),
      		operands[0], operands[1], operands[2], VNx4BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_164 (rtx_insn *, rtx *);
rtx_insn *
gen_split_164 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_164 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx1HImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx1HImode),
      		operands[0], operands[1], operands[2], VNx1BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_165 (rtx_insn *, rtx *);
rtx_insn *
gen_split_165 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_165 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx1HImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx1HImode),
      		operands[0], operands[1], operands[2], VNx1BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_166 (rtx_insn *, rtx *);
rtx_insn *
gen_split_166 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_166 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx2HImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx2HImode),
      		operands[0], operands[1], operands[2], VNx2BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_167 (rtx_insn *, rtx *);
rtx_insn *
gen_split_167 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_167 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx2HImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx2HImode),
      		operands[0], operands[1], operands[2], VNx2BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_168 (rtx_insn *, rtx *);
rtx_insn *
gen_split_168 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_168 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx1SImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx1SImode),
      		operands[0], operands[1], operands[2], VNx1BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_169 (rtx_insn *, rtx *);
rtx_insn *
gen_split_169 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_169 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx1SImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx1SImode),
      		operands[0], operands[1], operands[2], VNx1BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_170 (rtx_insn *, rtx *);
rtx_insn *
gen_split_170 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_170 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx1SFmode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx1SFmode),
      		operands[0], operands[1], operands[2], VNx1BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
extern rtx_insn *gen_split_171 (rtx_insn *, rtx *);
rtx_insn *
gen_split_171 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_171 (vector.md:654)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 662 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx1SFmode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx1SFmode),
      		operands[0], operands[1], operands[2], VNx1BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_172 (rtx_insn *, rtx *);
rtx_insn *
gen_split_172 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_172 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx1BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx1BImode),
      		operands[0], operands[1], operands[2], VNx1BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_173 (rtx_insn *, rtx *);
rtx_insn *
gen_split_173 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_173 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx2BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx2BImode),
      		operands[0], operands[1], operands[2], VNx2BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_174 (rtx_insn *, rtx *);
rtx_insn *
gen_split_174 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_174 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx4BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx4BImode),
      		operands[0], operands[1], operands[2], VNx4BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_175 (rtx_insn *, rtx *);
rtx_insn *
gen_split_175 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_175 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx8BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx8BImode),
      		operands[0], operands[1], operands[2], VNx8BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_176 (rtx_insn *, rtx *);
rtx_insn *
gen_split_176 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_176 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx16BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx16BImode),
      		operands[0], operands[1], operands[2], VNx16BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_177 (rtx_insn *, rtx *);
rtx_insn *
gen_split_177 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_177 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx32BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx32BImode),
      		operands[0], operands[1], operands[2], VNx32BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_178 (rtx_insn *, rtx *);
rtx_insn *
gen_split_178 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_178 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx64BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx64BImode),
      		operands[0], operands[1], operands[2], VNx64BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_179 (rtx_insn *, rtx *);
rtx_insn *
gen_split_179 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_179 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx1BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx1BImode),
      		operands[0], operands[1], operands[2], VNx1BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_180 (rtx_insn *, rtx *);
rtx_insn *
gen_split_180 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_180 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx2BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx2BImode),
      		operands[0], operands[1], operands[2], VNx2BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_181 (rtx_insn *, rtx *);
rtx_insn *
gen_split_181 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_181 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx4BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx4BImode),
      		operands[0], operands[1], operands[2], VNx4BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_182 (rtx_insn *, rtx *);
rtx_insn *
gen_split_182 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_182 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx8BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx8BImode),
      		operands[0], operands[1], operands[2], VNx8BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_183 (rtx_insn *, rtx *);
rtx_insn *
gen_split_183 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_183 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx16BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx16BImode),
      		operands[0], operands[1], operands[2], VNx16BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_184 (rtx_insn *, rtx *);
rtx_insn *
gen_split_184 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_184 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx32BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx32BImode),
      		operands[0], operands[1], operands[2], VNx32BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
extern rtx_insn *gen_split_185 (rtx_insn *, rtx *);
rtx_insn *
gen_split_185 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_185 (vector.md:674)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 682 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (REG_P (operands[0]) && REG_P (operands[1]))
      emit_insn (gen_rtx_SET (operands[0], operands[1]));
  else
    {
      riscv_vector::emit_vlmax_vsetvl (VNx64BImode, operands[2]);
      riscv_vector::emit_vlmax_op (code_for_pred_mov (VNx64BImode),
      		operands[0], operands[1], operands[2], VNx64BImode);
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx1qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx1QImode),
		operands[0], operands[1], VNx1BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx2qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx2QImode),
		operands[0], operands[1], VNx2BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx4qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx4QImode),
		operands[0], operands[1], VNx4BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx8QImode),
		operands[0], operands[1], VNx8BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx16QImode),
		operands[0], operands[1], VNx16BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx32qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx32QImode),
		operands[0], operands[1], VNx32BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx64qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx64QImode),
		operands[0], operands[1], VNx64BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx1hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx1HImode),
		operands[0], operands[1], VNx1BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx2hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx2HImode),
		operands[0], operands[1], VNx2BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx4HImode),
		operands[0], operands[1], VNx4BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx8HImode),
		operands[0], operands[1], VNx8BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx16hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx16HImode),
		operands[0], operands[1], VNx16BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx32hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx32HImode),
		operands[0], operands[1], VNx32BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx1si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx1SImode),
		operands[0], operands[1], VNx1BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx2SImode),
		operands[0], operands[1], VNx2BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx4SImode),
		operands[0], operands[1], VNx4BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx8si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx8SImode),
		operands[0], operands[1], VNx8BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx16si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx16SImode),
		operands[0], operands[1], VNx16BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx1di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx1DImode),
		operands[0], operands[1], VNx1BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx2DImode),
		operands[0], operands[1], VNx2BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx4di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx4DImode),
		operands[0], operands[1], VNx4BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx8di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx8DImode),
		operands[0], operands[1], VNx8BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx1sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx1SFmode),
		operands[0], operands[1], VNx1BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx2SFmode),
		operands[0], operands[1], VNx2BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx4SFmode),
		operands[0], operands[1], VNx4BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx8sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx8SFmode),
		operands[0], operands[1], VNx8BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx16sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx16SFmode),
		operands[0], operands[1], VNx16BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx1df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx1DFmode),
		operands[0], operands[1], VNx1BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx2DFmode),
		operands[0], operands[1], VNx2BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx4df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx4DFmode),
		operands[0], operands[1], VNx4BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
rtx
gen_vec_duplicatevnx8df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 707 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    riscv_vector::emit_vlmax_op (code_for_pred_broadcast (VNx8DFmode),
		operands[0], operands[1], VNx8BImode);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:883 */
extern rtx_insn *gen_split_186 (rtx_insn *, rtx *);
rtx_insn *
gen_split_186 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_186 (vector.md:883)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 902 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (5,
		operand1,
		operand2,
		operand3,
		operand4,
		operand5),
	66)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		copy_rtx (operand3)),
	66)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	67),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (4,
		copy_rtx (operand2),
		copy_rtx (operand3),
		copy_rtx (operand4),
		copy_rtx (operand5)),
	66)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:883 */
extern rtx_insn *gen_split_187 (rtx_insn *, rtx *);
rtx_insn *
gen_split_187 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_187 (vector.md:883)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 902 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (5,
		operand1,
		operand2,
		operand3,
		operand4,
		operand5),
	66)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	66),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		copy_rtx (operand3)),
	66)),
		gen_rtx_SET (gen_rtx_REG (SImode,
	67),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (4,
		copy_rtx (operand2),
		copy_rtx (operand3),
		copy_rtx (operand4),
		copy_rtx (operand5)),
	66)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_188 (rtx_insn *, rtx *);
rtx_insn *
gen_split_188 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_188 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_189 (rtx_insn *, rtx *);
rtx_insn *
gen_split_189 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_189 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_190 (rtx_insn *, rtx *);
rtx_insn *
gen_split_190 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_190 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_191 (rtx_insn *, rtx *);
rtx_insn *
gen_split_191 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_191 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_192 (rtx_insn *, rtx *);
rtx_insn *
gen_split_192 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_192 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_193 (rtx_insn *, rtx *);
rtx_insn *
gen_split_193 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_193 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_194 (rtx_insn *, rtx *);
rtx_insn *
gen_split_194 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_194 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_195 (rtx_insn *, rtx *);
rtx_insn *
gen_split_195 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_195 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_196 (rtx_insn *, rtx *);
rtx_insn *
gen_split_196 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_196 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_197 (rtx_insn *, rtx *);
rtx_insn *
gen_split_197 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_197 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_198 (rtx_insn *, rtx *);
rtx_insn *
gen_split_198 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_198 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_199 (rtx_insn *, rtx *);
rtx_insn *
gen_split_199 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_199 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_200 (rtx_insn *, rtx *);
rtx_insn *
gen_split_200 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_200 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_201 (rtx_insn *, rtx *);
rtx_insn *
gen_split_201 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_201 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_202 (rtx_insn *, rtx *);
rtx_insn *
gen_split_202 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_202 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_203 (rtx_insn *, rtx *);
rtx_insn *
gen_split_203 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_203 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_204 (rtx_insn *, rtx *);
rtx_insn *
gen_split_204 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_204 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_205 (rtx_insn *, rtx *);
rtx_insn *
gen_split_205 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_205 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_206 (rtx_insn *, rtx *);
rtx_insn *
gen_split_206 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_206 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_207 (rtx_insn *, rtx *);
rtx_insn *
gen_split_207 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_207 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_208 (rtx_insn *, rtx *);
rtx_insn *
gen_split_208 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_208 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_209 (rtx_insn *, rtx *);
rtx_insn *
gen_split_209 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_209 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_210 (rtx_insn *, rtx *);
rtx_insn *
gen_split_210 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_210 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_211 (rtx_insn *, rtx *);
rtx_insn *
gen_split_211 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_211 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_212 (rtx_insn *, rtx *);
rtx_insn *
gen_split_212 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_212 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_213 (rtx_insn *, rtx *);
rtx_insn *
gen_split_213 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_213 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_214 (rtx_insn *, rtx *);
rtx_insn *
gen_split_214 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_214 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_215 (rtx_insn *, rtx *);
rtx_insn *
gen_split_215 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_215 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_216 (rtx_insn *, rtx *);
rtx_insn *
gen_split_216 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_216 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_217 (rtx_insn *, rtx *);
rtx_insn *
gen_split_217 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_217 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
extern rtx_insn *gen_split_218 (rtx_insn *, rtx *);
rtx_insn *
gen_split_218 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_218 (vector.md:971)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1000 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
extern rtx_insn *gen_split_219 (rtx_insn *, rtx *);
rtx_insn *
gen_split_219 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_219 (vector.md:1028)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1050 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
extern rtx_insn *gen_split_220 (rtx_insn *, rtx *);
rtx_insn *
gen_split_220 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_220 (vector.md:1028)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1050 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
extern rtx_insn *gen_split_221 (rtx_insn *, rtx *);
rtx_insn *
gen_split_221 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_221 (vector.md:1028)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1050 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
extern rtx_insn *gen_split_222 (rtx_insn *, rtx *);
rtx_insn *
gen_split_222 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_222 (vector.md:1028)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1050 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
extern rtx_insn *gen_split_223 (rtx_insn *, rtx *);
rtx_insn *
gen_split_223 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_223 (vector.md:1028)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1050 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
extern rtx_insn *gen_split_224 (rtx_insn *, rtx *);
rtx_insn *
gen_split_224 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_224 (vector.md:1028)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1050 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
extern rtx_insn *gen_split_225 (rtx_insn *, rtx *);
rtx_insn *
gen_split_225 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_225 (vector.md:1028)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1050 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1112 */
rtx
gen_pred_mergevnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1128 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[3],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::simm5_p (operands[3]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mergevnx1di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[4], operands[5],
	       operands[6], operands[7]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand3),
	operand2,
	operand4),
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1112 */
rtx
gen_pred_mergevnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1128 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[3],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::simm5_p (operands[3]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mergevnx2di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[4], operands[5],
	       operands[6], operands[7]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand3),
	operand2,
	operand4),
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1112 */
rtx
gen_pred_mergevnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1128 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[3],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::simm5_p (operands[3]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mergevnx4di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[4], operands[5],
	       operands[6], operands[7]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand3),
	operand2,
	operand4),
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1112 */
rtx
gen_pred_mergevnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1128 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[3],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::simm5_p (operands[3]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mergevnx8di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[4], operands[5],
	       operands[6], operands[7]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_MERGE (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand3),
	operand2,
	operand4),
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx1qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (QImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx1BImode);
          else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx1BImode);
	    }
          else
            operands[3] = force_reg (QImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (QImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (QImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx2qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (QImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx2BImode);
          else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx2BImode);
	    }
          else
            operands[3] = force_reg (QImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (QImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (QImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx4qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (QImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx4BImode);
          else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx4BImode);
	    }
          else
            operands[3] = force_reg (QImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (QImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (QImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (QImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx8BImode);
          else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx8BImode);
	    }
          else
            operands[3] = force_reg (QImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (QImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (QImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (QImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx16BImode);
          else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx16BImode);
	    }
          else
            operands[3] = force_reg (QImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (QImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (QImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx32qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (QImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx32BImode);
          else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx32BImode);
	    }
          else
            operands[3] = force_reg (QImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (QImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (QImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx64qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (QImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx64BImode);
          else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx64BImode);
	    }
          else
            operands[3] = force_reg (QImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (QImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (QImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx1hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (HImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx1BImode);
          else if (GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx1BImode);
	    }
          else
            operands[3] = force_reg (HImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (HImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (HImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx2hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (HImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx2BImode);
          else if (GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx2BImode);
	    }
          else
            operands[3] = force_reg (HImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (HImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (HImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (HImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx4BImode);
          else if (GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx4BImode);
	    }
          else
            operands[3] = force_reg (HImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (HImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (HImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (HImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx8BImode);
          else if (GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx8BImode);
	    }
          else
            operands[3] = force_reg (HImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (HImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (HImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx16hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (HImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx16BImode);
          else if (GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx16BImode);
	    }
          else
            operands[3] = force_reg (HImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (HImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (HImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx32hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (HImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx32BImode);
          else if (GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx32BImode);
	    }
          else
            operands[3] = force_reg (HImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (HImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (HImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx1si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (SImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx1BImode);
          else if (GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx1BImode);
	    }
          else
            operands[3] = force_reg (SImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (SImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (SImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (SImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx2BImode);
          else if (GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx2BImode);
	    }
          else
            operands[3] = force_reg (SImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (SImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (SImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (SImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx4BImode);
          else if (GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx4BImode);
	    }
          else
            operands[3] = force_reg (SImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (SImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (SImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx8si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (SImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx8BImode);
          else if (GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx8BImode);
	    }
          else
            operands[3] = force_reg (SImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (SImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (SImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx16si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (SImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx16BImode);
          else if (GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx16BImode);
	    }
          else
            operands[3] = force_reg (SImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (SImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (SImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx1di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (DImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx1BImode);
          else if (GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx1BImode);
	    }
          else
            operands[3] = force_reg (DImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (DImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (DImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (DImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx2BImode);
          else if (GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx2BImode);
	    }
          else
            operands[3] = force_reg (DImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (DImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (DImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx4di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (DImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx4BImode);
          else if (GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx4BImode);
	    }
          else
            operands[3] = force_reg (DImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (DImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (DImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx8di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (DImode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx8BImode);
          else if (GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx8BImode);
	    }
          else
            operands[3] = force_reg (DImode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (DImode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (DImode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx1sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (SFmode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx1BImode);
          else if (GET_MODE_BITSIZE (SFmode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx1BImode);
	    }
          else
            operands[3] = force_reg (SFmode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (SFmode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (SFmode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (SFmode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (SFmode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx2BImode);
          else if (GET_MODE_BITSIZE (SFmode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx2BImode);
	    }
          else
            operands[3] = force_reg (SFmode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (SFmode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (SFmode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (SFmode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (SFmode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx4BImode);
          else if (GET_MODE_BITSIZE (SFmode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx4BImode);
	    }
          else
            operands[3] = force_reg (SFmode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (SFmode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (SFmode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (SFmode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx8sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (SFmode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx8BImode);
          else if (GET_MODE_BITSIZE (SFmode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx8BImode);
	    }
          else
            operands[3] = force_reg (SFmode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (SFmode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (SFmode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (SFmode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx16sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (SFmode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx16BImode);
          else if (GET_MODE_BITSIZE (SFmode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx16BImode);
	    }
          else
            operands[3] = force_reg (SFmode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (SFmode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (SFmode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (SFmode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx1df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (DFmode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx1BImode);
          else if (GET_MODE_BITSIZE (DFmode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx1BImode);
	    }
          else
            operands[3] = force_reg (DFmode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (DFmode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (DFmode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (DFmode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (DFmode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx2BImode);
          else if (GET_MODE_BITSIZE (DFmode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx2BImode);
	    }
          else
            operands[3] = force_reg (DFmode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (DFmode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (DFmode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (DFmode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx4df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (DFmode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx4BImode);
          else if (GET_MODE_BITSIZE (DFmode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx4BImode);
	    }
          else
            operands[3] = force_reg (DFmode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (DFmode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (DFmode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (DFmode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
rtx
gen_pred_broadcastvnx8df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1219 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Handle vmv.s.x instruction which has memory scalar.  */
  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
      || rtx_equal_p (operands[3], CONST0_RTX (DFmode)))
    {
      if (satisfies_constraint_Wb1 (operands[1]))
        {
          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
          if (satisfies_constraint_vu (operands[2]))
            operands[1] = CONSTM1_RTX (VNx8BImode);
          else if (GET_MODE_BITSIZE (DFmode) > GET_MODE_BITSIZE (Pmode))
            {
	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	      operands[1] = CONSTM1_RTX (VNx8BImode);
	    }
          else
            operands[3] = force_reg (DFmode, operands[3]);
	}
    }
  else if (GET_MODE_BITSIZE (DFmode) > GET_MODE_BITSIZE (Pmode)
           && immediate_operand (operands[3], Pmode))
    operands[3] = gen_rtx_SIGN_EXTEND (DFmode, force_reg (Pmode, operands[3]));
  else
    operands[3] = force_reg (DFmode, operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_226 (rtx_insn *, rtx *);
rtx_insn *
gen_split_226 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_226 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (QImode, GET_MODE_SIZE (QImode),
				GET_MODE_ALIGNMENT (QImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (QImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx1BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_227 (rtx_insn *, rtx *);
rtx_insn *
gen_split_227 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_227 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (QImode, GET_MODE_SIZE (QImode),
				GET_MODE_ALIGNMENT (QImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (QImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx2BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_228 (rtx_insn *, rtx *);
rtx_insn *
gen_split_228 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_228 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (QImode, GET_MODE_SIZE (QImode),
				GET_MODE_ALIGNMENT (QImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (QImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx4BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_229 (rtx_insn *, rtx *);
rtx_insn *
gen_split_229 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_229 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (QImode, GET_MODE_SIZE (QImode),
				GET_MODE_ALIGNMENT (QImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (QImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx8BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_230 (rtx_insn *, rtx *);
rtx_insn *
gen_split_230 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_230 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (QImode, GET_MODE_SIZE (QImode),
				GET_MODE_ALIGNMENT (QImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (QImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx16BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_231 (rtx_insn *, rtx *);
rtx_insn *
gen_split_231 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_231 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (QImode, GET_MODE_SIZE (QImode),
				GET_MODE_ALIGNMENT (QImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (QImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx32BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_232 (rtx_insn *, rtx *);
rtx_insn *
gen_split_232 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_232 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (QImode, GET_MODE_SIZE (QImode),
				GET_MODE_ALIGNMENT (QImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (QImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx64BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_233 (rtx_insn *, rtx *);
rtx_insn *
gen_split_233 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_233 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (HImode, GET_MODE_SIZE (HImode),
				GET_MODE_ALIGNMENT (HImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (HImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx1BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_234 (rtx_insn *, rtx *);
rtx_insn *
gen_split_234 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_234 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (HImode, GET_MODE_SIZE (HImode),
				GET_MODE_ALIGNMENT (HImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (HImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx2BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_235 (rtx_insn *, rtx *);
rtx_insn *
gen_split_235 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_235 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (HImode, GET_MODE_SIZE (HImode),
				GET_MODE_ALIGNMENT (HImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (HImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx4BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_236 (rtx_insn *, rtx *);
rtx_insn *
gen_split_236 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_236 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (HImode, GET_MODE_SIZE (HImode),
				GET_MODE_ALIGNMENT (HImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (HImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx8BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_237 (rtx_insn *, rtx *);
rtx_insn *
gen_split_237 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_237 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (HImode, GET_MODE_SIZE (HImode),
				GET_MODE_ALIGNMENT (HImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (HImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx16BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_238 (rtx_insn *, rtx *);
rtx_insn *
gen_split_238 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_238 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (HImode, GET_MODE_SIZE (HImode),
				GET_MODE_ALIGNMENT (HImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (HImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx32BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_239 (rtx_insn *, rtx *);
rtx_insn *
gen_split_239 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_239 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (SImode, GET_MODE_SIZE (SImode),
				GET_MODE_ALIGNMENT (SImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (SImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx1BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_240 (rtx_insn *, rtx *);
rtx_insn *
gen_split_240 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_240 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (SImode, GET_MODE_SIZE (SImode),
				GET_MODE_ALIGNMENT (SImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (SImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx2BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_241 (rtx_insn *, rtx *);
rtx_insn *
gen_split_241 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_241 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (SImode, GET_MODE_SIZE (SImode),
				GET_MODE_ALIGNMENT (SImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (SImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx4BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_242 (rtx_insn *, rtx *);
rtx_insn *
gen_split_242 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_242 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (SImode, GET_MODE_SIZE (SImode),
				GET_MODE_ALIGNMENT (SImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (SImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx8BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_243 (rtx_insn *, rtx *);
rtx_insn *
gen_split_243 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_243 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (SImode, GET_MODE_SIZE (SImode),
				GET_MODE_ALIGNMENT (SImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (SImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx16BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_244 (rtx_insn *, rtx *);
rtx_insn *
gen_split_244 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_244 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (DImode, GET_MODE_SIZE (DImode),
				GET_MODE_ALIGNMENT (DImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (DImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx1BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_245 (rtx_insn *, rtx *);
rtx_insn *
gen_split_245 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_245 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (DImode, GET_MODE_SIZE (DImode),
				GET_MODE_ALIGNMENT (DImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (DImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx2BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_246 (rtx_insn *, rtx *);
rtx_insn *
gen_split_246 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_246 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (DImode, GET_MODE_SIZE (DImode),
				GET_MODE_ALIGNMENT (DImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (DImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx4BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
extern rtx_insn *gen_split_247 (rtx_insn *, rtx *);
rtx_insn *
gen_split_247 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_247 (vector.md:1246)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    gcc_assert (can_create_pseudo_p ());
    rtx m = assign_stack_local (DImode, GET_MODE_SIZE (DImode),
				GET_MODE_ALIGNMENT (DImode));
    m = validize_mem (m);
    emit_move_insn (m, operands[3]);
    m = gen_rtx_MEM (DImode, force_reg (Pmode, XEXP (m, 0)));
    operands[3] = m;

    /* For SEW = 64 in RV32 system, we expand vmv.s.x:
       andi a2,a2,1
       vsetvl zero,a2,e64
       vlse64.v  */
    if (satisfies_constraint_Wb1 (operands[1]))
      {
	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
	operands[1] = CONSTM1_RTX (VNx8BImode);
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand4,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_addvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (PLUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_addvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_andvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (AND, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_andvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_iorvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (IOR, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_iorvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_xorvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (XOR, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_xorvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_smaxvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (SMAX, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_smaxvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_umaxvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (UMAX, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_umaxvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_sminvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (SMIN, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_sminvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_uminvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (UMIN, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_uminvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_mulvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (MULT, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_addvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (PLUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_addvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_andvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (AND, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_andvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_iorvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (IOR, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_iorvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_xorvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (XOR, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_xorvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_smaxvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (SMAX, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_smaxvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_umaxvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (UMAX, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_umaxvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_sminvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (SMIN, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_sminvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_uminvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (UMIN, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_uminvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_mulvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (MULT, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_addvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (PLUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_addvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_andvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (AND, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_andvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_iorvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (IOR, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_iorvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_xorvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (XOR, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_xorvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_smaxvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (SMAX, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_smaxvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_umaxvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (UMAX, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_umaxvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_sminvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (SMIN, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_sminvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_uminvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (UMIN, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_uminvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_mulvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (MULT, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_addvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (PLUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_addvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_andvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (AND, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_andvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_AND (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_iorvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (IOR, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_iorvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_IOR (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_xorvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (XOR, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_xorvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_XOR (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_smaxvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (SMAX, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_smaxvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMAX (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_umaxvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (UMAX, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_umaxvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMAX (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_sminvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (SMIN, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_sminvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SMIN (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_uminvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (UMIN, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_uminvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMIN (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
rtx
gen_pred_mulvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1822 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (MULT, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_subvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (MINUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_subvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_divvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (DIV, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_divvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx1DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_udivvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (UDIV, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_udivvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx1DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_modvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (MOD, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_modvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx1DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_umodvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (UMOD, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_umodvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx1DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_subvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (MINUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_subvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_divvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (DIV, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_divvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx2DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_udivvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (UDIV, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_udivvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx2DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_modvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (MOD, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_modvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx2DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_umodvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (UMOD, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_umodvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx2DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_subvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (MINUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_subvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_divvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (DIV, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_divvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx4DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_udivvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (UDIV, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_udivvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx4DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_modvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (MOD, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_modvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx4DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_umodvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (UMOD, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_umodvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx4DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_subvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (MINUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_subvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_divvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (DIV, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_divvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_DIV (VNx8DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_udivvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (UDIV, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_udivvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UDIV (VNx8DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_modvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (MOD, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_modvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MOD (VNx8DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
rtx
gen_pred_umodvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1898 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (UMOD, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_umodvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UMOD (VNx8DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1957 */
rtx
gen_pred_subvnx1di_reverse_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::neg_simm5_p (operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_subvnx1di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[3], operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1957 */
rtx
gen_pred_subvnx2di_reverse_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::neg_simm5_p (operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_subvnx2di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[3], operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1957 */
rtx
gen_pred_subvnx4di_reverse_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::neg_simm5_p (operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_subvnx4di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[3], operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1957 */
rtx
gen_pred_subvnx8di_reverse_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 1974 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::neg_simm5_p (operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_subvnx8di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[3], operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
rtx
gen_pred_mulhvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2092 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulhvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
		operand3),
	73),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
rtx
gen_pred_mulhuvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2092 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulhuvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
		operand3),
	74),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
rtx
gen_pred_mulhsuvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2092 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulhsuvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
		operand3),
	75),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
rtx
gen_pred_mulhvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2092 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulhvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
		operand3),
	73),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
rtx
gen_pred_mulhuvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2092 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulhuvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
		operand3),
	74),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
rtx
gen_pred_mulhsuvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2092 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulhsuvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
		operand3),
	75),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
rtx
gen_pred_mulhvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2092 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulhvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
		operand3),
	73),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
rtx
gen_pred_mulhuvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2092 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulhuvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
		operand3),
	74),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
rtx
gen_pred_mulhsuvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2092 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulhsuvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
		operand3),
	75),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
rtx
gen_pred_mulhvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2092 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulhvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
		operand3),
	73),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
rtx
gen_pred_mulhuvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2092 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulhuvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
		operand3),
	74),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
rtx
gen_pred_mulhsuvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2092 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mulhsuvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
		operand3),
	75),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2250 */
rtx
gen_pred_adcvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2267 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[3],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::simm5_p (operands[3]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_adcvnx1di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[4], operands[5],
	       operands[6], operands[7]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2250 */
rtx
gen_pred_adcvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2267 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[3],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::simm5_p (operands[3]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_adcvnx2di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[4], operands[5],
	       operands[6], operands[7]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2250 */
rtx
gen_pred_adcvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2267 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[3],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::simm5_p (operands[3]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_adcvnx4di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[4], operands[5],
	       operands[6], operands[7]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2250 */
rtx
gen_pred_adcvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2267 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[3],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::simm5_p (operands[3]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_adcvnx8di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[4], operands[5],
	       operands[6], operands[7]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand3),
	operand2),
		operand4),
	76),
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2334 */
rtx
gen_pred_sbcvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[3],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_sbcvnx1di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[4], operands[5],
	       operands[6], operands[7]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1DImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand3)),
		operand4),
	77),
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2334 */
rtx
gen_pred_sbcvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[3],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_sbcvnx2di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[4], operands[5],
	       operands[6], operands[7]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2DImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand3)),
		operand4),
	77),
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2334 */
rtx
gen_pred_sbcvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[3],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_sbcvnx4di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[4], operands[5],
	       operands[6], operands[7]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4DImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand3)),
		operand4),
	77),
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2334 */
rtx
gen_pred_sbcvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[3],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_sbcvnx8di (operands[0], operands[1],
	       operands[2], boardcast_scalar, operands[4], operands[5],
	       operands[6], operands[7]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (5,
		operand5,
		operand6,
		operand7,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8DImode,
	operand2,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand3)),
		operand4),
	77),
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2496 */
rtx
gen_pred_madcvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2510 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[4],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::simm5_p (operands[2]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_madcvnx1di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2496 */
rtx
gen_pred_madcvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2510 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[4],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::simm5_p (operands[2]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_madcvnx2di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2496 */
rtx
gen_pred_madcvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2510 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[4],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::simm5_p (operands[2]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_madcvnx4di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2496 */
rtx
gen_pred_madcvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2510 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[4],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::simm5_p (operands[2]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_madcvnx8di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_PLUS (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	78)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2566 */
rtx
gen_pred_msbcvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[4],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_msbcvnx1di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2566 */
rtx
gen_pred_msbcvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[4],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_msbcvnx2di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2566 */
rtx
gen_pred_msbcvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[4],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_msbcvnx4di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2566 */
rtx
gen_pred_msbcvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2580 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[4],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_msbcvnx8di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (3,
		gen_rtx_MINUS (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand2),
	operand1),
		operand3,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand4,
		operand5,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	79)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2710 */
rtx
gen_pred_madcvnx1di_overflow_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2723 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[3],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::simm5_p (operands[2]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_madcvnx1di_overflow (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2710 */
rtx
gen_pred_madcvnx2di_overflow_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2723 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[3],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::simm5_p (operands[2]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_madcvnx2di_overflow (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2710 */
rtx
gen_pred_madcvnx4di_overflow_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2723 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[3],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::simm5_p (operands[2]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_madcvnx4di_overflow (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2710 */
rtx
gen_pred_madcvnx8di_overflow_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2723 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[3],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::simm5_p (operands[2]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_madcvnx8di_overflow (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_PLUS (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2777 */
rtx
gen_pred_msbcvnx1di_overflow_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2790 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[3],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_msbcvnx1di_overflow (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2777 */
rtx
gen_pred_msbcvnx2di_overflow_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2790 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[3],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_msbcvnx2di_overflow (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2777 */
rtx
gen_pred_msbcvnx4di_overflow_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2790 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[3],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_msbcvnx4di_overflow (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2777 */
rtx
gen_pred_msbcvnx8di_overflow_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 2790 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[3],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_msbcvnx8di_overflow (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		gen_rtx_MINUS (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand2),
	operand1),
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (4,
		operand3,
		operand4,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68)),
	80)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
rtx
gen_pred_ssaddvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (SS_PLUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_ssaddvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
rtx
gen_pred_usaddvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (US_PLUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_usaddvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
rtx
gen_pred_ssaddvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (SS_PLUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_ssaddvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
rtx
gen_pred_usaddvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (US_PLUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_usaddvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
rtx
gen_pred_ssaddvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (SS_PLUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_ssaddvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
rtx
gen_pred_usaddvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (US_PLUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_usaddvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
rtx
gen_pred_ssaddvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (SS_PLUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_ssaddvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_PLUS (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
rtx
gen_pred_usaddvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3280 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (US_PLUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_usaddvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_PLUS (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4),
	operand3),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
rtx
gen_pred_sssubvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (SS_MINUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_sssubvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx1DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
rtx
gen_pred_ussubvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (US_MINUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_ussubvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx1DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
rtx
gen_pred_sssubvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (SS_MINUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_sssubvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx2DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
rtx
gen_pred_ussubvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (US_MINUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_ussubvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx2DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
rtx
gen_pred_sssubvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (SS_MINUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_sssubvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx4DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
rtx
gen_pred_ussubvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (US_MINUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_ussubvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx4DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
rtx
gen_pred_sssubvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (SS_MINUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_sssubvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_SS_MINUS (VNx8DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
rtx
gen_pred_ussubvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3356 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (US_MINUS, operands[4]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_ussubvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_US_MINUS (VNx8DImode,
	operand3,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand4)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_aadduvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_aadduvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_aaddvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_aaddvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_asubuvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_asubuvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_asubvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_asubvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_smulvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_smulvnx1di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_aadduvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_aadduvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_aaddvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_aaddvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_asubuvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_asubuvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_asubvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_asubvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_smulvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_smulvnx2di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_aadduvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_aadduvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_aaddvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_aaddvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_asubuvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_asubuvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_asubvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_asubvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_smulvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_smulvnx4di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_aadduvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_aadduvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	85),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_aaddvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_aaddvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	86),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_asubuvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_asubuvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	87),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_asubvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_asubvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	88),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
rtx
gen_pred_smulvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[4],
	/* vl */operands[5],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_smulvnx8di (operands[0], operands[1],
	       operands[2], operands[3], boardcast_scalar, operands[5],
	       operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand3,
		operand4),
	89),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx1qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx2qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx4qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx32qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx32BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx64qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx64BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx1hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx2hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx16hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx32hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx32BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx1si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx8si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx16si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx1di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx4di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
rtx
gen_pred_cmpvnx8di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3614 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx1qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx2qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx4qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx32qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx32BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx64qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx64BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx1hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx2hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx16hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx32hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx32BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx1si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx8si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx16si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx1di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx4di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
rtx
gen_pred_ltgevnx8di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3671 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx1qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx2qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx4qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx8qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx16qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx32qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx32BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx64qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx64BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx1hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx2hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx4hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx8hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx16hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx32hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx32BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx1si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx2si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx4si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx8si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
rtx
gen_pred_cmpvnx16si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3729 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx1qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx2qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx4qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx8qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx16qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx32qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx32BImode,
		gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx64qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx64BImode,
		gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx1hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx2hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx4hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx8hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx16hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx32hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx32BImode,
		gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx1si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx2si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx4si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx8si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
rtx
gen_pred_eqnevnx16si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3789 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3835 */
rtx
gen_pred_cmpvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3851 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[5],
	/* vl */operands[6],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (code, operands[5]),
	code == LT || code == LTU ?
	  [] (rtx *operands, rtx boardcast_scalar) {
	    emit_insn (gen_pred_ltgevnx1di (operands[0], operands[1],
	    	operands[2], operands[3], operands[4], boardcast_scalar,
	  	operands[6], operands[7], operands[8]));
          }
	:
	  [] (rtx *operands, rtx boardcast_scalar) {
	    emit_insn (gen_pred_cmpvnx1di (operands[0], operands[1],
	    	operands[2], operands[3], operands[4], boardcast_scalar,
	  	operands[6], operands[7], operands[8]));
          }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3835 */
rtx
gen_pred_cmpvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3851 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[5],
	/* vl */operands[6],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (code, operands[5]),
	code == LT || code == LTU ?
	  [] (rtx *operands, rtx boardcast_scalar) {
	    emit_insn (gen_pred_ltgevnx2di (operands[0], operands[1],
	    	operands[2], operands[3], operands[4], boardcast_scalar,
	  	operands[6], operands[7], operands[8]));
          }
	:
	  [] (rtx *operands, rtx boardcast_scalar) {
	    emit_insn (gen_pred_cmpvnx2di (operands[0], operands[1],
	    	operands[2], operands[3], operands[4], boardcast_scalar,
	  	operands[6], operands[7], operands[8]));
          }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3835 */
rtx
gen_pred_cmpvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3851 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[5],
	/* vl */operands[6],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (code, operands[5]),
	code == LT || code == LTU ?
	  [] (rtx *operands, rtx boardcast_scalar) {
	    emit_insn (gen_pred_ltgevnx4di (operands[0], operands[1],
	    	operands[2], operands[3], operands[4], boardcast_scalar,
	  	operands[6], operands[7], operands[8]));
          }
	:
	  [] (rtx *operands, rtx boardcast_scalar) {
	    emit_insn (gen_pred_cmpvnx4di (operands[0], operands[1],
	    	operands[2], operands[3], operands[4], boardcast_scalar,
	  	operands[6], operands[7], operands[8]));
          }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3835 */
rtx
gen_pred_cmpvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3851 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[5],
	/* vl */operands[6],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (code, operands[5]),
	code == LT || code == LTU ?
	  [] (rtx *operands, rtx boardcast_scalar) {
	    emit_insn (gen_pred_ltgevnx8di (operands[0], operands[1],
	    	operands[2], operands[3], operands[4], boardcast_scalar,
	  	operands[6], operands[7], operands[8]));
          }
	:
	  [] (rtx *operands, rtx boardcast_scalar) {
	    emit_insn (gen_pred_cmpvnx8di (operands[0], operands[1],
	    	operands[2], operands[3], operands[4], boardcast_scalar,
	  	operands[6], operands[7], operands[8]));
          }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3875 */
rtx
gen_pred_eqnevnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[5],
	/* vl */operands[6],
	VNx1DImode,
	VNx1BImode,
	riscv_vector::has_vi_variant_p (code, operands[5]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_cmpvnx1di (operands[0], operands[1],
	  	operands[2], operands[3], operands[4], boardcast_scalar,
		operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3875 */
rtx
gen_pred_eqnevnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[5],
	/* vl */operands[6],
	VNx2DImode,
	VNx2BImode,
	riscv_vector::has_vi_variant_p (code, operands[5]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_cmpvnx2di (operands[0], operands[1],
	  	operands[2], operands[3], operands[4], boardcast_scalar,
		operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3875 */
rtx
gen_pred_eqnevnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[5],
	/* vl */operands[6],
	VNx4DImode,
	VNx4BImode,
	riscv_vector::has_vi_variant_p (code, operands[5]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_cmpvnx4di (operands[0], operands[1],
	  	operands[2], operands[3], operands[4], boardcast_scalar,
		operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3875 */
rtx
gen_pred_eqnevnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 3891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[5],
	/* vl */operands[6],
	VNx8DImode,
	VNx8BImode,
	riscv_vector::has_vi_variant_p (code, operands[5]),
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_cmpvnx8di (operands[0], operands[1],
	  	operands[2], operands[3], operands[4], boardcast_scalar,
		operands[6], operands[7], operands[8]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx1qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx1BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx1BImode, operands[0], CONSTM1_RTX (VNx1BImode), undef,
			CONSTM1_RTX (VNx1BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx1BImode))
	    emit_insn (gen_pred (IOR, VNx1BImode, operands[0],
				 CONSTM1_RTX (VNx1BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx1BImode, operands[0],
				 CONSTM1_RTX (VNx1BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx1qi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx1QImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx1BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx1BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (QImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (QImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx1qi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx1bi (operands[0], CONSTM1_RTX (VNx1BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx1BImode);
	      emit_insn (gen_pred_cmpvnx1qi_scalar (
		reg, CONSTM1_RTX (VNx1BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx1bi (operands[0], CONSTM1_RTX (VNx1BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx1qi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx1BImode, operands[0],
				   CONSTM1_RTX (VNx1BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx2qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx2BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx2BImode, operands[0], CONSTM1_RTX (VNx2BImode), undef,
			CONSTM1_RTX (VNx2BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx2BImode))
	    emit_insn (gen_pred (IOR, VNx2BImode, operands[0],
				 CONSTM1_RTX (VNx2BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx2BImode, operands[0],
				 CONSTM1_RTX (VNx2BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx2qi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx2QImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx2BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx2BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (QImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (QImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx2qi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx2bi (operands[0], CONSTM1_RTX (VNx2BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx2BImode);
	      emit_insn (gen_pred_cmpvnx2qi_scalar (
		reg, CONSTM1_RTX (VNx2BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx2bi (operands[0], CONSTM1_RTX (VNx2BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx2qi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx2BImode, operands[0],
				   CONSTM1_RTX (VNx2BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx4qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx4BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx4BImode, operands[0], CONSTM1_RTX (VNx4BImode), undef,
			CONSTM1_RTX (VNx4BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx4BImode))
	    emit_insn (gen_pred (IOR, VNx4BImode, operands[0],
				 CONSTM1_RTX (VNx4BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx4BImode, operands[0],
				 CONSTM1_RTX (VNx4BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx4qi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx4QImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx4BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx4BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (QImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (QImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx4qi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx4bi (operands[0], CONSTM1_RTX (VNx4BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx4BImode);
	      emit_insn (gen_pred_cmpvnx4qi_scalar (
		reg, CONSTM1_RTX (VNx4BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx4bi (operands[0], CONSTM1_RTX (VNx4BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx4qi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx4BImode, operands[0],
				   CONSTM1_RTX (VNx4BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx8qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx8BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx8BImode, operands[0], CONSTM1_RTX (VNx8BImode), undef,
			CONSTM1_RTX (VNx8BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx8BImode))
	    emit_insn (gen_pred (IOR, VNx8BImode, operands[0],
				 CONSTM1_RTX (VNx8BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx8BImode, operands[0],
				 CONSTM1_RTX (VNx8BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx8qi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx8QImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx8BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx8BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (QImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (QImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx8qi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx8bi (operands[0], CONSTM1_RTX (VNx8BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx8BImode);
	      emit_insn (gen_pred_cmpvnx8qi_scalar (
		reg, CONSTM1_RTX (VNx8BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx8bi (operands[0], CONSTM1_RTX (VNx8BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx8qi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx8BImode, operands[0],
				   CONSTM1_RTX (VNx8BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx16qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx16BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx16BImode, operands[0], CONSTM1_RTX (VNx16BImode), undef,
			CONSTM1_RTX (VNx16BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx16BImode))
	    emit_insn (gen_pred (IOR, VNx16BImode, operands[0],
				 CONSTM1_RTX (VNx16BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx16BImode, operands[0],
				 CONSTM1_RTX (VNx16BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx16qi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx16QImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx16BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx16BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (QImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (QImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx16qi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx16bi (operands[0], CONSTM1_RTX (VNx16BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx16BImode);
	      emit_insn (gen_pred_cmpvnx16qi_scalar (
		reg, CONSTM1_RTX (VNx16BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx16bi (operands[0], CONSTM1_RTX (VNx16BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx16qi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx16BImode, operands[0],
				   CONSTM1_RTX (VNx16BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx32qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx32BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx32BImode, operands[0], CONSTM1_RTX (VNx32BImode), undef,
			CONSTM1_RTX (VNx32BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx32BImode))
	    emit_insn (gen_pred (IOR, VNx32BImode, operands[0],
				 CONSTM1_RTX (VNx32BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx32BImode, operands[0],
				 CONSTM1_RTX (VNx32BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx32qi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx32QImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx32BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx32BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (QImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (QImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx32qi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx32bi (operands[0], CONSTM1_RTX (VNx32BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx32BImode);
	      emit_insn (gen_pred_cmpvnx32qi_scalar (
		reg, CONSTM1_RTX (VNx32BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx32bi (operands[0], CONSTM1_RTX (VNx32BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx32qi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx32BImode, operands[0],
				   CONSTM1_RTX (VNx32BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx32BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx64qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx64BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx64BImode, operands[0], CONSTM1_RTX (VNx64BImode), undef,
			CONSTM1_RTX (VNx64BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx64BImode))
	    emit_insn (gen_pred (IOR, VNx64BImode, operands[0],
				 CONSTM1_RTX (VNx64BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx64BImode, operands[0],
				 CONSTM1_RTX (VNx64BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx64qi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx64QImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx64BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx64BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (QImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (QImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx64qi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx64bi (operands[0], CONSTM1_RTX (VNx64BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx64BImode);
	      emit_insn (gen_pred_cmpvnx64qi_scalar (
		reg, CONSTM1_RTX (VNx64BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx64bi (operands[0], CONSTM1_RTX (VNx64BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx64qi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx64BImode, operands[0],
				   CONSTM1_RTX (VNx64BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64BImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx64BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx1hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx1BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx1BImode, operands[0], CONSTM1_RTX (VNx1BImode), undef,
			CONSTM1_RTX (VNx1BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx1BImode))
	    emit_insn (gen_pred (IOR, VNx1BImode, operands[0],
				 CONSTM1_RTX (VNx1BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx1BImode, operands[0],
				 CONSTM1_RTX (VNx1BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx1hi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx1HImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx1BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx1BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (HImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (HImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx1hi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx1bi (operands[0], CONSTM1_RTX (VNx1BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx1BImode);
	      emit_insn (gen_pred_cmpvnx1hi_scalar (
		reg, CONSTM1_RTX (VNx1BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx1bi (operands[0], CONSTM1_RTX (VNx1BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx1hi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx1BImode, operands[0],
				   CONSTM1_RTX (VNx1BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx2hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx2BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx2BImode, operands[0], CONSTM1_RTX (VNx2BImode), undef,
			CONSTM1_RTX (VNx2BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx2BImode))
	    emit_insn (gen_pred (IOR, VNx2BImode, operands[0],
				 CONSTM1_RTX (VNx2BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx2BImode, operands[0],
				 CONSTM1_RTX (VNx2BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx2hi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx2HImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx2BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx2BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (HImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (HImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx2hi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx2bi (operands[0], CONSTM1_RTX (VNx2BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx2BImode);
	      emit_insn (gen_pred_cmpvnx2hi_scalar (
		reg, CONSTM1_RTX (VNx2BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx2bi (operands[0], CONSTM1_RTX (VNx2BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx2hi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx2BImode, operands[0],
				   CONSTM1_RTX (VNx2BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx4hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx4BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx4BImode, operands[0], CONSTM1_RTX (VNx4BImode), undef,
			CONSTM1_RTX (VNx4BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx4BImode))
	    emit_insn (gen_pred (IOR, VNx4BImode, operands[0],
				 CONSTM1_RTX (VNx4BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx4BImode, operands[0],
				 CONSTM1_RTX (VNx4BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx4hi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx4HImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx4BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx4BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (HImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (HImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx4hi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx4bi (operands[0], CONSTM1_RTX (VNx4BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx4BImode);
	      emit_insn (gen_pred_cmpvnx4hi_scalar (
		reg, CONSTM1_RTX (VNx4BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx4bi (operands[0], CONSTM1_RTX (VNx4BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx4hi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx4BImode, operands[0],
				   CONSTM1_RTX (VNx4BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx8hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx8BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx8BImode, operands[0], CONSTM1_RTX (VNx8BImode), undef,
			CONSTM1_RTX (VNx8BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx8BImode))
	    emit_insn (gen_pred (IOR, VNx8BImode, operands[0],
				 CONSTM1_RTX (VNx8BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx8BImode, operands[0],
				 CONSTM1_RTX (VNx8BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx8hi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx8HImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx8BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx8BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (HImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (HImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx8hi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx8bi (operands[0], CONSTM1_RTX (VNx8BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx8BImode);
	      emit_insn (gen_pred_cmpvnx8hi_scalar (
		reg, CONSTM1_RTX (VNx8BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx8bi (operands[0], CONSTM1_RTX (VNx8BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx8hi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx8BImode, operands[0],
				   CONSTM1_RTX (VNx8BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx16hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx16BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx16BImode, operands[0], CONSTM1_RTX (VNx16BImode), undef,
			CONSTM1_RTX (VNx16BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx16BImode))
	    emit_insn (gen_pred (IOR, VNx16BImode, operands[0],
				 CONSTM1_RTX (VNx16BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx16BImode, operands[0],
				 CONSTM1_RTX (VNx16BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx16hi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx16HImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx16BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx16BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (HImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (HImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx16hi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx16bi (operands[0], CONSTM1_RTX (VNx16BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx16BImode);
	      emit_insn (gen_pred_cmpvnx16hi_scalar (
		reg, CONSTM1_RTX (VNx16BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx16bi (operands[0], CONSTM1_RTX (VNx16BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx16hi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx16BImode, operands[0],
				   CONSTM1_RTX (VNx16BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx32hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx32BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx32BImode, operands[0], CONSTM1_RTX (VNx32BImode), undef,
			CONSTM1_RTX (VNx32BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx32BImode))
	    emit_insn (gen_pred (IOR, VNx32BImode, operands[0],
				 CONSTM1_RTX (VNx32BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx32BImode, operands[0],
				 CONSTM1_RTX (VNx32BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx32hi (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx32HImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx32BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx32BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (HImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (HImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx32hi_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx32bi (operands[0], CONSTM1_RTX (VNx32BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx32BImode);
	      emit_insn (gen_pred_cmpvnx32hi_scalar (
		reg, CONSTM1_RTX (VNx32BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx32bi (operands[0], CONSTM1_RTX (VNx32BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx32hi_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx32BImode, operands[0],
				   CONSTM1_RTX (VNx32BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32BImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx32BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx1si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx1BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx1BImode, operands[0], CONSTM1_RTX (VNx1BImode), undef,
			CONSTM1_RTX (VNx1BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx1BImode))
	    emit_insn (gen_pred (IOR, VNx1BImode, operands[0],
				 CONSTM1_RTX (VNx1BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx1BImode, operands[0],
				 CONSTM1_RTX (VNx1BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx1si (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx1SImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx1BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx1BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (SImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (SImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx1si_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx1bi (operands[0], CONSTM1_RTX (VNx1BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx1BImode);
	      emit_insn (gen_pred_cmpvnx1si_scalar (
		reg, CONSTM1_RTX (VNx1BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx1bi (operands[0], CONSTM1_RTX (VNx1BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx1si_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx1BImode, operands[0],
				   CONSTM1_RTX (VNx1BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx2si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx2BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx2BImode, operands[0], CONSTM1_RTX (VNx2BImode), undef,
			CONSTM1_RTX (VNx2BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx2BImode))
	    emit_insn (gen_pred (IOR, VNx2BImode, operands[0],
				 CONSTM1_RTX (VNx2BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx2BImode, operands[0],
				 CONSTM1_RTX (VNx2BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx2si (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx2SImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx2BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx2BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (SImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (SImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx2si_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx2bi (operands[0], CONSTM1_RTX (VNx2BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx2BImode);
	      emit_insn (gen_pred_cmpvnx2si_scalar (
		reg, CONSTM1_RTX (VNx2BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx2bi (operands[0], CONSTM1_RTX (VNx2BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx2si_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx2BImode, operands[0],
				   CONSTM1_RTX (VNx2BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx4si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx4BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx4BImode, operands[0], CONSTM1_RTX (VNx4BImode), undef,
			CONSTM1_RTX (VNx4BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx4BImode))
	    emit_insn (gen_pred (IOR, VNx4BImode, operands[0],
				 CONSTM1_RTX (VNx4BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx4BImode, operands[0],
				 CONSTM1_RTX (VNx4BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx4si (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx4SImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx4BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx4BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (SImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (SImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx4si_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx4bi (operands[0], CONSTM1_RTX (VNx4BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx4BImode);
	      emit_insn (gen_pred_cmpvnx4si_scalar (
		reg, CONSTM1_RTX (VNx4BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx4bi (operands[0], CONSTM1_RTX (VNx4BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx4si_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx4BImode, operands[0],
				   CONSTM1_RTX (VNx4BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx8si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx8BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx8BImode, operands[0], CONSTM1_RTX (VNx8BImode), undef,
			CONSTM1_RTX (VNx8BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx8BImode))
	    emit_insn (gen_pred (IOR, VNx8BImode, operands[0],
				 CONSTM1_RTX (VNx8BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx8BImode, operands[0],
				 CONSTM1_RTX (VNx8BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx8si (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx8SImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx8BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx8BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (SImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (SImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx8si_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx8bi (operands[0], CONSTM1_RTX (VNx8BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx8BImode);
	      emit_insn (gen_pred_cmpvnx8si_scalar (
		reg, CONSTM1_RTX (VNx8BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx8bi (operands[0], CONSTM1_RTX (VNx8BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx8si_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx8BImode, operands[0],
				   CONSTM1_RTX (VNx8BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx16si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx16BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx16BImode, operands[0], CONSTM1_RTX (VNx16BImode), undef,
			CONSTM1_RTX (VNx16BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx16BImode))
	    emit_insn (gen_pred (IOR, VNx16BImode, operands[0],
				 CONSTM1_RTX (VNx16BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx16BImode, operands[0],
				 CONSTM1_RTX (VNx16BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx16si (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx16SImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx16BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx16BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (SImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (SImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx16si_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx16bi (operands[0], CONSTM1_RTX (VNx16BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx16BImode);
	      emit_insn (gen_pred_cmpvnx16si_scalar (
		reg, CONSTM1_RTX (VNx16BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx16bi (operands[0], CONSTM1_RTX (VNx16BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx16si_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx16BImode, operands[0],
				   CONSTM1_RTX (VNx16BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx1BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx1BImode, operands[0], CONSTM1_RTX (VNx1BImode), undef,
			CONSTM1_RTX (VNx1BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx1BImode))
	    emit_insn (gen_pred (IOR, VNx1BImode, operands[0],
				 CONSTM1_RTX (VNx1BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx1BImode, operands[0],
				 CONSTM1_RTX (VNx1BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx1di (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx1DImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx1BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx1BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (DImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (DImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx1di_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx1bi (operands[0], CONSTM1_RTX (VNx1BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx1BImode);
	      emit_insn (gen_pred_cmpvnx1di_scalar (
		reg, CONSTM1_RTX (VNx1BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx1bi (operands[0], CONSTM1_RTX (VNx1BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx1di_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx1BImode, operands[0],
				   CONSTM1_RTX (VNx1BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx2BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx2BImode, operands[0], CONSTM1_RTX (VNx2BImode), undef,
			CONSTM1_RTX (VNx2BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx2BImode))
	    emit_insn (gen_pred (IOR, VNx2BImode, operands[0],
				 CONSTM1_RTX (VNx2BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx2BImode, operands[0],
				 CONSTM1_RTX (VNx2BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx2di (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx2DImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx2BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx2BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (DImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (DImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx2di_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx2bi (operands[0], CONSTM1_RTX (VNx2BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx2BImode);
	      emit_insn (gen_pred_cmpvnx2di_scalar (
		reg, CONSTM1_RTX (VNx2BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx2bi (operands[0], CONSTM1_RTX (VNx2BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx2di_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx2BImode, operands[0],
				   CONSTM1_RTX (VNx2BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx4BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx4BImode, operands[0], CONSTM1_RTX (VNx4BImode), undef,
			CONSTM1_RTX (VNx4BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx4BImode))
	    emit_insn (gen_pred (IOR, VNx4BImode, operands[0],
				 CONSTM1_RTX (VNx4BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx4BImode, operands[0],
				 CONSTM1_RTX (VNx4BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx4di (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx4DImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx4BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx4BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (DImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (DImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx4di_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx4bi (operands[0], CONSTM1_RTX (VNx4BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx4BImode);
	      emit_insn (gen_pred_cmpvnx4di_scalar (
		reg, CONSTM1_RTX (VNx4BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx4bi (operands[0], CONSTM1_RTX (VNx4BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx4di_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx4BImode, operands[0],
				   CONSTM1_RTX (VNx4BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
rtx
gen_pred_gevnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4107 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  enum rtx_code code = GET_CODE (operands[3]);
  rtx undef = RVV_VUNDEF (VNx8BImode);
  if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
    {
      /* If vmsgeu with 0 immediate, expand it to vmset.  */
      if (satisfies_constraint_Wc1 (operands[1]))
	emit_insn (
	  gen_pred_mov (VNx8BImode, operands[0], CONSTM1_RTX (VNx8BImode), undef,
			CONSTM1_RTX (VNx8BImode), operands[6], operands[8]));
      else
	{
	  /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
	   */
	  if (rtx_equal_p (operands[1], operands[2]))
	    emit_move_insn (operands[0], operands[1]);
	  else if (register_operand (operands[2], VNx8BImode))
	    emit_insn (gen_pred (IOR, VNx8BImode, operands[0],
				 CONSTM1_RTX (VNx8BImode), undef, operands[1],
				 operands[2], operands[6], operands[8]));
	  else
	    emit_insn (gen_pred (IOR, VNx8BImode, operands[0],
				 CONSTM1_RTX (VNx8BImode), undef, operands[1],
				 operands[1], operands[6], operands[8]));
	}
    }
  else if (riscv_vector::neg_simm5_p (operands[5]))
    emit_insn (
      gen_pred_ltgevnx8di (operands[0], operands[1], operands[2], operands[3],
			   operands[4],
			   gen_const_vec_duplicate (VNx8DImode, operands[5]),
			   operands[6], operands[7], operands[8]));
  else
    {
      if (code == GE)
	operands[3] = gen_rtx_fmt_ee (LT, VNx8BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      else
	operands[3] = gen_rtx_fmt_ee (LTU, VNx8BImode, XEXP (operands[3], 0),
				      XEXP (operands[3], 1));
      if (GET_MODE_BITSIZE (DImode) <= GET_MODE_BITSIZE (Pmode))
	operands[5] = force_reg (DImode, operands[5]);

      if (satisfies_constraint_Wc1 (operands[1]))
	{
	  /* unmasked va >= x
	    - pseudoinstruction: vmsge{u}.vx vd, va, x
	    - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd.  */
	  emit_insn (
	    gen_pred_cmpvnx8di_scalar (operands[0], operands[1], operands[2],
					operands[3], operands[4], operands[5],
					operands[6], operands[7], operands[8]));
	  emit_insn (gen_pred_nandvnx8bi (operands[0], CONSTM1_RTX (VNx8BImode),
					undef, operands[0], operands[0],
					operands[6], operands[8]));
	}
      else
	{
	  if (rtx_equal_p (operands[1], operands[2]))
	    {
	      /* masked va >= x, vd == v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
		- expansion: vmslt{u}.vx vt, va, x;  vmandn.mm vd, vd, vt.  */
	      rtx reg = gen_reg_rtx (VNx8BImode);
	      emit_insn (gen_pred_cmpvnx8di_scalar (
		reg, CONSTM1_RTX (VNx8BImode), undef, operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (
		gen_pred_andnotvnx8bi (operands[0], CONSTM1_RTX (VNx8BImode), undef,
				   operands[1], reg, operands[6], operands[8]));
	    }
	  else
	    {
	      /* masked va >= x, vd != v0
		- pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
		- expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
	      */
	      emit_insn (gen_pred_cmpvnx8di_scalar (
		operands[0], operands[1], operands[2], operands[3], operands[4],
		operands[5], operands[6], operands[7], operands[8]));
	      emit_insn (gen_pred (XOR, VNx8BImode, operands[0],
				   CONSTM1_RTX (VNx8BImode), undef, operands[0],
				   operands[1], operands[6], operands[8]));
	    }
	}
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx1qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1QImode,
	gen_rtx_MULT (VNx1QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx2qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2QImode,
	gen_rtx_MULT (VNx2QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx4qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4QImode,
	gen_rtx_MULT (VNx4QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8QImode,
	gen_rtx_MULT (VNx8QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16QImode,
	gen_rtx_MULT (VNx16QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx32qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32QImode,
	gen_rtx_MULT (VNx32QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx64qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx64QImode,
	gen_rtx_MULT (VNx64QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx1hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_MULT (VNx1HImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx2hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_MULT (VNx2HImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_MULT (VNx4HImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_MULT (VNx8HImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx16hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_MULT (VNx16HImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx32hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_MULT (VNx32HImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx1si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_MULT (VNx1SImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_MULT (VNx2SImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_MULT (VNx4SImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx8si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_MULT (VNx8SImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx16si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_MULT (VNx16SImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx1di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_MULT (VNx1DImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_MULT (VNx2DImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx4di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_MULT (VNx4DImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
rtx
gen_pred_mul_plusvnx8di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4221 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_MULT (VNx8DImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_248 (rtx_insn *, rtx *);
rtx_insn *
gen_split_248 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_248 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx1qi (operands[0], RVV_VUNDEF (VNx1QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1qi (operands[0], RVV_VUNDEF (VNx1QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1QImode,
	gen_rtx_MULT (VNx1QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_249 (rtx_insn *, rtx *);
rtx_insn *
gen_split_249 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_249 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx2qi (operands[0], RVV_VUNDEF (VNx2QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2qi (operands[0], RVV_VUNDEF (VNx2QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2QImode,
	gen_rtx_MULT (VNx2QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_250 (rtx_insn *, rtx *);
rtx_insn *
gen_split_250 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_250 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx4qi (operands[0], RVV_VUNDEF (VNx4QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4qi (operands[0], RVV_VUNDEF (VNx4QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4QImode,
	gen_rtx_MULT (VNx4QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_251 (rtx_insn *, rtx *);
rtx_insn *
gen_split_251 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_251 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx8qi (operands[0], RVV_VUNDEF (VNx8QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8qi (operands[0], RVV_VUNDEF (VNx8QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8QImode,
	gen_rtx_MULT (VNx8QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_252 (rtx_insn *, rtx *);
rtx_insn *
gen_split_252 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_252 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx16qi (operands[0], RVV_VUNDEF (VNx16QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx16qi (operands[0], RVV_VUNDEF (VNx16QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16QImode,
	gen_rtx_MULT (VNx16QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_253 (rtx_insn *, rtx *);
rtx_insn *
gen_split_253 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_253 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx32qi (operands[0], RVV_VUNDEF (VNx32QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx32qi (operands[0], RVV_VUNDEF (VNx32QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32QImode,
	gen_rtx_MULT (VNx32QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_254 (rtx_insn *, rtx *);
rtx_insn *
gen_split_254 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_254 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx64qi (operands[0], RVV_VUNDEF (VNx64QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx64qi (operands[0], RVV_VUNDEF (VNx64QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx64QImode,
	gen_rtx_MULT (VNx64QImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_255 (rtx_insn *, rtx *);
rtx_insn *
gen_split_255 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_255 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx1hi (operands[0], RVV_VUNDEF (VNx1HImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1hi (operands[0], RVV_VUNDEF (VNx1HImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_MULT (VNx1HImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_256 (rtx_insn *, rtx *);
rtx_insn *
gen_split_256 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_256 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx2hi (operands[0], RVV_VUNDEF (VNx2HImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2hi (operands[0], RVV_VUNDEF (VNx2HImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_MULT (VNx2HImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_257 (rtx_insn *, rtx *);
rtx_insn *
gen_split_257 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_257 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx4hi (operands[0], RVV_VUNDEF (VNx4HImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4hi (operands[0], RVV_VUNDEF (VNx4HImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_MULT (VNx4HImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_258 (rtx_insn *, rtx *);
rtx_insn *
gen_split_258 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_258 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx8hi (operands[0], RVV_VUNDEF (VNx8HImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8hi (operands[0], RVV_VUNDEF (VNx8HImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_MULT (VNx8HImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_259 (rtx_insn *, rtx *);
rtx_insn *
gen_split_259 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_259 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx16hi (operands[0], RVV_VUNDEF (VNx16HImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx16hi (operands[0], RVV_VUNDEF (VNx16HImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_MULT (VNx16HImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_260 (rtx_insn *, rtx *);
rtx_insn *
gen_split_260 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_260 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx32hi (operands[0], RVV_VUNDEF (VNx32HImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx32hi (operands[0], RVV_VUNDEF (VNx32HImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_MULT (VNx32HImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_261 (rtx_insn *, rtx *);
rtx_insn *
gen_split_261 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_261 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx1si (operands[0], RVV_VUNDEF (VNx1SImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1si (operands[0], RVV_VUNDEF (VNx1SImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_MULT (VNx1SImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_262 (rtx_insn *, rtx *);
rtx_insn *
gen_split_262 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_262 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx2si (operands[0], RVV_VUNDEF (VNx2SImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2si (operands[0], RVV_VUNDEF (VNx2SImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_MULT (VNx2SImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_263 (rtx_insn *, rtx *);
rtx_insn *
gen_split_263 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_263 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx4si (operands[0], RVV_VUNDEF (VNx4SImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4si (operands[0], RVV_VUNDEF (VNx4SImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_MULT (VNx4SImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_264 (rtx_insn *, rtx *);
rtx_insn *
gen_split_264 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_264 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx8si (operands[0], RVV_VUNDEF (VNx8SImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8si (operands[0], RVV_VUNDEF (VNx8SImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_MULT (VNx8SImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_265 (rtx_insn *, rtx *);
rtx_insn *
gen_split_265 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_265 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx16si (operands[0], RVV_VUNDEF (VNx16SImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx16si (operands[0], RVV_VUNDEF (VNx16SImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_MULT (VNx16SImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_266 (rtx_insn *, rtx *);
rtx_insn *
gen_split_266 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_266 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx1di (operands[0], RVV_VUNDEF (VNx1DImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1di (operands[0], RVV_VUNDEF (VNx1DImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_MULT (VNx1DImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_267 (rtx_insn *, rtx *);
rtx_insn *
gen_split_267 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_267 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx2di (operands[0], RVV_VUNDEF (VNx2DImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2di (operands[0], RVV_VUNDEF (VNx2DImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_MULT (VNx2DImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_268 (rtx_insn *, rtx *);
rtx_insn *
gen_split_268 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_268 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx4di (operands[0], RVV_VUNDEF (VNx4DImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4di (operands[0], RVV_VUNDEF (VNx4DImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_MULT (VNx4DImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
extern rtx_insn *gen_split_269 (rtx_insn *, rtx *);
rtx_insn *
gen_split_269 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_269 (vector.md:4290)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4319 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx8di (operands[0], RVV_VUNDEF (VNx8DImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8di (operands[0], RVV_VUNDEF (VNx8DImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_MULT (VNx8DImode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx1qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1QImode,
	gen_rtx_MULT (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx2qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2QImode,
	gen_rtx_MULT (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx4qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4QImode,
	gen_rtx_MULT (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx8qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8QImode,
	gen_rtx_MULT (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx16qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16QImode,
	gen_rtx_MULT (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx32qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32QImode,
	gen_rtx_MULT (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx64qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx64QImode,
	gen_rtx_MULT (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx1hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (HImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx2hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (HImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx4hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (HImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx8hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (HImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx16hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (HImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx32hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (HImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx1si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (SImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx2si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (SImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx4si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (SImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx8si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (SImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
rtx
gen_pred_mul_plusvnx16si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (SImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_270 (rtx_insn *, rtx *);
rtx_insn *
gen_split_270 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_270 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx1qi (operands[0], RVV_VUNDEF (VNx1QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1qi (operands[0], RVV_VUNDEF (VNx1QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1QImode,
	gen_rtx_MULT (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_271 (rtx_insn *, rtx *);
rtx_insn *
gen_split_271 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_271 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx2qi (operands[0], RVV_VUNDEF (VNx2QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2qi (operands[0], RVV_VUNDEF (VNx2QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2QImode,
	gen_rtx_MULT (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_272 (rtx_insn *, rtx *);
rtx_insn *
gen_split_272 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_272 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx4qi (operands[0], RVV_VUNDEF (VNx4QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4qi (operands[0], RVV_VUNDEF (VNx4QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4QImode,
	gen_rtx_MULT (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_273 (rtx_insn *, rtx *);
rtx_insn *
gen_split_273 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_273 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx8qi (operands[0], RVV_VUNDEF (VNx8QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8qi (operands[0], RVV_VUNDEF (VNx8QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8QImode,
	gen_rtx_MULT (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_274 (rtx_insn *, rtx *);
rtx_insn *
gen_split_274 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_274 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx16qi (operands[0], RVV_VUNDEF (VNx16QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx16qi (operands[0], RVV_VUNDEF (VNx16QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16QImode,
	gen_rtx_MULT (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_275 (rtx_insn *, rtx *);
rtx_insn *
gen_split_275 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_275 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx32qi (operands[0], RVV_VUNDEF (VNx32QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx32qi (operands[0], RVV_VUNDEF (VNx32QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32QImode,
	gen_rtx_MULT (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_276 (rtx_insn *, rtx *);
rtx_insn *
gen_split_276 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_276 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx64qi (operands[0], RVV_VUNDEF (VNx64QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx64qi (operands[0], RVV_VUNDEF (VNx64QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx64QImode,
	gen_rtx_MULT (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_277 (rtx_insn *, rtx *);
rtx_insn *
gen_split_277 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_277 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx1hi (operands[0], RVV_VUNDEF (VNx1HImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1hi (operands[0], RVV_VUNDEF (VNx1HImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1HImode,
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_278 (rtx_insn *, rtx *);
rtx_insn *
gen_split_278 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_278 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx2hi (operands[0], RVV_VUNDEF (VNx2HImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2hi (operands[0], RVV_VUNDEF (VNx2HImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2HImode,
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_279 (rtx_insn *, rtx *);
rtx_insn *
gen_split_279 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_279 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx4hi (operands[0], RVV_VUNDEF (VNx4HImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4hi (operands[0], RVV_VUNDEF (VNx4HImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4HImode,
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_280 (rtx_insn *, rtx *);
rtx_insn *
gen_split_280 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_280 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx8hi (operands[0], RVV_VUNDEF (VNx8HImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8hi (operands[0], RVV_VUNDEF (VNx8HImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8HImode,
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_281 (rtx_insn *, rtx *);
rtx_insn *
gen_split_281 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_281 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx16hi (operands[0], RVV_VUNDEF (VNx16HImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx16hi (operands[0], RVV_VUNDEF (VNx16HImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16HImode,
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_282 (rtx_insn *, rtx *);
rtx_insn *
gen_split_282 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_282 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx32hi (operands[0], RVV_VUNDEF (VNx32HImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx32hi (operands[0], RVV_VUNDEF (VNx32HImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx32HImode,
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_283 (rtx_insn *, rtx *);
rtx_insn *
gen_split_283 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_283 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx1si (operands[0], RVV_VUNDEF (VNx1SImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1si (operands[0], RVV_VUNDEF (VNx1SImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SImode,
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_284 (rtx_insn *, rtx *);
rtx_insn *
gen_split_284 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_284 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx2si (operands[0], RVV_VUNDEF (VNx2SImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2si (operands[0], RVV_VUNDEF (VNx2SImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SImode,
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_285 (rtx_insn *, rtx *);
rtx_insn *
gen_split_285 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_285 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx4si (operands[0], RVV_VUNDEF (VNx4SImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4si (operands[0], RVV_VUNDEF (VNx4SImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SImode,
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_286 (rtx_insn *, rtx *);
rtx_insn *
gen_split_286 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_286 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx8si (operands[0], RVV_VUNDEF (VNx8SImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8si (operands[0], RVV_VUNDEF (VNx8SImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SImode,
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_287 (rtx_insn *, rtx *);
rtx_insn *
gen_split_287 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_287 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx16si (operands[0], RVV_VUNDEF (VNx16SImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx16si (operands[0], RVV_VUNDEF (VNx16SImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SImode,
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_288 (rtx_insn *, rtx *);
rtx_insn *
gen_split_288 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_288 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx1di (operands[0], RVV_VUNDEF (VNx1DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1di (operands[0], RVV_VUNDEF (VNx1DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_289 (rtx_insn *, rtx *);
rtx_insn *
gen_split_289 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_289 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx2di (operands[0], RVV_VUNDEF (VNx2DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2di (operands[0], RVV_VUNDEF (VNx2DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_290 (rtx_insn *, rtx *);
rtx_insn *
gen_split_290 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_290 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx4di (operands[0], RVV_VUNDEF (VNx4DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4di (operands[0], RVV_VUNDEF (VNx4DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
extern rtx_insn *gen_split_291 (rtx_insn *, rtx *);
rtx_insn *
gen_split_291 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_291 (vector.md:4428)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4456 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx8di (operands[0], RVV_VUNDEF (VNx8DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8di (operands[0], RVV_VUNDEF (VNx8DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4475 */
rtx
gen_pred_mul_plusvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[6],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mul_plusvnx1di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5],
	       operands[6], operands[7], operands[8], operands[9]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4475 */
rtx
gen_pred_mul_plusvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[6],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mul_plusvnx2di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5],
	       operands[6], operands[7], operands[8], operands[9]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4475 */
rtx
gen_pred_mul_plusvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[6],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mul_plusvnx4di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5],
	       operands[6], operands[7], operands[8], operands[9]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4475 */
rtx
gen_pred_mul_plusvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4494 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[6],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_mul_plusvnx8di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5],
	       operands[6], operands[7], operands[8], operands[9]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4576 */
extern rtx_insn *gen_split_292 (rtx_insn *, rtx *);
rtx_insn *
gen_split_292 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_292 (vector.md:4576)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx1di (operands[0], RVV_VUNDEF (VNx1DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1di (operands[0], RVV_VUNDEF (VNx1DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DImode,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4576 */
extern rtx_insn *gen_split_293 (rtx_insn *, rtx *);
rtx_insn *
gen_split_293 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_293 (vector.md:4576)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx2di (operands[0], RVV_VUNDEF (VNx2DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2di (operands[0], RVV_VUNDEF (VNx2DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DImode,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4576 */
extern rtx_insn *gen_split_294 (rtx_insn *, rtx *);
rtx_insn *
gen_split_294 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_294 (vector.md:4576)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx4di (operands[0], RVV_VUNDEF (VNx4DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4di (operands[0], RVV_VUNDEF (VNx4DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DImode,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4576 */
extern rtx_insn *gen_split_295 (rtx_insn *, rtx *);
rtx_insn *
gen_split_295 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_295 (vector.md:4576)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4605 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx8di (operands[0], RVV_VUNDEF (VNx8DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8di (operands[0], RVV_VUNDEF (VNx8DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DImode,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx1qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1QImode,
	operand4,
	gen_rtx_MULT (VNx1QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx2qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2QImode,
	operand4,
	gen_rtx_MULT (VNx2QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx4qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4QImode,
	operand4,
	gen_rtx_MULT (VNx4QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8QImode,
	operand4,
	gen_rtx_MULT (VNx8QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16QImode,
	operand4,
	gen_rtx_MULT (VNx16QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx32qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32QImode,
	operand4,
	gen_rtx_MULT (VNx32QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx64qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx64QImode,
	operand4,
	gen_rtx_MULT (VNx64QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx1hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	operand4,
	gen_rtx_MULT (VNx1HImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx2hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	operand4,
	gen_rtx_MULT (VNx2HImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	operand4,
	gen_rtx_MULT (VNx4HImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	operand4,
	gen_rtx_MULT (VNx8HImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx16hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	operand4,
	gen_rtx_MULT (VNx16HImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx32hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	operand4,
	gen_rtx_MULT (VNx32HImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx1si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	operand4,
	gen_rtx_MULT (VNx1SImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	operand4,
	gen_rtx_MULT (VNx2SImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	operand4,
	gen_rtx_MULT (VNx4SImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx8si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	operand4,
	gen_rtx_MULT (VNx8SImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx16si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	operand4,
	gen_rtx_MULT (VNx16SImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx1di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	operand4,
	gen_rtx_MULT (VNx1DImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	operand4,
	gen_rtx_MULT (VNx2DImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx4di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	operand4,
	gen_rtx_MULT (VNx4DImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
rtx
gen_pred_minus_mulvnx8di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4642 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	operand4,
	gen_rtx_MULT (VNx8DImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_296 (rtx_insn *, rtx *);
rtx_insn *
gen_split_296 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_296 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx1qi (operands[0], RVV_VUNDEF (VNx1QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1qi (operands[0], RVV_VUNDEF (VNx1QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1QImode,
	operand4,
	gen_rtx_MULT (VNx1QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_297 (rtx_insn *, rtx *);
rtx_insn *
gen_split_297 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_297 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx2qi (operands[0], RVV_VUNDEF (VNx2QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2qi (operands[0], RVV_VUNDEF (VNx2QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2QImode,
	operand4,
	gen_rtx_MULT (VNx2QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_298 (rtx_insn *, rtx *);
rtx_insn *
gen_split_298 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_298 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx4qi (operands[0], RVV_VUNDEF (VNx4QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4qi (operands[0], RVV_VUNDEF (VNx4QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4QImode,
	operand4,
	gen_rtx_MULT (VNx4QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_299 (rtx_insn *, rtx *);
rtx_insn *
gen_split_299 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_299 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx8qi (operands[0], RVV_VUNDEF (VNx8QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8qi (operands[0], RVV_VUNDEF (VNx8QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8QImode,
	operand4,
	gen_rtx_MULT (VNx8QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_300 (rtx_insn *, rtx *);
rtx_insn *
gen_split_300 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_300 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx16qi (operands[0], RVV_VUNDEF (VNx16QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx16qi (operands[0], RVV_VUNDEF (VNx16QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16QImode,
	operand4,
	gen_rtx_MULT (VNx16QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_301 (rtx_insn *, rtx *);
rtx_insn *
gen_split_301 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_301 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx32qi (operands[0], RVV_VUNDEF (VNx32QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx32qi (operands[0], RVV_VUNDEF (VNx32QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32QImode,
	operand4,
	gen_rtx_MULT (VNx32QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_302 (rtx_insn *, rtx *);
rtx_insn *
gen_split_302 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_302 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx64qi (operands[0], RVV_VUNDEF (VNx64QImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx64qi (operands[0], RVV_VUNDEF (VNx64QImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx64QImode,
	operand4,
	gen_rtx_MULT (VNx64QImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_303 (rtx_insn *, rtx *);
rtx_insn *
gen_split_303 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_303 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx1hi (operands[0], RVV_VUNDEF (VNx1HImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1hi (operands[0], RVV_VUNDEF (VNx1HImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	operand4,
	gen_rtx_MULT (VNx1HImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_304 (rtx_insn *, rtx *);
rtx_insn *
gen_split_304 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_304 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx2hi (operands[0], RVV_VUNDEF (VNx2HImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2hi (operands[0], RVV_VUNDEF (VNx2HImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	operand4,
	gen_rtx_MULT (VNx2HImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_305 (rtx_insn *, rtx *);
rtx_insn *
gen_split_305 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_305 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx4hi (operands[0], RVV_VUNDEF (VNx4HImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4hi (operands[0], RVV_VUNDEF (VNx4HImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	operand4,
	gen_rtx_MULT (VNx4HImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_306 (rtx_insn *, rtx *);
rtx_insn *
gen_split_306 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_306 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx8hi (operands[0], RVV_VUNDEF (VNx8HImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8hi (operands[0], RVV_VUNDEF (VNx8HImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	operand4,
	gen_rtx_MULT (VNx8HImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_307 (rtx_insn *, rtx *);
rtx_insn *
gen_split_307 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_307 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx16hi (operands[0], RVV_VUNDEF (VNx16HImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx16hi (operands[0], RVV_VUNDEF (VNx16HImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	operand4,
	gen_rtx_MULT (VNx16HImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_308 (rtx_insn *, rtx *);
rtx_insn *
gen_split_308 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_308 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx32hi (operands[0], RVV_VUNDEF (VNx32HImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx32hi (operands[0], RVV_VUNDEF (VNx32HImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	operand4,
	gen_rtx_MULT (VNx32HImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_309 (rtx_insn *, rtx *);
rtx_insn *
gen_split_309 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_309 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx1si (operands[0], RVV_VUNDEF (VNx1SImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1si (operands[0], RVV_VUNDEF (VNx1SImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	operand4,
	gen_rtx_MULT (VNx1SImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_310 (rtx_insn *, rtx *);
rtx_insn *
gen_split_310 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_310 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx2si (operands[0], RVV_VUNDEF (VNx2SImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2si (operands[0], RVV_VUNDEF (VNx2SImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	operand4,
	gen_rtx_MULT (VNx2SImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_311 (rtx_insn *, rtx *);
rtx_insn *
gen_split_311 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_311 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx4si (operands[0], RVV_VUNDEF (VNx4SImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4si (operands[0], RVV_VUNDEF (VNx4SImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	operand4,
	gen_rtx_MULT (VNx4SImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_312 (rtx_insn *, rtx *);
rtx_insn *
gen_split_312 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_312 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx8si (operands[0], RVV_VUNDEF (VNx8SImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8si (operands[0], RVV_VUNDEF (VNx8SImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	operand4,
	gen_rtx_MULT (VNx8SImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_313 (rtx_insn *, rtx *);
rtx_insn *
gen_split_313 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_313 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx16si (operands[0], RVV_VUNDEF (VNx16SImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx16si (operands[0], RVV_VUNDEF (VNx16SImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	operand4,
	gen_rtx_MULT (VNx16SImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_314 (rtx_insn *, rtx *);
rtx_insn *
gen_split_314 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_314 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx1di (operands[0], RVV_VUNDEF (VNx1DImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1di (operands[0], RVV_VUNDEF (VNx1DImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	operand4,
	gen_rtx_MULT (VNx1DImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_315 (rtx_insn *, rtx *);
rtx_insn *
gen_split_315 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_315 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx2di (operands[0], RVV_VUNDEF (VNx2DImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2di (operands[0], RVV_VUNDEF (VNx2DImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	operand4,
	gen_rtx_MULT (VNx2DImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_316 (rtx_insn *, rtx *);
rtx_insn *
gen_split_316 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_316 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx4di (operands[0], RVV_VUNDEF (VNx4DImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4di (operands[0], RVV_VUNDEF (VNx4DImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	operand4,
	gen_rtx_MULT (VNx4DImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
extern rtx_insn *gen_split_317 (rtx_insn *, rtx *);
rtx_insn *
gen_split_317 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_317 (vector.md:4711)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4740 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      std::swap (operands[2], operands[3]);

    if (satisfies_constraint_vi (operands[2]))
      {
        emit_insn (gen_pred_mergevnx8di (operands[0], RVV_VUNDEF (VNx8DImode),
                	operands[5], operands[2], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[2] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8di (operands[0], RVV_VUNDEF (VNx8DImode),
                	operands[5], operands[4], operands[1], operands[6], 
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	operand4,
	gen_rtx_MULT (VNx8DImode,
	operand2,
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx1qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1QImode,
	operand4,
	gen_rtx_MULT (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx2qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2QImode,
	operand4,
	gen_rtx_MULT (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx4qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4QImode,
	operand4,
	gen_rtx_MULT (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx8qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8QImode,
	operand4,
	gen_rtx_MULT (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx16qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16QImode,
	operand4,
	gen_rtx_MULT (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx32qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32QImode,
	operand4,
	gen_rtx_MULT (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx64qi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (QImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx64QImode,
	operand4,
	gen_rtx_MULT (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx1hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (HImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	operand4,
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx2hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (HImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	operand4,
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx4hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (HImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	operand4,
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx8hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (HImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	operand4,
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx16hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (HImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	operand4,
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx32hi_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (HImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	operand4,
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx1si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (SImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	operand4,
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx2si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (SImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	operand4,
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx4si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (SImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	operand4,
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx8si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (SImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	operand4,
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
rtx
gen_pred_minus_mulvnx16si_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4781 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  operands[2] = force_reg (SImode, operands[2]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	operand4,
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_318 (rtx_insn *, rtx *);
rtx_insn *
gen_split_318 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_318 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx1qi (operands[0], RVV_VUNDEF (VNx1QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1qi (operands[0], RVV_VUNDEF (VNx1QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1QImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1QImode,
	operand4,
	gen_rtx_MULT (VNx1QImode,
	gen_rtx_VEC_DUPLICATE (VNx1QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_319 (rtx_insn *, rtx *);
rtx_insn *
gen_split_319 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_319 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx2qi (operands[0], RVV_VUNDEF (VNx2QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2qi (operands[0], RVV_VUNDEF (VNx2QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2QImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2QImode,
	operand4,
	gen_rtx_MULT (VNx2QImode,
	gen_rtx_VEC_DUPLICATE (VNx2QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_320 (rtx_insn *, rtx *);
rtx_insn *
gen_split_320 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_320 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx4qi (operands[0], RVV_VUNDEF (VNx4QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4qi (operands[0], RVV_VUNDEF (VNx4QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4QImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4QImode,
	operand4,
	gen_rtx_MULT (VNx4QImode,
	gen_rtx_VEC_DUPLICATE (VNx4QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_321 (rtx_insn *, rtx *);
rtx_insn *
gen_split_321 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_321 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx8qi (operands[0], RVV_VUNDEF (VNx8QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8qi (operands[0], RVV_VUNDEF (VNx8QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8QImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8QImode,
	operand4,
	gen_rtx_MULT (VNx8QImode,
	gen_rtx_VEC_DUPLICATE (VNx8QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_322 (rtx_insn *, rtx *);
rtx_insn *
gen_split_322 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_322 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx16qi (operands[0], RVV_VUNDEF (VNx16QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx16qi (operands[0], RVV_VUNDEF (VNx16QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16QImode,
	operand4,
	gen_rtx_MULT (VNx16QImode,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_323 (rtx_insn *, rtx *);
rtx_insn *
gen_split_323 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_323 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx32qi (operands[0], RVV_VUNDEF (VNx32QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx32qi (operands[0], RVV_VUNDEF (VNx32QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32QImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32QImode,
	operand4,
	gen_rtx_MULT (VNx32QImode,
	gen_rtx_VEC_DUPLICATE (VNx32QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_324 (rtx_insn *, rtx *);
rtx_insn *
gen_split_324 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_324 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx64qi (operands[0], RVV_VUNDEF (VNx64QImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx64qi (operands[0], RVV_VUNDEF (VNx64QImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx64QImode,
	gen_rtx_UNSPEC (VNx64BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx64QImode,
	operand4,
	gen_rtx_MULT (VNx64QImode,
	gen_rtx_VEC_DUPLICATE (VNx64QImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_325 (rtx_insn *, rtx *);
rtx_insn *
gen_split_325 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_325 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx1hi (operands[0], RVV_VUNDEF (VNx1HImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1hi (operands[0], RVV_VUNDEF (VNx1HImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1HImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1HImode,
	operand4,
	gen_rtx_MULT (VNx1HImode,
	gen_rtx_VEC_DUPLICATE (VNx1HImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_326 (rtx_insn *, rtx *);
rtx_insn *
gen_split_326 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_326 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx2hi (operands[0], RVV_VUNDEF (VNx2HImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2hi (operands[0], RVV_VUNDEF (VNx2HImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2HImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2HImode,
	operand4,
	gen_rtx_MULT (VNx2HImode,
	gen_rtx_VEC_DUPLICATE (VNx2HImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_327 (rtx_insn *, rtx *);
rtx_insn *
gen_split_327 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_327 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx4hi (operands[0], RVV_VUNDEF (VNx4HImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4hi (operands[0], RVV_VUNDEF (VNx4HImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4HImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4HImode,
	operand4,
	gen_rtx_MULT (VNx4HImode,
	gen_rtx_VEC_DUPLICATE (VNx4HImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_328 (rtx_insn *, rtx *);
rtx_insn *
gen_split_328 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_328 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx8hi (operands[0], RVV_VUNDEF (VNx8HImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8hi (operands[0], RVV_VUNDEF (VNx8HImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8HImode,
	operand4,
	gen_rtx_MULT (VNx8HImode,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_329 (rtx_insn *, rtx *);
rtx_insn *
gen_split_329 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_329 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx16hi (operands[0], RVV_VUNDEF (VNx16HImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx16hi (operands[0], RVV_VUNDEF (VNx16HImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16HImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16HImode,
	operand4,
	gen_rtx_MULT (VNx16HImode,
	gen_rtx_VEC_DUPLICATE (VNx16HImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_330 (rtx_insn *, rtx *);
rtx_insn *
gen_split_330 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_330 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx32hi (operands[0], RVV_VUNDEF (VNx32HImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx32hi (operands[0], RVV_VUNDEF (VNx32HImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx32HImode,
	gen_rtx_UNSPEC (VNx32BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx32HImode,
	operand4,
	gen_rtx_MULT (VNx32HImode,
	gen_rtx_VEC_DUPLICATE (VNx32HImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_331 (rtx_insn *, rtx *);
rtx_insn *
gen_split_331 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_331 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx1si (operands[0], RVV_VUNDEF (VNx1SImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1si (operands[0], RVV_VUNDEF (VNx1SImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SImode,
	operand4,
	gen_rtx_MULT (VNx1SImode,
	gen_rtx_VEC_DUPLICATE (VNx1SImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_332 (rtx_insn *, rtx *);
rtx_insn *
gen_split_332 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_332 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx2si (operands[0], RVV_VUNDEF (VNx2SImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2si (operands[0], RVV_VUNDEF (VNx2SImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SImode,
	operand4,
	gen_rtx_MULT (VNx2SImode,
	gen_rtx_VEC_DUPLICATE (VNx2SImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_333 (rtx_insn *, rtx *);
rtx_insn *
gen_split_333 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_333 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx4si (operands[0], RVV_VUNDEF (VNx4SImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4si (operands[0], RVV_VUNDEF (VNx4SImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SImode,
	operand4,
	gen_rtx_MULT (VNx4SImode,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_334 (rtx_insn *, rtx *);
rtx_insn *
gen_split_334 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_334 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx8si (operands[0], RVV_VUNDEF (VNx8SImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8si (operands[0], RVV_VUNDEF (VNx8SImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SImode,
	operand4,
	gen_rtx_MULT (VNx8SImode,
	gen_rtx_VEC_DUPLICATE (VNx8SImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_335 (rtx_insn *, rtx *);
rtx_insn *
gen_split_335 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_335 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx16si (operands[0], RVV_VUNDEF (VNx16SImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx16si (operands[0], RVV_VUNDEF (VNx16SImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SImode,
	operand4,
	gen_rtx_MULT (VNx16SImode,
	gen_rtx_VEC_DUPLICATE (VNx16SImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_336 (rtx_insn *, rtx *);
rtx_insn *
gen_split_336 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_336 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx1di (operands[0], RVV_VUNDEF (VNx1DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1di (operands[0], RVV_VUNDEF (VNx1DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	operand4,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_337 (rtx_insn *, rtx *);
rtx_insn *
gen_split_337 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_337 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx2di (operands[0], RVV_VUNDEF (VNx2DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2di (operands[0], RVV_VUNDEF (VNx2DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	operand4,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_338 (rtx_insn *, rtx *);
rtx_insn *
gen_split_338 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_338 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx4di (operands[0], RVV_VUNDEF (VNx4DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4di (operands[0], RVV_VUNDEF (VNx4DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	operand4,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
extern rtx_insn *gen_split_339 (rtx_insn *, rtx *);
rtx_insn *
gen_split_339 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_339 (vector.md:4849)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx8di (operands[0], RVV_VUNDEF (VNx8DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8di (operands[0], RVV_VUNDEF (VNx8DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	operand4,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4896 */
rtx
gen_pred_minus_mulvnx1di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4915 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[6],
	VNx1DImode,
	VNx1BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_minus_mulvnx1di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5],
	       operands[6], operands[7], operands[8], operands[9]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	operand4,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4896 */
rtx
gen_pred_minus_mulvnx2di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4915 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[6],
	VNx2DImode,
	VNx2BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_minus_mulvnx2di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5],
	       operands[6], operands[7], operands[8], operands[9]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	operand4,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4896 */
rtx
gen_pred_minus_mulvnx4di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4915 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[6],
	VNx4DImode,
	VNx4BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_minus_mulvnx4di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5],
	       operands[6], operands[7], operands[8], operands[9]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	operand4,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4896 */
rtx
gen_pred_minus_mulvnx8di_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 4915 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::sew64_scalar_helper (
	operands,
	/* scalar op */&operands[2],
	/* vl */operands[6],
	VNx8DImode,
	VNx8BImode,
	false,
	[] (rtx *operands, rtx boardcast_scalar) {
	  emit_insn (gen_pred_minus_mulvnx8di (operands[0], operands[1],
	       boardcast_scalar, operands[3], operands[4], operands[5],
	       operands[6], operands[7], operands[8], operands[9]));
        }))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	operand4,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	operand2),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4997 */
extern rtx_insn *gen_split_340 (rtx_insn *, rtx *);
rtx_insn *
gen_split_340 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_340 (vector.md:4997)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5026 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx1di (operands[0], RVV_VUNDEF (VNx1DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx1di (operands[0], RVV_VUNDEF (VNx1DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DImode,
	operand4,
	gen_rtx_MULT (VNx1DImode,
	gen_rtx_VEC_DUPLICATE (VNx1DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4997 */
extern rtx_insn *gen_split_341 (rtx_insn *, rtx *);
rtx_insn *
gen_split_341 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_341 (vector.md:4997)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5026 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx2di (operands[0], RVV_VUNDEF (VNx2DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx2di (operands[0], RVV_VUNDEF (VNx2DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DImode,
	operand4,
	gen_rtx_MULT (VNx2DImode,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4997 */
extern rtx_insn *gen_split_342 (rtx_insn *, rtx *);
rtx_insn *
gen_split_342 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_342 (vector.md:4997)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5026 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx4di (operands[0], RVV_VUNDEF (VNx4DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx4di (operands[0], RVV_VUNDEF (VNx4DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DImode,
	operand4,
	gen_rtx_MULT (VNx4DImode,
	gen_rtx_VEC_DUPLICATE (VNx4DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4997 */
extern rtx_insn *gen_split_343 (rtx_insn *, rtx *);
rtx_insn *
gen_split_343 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_343 (vector.md:4997)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5026 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    if (satisfies_constraint_vi (operands[3]))
      {
        emit_insn (gen_pred_mergevnx8di (operands[0], RVV_VUNDEF (VNx8DImode),
                	operands[5], operands[3], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[3] = operands[0];
      }
    else
      {
        emit_insn (gen_pred_mergevnx8di (operands[0], RVV_VUNDEF (VNx8DImode),
                	operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
        operands[5] = operands[4] = operands[0];
      }
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DImode,
	operand4,
	gen_rtx_MULT (VNx8DImode,
	gen_rtx_VEC_DUPLICATE (VNx8DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	operand3)),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_addvnx1sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_subvnx1sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_addvnx2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_subvnx2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_addvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_subvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_addvnx8sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_subvnx8sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_addvnx16sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_subvnx16sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_addvnx1df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_subvnx1df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_addvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_subvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_addvnx4df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_subvnx4df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_addvnx8df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
rtx
gen_pred_mul_subvnx8df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5521 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_344 (rtx_insn *, rtx *);
rtx_insn *
gen_split_344 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_344 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1sf (operands[0], RVV_VUNDEF (VNx1SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_345 (rtx_insn *, rtx *);
rtx_insn *
gen_split_345 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_345 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1sf (operands[0], RVV_VUNDEF (VNx1SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_346 (rtx_insn *, rtx *);
rtx_insn *
gen_split_346 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_346 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2sf (operands[0], RVV_VUNDEF (VNx2SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_347 (rtx_insn *, rtx *);
rtx_insn *
gen_split_347 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_347 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2sf (operands[0], RVV_VUNDEF (VNx2SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_348 (rtx_insn *, rtx *);
rtx_insn *
gen_split_348 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_348 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4sf (operands[0], RVV_VUNDEF (VNx4SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_349 (rtx_insn *, rtx *);
rtx_insn *
gen_split_349 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_349 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4sf (operands[0], RVV_VUNDEF (VNx4SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_350 (rtx_insn *, rtx *);
rtx_insn *
gen_split_350 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_350 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8sf (operands[0], RVV_VUNDEF (VNx8SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_351 (rtx_insn *, rtx *);
rtx_insn *
gen_split_351 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_351 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8sf (operands[0], RVV_VUNDEF (VNx8SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_352 (rtx_insn *, rtx *);
rtx_insn *
gen_split_352 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_352 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx16sf (operands[0], RVV_VUNDEF (VNx16SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_353 (rtx_insn *, rtx *);
rtx_insn *
gen_split_353 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_353 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx16sf (operands[0], RVV_VUNDEF (VNx16SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_354 (rtx_insn *, rtx *);
rtx_insn *
gen_split_354 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_354 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1df (operands[0], RVV_VUNDEF (VNx1DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_355 (rtx_insn *, rtx *);
rtx_insn *
gen_split_355 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_355 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1df (operands[0], RVV_VUNDEF (VNx1DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_356 (rtx_insn *, rtx *);
rtx_insn *
gen_split_356 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_356 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2df (operands[0], RVV_VUNDEF (VNx2DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_357 (rtx_insn *, rtx *);
rtx_insn *
gen_split_357 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_357 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2df (operands[0], RVV_VUNDEF (VNx2DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_358 (rtx_insn *, rtx *);
rtx_insn *
gen_split_358 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_358 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4df (operands[0], RVV_VUNDEF (VNx4DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_359 (rtx_insn *, rtx *);
rtx_insn *
gen_split_359 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_359 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4df (operands[0], RVV_VUNDEF (VNx4DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_360 (rtx_insn *, rtx *);
rtx_insn *
gen_split_360 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_360 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8df (operands[0], RVV_VUNDEF (VNx8DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
extern rtx_insn *gen_split_361 (rtx_insn *, rtx *);
rtx_insn *
gen_split_361 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_361 (vector.md:5590)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5616 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8df (operands[0], RVV_VUNDEF (VNx8DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	operand2,
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_addvnx1sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_subvnx1sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_addvnx2sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_subvnx2sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_addvnx4sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_subvnx4sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_addvnx8sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_subvnx8sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_addvnx16sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_subvnx16sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_addvnx1df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_subvnx1df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_addvnx2df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_subvnx2df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_addvnx4df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_subvnx4df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_addvnx8df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
rtx
gen_pred_mul_subvnx8df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5644 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_362 (rtx_insn *, rtx *);
rtx_insn *
gen_split_362 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_362 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1sf (operands[0], RVV_VUNDEF (VNx1SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_363 (rtx_insn *, rtx *);
rtx_insn *
gen_split_363 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_363 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1sf (operands[0], RVV_VUNDEF (VNx1SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_364 (rtx_insn *, rtx *);
rtx_insn *
gen_split_364 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_364 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2sf (operands[0], RVV_VUNDEF (VNx2SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_365 (rtx_insn *, rtx *);
rtx_insn *
gen_split_365 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_365 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2sf (operands[0], RVV_VUNDEF (VNx2SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_366 (rtx_insn *, rtx *);
rtx_insn *
gen_split_366 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_366 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4sf (operands[0], RVV_VUNDEF (VNx4SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_367 (rtx_insn *, rtx *);
rtx_insn *
gen_split_367 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_367 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4sf (operands[0], RVV_VUNDEF (VNx4SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_368 (rtx_insn *, rtx *);
rtx_insn *
gen_split_368 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_368 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8sf (operands[0], RVV_VUNDEF (VNx8SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_369 (rtx_insn *, rtx *);
rtx_insn *
gen_split_369 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_369 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8sf (operands[0], RVV_VUNDEF (VNx8SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_370 (rtx_insn *, rtx *);
rtx_insn *
gen_split_370 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_370 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx16sf (operands[0], RVV_VUNDEF (VNx16SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_371 (rtx_insn *, rtx *);
rtx_insn *
gen_split_371 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_371 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx16sf (operands[0], RVV_VUNDEF (VNx16SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_372 (rtx_insn *, rtx *);
rtx_insn *
gen_split_372 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_372 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1df (operands[0], RVV_VUNDEF (VNx1DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_373 (rtx_insn *, rtx *);
rtx_insn *
gen_split_373 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_373 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1df (operands[0], RVV_VUNDEF (VNx1DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_374 (rtx_insn *, rtx *);
rtx_insn *
gen_split_374 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_374 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2df (operands[0], RVV_VUNDEF (VNx2DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_375 (rtx_insn *, rtx *);
rtx_insn *
gen_split_375 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_375 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2df (operands[0], RVV_VUNDEF (VNx2DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_376 (rtx_insn *, rtx *);
rtx_insn *
gen_split_376 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_376 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4df (operands[0], RVV_VUNDEF (VNx4DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_377 (rtx_insn *, rtx *);
rtx_insn *
gen_split_377 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_377 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4df (operands[0], RVV_VUNDEF (VNx4DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_378 (rtx_insn *, rtx *);
rtx_insn *
gen_split_378 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_378 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8df (operands[0], RVV_VUNDEF (VNx8DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
extern rtx_insn *gen_split_379 (rtx_insn *, rtx *);
rtx_insn *
gen_split_379 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_379 (vector.md:5710)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5736 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8df (operands[0], RVV_VUNDEF (VNx8DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand2),
	operand3),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_addvnx1sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_NEG (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_subvnx1sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SFmode,
	gen_rtx_NEG (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_addvnx2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_NEG (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_subvnx2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SFmode,
	gen_rtx_NEG (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_addvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_NEG (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_subvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SFmode,
	gen_rtx_NEG (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_addvnx8sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_NEG (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_subvnx8sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SFmode,
	gen_rtx_NEG (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_addvnx16sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SFmode,
	gen_rtx_NEG (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_subvnx16sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SFmode,
	gen_rtx_NEG (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_addvnx1df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_NEG (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_subvnx1df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_NEG (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_addvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_subvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_addvnx4df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_NEG (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_subvnx4df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_NEG (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_addvnx8df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_NEG (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
rtx
gen_pred_mul_neg_subvnx8df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5764 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_NEG (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_380 (rtx_insn *, rtx *);
rtx_insn *
gen_split_380 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_380 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1sf (operands[0], RVV_VUNDEF (VNx1SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_NEG (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_381 (rtx_insn *, rtx *);
rtx_insn *
gen_split_381 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_381 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1sf (operands[0], RVV_VUNDEF (VNx1SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SFmode,
	gen_rtx_NEG (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_382 (rtx_insn *, rtx *);
rtx_insn *
gen_split_382 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_382 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2sf (operands[0], RVV_VUNDEF (VNx2SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_NEG (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_383 (rtx_insn *, rtx *);
rtx_insn *
gen_split_383 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_383 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2sf (operands[0], RVV_VUNDEF (VNx2SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SFmode,
	gen_rtx_NEG (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_384 (rtx_insn *, rtx *);
rtx_insn *
gen_split_384 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_384 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4sf (operands[0], RVV_VUNDEF (VNx4SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_NEG (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_385 (rtx_insn *, rtx *);
rtx_insn *
gen_split_385 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_385 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4sf (operands[0], RVV_VUNDEF (VNx4SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SFmode,
	gen_rtx_NEG (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_386 (rtx_insn *, rtx *);
rtx_insn *
gen_split_386 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_386 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8sf (operands[0], RVV_VUNDEF (VNx8SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_NEG (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_387 (rtx_insn *, rtx *);
rtx_insn *
gen_split_387 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_387 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8sf (operands[0], RVV_VUNDEF (VNx8SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SFmode,
	gen_rtx_NEG (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_388 (rtx_insn *, rtx *);
rtx_insn *
gen_split_388 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_388 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx16sf (operands[0], RVV_VUNDEF (VNx16SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SFmode,
	gen_rtx_NEG (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_389 (rtx_insn *, rtx *);
rtx_insn *
gen_split_389 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_389 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx16sf (operands[0], RVV_VUNDEF (VNx16SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SFmode,
	gen_rtx_NEG (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_390 (rtx_insn *, rtx *);
rtx_insn *
gen_split_390 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_390 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1df (operands[0], RVV_VUNDEF (VNx1DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_NEG (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_391 (rtx_insn *, rtx *);
rtx_insn *
gen_split_391 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_391 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1df (operands[0], RVV_VUNDEF (VNx1DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_NEG (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_392 (rtx_insn *, rtx *);
rtx_insn *
gen_split_392 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_392 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2df (operands[0], RVV_VUNDEF (VNx2DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_393 (rtx_insn *, rtx *);
rtx_insn *
gen_split_393 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_393 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2df (operands[0], RVV_VUNDEF (VNx2DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_394 (rtx_insn *, rtx *);
rtx_insn *
gen_split_394 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_394 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4df (operands[0], RVV_VUNDEF (VNx4DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_NEG (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_395 (rtx_insn *, rtx *);
rtx_insn *
gen_split_395 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_395 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4df (operands[0], RVV_VUNDEF (VNx4DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_NEG (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_396 (rtx_insn *, rtx *);
rtx_insn *
gen_split_396 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_396 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8df (operands[0], RVV_VUNDEF (VNx8DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_NEG (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
extern rtx_insn *gen_split_397 (rtx_insn *, rtx *);
rtx_insn *
gen_split_397 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_397 (vector.md:5835)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5862 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8df (operands[0], RVV_VUNDEF (VNx8DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_NEG (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	operand2,
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_addvnx1sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_NEG (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_subvnx1sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SFmode,
	gen_rtx_NEG (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_addvnx2sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_NEG (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_subvnx2sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SFmode,
	gen_rtx_NEG (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_addvnx4sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_NEG (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_subvnx4sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SFmode,
	gen_rtx_NEG (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_addvnx8sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_NEG (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_subvnx8sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SFmode,
	gen_rtx_NEG (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_addvnx16sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SFmode,
	gen_rtx_NEG (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_subvnx16sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SFmode,
	gen_rtx_NEG (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_addvnx1df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_NEG (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_subvnx1df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_NEG (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_addvnx2df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_subvnx2df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_addvnx4df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_NEG (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_subvnx4df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_NEG (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_addvnx8df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_NEG (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
rtx
gen_pred_mul_neg_subvnx8df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8,
	rtx operand9)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[10];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
    operands[9] = operand9;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
    operand9 = operands[9];
    (void) operand9;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_NEG (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_398 (rtx_insn *, rtx *);
rtx_insn *
gen_split_398 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_398 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1sf (operands[0], RVV_VUNDEF (VNx1SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1SFmode,
	gen_rtx_NEG (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_399 (rtx_insn *, rtx *);
rtx_insn *
gen_split_399 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_399 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1sf (operands[0], RVV_VUNDEF (VNx1SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1SFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1SFmode,
	gen_rtx_NEG (VNx1SFmode,
	gen_rtx_MULT (VNx1SFmode,
	gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_400 (rtx_insn *, rtx *);
rtx_insn *
gen_split_400 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_400 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2sf (operands[0], RVV_VUNDEF (VNx2SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2SFmode,
	gen_rtx_NEG (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_401 (rtx_insn *, rtx *);
rtx_insn *
gen_split_401 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_401 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2sf (operands[0], RVV_VUNDEF (VNx2SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2SFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2SFmode,
	gen_rtx_NEG (VNx2SFmode,
	gen_rtx_MULT (VNx2SFmode,
	gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_402 (rtx_insn *, rtx *);
rtx_insn *
gen_split_402 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_402 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4sf (operands[0], RVV_VUNDEF (VNx4SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4SFmode,
	gen_rtx_NEG (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_403 (rtx_insn *, rtx *);
rtx_insn *
gen_split_403 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_403 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4sf (operands[0], RVV_VUNDEF (VNx4SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4SFmode,
	gen_rtx_NEG (VNx4SFmode,
	gen_rtx_MULT (VNx4SFmode,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_404 (rtx_insn *, rtx *);
rtx_insn *
gen_split_404 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_404 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8sf (operands[0], RVV_VUNDEF (VNx8SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8SFmode,
	gen_rtx_NEG (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_405 (rtx_insn *, rtx *);
rtx_insn *
gen_split_405 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_405 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8sf (operands[0], RVV_VUNDEF (VNx8SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8SFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8SFmode,
	gen_rtx_NEG (VNx8SFmode,
	gen_rtx_MULT (VNx8SFmode,
	gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_406 (rtx_insn *, rtx *);
rtx_insn *
gen_split_406 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_406 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx16sf (operands[0], RVV_VUNDEF (VNx16SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx16SFmode,
	gen_rtx_NEG (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_407 (rtx_insn *, rtx *);
rtx_insn *
gen_split_407 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_407 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx16sf (operands[0], RVV_VUNDEF (VNx16SFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16SFmode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx16SFmode,
	gen_rtx_NEG (VNx16SFmode,
	gen_rtx_MULT (VNx16SFmode,
	gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_408 (rtx_insn *, rtx *);
rtx_insn *
gen_split_408 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_408 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1df (operands[0], RVV_VUNDEF (VNx1DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx1DFmode,
	gen_rtx_NEG (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_409 (rtx_insn *, rtx *);
rtx_insn *
gen_split_409 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_409 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx1df (operands[0], RVV_VUNDEF (VNx1DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1DFmode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx1DFmode,
	gen_rtx_NEG (VNx1DFmode,
	gen_rtx_MULT (VNx1DFmode,
	gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_410 (rtx_insn *, rtx *);
rtx_insn *
gen_split_410 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_410 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2df (operands[0], RVV_VUNDEF (VNx2DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_411 (rtx_insn *, rtx *);
rtx_insn *
gen_split_411 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_411 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx2df (operands[0], RVV_VUNDEF (VNx2DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	gen_rtx_MULT (VNx2DFmode,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_412 (rtx_insn *, rtx *);
rtx_insn *
gen_split_412 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_412 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4df (operands[0], RVV_VUNDEF (VNx4DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx4DFmode,
	gen_rtx_NEG (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_413 (rtx_insn *, rtx *);
rtx_insn *
gen_split_413 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_413 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx4df (operands[0], RVV_VUNDEF (VNx4DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4DFmode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx4DFmode,
	gen_rtx_NEG (VNx4DFmode,
	gen_rtx_MULT (VNx4DFmode,
	gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_414 (rtx_insn *, rtx *);
rtx_insn *
gen_split_414 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_414 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8df (operands[0], RVV_VUNDEF (VNx8DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_PLUS (VNx8DFmode,
	gen_rtx_NEG (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
extern rtx_insn *gen_split_415 (rtx_insn *, rtx *);
rtx_insn *
gen_split_415 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx operand7;
  rtx operand8;
  rtx operand9;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_415 (vector.md:5959)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 5986 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
    emit_insn (gen_pred_mergevnx8df (operands[0], RVV_VUNDEF (VNx8DFmode),
			operands[5], operands[4], operands[1], operands[6],
			operands[7], operands[9]));
    operands[5] = operands[4] = operands[0];
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  operand6 = operands[6];
  (void) operand6;
  operand7 = operands[7];
  (void) operand7;
  operand8 = operands[8];
  (void) operand8;
  operand9 = operands[9];
  (void) operand9;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8DFmode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand6,
		operand7,
		operand8,
		operand9,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_MINUS (VNx8DFmode,
	gen_rtx_NEG (VNx8DFmode,
	gen_rtx_MULT (VNx8DFmode,
	gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand2),
	operand3)),
	operand4),
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
rtx
gen_pred_cmpvnx1sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6293 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
rtx
gen_pred_cmpvnx2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6293 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
rtx
gen_pred_cmpvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6293 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
rtx
gen_pred_cmpvnx8sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6293 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
rtx
gen_pred_cmpvnx16sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6293 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
rtx
gen_pred_cmpvnx1df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6293 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
rtx
gen_pred_cmpvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6293 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
rtx
gen_pred_cmpvnx4df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6293 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
rtx
gen_pred_cmpvnx8df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6293 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		operand5),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
rtx
gen_pred_cmpvnx1sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
rtx
gen_pred_cmpvnx2sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
rtx
gen_pred_cmpvnx4sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
rtx
gen_pred_cmpvnx8sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
rtx
gen_pred_cmpvnx16sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
rtx
gen_pred_cmpvnx1df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
rtx
gen_pred_cmpvnx2df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
rtx
gen_pred_cmpvnx4df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
rtx
gen_pred_cmpvnx8df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6351 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		operand4,
		gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand5)),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
rtx
gen_pred_eqnevnx1sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		gen_rtx_VEC_DUPLICATE (VNx1SFmode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
rtx
gen_pred_eqnevnx2sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		gen_rtx_VEC_DUPLICATE (VNx2SFmode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
rtx
gen_pred_eqnevnx4sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
rtx
gen_pred_eqnevnx8sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		gen_rtx_VEC_DUPLICATE (VNx8SFmode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
rtx
gen_pred_eqnevnx16sf_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16BImode,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx16BImode,
		gen_rtx_VEC_DUPLICATE (VNx16SFmode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
rtx
gen_pred_eqnevnx1df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx1BImode,
	gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx1BImode,
		gen_rtx_VEC_DUPLICATE (VNx1DFmode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
rtx
gen_pred_eqnevnx2df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2BImode,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx2BImode,
		gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
rtx
gen_pred_eqnevnx4df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4BImode,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx4BImode,
		gen_rtx_VEC_DUPLICATE (VNx4DFmode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
rtx
gen_pred_eqnevnx8df_scalar (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6411 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8BImode,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (6,
		operand1,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
	gen_rtx_fmt_ee (GET_CODE (operand3), VNx8BImode,
		gen_rtx_VEC_DUPLICATE (VNx8DFmode,
	operand5),
		operand4),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx1qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (QImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx2qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (QImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx4qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (QImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (QImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (QImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx32qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (QImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx64qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (QImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx1hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (HImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx2hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (HImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (HImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (HImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx16hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (HImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx32hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (HImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx1si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (SImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (SImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (SImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx8si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (SImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx16si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (SImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx1di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (DImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (DImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx4di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (DImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
rtx
gen_pred_extract_firstvnx8di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6956 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.x.s ==> lw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (DImode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_416 (rtx_insn *, rtx *);
rtx_insn *
gen_split_416 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_416 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx1QImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx1QImode, high_bits, CONSTM1_RTX (VNx1BImode),
  			RVV_VUNDEF (VNx1QImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx1QImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx1QImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_417 (rtx_insn *, rtx *);
rtx_insn *
gen_split_417 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_417 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx2QImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx2QImode, high_bits, CONSTM1_RTX (VNx2BImode),
  			RVV_VUNDEF (VNx2QImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx2QImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx2QImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_418 (rtx_insn *, rtx *);
rtx_insn *
gen_split_418 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_418 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx4QImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx4QImode, high_bits, CONSTM1_RTX (VNx4BImode),
  			RVV_VUNDEF (VNx4QImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx4QImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx4QImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_419 (rtx_insn *, rtx *);
rtx_insn *
gen_split_419 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_419 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx8QImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx8QImode, high_bits, CONSTM1_RTX (VNx8BImode),
  			RVV_VUNDEF (VNx8QImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx8QImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx8QImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_420 (rtx_insn *, rtx *);
rtx_insn *
gen_split_420 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_420 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx16QImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx16QImode, high_bits, CONSTM1_RTX (VNx16BImode),
  			RVV_VUNDEF (VNx16QImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx16QImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx16QImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_421 (rtx_insn *, rtx *);
rtx_insn *
gen_split_421 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_421 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx32QImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx32QImode, high_bits, CONSTM1_RTX (VNx32BImode),
  			RVV_VUNDEF (VNx32QImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx32QImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx32QImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_422 (rtx_insn *, rtx *);
rtx_insn *
gen_split_422 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_422 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx64QImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx64QImode, high_bits, CONSTM1_RTX (VNx64BImode),
  			RVV_VUNDEF (VNx64QImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx64QImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx64QImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_423 (rtx_insn *, rtx *);
rtx_insn *
gen_split_423 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_423 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx1HImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx1HImode, high_bits, CONSTM1_RTX (VNx1BImode),
  			RVV_VUNDEF (VNx1HImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx1HImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx1HImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_424 (rtx_insn *, rtx *);
rtx_insn *
gen_split_424 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_424 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx2HImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx2HImode, high_bits, CONSTM1_RTX (VNx2BImode),
  			RVV_VUNDEF (VNx2HImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx2HImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx2HImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_425 (rtx_insn *, rtx *);
rtx_insn *
gen_split_425 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_425 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx4HImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx4HImode, high_bits, CONSTM1_RTX (VNx4BImode),
  			RVV_VUNDEF (VNx4HImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx4HImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx4HImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_426 (rtx_insn *, rtx *);
rtx_insn *
gen_split_426 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_426 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx8HImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx8HImode, high_bits, CONSTM1_RTX (VNx8BImode),
  			RVV_VUNDEF (VNx8HImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx8HImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx8HImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_427 (rtx_insn *, rtx *);
rtx_insn *
gen_split_427 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_427 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx16HImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx16HImode, high_bits, CONSTM1_RTX (VNx16BImode),
  			RVV_VUNDEF (VNx16HImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx16HImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx16HImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_428 (rtx_insn *, rtx *);
rtx_insn *
gen_split_428 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_428 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx32HImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx32HImode, high_bits, CONSTM1_RTX (VNx32BImode),
  			RVV_VUNDEF (VNx32HImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx32HImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx32HImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_429 (rtx_insn *, rtx *);
rtx_insn *
gen_split_429 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_429 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx1SImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx1SImode, high_bits, CONSTM1_RTX (VNx1BImode),
  			RVV_VUNDEF (VNx1SImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx1SImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx1SImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_430 (rtx_insn *, rtx *);
rtx_insn *
gen_split_430 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_430 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx2SImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx2SImode, high_bits, CONSTM1_RTX (VNx2BImode),
  			RVV_VUNDEF (VNx2SImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx2SImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx2SImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_431 (rtx_insn *, rtx *);
rtx_insn *
gen_split_431 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_431 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx4SImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx4SImode, high_bits, CONSTM1_RTX (VNx4BImode),
  			RVV_VUNDEF (VNx4SImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx4SImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx4SImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_432 (rtx_insn *, rtx *);
rtx_insn *
gen_split_432 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_432 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx8SImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx8SImode, high_bits, CONSTM1_RTX (VNx8BImode),
  			RVV_VUNDEF (VNx8SImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx8SImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx8SImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_433 (rtx_insn *, rtx *);
rtx_insn *
gen_split_433 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_433 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx16SImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx16SImode, high_bits, CONSTM1_RTX (VNx16BImode),
  			RVV_VUNDEF (VNx16SImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx16SImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx16SImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_434 (rtx_insn *, rtx *);
rtx_insn *
gen_split_434 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_434 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx1DImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx1DImode, high_bits, CONSTM1_RTX (VNx1BImode),
  			RVV_VUNDEF (VNx1DImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx1DImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx1DImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_435 (rtx_insn *, rtx *);
rtx_insn *
gen_split_435 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_435 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx2DImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx2DImode, high_bits, CONSTM1_RTX (VNx2BImode),
  			RVV_VUNDEF (VNx2DImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx2DImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx2DImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_436 (rtx_insn *, rtx *);
rtx_insn *
gen_split_436 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_436 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx4DImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx4DImode, high_bits, CONSTM1_RTX (VNx4BImode),
  			RVV_VUNDEF (VNx4DImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx4DImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx4DImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
extern rtx_insn *gen_split_437 (rtx_insn *, rtx *);
rtx_insn *
gen_split_437 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_437 (vector.md:6965)\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 6976 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  /* In rv32 system, we can't use vmv.x.s directly.
     Instead, we should generate this following code sequence:
       vsrl.vx v16,v8,a0
       vmv.x.s a1,v16
       vmv.x.s a0,v8  */
  rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
  rtx high_bits = gen_reg_rtx (VNx8DImode);
  emit_insn (gen_pred_scalar (LSHIFTRT, VNx8DImode, high_bits, CONSTM1_RTX (VNx8BImode),
  			RVV_VUNDEF (VNx8DImode), operands[1], nbits, /* vl */ const1_rtx,
			gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
			gen_int_mode (riscv_vector::MASK_ANY, Pmode),
			gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
  emit_insn (gen_pred_extract_first_trunc (VNx8DImode,
  			gen_highpart (SImode, operands[0]), high_bits));
  emit_insn (gen_pred_extract_first_trunc (VNx8DImode,
  			gen_lowpart (SImode, operands[0]), operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
rtx
gen_pred_extract_firstvnx1sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7019 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.f.s ==> flw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (SFmode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
rtx
gen_pred_extract_firstvnx2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7019 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.f.s ==> flw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (SFmode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
rtx
gen_pred_extract_firstvnx4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7019 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.f.s ==> flw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (SFmode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
rtx
gen_pred_extract_firstvnx8sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7019 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.f.s ==> flw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (SFmode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
rtx
gen_pred_extract_firstvnx16sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7019 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.f.s ==> flw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (SFmode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
rtx
gen_pred_extract_firstvnx1df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7019 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.f.s ==> flw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (DFmode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (DFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
rtx
gen_pred_extract_firstvnx2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7019 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.f.s ==> flw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (DFmode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (DFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
rtx
gen_pred_extract_firstvnx4df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7019 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.f.s ==> flw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (DFmode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (DFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
rtx
gen_pred_extract_firstvnx8df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7019 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (MEM_P (operands[1]))
    {
      /* Combine vle.v + vmv.f.s ==> flw.  */
      emit_move_insn (operands[0], gen_rtx_MEM (DFmode, XEXP (operands[1], 0)));
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		gen_rtx_VEC_SELECT (DFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx))),
		gen_rtx_REG (SImode,
	67)),
	68)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
rtx
gen_pred_slide1upvnx1di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::slide1_sew64_helper (UNSPEC_VSLIDE1UP, VNx1DImode,
					 VNx2SImode, VNx2BImode,
					 operands))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
rtx
gen_pred_slide1downvnx1di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::slide1_sew64_helper (UNSPEC_VSLIDE1DOWN, VNx1DImode,
					 VNx2SImode, VNx2BImode,
					 operands))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx1DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx1BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
rtx
gen_pred_slide1upvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::slide1_sew64_helper (UNSPEC_VSLIDE1UP, VNx2DImode,
					 VNx4SImode, VNx4BImode,
					 operands))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
rtx
gen_pred_slide1downvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::slide1_sew64_helper (UNSPEC_VSLIDE1DOWN, VNx2DImode,
					 VNx4SImode, VNx4BImode,
					 operands))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
rtx
gen_pred_slide1upvnx4di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::slide1_sew64_helper (UNSPEC_VSLIDE1UP, VNx4DImode,
					 VNx8SImode, VNx8BImode,
					 operands))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
rtx
gen_pred_slide1downvnx4di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::slide1_sew64_helper (UNSPEC_VSLIDE1DOWN, VNx4DImode,
					 VNx8SImode, VNx8BImode,
					 operands))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
rtx
gen_pred_slide1upvnx8di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::slide1_sew64_helper (UNSPEC_VSLIDE1UP, VNx8DImode,
					 VNx16SImode, VNx16BImode,
					 operands))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	108)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
rtx
gen_pred_slide1downvnx8di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7,
	rtx operand8)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[9];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
    operands[8] = operand8;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (), end_sequence (), _val)
#line 7095 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md"
{
  if (riscv_vector::slide1_sew64_helper (UNSPEC_VSLIDE1DOWN, VNx8DImode,
					 VNx16SImode, VNx16BImode,
					 operands))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
    operand8 = operands[8];
    (void) operand8;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (4,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (7,
		operand1,
		operand5,
		operand6,
		operand7,
		operand8,
		gen_rtx_REG (SImode,
	66),
		gen_rtx_REG (SImode,
	67)),
	68),
		operand2,
		operand3,
		operand4),
	109)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}



void
add_clobbers (rtx pattern ATTRIBUTE_UNUSED, int insn_code_number)
{
  switch (insn_code_number)
    {
    case 508:
      XVECEXP (pattern, 0, 5) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 507:
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      break;

    case 506:
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 505:
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 502:
    case 501:
    case 500:
    case 499:
    case 498:
      XVECEXP (pattern, 0, 4) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      XVECEXP (pattern, 0, 5) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 419:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 420:
    case 384:
    case 383:
    case 382:
    case 381:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      break;

    case 300:
    case 299:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (SImode, 1);
      break;

    case 785:
    case 784:
    case 783:
    case 782:
    case 781:
    case 780:
    case 779:
    case 777:
    case 775:
    case 773:
    case 771:
    case 769:
    case 767:
    case 765:
    case 568:
    case 567:
    case 566:
    case 562:
    case 561:
    case 560:
    case 556:
    case 555:
    case 554:
    case 549:
    case 548:
    case 547:
    case 546:
    case 539:
    case 538:
    case 537:
    case 533:
    case 532:
    case 531:
    case 318:
    case 294:
    case 248:
    case 246:
    case 236:
    case 235:
    case 234:
    case 233:
    case 228:
    case 227:
    case 226:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 792:
    case 791:
    case 790:
    case 789:
    case 788:
    case 787:
    case 786:
    case 778:
    case 776:
    case 774:
    case 772:
    case 770:
    case 768:
    case 766:
    case 571:
    case 570:
    case 569:
    case 565:
    case 564:
    case 563:
    case 559:
    case 558:
    case 557:
    case 553:
    case 552:
    case 551:
    case 550:
    case 542:
    case 541:
    case 540:
    case 536:
    case 535:
    case 534:
    case 334:
    case 319:
    case 295:
    case 249:
    case 247:
    case 240:
    case 239:
    case 238:
    case 237:
    case 232:
    case 231:
    case 230:
    case 229:
    case 225:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      break;

    default:
      gcc_unreachable ();
    }
}


int
added_clobbers_hard_reg_p (int insn_code_number)
{
  switch (insn_code_number)
    {
    case 508:
    case 507:
    case 506:
    case 505:
    case 502:
    case 501:
    case 500:
    case 499:
    case 498:
    case 419:
    case 420:
    case 384:
    case 383:
    case 382:
    case 381:
    case 785:
    case 784:
    case 783:
    case 782:
    case 781:
    case 780:
    case 779:
    case 777:
    case 775:
    case 773:
    case 771:
    case 769:
    case 767:
    case 765:
    case 568:
    case 567:
    case 566:
    case 562:
    case 561:
    case 560:
    case 556:
    case 555:
    case 554:
    case 549:
    case 548:
    case 547:
    case 546:
    case 539:
    case 538:
    case 537:
    case 533:
    case 532:
    case 531:
    case 318:
    case 294:
    case 248:
    case 246:
    case 236:
    case 235:
    case 234:
    case 233:
    case 228:
    case 227:
    case 226:
    case 792:
    case 791:
    case 790:
    case 789:
    case 788:
    case 787:
    case 786:
    case 778:
    case 776:
    case 774:
    case 772:
    case 770:
    case 768:
    case 766:
    case 571:
    case 570:
    case 569:
    case 565:
    case 564:
    case 563:
    case 559:
    case 558:
    case 557:
    case 553:
    case 552:
    case 551:
    case 550:
    case 542:
    case 541:
    case 540:
    case 536:
    case 535:
    case 534:
    case 334:
    case 319:
    case 295:
    case 249:
    case 247:
    case 240:
    case 239:
    case 238:
    case 237:
    case 232:
    case 231:
    case 230:
    case 229:
    case 225:
      return 0;

    case 300:
    case 299:
      return 1;

    default:
      gcc_unreachable ();
    }
}

insn_code
maybe_code_for_cbranch4 (machine_mode arg0)
{
  if (arg0 == E_QImode)
    return CODE_FOR_cbranchqi4;
  if (arg0 == E_SImode)
    return CODE_FOR_cbranchsi4;
  if (arg0 == E_DImode)
    return CODE_FOR_cbranchdi4;
  if (arg0 == E_SFmode)
    return CODE_FOR_cbranchsf4;
  if (arg0 == E_DFmode)
    return CODE_FOR_cbranchdf4;
  if (arg0 == E_HFmode)
    return CODE_FOR_cbranchhf4;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_cbranch4 (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3)
{
  insn_code code = maybe_code_for_cbranch4 (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 4);
      return GEN_FCN (code) (x0, x1, x2, x3);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_vundefined (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_vundefinedvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_vundefinedvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_vundefinedvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_vundefinedvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_vundefinedvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_vundefinedvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_vundefinedvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_vundefinedvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_vundefinedvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_vundefinedvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_vundefinedvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_vundefinedvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_vundefinedvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_vundefinedvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_vundefinedvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_vundefinedvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_vundefinedvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_vundefinedvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_vundefinedvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_vundefinedvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_vundefinedvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_vundefinedvnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_vundefinedvnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_vundefinedvnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_vundefinedvnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_vundefinedvnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_vundefinedvnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_vundefinedvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_vundefinedvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_vundefinedvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_vundefinedvnx8df;
  if (arg0 == E_VNx1BImode)
    return CODE_FOR_vundefinedvnx1bi;
  if (arg0 == E_VNx2BImode)
    return CODE_FOR_vundefinedvnx2bi;
  if (arg0 == E_VNx4BImode)
    return CODE_FOR_vundefinedvnx4bi;
  if (arg0 == E_VNx8BImode)
    return CODE_FOR_vundefinedvnx8bi;
  if (arg0 == E_VNx16BImode)
    return CODE_FOR_vundefinedvnx16bi;
  if (arg0 == E_VNx32BImode)
    return CODE_FOR_vundefinedvnx32bi;
  if (arg0 == E_VNx64BImode)
    return CODE_FOR_vundefinedvnx64bi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_vundefined (machine_mode arg0, rtx x0)
{
  insn_code code = maybe_code_for_vundefined (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 1);
      return GEN_FCN (code) (x0);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_vreinterpret (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_vreinterpretvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_vreinterpretvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_vreinterpretvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_vreinterpretvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_vreinterpretvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_vreinterpretvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_vreinterpretvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_vreinterpretvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_vreinterpretvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_vreinterpretvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_vreinterpretvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_vreinterpretvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_vreinterpretvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_vreinterpretvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_vreinterpretvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_vreinterpretvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_vreinterpretvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_vreinterpretvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_vreinterpretvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_vreinterpretvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_vreinterpretvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_vreinterpretvnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_vreinterpretvnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_vreinterpretvnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_vreinterpretvnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_vreinterpretvnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_vreinterpretvnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_vreinterpretvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_vreinterpretvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_vreinterpretvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_vreinterpretvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_vreinterpret (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_vreinterpret (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 2);
      return GEN_FCN (code) (x0, x1);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_vlmul_extx2 (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_vlmul_extx2vnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_vlmul_extx2vnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_vlmul_extx2vnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_vlmul_extx2vnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_vlmul_extx2vnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_vlmul_extx2vnx32qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_vlmul_extx2vnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_vlmul_extx2vnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_vlmul_extx2vnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_vlmul_extx2vnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_vlmul_extx2vnx16hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_vlmul_extx2vnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_vlmul_extx2vnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_vlmul_extx2vnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_vlmul_extx2vnx8si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_vlmul_extx2vnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_vlmul_extx2vnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_vlmul_extx2vnx4di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_vlmul_extx2vnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_vlmul_extx2vnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_vlmul_extx2vnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_vlmul_extx2vnx8sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_vlmul_extx2vnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_vlmul_extx2vnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_vlmul_extx2vnx4df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_vlmul_extx2 (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_vlmul_extx2 (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 2);
      return GEN_FCN (code) (x0, x1);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_vlmul_extx4 (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_vlmul_extx4vnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_vlmul_extx4vnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_vlmul_extx4vnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_vlmul_extx4vnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_vlmul_extx4vnx16qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_vlmul_extx4vnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_vlmul_extx4vnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_vlmul_extx4vnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_vlmul_extx4vnx8hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_vlmul_extx4vnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_vlmul_extx4vnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_vlmul_extx4vnx4si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_vlmul_extx4vnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_vlmul_extx4vnx2di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_vlmul_extx4vnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_vlmul_extx4vnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_vlmul_extx4vnx4sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_vlmul_extx4vnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_vlmul_extx4vnx2df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_vlmul_extx4 (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_vlmul_extx4 (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 2);
      return GEN_FCN (code) (x0, x1);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_vlmul_extx8 (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_vlmul_extx8vnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_vlmul_extx8vnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_vlmul_extx8vnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_vlmul_extx8vnx8qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_vlmul_extx8vnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_vlmul_extx8vnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_vlmul_extx8vnx4hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_vlmul_extx8vnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_vlmul_extx8vnx2si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_vlmul_extx8vnx1di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_vlmul_extx8vnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_vlmul_extx8vnx2sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_vlmul_extx8vnx1df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_vlmul_extx8 (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_vlmul_extx8 (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 2);
      return GEN_FCN (code) (x0, x1);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_vlmul_extx16 (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_vlmul_extx16vnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_vlmul_extx16vnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_vlmul_extx16vnx4qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_vlmul_extx16vnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_vlmul_extx16vnx2hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_vlmul_extx16vnx1si;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_vlmul_extx16vnx1sf;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_vlmul_extx16 (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_vlmul_extx16 (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 2);
      return GEN_FCN (code) (x0, x1);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_vlmul_extx32 (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_vlmul_extx32vnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_vlmul_extx32vnx2qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_vlmul_extx32vnx1hi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_vlmul_extx32 (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_vlmul_extx32 (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 2);
      return GEN_FCN (code) (x0, x1);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_vlmul_extx64 (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_vlmul_extx64vnx1qi;
  return CODE_FOR_nothing;
}

insn_code
maybe_code_for_vlmax_avl (machine_mode arg0)
{
  if (arg0 == E_SImode)
    return CODE_FOR_vlmax_avlsi;
  if (arg0 == E_DImode)
    return CODE_FOR_vlmax_avldi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_vlmax_avl (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_vlmax_avl (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 2);
      return GEN_FCN (code) (x0, x1);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_mov_lra (machine_mode arg0, machine_mode arg1)
{
  if (arg0 == E_VNx1QImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx1qisi_lra;
  if (arg0 == E_VNx1QImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx1qidi_lra;
  if (arg0 == E_VNx2QImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx2qisi_lra;
  if (arg0 == E_VNx2QImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx2qidi_lra;
  if (arg0 == E_VNx4QImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx4qisi_lra;
  if (arg0 == E_VNx4QImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx4qidi_lra;
  if (arg0 == E_VNx1HImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx1hisi_lra;
  if (arg0 == E_VNx1HImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx1hidi_lra;
  if (arg0 == E_VNx2HImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx2hisi_lra;
  if (arg0 == E_VNx2HImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx2hidi_lra;
  if (arg0 == E_VNx1SImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx1sisi_lra;
  if (arg0 == E_VNx1SImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx1sidi_lra;
  if (arg0 == E_VNx1SFmode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx1sfsi_lra;
  if (arg0 == E_VNx1SFmode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx1sfdi_lra;
  if (arg0 == E_VNx1BImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx1bisi_lra;
  if (arg0 == E_VNx2BImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx2bisi_lra;
  if (arg0 == E_VNx4BImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx4bisi_lra;
  if (arg0 == E_VNx8BImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx8bisi_lra;
  if (arg0 == E_VNx16BImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx16bisi_lra;
  if (arg0 == E_VNx32BImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx32bisi_lra;
  if (arg0 == E_VNx64BImode
      && arg1 == E_SImode)
    return CODE_FOR_movvnx64bisi_lra;
  if (arg0 == E_VNx1BImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx1bidi_lra;
  if (arg0 == E_VNx2BImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx2bidi_lra;
  if (arg0 == E_VNx4BImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx4bidi_lra;
  if (arg0 == E_VNx8BImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx8bidi_lra;
  if (arg0 == E_VNx16BImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx16bidi_lra;
  if (arg0 == E_VNx32BImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx32bidi_lra;
  if (arg0 == E_VNx64BImode
      && arg1 == E_DImode)
    return CODE_FOR_movvnx64bidi_lra;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_mov_lra (machine_mode arg0, machine_mode arg1, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_mov_lra (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 2);
      return GEN_FCN (code) (x0, x1);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_vsetvl (machine_mode arg0)
{
  if (arg0 == E_SImode)
    return CODE_FOR_vsetvlsi;
  if (arg0 == E_DImode)
    return CODE_FOR_vsetvldi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_vsetvl (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5)
{
  insn_code code = maybe_code_for_vsetvl (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 6);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_vsetvl_discard_result (machine_mode arg0)
{
  if (arg0 == E_SImode)
    return CODE_FOR_vsetvl_discard_resultsi;
  if (arg0 == E_DImode)
    return CODE_FOR_vsetvl_discard_resultdi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_vsetvl_discard_result (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)
{
  insn_code code = maybe_code_for_vsetvl_discard_result (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 5);
      return GEN_FCN (code) (x0, x1, x2, x3, x4);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_vsetvl_no_side_effects (machine_mode arg0)
{
  if (arg0 == E_SImode)
    return CODE_FOR_vsetvlsi_no_side_effects;
  if (arg0 == E_DImode)
    return CODE_FOR_vsetvldi_no_side_effects;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_vsetvl_no_side_effects (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5)
{
  insn_code code = maybe_code_for_vsetvl_no_side_effects (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 6);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_mov (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_movvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_movvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_movvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_movvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_movvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_movvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_movvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_movvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_movvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_movvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_movvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_movvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_movvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_movvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_movvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_movvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_movvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_movvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_movvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_movvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_movvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_movvnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_movvnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_movvnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_movvnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_movvnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_movvnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_movvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_movvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_movvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_movvnx8df;
  if (arg0 == E_VNx1BImode)
    return CODE_FOR_pred_movvnx1bi;
  if (arg0 == E_VNx2BImode)
    return CODE_FOR_pred_movvnx2bi;
  if (arg0 == E_VNx4BImode)
    return CODE_FOR_pred_movvnx4bi;
  if (arg0 == E_VNx8BImode)
    return CODE_FOR_pred_movvnx8bi;
  if (arg0 == E_VNx16BImode)
    return CODE_FOR_pred_movvnx16bi;
  if (arg0 == E_VNx32BImode)
    return CODE_FOR_pred_movvnx32bi;
  if (arg0 == E_VNx64BImode)
    return CODE_FOR_pred_movvnx64bi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_mov (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_mov (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

rtx
maybe_gen_pred_mov (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5)
{
  insn_code code = maybe_code_for_pred_mov (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 6);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_store (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_storevnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_storevnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_storevnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_storevnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_storevnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_storevnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_storevnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_storevnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_storevnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_storevnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_storevnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_storevnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_storevnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_storevnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_storevnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_storevnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_storevnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_storevnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_storevnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_storevnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_storevnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_storevnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_storevnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_storevnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_storevnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_storevnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_storevnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_storevnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_storevnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_storevnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_storevnx8df;
  if (arg0 == E_VNx1BImode)
    return CODE_FOR_pred_storevnx1bi;
  if (arg0 == E_VNx2BImode)
    return CODE_FOR_pred_storevnx2bi;
  if (arg0 == E_VNx4BImode)
    return CODE_FOR_pred_storevnx4bi;
  if (arg0 == E_VNx8BImode)
    return CODE_FOR_pred_storevnx8bi;
  if (arg0 == E_VNx16BImode)
    return CODE_FOR_pred_storevnx16bi;
  if (arg0 == E_VNx32BImode)
    return CODE_FOR_pred_storevnx32bi;
  if (arg0 == E_VNx64BImode)
    return CODE_FOR_pred_storevnx64bi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_store (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3)
{
  insn_code code = maybe_code_for_pred_store (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 4);
      return GEN_FCN (code) (x0, x1, x2, x3);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_merge (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_mergevnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_mergevnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_mergevnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_mergevnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_mergevnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_mergevnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_mergevnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_mergevnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_mergevnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_mergevnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_mergevnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_mergevnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_mergevnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_mergevnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_mergevnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_mergevnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_mergevnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_mergevnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_mergevnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_mergevnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_mergevnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_mergevnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_mergevnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_mergevnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_mergevnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_mergevnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_mergevnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_mergevnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_mergevnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_mergevnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_mergevnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_merge (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_merge (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_merge_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_mergevnx1qi_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_mergevnx2qi_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_mergevnx4qi_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_mergevnx8qi_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_mergevnx16qi_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_mergevnx32qi_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_mergevnx64qi_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_mergevnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_mergevnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_mergevnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_mergevnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_mergevnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_mergevnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_mergevnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_mergevnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_mergevnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_mergevnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_mergevnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_mergevnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_mergevnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_mergevnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_mergevnx8di_scalar;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_mergevnx1sf_scalar;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_mergevnx2sf_scalar;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_mergevnx4sf_scalar;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_mergevnx8sf_scalar;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_mergevnx16sf_scalar;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_mergevnx1df_scalar;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_mergevnx2df_scalar;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_mergevnx4df_scalar;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_mergevnx8df_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_merge_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_merge_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_broadcast (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_broadcastvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_broadcastvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_broadcastvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_broadcastvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_broadcastvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_broadcastvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_broadcastvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_broadcastvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_broadcastvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_broadcastvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_broadcastvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_broadcastvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_broadcastvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_broadcastvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_broadcastvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_broadcastvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_broadcastvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_broadcastvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_broadcastvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_broadcastvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_broadcastvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_broadcastvnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_broadcastvnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_broadcastvnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_broadcastvnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_broadcastvnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_broadcastvnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_broadcastvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_broadcastvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_broadcastvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_broadcastvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_broadcast (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_broadcast (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_strided_load (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_strided_loadvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_strided_loadvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_strided_loadvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_strided_loadvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_strided_loadvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_strided_loadvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_strided_loadvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_strided_loadvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_strided_loadvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_strided_loadvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_strided_loadvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_strided_loadvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_strided_loadvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_strided_loadvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_strided_loadvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_strided_loadvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_strided_loadvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_strided_loadvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_strided_loadvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_strided_loadvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_strided_loadvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_strided_loadvnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_strided_loadvnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_strided_loadvnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_strided_loadvnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_strided_loadvnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_strided_loadvnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_strided_loadvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_strided_loadvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_strided_loadvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_strided_loadvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_strided_load (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_strided_load (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_strided_store (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_strided_storevnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_strided_storevnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_strided_storevnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_strided_storevnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_strided_storevnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_strided_storevnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_strided_storevnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_strided_storevnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_strided_storevnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_strided_storevnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_strided_storevnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_strided_storevnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_strided_storevnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_strided_storevnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_strided_storevnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_strided_storevnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_strided_storevnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_strided_storevnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_strided_storevnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_strided_storevnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_strided_storevnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_strided_storevnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_strided_storevnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_strided_storevnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_strided_storevnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_strided_storevnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_strided_storevnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_strided_storevnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_strided_storevnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_strided_storevnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_strided_storevnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_strided_store (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)
{
  insn_code code = maybe_code_for_pred_strided_store (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 5);
      return GEN_FCN (code) (x0, x1, x2, x3, x4);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_indexed_load_same_eew (int arg0, machine_mode arg1)
{
  if (arg0 == 71
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_oloadvnx1qi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_uloadvnx1qi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_oloadvnx2qi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_uloadvnx2qi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_oloadvnx4qi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_uloadvnx4qi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_oloadvnx8qi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_uloadvnx8qi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_oloadvnx16qi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_uloadvnx16qi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_indexed_oloadvnx32qi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_indexed_uloadvnx32qi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_indexed_oloadvnx64qi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_indexed_uloadvnx64qi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_oloadvnx1hi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_uloadvnx1hi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_oloadvnx2hi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_uloadvnx2hi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_oloadvnx4hi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_uloadvnx4hi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_oloadvnx8hi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_uloadvnx8hi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_oloadvnx16hi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_uloadvnx16hi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_indexed_oloadvnx32hi_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_indexed_uloadvnx32hi_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_oloadvnx1si_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_uloadvnx1si_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_oloadvnx2si_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_uloadvnx2si_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_oloadvnx4si_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_uloadvnx4si_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_oloadvnx8si_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_uloadvnx8si_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_oloadvnx16si_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_uloadvnx16si_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_oloadvnx1di_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_uloadvnx1di_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_oloadvnx2di_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_uloadvnx2di_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_oloadvnx4di_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_uloadvnx4di_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_oloadvnx8di_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_uloadvnx8di_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_indexed_oloadvnx1sf_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_indexed_uloadvnx1sf_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_indexed_oloadvnx2sf_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_indexed_uloadvnx2sf_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_indexed_oloadvnx4sf_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_indexed_uloadvnx4sf_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_indexed_oloadvnx8sf_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_indexed_uloadvnx8sf_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_indexed_oloadvnx16sf_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_indexed_uloadvnx16sf_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_indexed_oloadvnx1df_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_indexed_uloadvnx1df_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_indexed_oloadvnx2df_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_indexed_uloadvnx2df_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_indexed_oloadvnx4df_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_indexed_uloadvnx4df_same_eew;
  if (arg0 == 71
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_indexed_oloadvnx8df_same_eew;
  if (arg0 == 72
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_indexed_uloadvnx8df_same_eew;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_indexed_load_same_eew (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_indexed_load_same_eew (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_indexed_load_x2_greater_eew (int arg0, machine_mode arg1)
{
  if (arg0 == 71
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_oloadvnx1hi_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_uloadvnx1hi_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_oloadvnx2hi_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_uloadvnx2hi_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_oloadvnx4hi_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_uloadvnx4hi_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_oloadvnx8hi_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_uloadvnx8hi_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_oloadvnx16hi_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_uloadvnx16hi_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_indexed_oloadvnx32hi_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_indexed_uloadvnx32hi_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_oloadvnx1si_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_uloadvnx1si_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_oloadvnx2si_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_uloadvnx2si_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_oloadvnx4si_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_uloadvnx4si_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_oloadvnx8si_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_uloadvnx8si_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_oloadvnx16si_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_uloadvnx16si_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_oloadvnx1di_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_uloadvnx1di_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_oloadvnx2di_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_uloadvnx2di_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_oloadvnx4di_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_uloadvnx4di_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_oloadvnx8di_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_uloadvnx8di_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_indexed_oloadvnx1sf_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_indexed_uloadvnx1sf_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_indexed_oloadvnx2sf_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_indexed_uloadvnx2sf_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_indexed_oloadvnx4sf_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_indexed_uloadvnx4sf_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_indexed_oloadvnx8sf_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_indexed_uloadvnx8sf_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_indexed_oloadvnx16sf_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_indexed_uloadvnx16sf_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_indexed_oloadvnx1df_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_indexed_uloadvnx1df_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_indexed_oloadvnx2df_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_indexed_uloadvnx2df_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_indexed_oloadvnx4df_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_indexed_uloadvnx4df_x2_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_indexed_oloadvnx8df_x2_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_indexed_uloadvnx8df_x2_greater_eew;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_indexed_load_x2_greater_eew (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_indexed_load_x2_greater_eew (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_indexed_load_x4_greater_eew (int arg0, machine_mode arg1)
{
  if (arg0 == 71
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_oloadvnx1si_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_uloadvnx1si_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_oloadvnx2si_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_uloadvnx2si_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_oloadvnx4si_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_uloadvnx4si_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_oloadvnx8si_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_uloadvnx8si_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_oloadvnx16si_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_uloadvnx16si_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_oloadvnx1di_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_uloadvnx1di_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_oloadvnx2di_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_uloadvnx2di_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_oloadvnx4di_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_uloadvnx4di_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_oloadvnx8di_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_uloadvnx8di_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_indexed_oloadvnx1sf_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_indexed_uloadvnx1sf_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_indexed_oloadvnx2sf_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_indexed_uloadvnx2sf_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_indexed_oloadvnx4sf_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_indexed_uloadvnx4sf_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_indexed_oloadvnx8sf_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_indexed_uloadvnx8sf_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_indexed_oloadvnx16sf_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_indexed_uloadvnx16sf_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_indexed_oloadvnx1df_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_indexed_uloadvnx1df_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_indexed_oloadvnx2df_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_indexed_uloadvnx2df_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_indexed_oloadvnx4df_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_indexed_uloadvnx4df_x4_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_indexed_oloadvnx8df_x4_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_indexed_uloadvnx8df_x4_greater_eew;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_indexed_load_x4_greater_eew (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_indexed_load_x4_greater_eew (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_indexed_load_x8_greater_eew (int arg0, machine_mode arg1)
{
  if (arg0 == 71
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_oloadvnx1di_x8_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_uloadvnx1di_x8_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_oloadvnx2di_x8_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_uloadvnx2di_x8_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_oloadvnx4di_x8_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_uloadvnx4di_x8_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_oloadvnx8di_x8_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_uloadvnx8di_x8_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_indexed_oloadvnx1df_x8_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_indexed_uloadvnx1df_x8_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_indexed_oloadvnx2df_x8_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_indexed_uloadvnx2df_x8_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_indexed_oloadvnx4df_x8_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_indexed_uloadvnx4df_x8_greater_eew;
  if (arg0 == 71
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_indexed_oloadvnx8df_x8_greater_eew;
  if (arg0 == 72
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_indexed_uloadvnx8df_x8_greater_eew;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_indexed_load_x8_greater_eew (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_indexed_load_x8_greater_eew (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_indexed_load_x2_smaller_eew (int arg0, machine_mode arg1)
{
  if (arg0 == 71
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_oloadvnx1qi_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_uloadvnx1qi_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_oloadvnx2qi_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_uloadvnx2qi_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_oloadvnx4qi_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_uloadvnx4qi_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_oloadvnx8qi_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_uloadvnx8qi_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_oloadvnx16qi_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_uloadvnx16qi_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_indexed_oloadvnx32qi_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_indexed_uloadvnx32qi_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_oloadvnx1hi_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_uloadvnx1hi_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_oloadvnx2hi_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_uloadvnx2hi_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_oloadvnx4hi_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_uloadvnx4hi_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_oloadvnx8hi_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_uloadvnx8hi_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_oloadvnx16hi_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_uloadvnx16hi_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_oloadvnx1si_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_uloadvnx1si_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_oloadvnx2si_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_uloadvnx2si_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_oloadvnx4si_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_uloadvnx4si_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_oloadvnx8si_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_uloadvnx8si_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_indexed_oloadvnx1sf_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_indexed_uloadvnx1sf_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_indexed_oloadvnx2sf_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_indexed_uloadvnx2sf_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_indexed_oloadvnx4sf_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_indexed_uloadvnx4sf_x2_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_indexed_oloadvnx8sf_x2_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_indexed_uloadvnx8sf_x2_smaller_eew;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_indexed_load_x2_smaller_eew (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_indexed_load_x2_smaller_eew (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_indexed_load_x4_smaller_eew (int arg0, machine_mode arg1)
{
  if (arg0 == 71
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_oloadvnx1qi_x4_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_uloadvnx1qi_x4_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_oloadvnx2qi_x4_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_uloadvnx2qi_x4_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_oloadvnx4qi_x4_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_uloadvnx4qi_x4_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_oloadvnx8qi_x4_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_uloadvnx8qi_x4_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_oloadvnx16qi_x4_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_uloadvnx16qi_x4_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_oloadvnx1hi_x4_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_uloadvnx1hi_x4_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_oloadvnx2hi_x4_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_uloadvnx2hi_x4_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_oloadvnx4hi_x4_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_uloadvnx4hi_x4_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_oloadvnx8hi_x4_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_uloadvnx8hi_x4_smaller_eew;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_indexed_load_x4_smaller_eew (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_indexed_load_x4_smaller_eew (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_indexed_load_x8_smaller_eew (int arg0, machine_mode arg1)
{
  if (arg0 == 71
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_oloadvnx1qi_x8_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_uloadvnx1qi_x8_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_oloadvnx2qi_x8_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_uloadvnx2qi_x8_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_oloadvnx4qi_x8_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_uloadvnx4qi_x8_smaller_eew;
  if (arg0 == 71
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_oloadvnx8qi_x8_smaller_eew;
  if (arg0 == 72
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_uloadvnx8qi_x8_smaller_eew;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_indexed_load_x8_smaller_eew (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_indexed_load_x8_smaller_eew (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_indexed_store (int arg0, machine_mode arg1, machine_mode arg2)
{
  if (arg0 == 71
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_ostorevnx1qivnx1qi;
  if (arg0 == 72
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_ustorevnx1qivnx1qi;
  if (arg0 == 71
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_ostorevnx1qivnx1hi;
  if (arg0 == 72
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_ustorevnx1qivnx1hi;
  if (arg0 == 71
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_ostorevnx1qivnx1si;
  if (arg0 == 72
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_ustorevnx1qivnx1si;
  if (arg0 == 71
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_ostorevnx1qivnx1di;
  if (arg0 == 72
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_ustorevnx1qivnx1di;
  if (arg0 == 71
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_ostorevnx1hivnx1qi;
  if (arg0 == 72
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_ustorevnx1hivnx1qi;
  if (arg0 == 71
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_ostorevnx1hivnx1hi;
  if (arg0 == 72
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_ustorevnx1hivnx1hi;
  if (arg0 == 71
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_ostorevnx1hivnx1si;
  if (arg0 == 72
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_ustorevnx1hivnx1si;
  if (arg0 == 71
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_ostorevnx1hivnx1di;
  if (arg0 == 72
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_ustorevnx1hivnx1di;
  if (arg0 == 71
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_ostorevnx1sivnx1qi;
  if (arg0 == 72
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_ustorevnx1sivnx1qi;
  if (arg0 == 71
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_ostorevnx1sivnx1hi;
  if (arg0 == 72
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_ustorevnx1sivnx1hi;
  if (arg0 == 71
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_ostorevnx1sivnx1si;
  if (arg0 == 72
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_ustorevnx1sivnx1si;
  if (arg0 == 71
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_ostorevnx1sivnx1di;
  if (arg0 == 72
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_ustorevnx1sivnx1di;
  if (arg0 == 71
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_ostorevnx1divnx1qi;
  if (arg0 == 72
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_ustorevnx1divnx1qi;
  if (arg0 == 71
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_ostorevnx1divnx1hi;
  if (arg0 == 72
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_ustorevnx1divnx1hi;
  if (arg0 == 71
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_ostorevnx1divnx1si;
  if (arg0 == 72
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_ustorevnx1divnx1si;
  if (arg0 == 71
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_ostorevnx1divnx1di;
  if (arg0 == 72
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_ustorevnx1divnx1di;
  if (arg0 == 71
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_ostorevnx1sfvnx1qi;
  if (arg0 == 72
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_ustorevnx1sfvnx1qi;
  if (arg0 == 71
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_ostorevnx1sfvnx1hi;
  if (arg0 == 72
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_ustorevnx1sfvnx1hi;
  if (arg0 == 71
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_ostorevnx1sfvnx1si;
  if (arg0 == 72
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_ustorevnx1sfvnx1si;
  if (arg0 == 71
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_ostorevnx1sfvnx1di;
  if (arg0 == 72
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_ustorevnx1sfvnx1di;
  if (arg0 == 71
      && arg1 == E_VNx1DFmode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_ostorevnx1dfvnx1qi;
  if (arg0 == 72
      && arg1 == E_VNx1DFmode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_indexed_ustorevnx1dfvnx1qi;
  if (arg0 == 71
      && arg1 == E_VNx1DFmode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_ostorevnx1dfvnx1hi;
  if (arg0 == 72
      && arg1 == E_VNx1DFmode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_indexed_ustorevnx1dfvnx1hi;
  if (arg0 == 71
      && arg1 == E_VNx1DFmode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_ostorevnx1dfvnx1si;
  if (arg0 == 72
      && arg1 == E_VNx1DFmode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_indexed_ustorevnx1dfvnx1si;
  if (arg0 == 71
      && arg1 == E_VNx1DFmode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_ostorevnx1dfvnx1di;
  if (arg0 == 72
      && arg1 == E_VNx1DFmode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_indexed_ustorevnx1dfvnx1di;
  if (arg0 == 71
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_ostorevnx2qivnx2qi;
  if (arg0 == 72
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_ustorevnx2qivnx2qi;
  if (arg0 == 71
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_ostorevnx2hivnx2qi;
  if (arg0 == 72
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_ustorevnx2hivnx2qi;
  if (arg0 == 71
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_ostorevnx2sivnx2qi;
  if (arg0 == 72
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_ustorevnx2sivnx2qi;
  if (arg0 == 71
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_ostorevnx2divnx2qi;
  if (arg0 == 72
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_ustorevnx2divnx2qi;
  if (arg0 == 71
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_ostorevnx2sfvnx2qi;
  if (arg0 == 72
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_ustorevnx2sfvnx2qi;
  if (arg0 == 71
      && arg1 == E_VNx2DFmode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_ostorevnx2dfvnx2qi;
  if (arg0 == 72
      && arg1 == E_VNx2DFmode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_indexed_ustorevnx2dfvnx2qi;
  if (arg0 == 71
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_ostorevnx2qivnx2hi;
  if (arg0 == 72
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_ustorevnx2qivnx2hi;
  if (arg0 == 71
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_ostorevnx2hivnx2hi;
  if (arg0 == 72
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_ustorevnx2hivnx2hi;
  if (arg0 == 71
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_ostorevnx2sivnx2hi;
  if (arg0 == 72
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_ustorevnx2sivnx2hi;
  if (arg0 == 71
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_ostorevnx2divnx2hi;
  if (arg0 == 72
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_ustorevnx2divnx2hi;
  if (arg0 == 71
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_ostorevnx2sfvnx2hi;
  if (arg0 == 72
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_ustorevnx2sfvnx2hi;
  if (arg0 == 71
      && arg1 == E_VNx2DFmode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_ostorevnx2dfvnx2hi;
  if (arg0 == 72
      && arg1 == E_VNx2DFmode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_indexed_ustorevnx2dfvnx2hi;
  if (arg0 == 71
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_ostorevnx2qivnx2si;
  if (arg0 == 72
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_ustorevnx2qivnx2si;
  if (arg0 == 71
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_ostorevnx2hivnx2si;
  if (arg0 == 72
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_ustorevnx2hivnx2si;
  if (arg0 == 71
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_ostorevnx2sivnx2si;
  if (arg0 == 72
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_ustorevnx2sivnx2si;
  if (arg0 == 71
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_ostorevnx2divnx2si;
  if (arg0 == 72
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_ustorevnx2divnx2si;
  if (arg0 == 71
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_ostorevnx2sfvnx2si;
  if (arg0 == 72
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_ustorevnx2sfvnx2si;
  if (arg0 == 71
      && arg1 == E_VNx2DFmode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_ostorevnx2dfvnx2si;
  if (arg0 == 72
      && arg1 == E_VNx2DFmode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_indexed_ustorevnx2dfvnx2si;
  if (arg0 == 71
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_ostorevnx2qivnx2di;
  if (arg0 == 72
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_ustorevnx2qivnx2di;
  if (arg0 == 71
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_ostorevnx2hivnx2di;
  if (arg0 == 72
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_ustorevnx2hivnx2di;
  if (arg0 == 71
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_ostorevnx2sivnx2di;
  if (arg0 == 72
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_ustorevnx2sivnx2di;
  if (arg0 == 71
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_ostorevnx2divnx2di;
  if (arg0 == 72
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_ustorevnx2divnx2di;
  if (arg0 == 71
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_ostorevnx2sfvnx2di;
  if (arg0 == 72
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_ustorevnx2sfvnx2di;
  if (arg0 == 71
      && arg1 == E_VNx2DFmode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_ostorevnx2dfvnx2di;
  if (arg0 == 72
      && arg1 == E_VNx2DFmode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_indexed_ustorevnx2dfvnx2di;
  if (arg0 == 71
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_ostorevnx4qivnx4qi;
  if (arg0 == 72
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_ustorevnx4qivnx4qi;
  if (arg0 == 71
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_ostorevnx4hivnx4qi;
  if (arg0 == 72
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_ustorevnx4hivnx4qi;
  if (arg0 == 71
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_ostorevnx4sivnx4qi;
  if (arg0 == 72
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_ustorevnx4sivnx4qi;
  if (arg0 == 71
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_ostorevnx4divnx4qi;
  if (arg0 == 72
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_ustorevnx4divnx4qi;
  if (arg0 == 71
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_ostorevnx4sfvnx4qi;
  if (arg0 == 72
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_ustorevnx4sfvnx4qi;
  if (arg0 == 71
      && arg1 == E_VNx4DFmode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_ostorevnx4dfvnx4qi;
  if (arg0 == 72
      && arg1 == E_VNx4DFmode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_indexed_ustorevnx4dfvnx4qi;
  if (arg0 == 71
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_ostorevnx4qivnx4hi;
  if (arg0 == 72
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_ustorevnx4qivnx4hi;
  if (arg0 == 71
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_ostorevnx4hivnx4hi;
  if (arg0 == 72
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_ustorevnx4hivnx4hi;
  if (arg0 == 71
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_ostorevnx4sivnx4hi;
  if (arg0 == 72
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_ustorevnx4sivnx4hi;
  if (arg0 == 71
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_ostorevnx4divnx4hi;
  if (arg0 == 72
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_ustorevnx4divnx4hi;
  if (arg0 == 71
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_ostorevnx4sfvnx4hi;
  if (arg0 == 72
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_ustorevnx4sfvnx4hi;
  if (arg0 == 71
      && arg1 == E_VNx4DFmode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_ostorevnx4dfvnx4hi;
  if (arg0 == 72
      && arg1 == E_VNx4DFmode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_indexed_ustorevnx4dfvnx4hi;
  if (arg0 == 71
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_ostorevnx4qivnx4si;
  if (arg0 == 72
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_ustorevnx4qivnx4si;
  if (arg0 == 71
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_ostorevnx4hivnx4si;
  if (arg0 == 72
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_ustorevnx4hivnx4si;
  if (arg0 == 71
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_ostorevnx4sivnx4si;
  if (arg0 == 72
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_ustorevnx4sivnx4si;
  if (arg0 == 71
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_ostorevnx4divnx4si;
  if (arg0 == 72
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_ustorevnx4divnx4si;
  if (arg0 == 71
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_ostorevnx4sfvnx4si;
  if (arg0 == 72
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_ustorevnx4sfvnx4si;
  if (arg0 == 71
      && arg1 == E_VNx4DFmode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_ostorevnx4dfvnx4si;
  if (arg0 == 72
      && arg1 == E_VNx4DFmode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_indexed_ustorevnx4dfvnx4si;
  if (arg0 == 71
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_ostorevnx4qivnx4di;
  if (arg0 == 72
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_ustorevnx4qivnx4di;
  if (arg0 == 71
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_ostorevnx4hivnx4di;
  if (arg0 == 72
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_ustorevnx4hivnx4di;
  if (arg0 == 71
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_ostorevnx4sivnx4di;
  if (arg0 == 72
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_ustorevnx4sivnx4di;
  if (arg0 == 71
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_ostorevnx4divnx4di;
  if (arg0 == 72
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_ustorevnx4divnx4di;
  if (arg0 == 71
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_ostorevnx4sfvnx4di;
  if (arg0 == 72
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_ustorevnx4sfvnx4di;
  if (arg0 == 71
      && arg1 == E_VNx4DFmode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_ostorevnx4dfvnx4di;
  if (arg0 == 72
      && arg1 == E_VNx4DFmode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_indexed_ustorevnx4dfvnx4di;
  if (arg0 == 71
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_ostorevnx8qivnx8qi;
  if (arg0 == 72
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_ustorevnx8qivnx8qi;
  if (arg0 == 71
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_ostorevnx8hivnx8qi;
  if (arg0 == 72
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_ustorevnx8hivnx8qi;
  if (arg0 == 71
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_ostorevnx8sivnx8qi;
  if (arg0 == 72
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_ustorevnx8sivnx8qi;
  if (arg0 == 71
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_ostorevnx8divnx8qi;
  if (arg0 == 72
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_ustorevnx8divnx8qi;
  if (arg0 == 71
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_ostorevnx8sfvnx8qi;
  if (arg0 == 72
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_ustorevnx8sfvnx8qi;
  if (arg0 == 71
      && arg1 == E_VNx8DFmode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_ostorevnx8dfvnx8qi;
  if (arg0 == 72
      && arg1 == E_VNx8DFmode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_indexed_ustorevnx8dfvnx8qi;
  if (arg0 == 71
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_ostorevnx8qivnx8hi;
  if (arg0 == 72
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_ustorevnx8qivnx8hi;
  if (arg0 == 71
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_ostorevnx8hivnx8hi;
  if (arg0 == 72
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_ustorevnx8hivnx8hi;
  if (arg0 == 71
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_ostorevnx8sivnx8hi;
  if (arg0 == 72
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_ustorevnx8sivnx8hi;
  if (arg0 == 71
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_ostorevnx8divnx8hi;
  if (arg0 == 72
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_ustorevnx8divnx8hi;
  if (arg0 == 71
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_ostorevnx8sfvnx8hi;
  if (arg0 == 72
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_ustorevnx8sfvnx8hi;
  if (arg0 == 71
      && arg1 == E_VNx8DFmode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_ostorevnx8dfvnx8hi;
  if (arg0 == 72
      && arg1 == E_VNx8DFmode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_indexed_ustorevnx8dfvnx8hi;
  if (arg0 == 71
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_ostorevnx8qivnx8si;
  if (arg0 == 72
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_ustorevnx8qivnx8si;
  if (arg0 == 71
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_ostorevnx8hivnx8si;
  if (arg0 == 72
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_ustorevnx8hivnx8si;
  if (arg0 == 71
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_ostorevnx8sivnx8si;
  if (arg0 == 72
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_ustorevnx8sivnx8si;
  if (arg0 == 71
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_ostorevnx8divnx8si;
  if (arg0 == 72
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_ustorevnx8divnx8si;
  if (arg0 == 71
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_ostorevnx8sfvnx8si;
  if (arg0 == 72
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_ustorevnx8sfvnx8si;
  if (arg0 == 71
      && arg1 == E_VNx8DFmode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_ostorevnx8dfvnx8si;
  if (arg0 == 72
      && arg1 == E_VNx8DFmode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_indexed_ustorevnx8dfvnx8si;
  if (arg0 == 71
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_ostorevnx8qivnx8di;
  if (arg0 == 72
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_ustorevnx8qivnx8di;
  if (arg0 == 71
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_ostorevnx8hivnx8di;
  if (arg0 == 72
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_ustorevnx8hivnx8di;
  if (arg0 == 71
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_ostorevnx8sivnx8di;
  if (arg0 == 72
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_ustorevnx8sivnx8di;
  if (arg0 == 71
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_ostorevnx8divnx8di;
  if (arg0 == 72
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_ustorevnx8divnx8di;
  if (arg0 == 71
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_ostorevnx8sfvnx8di;
  if (arg0 == 72
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_ustorevnx8sfvnx8di;
  if (arg0 == 71
      && arg1 == E_VNx8DFmode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_ostorevnx8dfvnx8di;
  if (arg0 == 72
      && arg1 == E_VNx8DFmode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_indexed_ustorevnx8dfvnx8di;
  if (arg0 == 71
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_ostorevnx16qivnx16qi;
  if (arg0 == 72
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_ustorevnx16qivnx16qi;
  if (arg0 == 71
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_ostorevnx16hivnx16qi;
  if (arg0 == 72
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_ustorevnx16hivnx16qi;
  if (arg0 == 71
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_ostorevnx16sivnx16qi;
  if (arg0 == 72
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_ustorevnx16sivnx16qi;
  if (arg0 == 71
      && arg1 == E_VNx16SFmode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_ostorevnx16sfvnx16qi;
  if (arg0 == 72
      && arg1 == E_VNx16SFmode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_indexed_ustorevnx16sfvnx16qi;
  if (arg0 == 71
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_ostorevnx16qivnx16hi;
  if (arg0 == 72
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_ustorevnx16qivnx16hi;
  if (arg0 == 71
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_ostorevnx16hivnx16hi;
  if (arg0 == 72
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_ustorevnx16hivnx16hi;
  if (arg0 == 71
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_ostorevnx16sivnx16hi;
  if (arg0 == 72
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_ustorevnx16sivnx16hi;
  if (arg0 == 71
      && arg1 == E_VNx16SFmode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_ostorevnx16sfvnx16hi;
  if (arg0 == 72
      && arg1 == E_VNx16SFmode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_indexed_ustorevnx16sfvnx16hi;
  if (arg0 == 71
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_ostorevnx16qivnx16si;
  if (arg0 == 72
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_ustorevnx16qivnx16si;
  if (arg0 == 71
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_ostorevnx16hivnx16si;
  if (arg0 == 72
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_ustorevnx16hivnx16si;
  if (arg0 == 71
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_ostorevnx16sivnx16si;
  if (arg0 == 72
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_ustorevnx16sivnx16si;
  if (arg0 == 71
      && arg1 == E_VNx16SFmode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_ostorevnx16sfvnx16si;
  if (arg0 == 72
      && arg1 == E_VNx16SFmode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_indexed_ustorevnx16sfvnx16si;
  if (arg0 == 71
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_indexed_ostorevnx32qivnx32qi;
  if (arg0 == 72
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_indexed_ustorevnx32qivnx32qi;
  if (arg0 == 71
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_indexed_ostorevnx32qivnx32hi;
  if (arg0 == 72
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_indexed_ustorevnx32qivnx32hi;
  if (arg0 == 71
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_indexed_ostorevnx32hivnx32qi;
  if (arg0 == 72
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_indexed_ustorevnx32hivnx32qi;
  if (arg0 == 71
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_indexed_ostorevnx32hivnx32hi;
  if (arg0 == 72
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_indexed_ustorevnx32hivnx32hi;
  if (arg0 == 71
      && arg1 == E_VNx64QImode
      && arg2 == E_VNx64QImode)
    return CODE_FOR_pred_indexed_ostorevnx64qivnx64qi;
  if (arg0 == 72
      && arg1 == E_VNx64QImode
      && arg2 == E_VNx64QImode)
    return CODE_FOR_pred_indexed_ustorevnx64qivnx64qi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_indexed_store (int arg0, machine_mode arg1, machine_mode arg2, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5)
{
  insn_code code = maybe_code_for_pred_indexed_store (arg0, arg1, arg2);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 6);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_addvnx1qi;
  if (arg0 == MINUS
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_subvnx1qi;
  if (arg0 == AND
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_andvnx1qi;
  if (arg0 == IOR
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_iorvnx1qi;
  if (arg0 == XOR
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_xorvnx1qi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_ashlvnx1qi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_ashrvnx1qi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_lshrvnx1qi;
  if (arg0 == SMAX
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_smaxvnx1qi;
  if (arg0 == UMAX
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_umaxvnx1qi;
  if (arg0 == SMIN
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_sminvnx1qi;
  if (arg0 == UMIN
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_uminvnx1qi;
  if (arg0 == MULT
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_mulvnx1qi;
  if (arg0 == DIV
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_divvnx1qi;
  if (arg0 == UDIV
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_udivvnx1qi;
  if (arg0 == MOD
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_modvnx1qi;
  if (arg0 == UMOD
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_umodvnx1qi;
  if (arg0 == PLUS
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_addvnx2qi;
  if (arg0 == MINUS
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_subvnx2qi;
  if (arg0 == AND
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_andvnx2qi;
  if (arg0 == IOR
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_iorvnx2qi;
  if (arg0 == XOR
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_xorvnx2qi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_ashlvnx2qi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_ashrvnx2qi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_lshrvnx2qi;
  if (arg0 == SMAX
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_smaxvnx2qi;
  if (arg0 == UMAX
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_umaxvnx2qi;
  if (arg0 == SMIN
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_sminvnx2qi;
  if (arg0 == UMIN
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_uminvnx2qi;
  if (arg0 == MULT
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_mulvnx2qi;
  if (arg0 == DIV
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_divvnx2qi;
  if (arg0 == UDIV
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_udivvnx2qi;
  if (arg0 == MOD
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_modvnx2qi;
  if (arg0 == UMOD
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_umodvnx2qi;
  if (arg0 == PLUS
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_addvnx4qi;
  if (arg0 == MINUS
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_subvnx4qi;
  if (arg0 == AND
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_andvnx4qi;
  if (arg0 == IOR
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_iorvnx4qi;
  if (arg0 == XOR
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_xorvnx4qi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_ashlvnx4qi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_ashrvnx4qi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_lshrvnx4qi;
  if (arg0 == SMAX
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_smaxvnx4qi;
  if (arg0 == UMAX
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_umaxvnx4qi;
  if (arg0 == SMIN
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_sminvnx4qi;
  if (arg0 == UMIN
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_uminvnx4qi;
  if (arg0 == MULT
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_mulvnx4qi;
  if (arg0 == DIV
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_divvnx4qi;
  if (arg0 == UDIV
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_udivvnx4qi;
  if (arg0 == MOD
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_modvnx4qi;
  if (arg0 == UMOD
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_umodvnx4qi;
  if (arg0 == PLUS
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_addvnx8qi;
  if (arg0 == MINUS
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_subvnx8qi;
  if (arg0 == AND
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_andvnx8qi;
  if (arg0 == IOR
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_iorvnx8qi;
  if (arg0 == XOR
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_xorvnx8qi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_ashlvnx8qi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_ashrvnx8qi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_lshrvnx8qi;
  if (arg0 == SMAX
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_smaxvnx8qi;
  if (arg0 == UMAX
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_umaxvnx8qi;
  if (arg0 == SMIN
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_sminvnx8qi;
  if (arg0 == UMIN
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_uminvnx8qi;
  if (arg0 == MULT
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_mulvnx8qi;
  if (arg0 == DIV
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_divvnx8qi;
  if (arg0 == UDIV
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_udivvnx8qi;
  if (arg0 == MOD
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_modvnx8qi;
  if (arg0 == UMOD
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_umodvnx8qi;
  if (arg0 == PLUS
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_addvnx16qi;
  if (arg0 == MINUS
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_subvnx16qi;
  if (arg0 == AND
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_andvnx16qi;
  if (arg0 == IOR
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_iorvnx16qi;
  if (arg0 == XOR
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_xorvnx16qi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_ashlvnx16qi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_ashrvnx16qi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_lshrvnx16qi;
  if (arg0 == SMAX
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_smaxvnx16qi;
  if (arg0 == UMAX
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_umaxvnx16qi;
  if (arg0 == SMIN
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_sminvnx16qi;
  if (arg0 == UMIN
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_uminvnx16qi;
  if (arg0 == MULT
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_mulvnx16qi;
  if (arg0 == DIV
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_divvnx16qi;
  if (arg0 == UDIV
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_udivvnx16qi;
  if (arg0 == MOD
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_modvnx16qi;
  if (arg0 == UMOD
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_umodvnx16qi;
  if (arg0 == PLUS
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_addvnx32qi;
  if (arg0 == MINUS
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_subvnx32qi;
  if (arg0 == AND
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_andvnx32qi;
  if (arg0 == IOR
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_iorvnx32qi;
  if (arg0 == XOR
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_xorvnx32qi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_ashlvnx32qi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_ashrvnx32qi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_lshrvnx32qi;
  if (arg0 == SMAX
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_smaxvnx32qi;
  if (arg0 == UMAX
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_umaxvnx32qi;
  if (arg0 == SMIN
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_sminvnx32qi;
  if (arg0 == UMIN
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_uminvnx32qi;
  if (arg0 == MULT
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_mulvnx32qi;
  if (arg0 == DIV
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_divvnx32qi;
  if (arg0 == UDIV
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_udivvnx32qi;
  if (arg0 == MOD
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_modvnx32qi;
  if (arg0 == UMOD
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_umodvnx32qi;
  if (arg0 == PLUS
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_addvnx64qi;
  if (arg0 == MINUS
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_subvnx64qi;
  if (arg0 == AND
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_andvnx64qi;
  if (arg0 == IOR
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_iorvnx64qi;
  if (arg0 == XOR
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_xorvnx64qi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_ashlvnx64qi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_ashrvnx64qi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_lshrvnx64qi;
  if (arg0 == SMAX
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_smaxvnx64qi;
  if (arg0 == UMAX
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_umaxvnx64qi;
  if (arg0 == SMIN
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_sminvnx64qi;
  if (arg0 == UMIN
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_uminvnx64qi;
  if (arg0 == MULT
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_mulvnx64qi;
  if (arg0 == DIV
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_divvnx64qi;
  if (arg0 == UDIV
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_udivvnx64qi;
  if (arg0 == MOD
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_modvnx64qi;
  if (arg0 == UMOD
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_umodvnx64qi;
  if (arg0 == PLUS
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_addvnx1hi;
  if (arg0 == MINUS
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_subvnx1hi;
  if (arg0 == AND
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_andvnx1hi;
  if (arg0 == IOR
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_iorvnx1hi;
  if (arg0 == XOR
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_xorvnx1hi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_ashlvnx1hi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_ashrvnx1hi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_lshrvnx1hi;
  if (arg0 == SMAX
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_smaxvnx1hi;
  if (arg0 == UMAX
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_umaxvnx1hi;
  if (arg0 == SMIN
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_sminvnx1hi;
  if (arg0 == UMIN
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_uminvnx1hi;
  if (arg0 == MULT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_mulvnx1hi;
  if (arg0 == DIV
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_divvnx1hi;
  if (arg0 == UDIV
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_udivvnx1hi;
  if (arg0 == MOD
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_modvnx1hi;
  if (arg0 == UMOD
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_umodvnx1hi;
  if (arg0 == PLUS
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_addvnx2hi;
  if (arg0 == MINUS
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_subvnx2hi;
  if (arg0 == AND
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_andvnx2hi;
  if (arg0 == IOR
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_iorvnx2hi;
  if (arg0 == XOR
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_xorvnx2hi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_ashlvnx2hi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_ashrvnx2hi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_lshrvnx2hi;
  if (arg0 == SMAX
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_smaxvnx2hi;
  if (arg0 == UMAX
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_umaxvnx2hi;
  if (arg0 == SMIN
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_sminvnx2hi;
  if (arg0 == UMIN
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_uminvnx2hi;
  if (arg0 == MULT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_mulvnx2hi;
  if (arg0 == DIV
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_divvnx2hi;
  if (arg0 == UDIV
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_udivvnx2hi;
  if (arg0 == MOD
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_modvnx2hi;
  if (arg0 == UMOD
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_umodvnx2hi;
  if (arg0 == PLUS
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_addvnx4hi;
  if (arg0 == MINUS
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_subvnx4hi;
  if (arg0 == AND
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_andvnx4hi;
  if (arg0 == IOR
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_iorvnx4hi;
  if (arg0 == XOR
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_xorvnx4hi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_ashlvnx4hi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_ashrvnx4hi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_lshrvnx4hi;
  if (arg0 == SMAX
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_smaxvnx4hi;
  if (arg0 == UMAX
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_umaxvnx4hi;
  if (arg0 == SMIN
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_sminvnx4hi;
  if (arg0 == UMIN
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_uminvnx4hi;
  if (arg0 == MULT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_mulvnx4hi;
  if (arg0 == DIV
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_divvnx4hi;
  if (arg0 == UDIV
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_udivvnx4hi;
  if (arg0 == MOD
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_modvnx4hi;
  if (arg0 == UMOD
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_umodvnx4hi;
  if (arg0 == PLUS
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_addvnx8hi;
  if (arg0 == MINUS
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_subvnx8hi;
  if (arg0 == AND
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_andvnx8hi;
  if (arg0 == IOR
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_iorvnx8hi;
  if (arg0 == XOR
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_xorvnx8hi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_ashlvnx8hi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_ashrvnx8hi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_lshrvnx8hi;
  if (arg0 == SMAX
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_smaxvnx8hi;
  if (arg0 == UMAX
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_umaxvnx8hi;
  if (arg0 == SMIN
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_sminvnx8hi;
  if (arg0 == UMIN
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_uminvnx8hi;
  if (arg0 == MULT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_mulvnx8hi;
  if (arg0 == DIV
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_divvnx8hi;
  if (arg0 == UDIV
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_udivvnx8hi;
  if (arg0 == MOD
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_modvnx8hi;
  if (arg0 == UMOD
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_umodvnx8hi;
  if (arg0 == PLUS
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_addvnx16hi;
  if (arg0 == MINUS
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_subvnx16hi;
  if (arg0 == AND
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_andvnx16hi;
  if (arg0 == IOR
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_iorvnx16hi;
  if (arg0 == XOR
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_xorvnx16hi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_ashlvnx16hi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_ashrvnx16hi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_lshrvnx16hi;
  if (arg0 == SMAX
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_smaxvnx16hi;
  if (arg0 == UMAX
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_umaxvnx16hi;
  if (arg0 == SMIN
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_sminvnx16hi;
  if (arg0 == UMIN
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_uminvnx16hi;
  if (arg0 == MULT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_mulvnx16hi;
  if (arg0 == DIV
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_divvnx16hi;
  if (arg0 == UDIV
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_udivvnx16hi;
  if (arg0 == MOD
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_modvnx16hi;
  if (arg0 == UMOD
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_umodvnx16hi;
  if (arg0 == PLUS
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_addvnx32hi;
  if (arg0 == MINUS
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_subvnx32hi;
  if (arg0 == AND
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_andvnx32hi;
  if (arg0 == IOR
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_iorvnx32hi;
  if (arg0 == XOR
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_xorvnx32hi;
  if (arg0 == ASHIFT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_ashlvnx32hi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_ashrvnx32hi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_lshrvnx32hi;
  if (arg0 == SMAX
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_smaxvnx32hi;
  if (arg0 == UMAX
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_umaxvnx32hi;
  if (arg0 == SMIN
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_sminvnx32hi;
  if (arg0 == UMIN
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_uminvnx32hi;
  if (arg0 == MULT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_mulvnx32hi;
  if (arg0 == DIV
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_divvnx32hi;
  if (arg0 == UDIV
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_udivvnx32hi;
  if (arg0 == MOD
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_modvnx32hi;
  if (arg0 == UMOD
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_umodvnx32hi;
  if (arg0 == PLUS
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_addvnx1si;
  if (arg0 == MINUS
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_subvnx1si;
  if (arg0 == AND
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_andvnx1si;
  if (arg0 == IOR
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_iorvnx1si;
  if (arg0 == XOR
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_xorvnx1si;
  if (arg0 == ASHIFT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_ashlvnx1si;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_ashrvnx1si;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_lshrvnx1si;
  if (arg0 == SMAX
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_smaxvnx1si;
  if (arg0 == UMAX
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_umaxvnx1si;
  if (arg0 == SMIN
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_sminvnx1si;
  if (arg0 == UMIN
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_uminvnx1si;
  if (arg0 == MULT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_mulvnx1si;
  if (arg0 == DIV
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_divvnx1si;
  if (arg0 == UDIV
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_udivvnx1si;
  if (arg0 == MOD
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_modvnx1si;
  if (arg0 == UMOD
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_umodvnx1si;
  if (arg0 == PLUS
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_addvnx2si;
  if (arg0 == MINUS
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_subvnx2si;
  if (arg0 == AND
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_andvnx2si;
  if (arg0 == IOR
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_iorvnx2si;
  if (arg0 == XOR
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_xorvnx2si;
  if (arg0 == ASHIFT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_ashlvnx2si;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_ashrvnx2si;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_lshrvnx2si;
  if (arg0 == SMAX
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_smaxvnx2si;
  if (arg0 == UMAX
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_umaxvnx2si;
  if (arg0 == SMIN
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_sminvnx2si;
  if (arg0 == UMIN
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_uminvnx2si;
  if (arg0 == MULT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_mulvnx2si;
  if (arg0 == DIV
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_divvnx2si;
  if (arg0 == UDIV
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_udivvnx2si;
  if (arg0 == MOD
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_modvnx2si;
  if (arg0 == UMOD
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_umodvnx2si;
  if (arg0 == PLUS
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_addvnx4si;
  if (arg0 == MINUS
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_subvnx4si;
  if (arg0 == AND
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_andvnx4si;
  if (arg0 == IOR
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_iorvnx4si;
  if (arg0 == XOR
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_xorvnx4si;
  if (arg0 == ASHIFT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_ashlvnx4si;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_ashrvnx4si;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_lshrvnx4si;
  if (arg0 == SMAX
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_smaxvnx4si;
  if (arg0 == UMAX
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_umaxvnx4si;
  if (arg0 == SMIN
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_sminvnx4si;
  if (arg0 == UMIN
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_uminvnx4si;
  if (arg0 == MULT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_mulvnx4si;
  if (arg0 == DIV
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_divvnx4si;
  if (arg0 == UDIV
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_udivvnx4si;
  if (arg0 == MOD
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_modvnx4si;
  if (arg0 == UMOD
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_umodvnx4si;
  if (arg0 == PLUS
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_addvnx8si;
  if (arg0 == MINUS
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_subvnx8si;
  if (arg0 == AND
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_andvnx8si;
  if (arg0 == IOR
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_iorvnx8si;
  if (arg0 == XOR
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_xorvnx8si;
  if (arg0 == ASHIFT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_ashlvnx8si;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_ashrvnx8si;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_lshrvnx8si;
  if (arg0 == SMAX
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_smaxvnx8si;
  if (arg0 == UMAX
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_umaxvnx8si;
  if (arg0 == SMIN
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_sminvnx8si;
  if (arg0 == UMIN
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_uminvnx8si;
  if (arg0 == MULT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_mulvnx8si;
  if (arg0 == DIV
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_divvnx8si;
  if (arg0 == UDIV
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_udivvnx8si;
  if (arg0 == MOD
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_modvnx8si;
  if (arg0 == UMOD
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_umodvnx8si;
  if (arg0 == PLUS
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_addvnx16si;
  if (arg0 == MINUS
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_subvnx16si;
  if (arg0 == AND
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_andvnx16si;
  if (arg0 == IOR
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_iorvnx16si;
  if (arg0 == XOR
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_xorvnx16si;
  if (arg0 == ASHIFT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_ashlvnx16si;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_ashrvnx16si;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_lshrvnx16si;
  if (arg0 == SMAX
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_smaxvnx16si;
  if (arg0 == UMAX
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_umaxvnx16si;
  if (arg0 == SMIN
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_sminvnx16si;
  if (arg0 == UMIN
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_uminvnx16si;
  if (arg0 == MULT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_mulvnx16si;
  if (arg0 == DIV
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_divvnx16si;
  if (arg0 == UDIV
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_udivvnx16si;
  if (arg0 == MOD
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_modvnx16si;
  if (arg0 == UMOD
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_umodvnx16si;
  if (arg0 == PLUS
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_addvnx1di;
  if (arg0 == MINUS
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_subvnx1di;
  if (arg0 == AND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_andvnx1di;
  if (arg0 == IOR
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_iorvnx1di;
  if (arg0 == XOR
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_xorvnx1di;
  if (arg0 == ASHIFT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_ashlvnx1di;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_ashrvnx1di;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_lshrvnx1di;
  if (arg0 == SMAX
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_smaxvnx1di;
  if (arg0 == UMAX
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_umaxvnx1di;
  if (arg0 == SMIN
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_sminvnx1di;
  if (arg0 == UMIN
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_uminvnx1di;
  if (arg0 == MULT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_mulvnx1di;
  if (arg0 == DIV
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_divvnx1di;
  if (arg0 == UDIV
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_udivvnx1di;
  if (arg0 == MOD
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_modvnx1di;
  if (arg0 == UMOD
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_umodvnx1di;
  if (arg0 == PLUS
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_addvnx2di;
  if (arg0 == MINUS
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_subvnx2di;
  if (arg0 == AND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_andvnx2di;
  if (arg0 == IOR
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_iorvnx2di;
  if (arg0 == XOR
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_xorvnx2di;
  if (arg0 == ASHIFT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_ashlvnx2di;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_ashrvnx2di;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_lshrvnx2di;
  if (arg0 == SMAX
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_smaxvnx2di;
  if (arg0 == UMAX
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_umaxvnx2di;
  if (arg0 == SMIN
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_sminvnx2di;
  if (arg0 == UMIN
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_uminvnx2di;
  if (arg0 == MULT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_mulvnx2di;
  if (arg0 == DIV
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_divvnx2di;
  if (arg0 == UDIV
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_udivvnx2di;
  if (arg0 == MOD
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_modvnx2di;
  if (arg0 == UMOD
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_umodvnx2di;
  if (arg0 == PLUS
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_addvnx4di;
  if (arg0 == MINUS
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_subvnx4di;
  if (arg0 == AND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_andvnx4di;
  if (arg0 == IOR
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_iorvnx4di;
  if (arg0 == XOR
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_xorvnx4di;
  if (arg0 == ASHIFT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_ashlvnx4di;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_ashrvnx4di;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_lshrvnx4di;
  if (arg0 == SMAX
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_smaxvnx4di;
  if (arg0 == UMAX
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_umaxvnx4di;
  if (arg0 == SMIN
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_sminvnx4di;
  if (arg0 == UMIN
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_uminvnx4di;
  if (arg0 == MULT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_mulvnx4di;
  if (arg0 == DIV
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_divvnx4di;
  if (arg0 == UDIV
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_udivvnx4di;
  if (arg0 == MOD
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_modvnx4di;
  if (arg0 == UMOD
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_umodvnx4di;
  if (arg0 == PLUS
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_addvnx8di;
  if (arg0 == MINUS
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_subvnx8di;
  if (arg0 == AND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_andvnx8di;
  if (arg0 == IOR
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_iorvnx8di;
  if (arg0 == XOR
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_xorvnx8di;
  if (arg0 == ASHIFT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_ashlvnx8di;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_ashrvnx8di;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_lshrvnx8di;
  if (arg0 == SMAX
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_smaxvnx8di;
  if (arg0 == UMAX
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_umaxvnx8di;
  if (arg0 == SMIN
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_sminvnx8di;
  if (arg0 == UMIN
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_uminvnx8di;
  if (arg0 == MULT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_mulvnx8di;
  if (arg0 == DIV
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_divvnx8di;
  if (arg0 == UDIV
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_udivvnx8di;
  if (arg0 == MOD
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_modvnx8di;
  if (arg0 == UMOD
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_umodvnx8di;
  if (arg0 == NEG
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_negvnx1qi;
  if (arg0 == NOT
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_one_cmplvnx1qi;
  if (arg0 == NEG
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_negvnx2qi;
  if (arg0 == NOT
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_one_cmplvnx2qi;
  if (arg0 == NEG
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_negvnx4qi;
  if (arg0 == NOT
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_one_cmplvnx4qi;
  if (arg0 == NEG
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_negvnx8qi;
  if (arg0 == NOT
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_one_cmplvnx8qi;
  if (arg0 == NEG
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_negvnx16qi;
  if (arg0 == NOT
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_one_cmplvnx16qi;
  if (arg0 == NEG
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_negvnx32qi;
  if (arg0 == NOT
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_one_cmplvnx32qi;
  if (arg0 == NEG
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_negvnx64qi;
  if (arg0 == NOT
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_one_cmplvnx64qi;
  if (arg0 == NEG
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_negvnx1hi;
  if (arg0 == NOT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_one_cmplvnx1hi;
  if (arg0 == NEG
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_negvnx2hi;
  if (arg0 == NOT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_one_cmplvnx2hi;
  if (arg0 == NEG
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_negvnx4hi;
  if (arg0 == NOT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_one_cmplvnx4hi;
  if (arg0 == NEG
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_negvnx8hi;
  if (arg0 == NOT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_one_cmplvnx8hi;
  if (arg0 == NEG
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_negvnx16hi;
  if (arg0 == NOT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_one_cmplvnx16hi;
  if (arg0 == NEG
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_negvnx32hi;
  if (arg0 == NOT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_one_cmplvnx32hi;
  if (arg0 == NEG
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_negvnx1si;
  if (arg0 == NOT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_one_cmplvnx1si;
  if (arg0 == NEG
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_negvnx2si;
  if (arg0 == NOT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_one_cmplvnx2si;
  if (arg0 == NEG
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_negvnx4si;
  if (arg0 == NOT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_one_cmplvnx4si;
  if (arg0 == NEG
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_negvnx8si;
  if (arg0 == NOT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_one_cmplvnx8si;
  if (arg0 == NEG
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_negvnx16si;
  if (arg0 == NOT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_one_cmplvnx16si;
  if (arg0 == NEG
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_negvnx1di;
  if (arg0 == NOT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_one_cmplvnx1di;
  if (arg0 == NEG
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_negvnx2di;
  if (arg0 == NOT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_one_cmplvnx2di;
  if (arg0 == NEG
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_negvnx4di;
  if (arg0 == NOT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_one_cmplvnx4di;
  if (arg0 == NEG
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_negvnx8di;
  if (arg0 == NOT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_one_cmplvnx8di;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_extendvnx1hi;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_zero_extendvnx1hi;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_extendvnx2hi;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_zero_extendvnx2hi;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_extendvnx4hi;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_zero_extendvnx4hi;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_extendvnx8hi;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_zero_extendvnx8hi;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_extendvnx16hi;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_zero_extendvnx16hi;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_extendvnx32hi;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_zero_extendvnx32hi;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_extendvnx1si;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_zero_extendvnx1si;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_extendvnx2si;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_zero_extendvnx2si;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_extendvnx4si;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_zero_extendvnx4si;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_extendvnx8si;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_zero_extendvnx8si;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_extendvnx16si;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_zero_extendvnx16si;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_extendvnx1di;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_zero_extendvnx1di;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_extendvnx2di;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_zero_extendvnx2di;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_extendvnx4di;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_zero_extendvnx4di;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_extendvnx8di;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_zero_extendvnx8di;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_ssaddvnx1qi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_sssubvnx1qi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_usaddvnx1qi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_ussubvnx1qi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_ssaddvnx2qi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_sssubvnx2qi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_usaddvnx2qi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_ussubvnx2qi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_ssaddvnx4qi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_sssubvnx4qi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_usaddvnx4qi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_ussubvnx4qi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_ssaddvnx8qi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_sssubvnx8qi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_usaddvnx8qi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_ussubvnx8qi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_ssaddvnx16qi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_sssubvnx16qi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_usaddvnx16qi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_ussubvnx16qi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_ssaddvnx32qi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_sssubvnx32qi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_usaddvnx32qi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_ussubvnx32qi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_ssaddvnx64qi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_sssubvnx64qi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_usaddvnx64qi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_ussubvnx64qi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_ssaddvnx1hi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_sssubvnx1hi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_usaddvnx1hi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_ussubvnx1hi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_ssaddvnx2hi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_sssubvnx2hi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_usaddvnx2hi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_ussubvnx2hi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_ssaddvnx4hi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_sssubvnx4hi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_usaddvnx4hi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_ussubvnx4hi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_ssaddvnx8hi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_sssubvnx8hi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_usaddvnx8hi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_ussubvnx8hi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_ssaddvnx16hi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_sssubvnx16hi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_usaddvnx16hi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_ussubvnx16hi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_ssaddvnx32hi;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_sssubvnx32hi;
  if (arg0 == US_PLUS
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_usaddvnx32hi;
  if (arg0 == US_MINUS
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_ussubvnx32hi;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_ssaddvnx1si;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_sssubvnx1si;
  if (arg0 == US_PLUS
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_usaddvnx1si;
  if (arg0 == US_MINUS
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_ussubvnx1si;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_ssaddvnx2si;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_sssubvnx2si;
  if (arg0 == US_PLUS
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_usaddvnx2si;
  if (arg0 == US_MINUS
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_ussubvnx2si;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_ssaddvnx4si;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_sssubvnx4si;
  if (arg0 == US_PLUS
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_usaddvnx4si;
  if (arg0 == US_MINUS
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_ussubvnx4si;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_ssaddvnx8si;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_sssubvnx8si;
  if (arg0 == US_PLUS
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_usaddvnx8si;
  if (arg0 == US_MINUS
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_ussubvnx8si;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_ssaddvnx16si;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_sssubvnx16si;
  if (arg0 == US_PLUS
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_usaddvnx16si;
  if (arg0 == US_MINUS
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_ussubvnx16si;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_ssaddvnx1di;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_sssubvnx1di;
  if (arg0 == US_PLUS
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_usaddvnx1di;
  if (arg0 == US_MINUS
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_ussubvnx1di;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_ssaddvnx2di;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_sssubvnx2di;
  if (arg0 == US_PLUS
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_usaddvnx2di;
  if (arg0 == US_MINUS
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_ussubvnx2di;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_ssaddvnx4di;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_sssubvnx4di;
  if (arg0 == US_PLUS
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_usaddvnx4di;
  if (arg0 == US_MINUS
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_ussubvnx4di;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_ssaddvnx8di;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_sssubvnx8di;
  if (arg0 == US_PLUS
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_usaddvnx8di;
  if (arg0 == US_MINUS
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_ussubvnx8di;
  if (arg0 == AND
      && arg1 == E_VNx1BImode)
    return CODE_FOR_pred_andvnx1bi;
  if (arg0 == IOR
      && arg1 == E_VNx1BImode)
    return CODE_FOR_pred_iorvnx1bi;
  if (arg0 == XOR
      && arg1 == E_VNx1BImode)
    return CODE_FOR_pred_xorvnx1bi;
  if (arg0 == AND
      && arg1 == E_VNx2BImode)
    return CODE_FOR_pred_andvnx2bi;
  if (arg0 == IOR
      && arg1 == E_VNx2BImode)
    return CODE_FOR_pred_iorvnx2bi;
  if (arg0 == XOR
      && arg1 == E_VNx2BImode)
    return CODE_FOR_pred_xorvnx2bi;
  if (arg0 == AND
      && arg1 == E_VNx4BImode)
    return CODE_FOR_pred_andvnx4bi;
  if (arg0 == IOR
      && arg1 == E_VNx4BImode)
    return CODE_FOR_pred_iorvnx4bi;
  if (arg0 == XOR
      && arg1 == E_VNx4BImode)
    return CODE_FOR_pred_xorvnx4bi;
  if (arg0 == AND
      && arg1 == E_VNx8BImode)
    return CODE_FOR_pred_andvnx8bi;
  if (arg0 == IOR
      && arg1 == E_VNx8BImode)
    return CODE_FOR_pred_iorvnx8bi;
  if (arg0 == XOR
      && arg1 == E_VNx8BImode)
    return CODE_FOR_pred_xorvnx8bi;
  if (arg0 == AND
      && arg1 == E_VNx16BImode)
    return CODE_FOR_pred_andvnx16bi;
  if (arg0 == IOR
      && arg1 == E_VNx16BImode)
    return CODE_FOR_pred_iorvnx16bi;
  if (arg0 == XOR
      && arg1 == E_VNx16BImode)
    return CODE_FOR_pred_xorvnx16bi;
  if (arg0 == AND
      && arg1 == E_VNx32BImode)
    return CODE_FOR_pred_andvnx32bi;
  if (arg0 == IOR
      && arg1 == E_VNx32BImode)
    return CODE_FOR_pred_iorvnx32bi;
  if (arg0 == XOR
      && arg1 == E_VNx32BImode)
    return CODE_FOR_pred_xorvnx32bi;
  if (arg0 == AND
      && arg1 == E_VNx64BImode)
    return CODE_FOR_pred_andvnx64bi;
  if (arg0 == IOR
      && arg1 == E_VNx64BImode)
    return CODE_FOR_pred_iorvnx64bi;
  if (arg0 == XOR
      && arg1 == E_VNx64BImode)
    return CODE_FOR_pred_xorvnx64bi;
  if (arg0 == PLUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_addvnx1sf;
  if (arg0 == MULT
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_mulvnx1sf;
  if (arg0 == SMAX
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_smaxvnx1sf;
  if (arg0 == SMIN
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_sminvnx1sf;
  if (arg0 == MINUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_subvnx1sf;
  if (arg0 == DIV
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_divvnx1sf;
  if (arg0 == PLUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_addvnx2sf;
  if (arg0 == MULT
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_mulvnx2sf;
  if (arg0 == SMAX
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_smaxvnx2sf;
  if (arg0 == SMIN
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_sminvnx2sf;
  if (arg0 == MINUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_subvnx2sf;
  if (arg0 == DIV
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_divvnx2sf;
  if (arg0 == PLUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_addvnx4sf;
  if (arg0 == MULT
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_mulvnx4sf;
  if (arg0 == SMAX
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_smaxvnx4sf;
  if (arg0 == SMIN
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_sminvnx4sf;
  if (arg0 == MINUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_subvnx4sf;
  if (arg0 == DIV
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_divvnx4sf;
  if (arg0 == PLUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_addvnx8sf;
  if (arg0 == MULT
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_mulvnx8sf;
  if (arg0 == SMAX
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_smaxvnx8sf;
  if (arg0 == SMIN
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_sminvnx8sf;
  if (arg0 == MINUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_subvnx8sf;
  if (arg0 == DIV
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_divvnx8sf;
  if (arg0 == PLUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_addvnx16sf;
  if (arg0 == MULT
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_mulvnx16sf;
  if (arg0 == SMAX
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_smaxvnx16sf;
  if (arg0 == SMIN
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_sminvnx16sf;
  if (arg0 == MINUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_subvnx16sf;
  if (arg0 == DIV
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_divvnx16sf;
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_addvnx1df;
  if (arg0 == MULT
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_mulvnx1df;
  if (arg0 == SMAX
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_smaxvnx1df;
  if (arg0 == SMIN
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_sminvnx1df;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_subvnx1df;
  if (arg0 == DIV
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_divvnx1df;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_addvnx2df;
  if (arg0 == MULT
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_mulvnx2df;
  if (arg0 == SMAX
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_smaxvnx2df;
  if (arg0 == SMIN
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_sminvnx2df;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_subvnx2df;
  if (arg0 == DIV
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_divvnx2df;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_addvnx4df;
  if (arg0 == MULT
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_mulvnx4df;
  if (arg0 == SMAX
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_smaxvnx4df;
  if (arg0 == SMIN
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_sminvnx4df;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_subvnx4df;
  if (arg0 == DIV
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_divvnx4df;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_addvnx8df;
  if (arg0 == MULT
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_mulvnx8df;
  if (arg0 == SMAX
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_smaxvnx8df;
  if (arg0 == SMIN
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_sminvnx8df;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_subvnx8df;
  if (arg0 == DIV
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_divvnx8df;
  if (arg0 == NEG
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_negvnx1sf;
  if (arg0 == ABS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_absvnx1sf;
  if (arg0 == SQRT
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_sqrtvnx1sf;
  if (arg0 == NEG
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_negvnx2sf;
  if (arg0 == ABS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_absvnx2sf;
  if (arg0 == SQRT
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_sqrtvnx2sf;
  if (arg0 == NEG
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_negvnx4sf;
  if (arg0 == ABS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_absvnx4sf;
  if (arg0 == SQRT
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_sqrtvnx4sf;
  if (arg0 == NEG
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_negvnx8sf;
  if (arg0 == ABS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_absvnx8sf;
  if (arg0 == SQRT
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_sqrtvnx8sf;
  if (arg0 == NEG
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_negvnx16sf;
  if (arg0 == ABS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_absvnx16sf;
  if (arg0 == SQRT
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_sqrtvnx16sf;
  if (arg0 == NEG
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_negvnx1df;
  if (arg0 == ABS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_absvnx1df;
  if (arg0 == SQRT
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_sqrtvnx1df;
  if (arg0 == NEG
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_negvnx2df;
  if (arg0 == ABS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_absvnx2df;
  if (arg0 == SQRT
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_sqrtvnx2df;
  if (arg0 == NEG
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_negvnx4df;
  if (arg0 == ABS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_absvnx4df;
  if (arg0 == SQRT
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_sqrtvnx4df;
  if (arg0 == NEG
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_negvnx8df;
  if (arg0 == ABS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_absvnx8df;
  if (arg0 == SQRT
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_sqrtvnx8df;
  if (arg0 == FIX
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_fix_truncvnx1sf;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_fixuns_truncvnx1sf;
  if (arg0 == FIX
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_fix_truncvnx2sf;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_fixuns_truncvnx2sf;
  if (arg0 == FIX
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_fix_truncvnx4sf;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_fixuns_truncvnx4sf;
  if (arg0 == FIX
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_fix_truncvnx8sf;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_fixuns_truncvnx8sf;
  if (arg0 == FIX
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_fix_truncvnx16sf;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_fixuns_truncvnx16sf;
  if (arg0 == FIX
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_fix_truncvnx1df;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_fixuns_truncvnx1df;
  if (arg0 == FIX
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_fix_truncvnx2df;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_fixuns_truncvnx2df;
  if (arg0 == FIX
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_fix_truncvnx4df;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_fixuns_truncvnx4df;
  if (arg0 == FIX
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_fix_truncvnx8df;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_fixuns_truncvnx8df;
  if (arg0 == FLOAT
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_floatvnx1sf;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_floatunsvnx1sf;
  if (arg0 == FLOAT
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_floatvnx2sf;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_floatunsvnx2sf;
  if (arg0 == FLOAT
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_floatvnx4sf;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_floatunsvnx4sf;
  if (arg0 == FLOAT
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_floatvnx8sf;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_floatunsvnx8sf;
  if (arg0 == FLOAT
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_floatvnx16sf;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_floatunsvnx16sf;
  if (arg0 == FLOAT
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_floatvnx1df;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_floatunsvnx1df;
  if (arg0 == FLOAT
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_floatvnx2df;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_floatunsvnx2df;
  if (arg0 == FLOAT
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_floatvnx4df;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_floatunsvnx4df;
  if (arg0 == FLOAT
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_floatvnx8df;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_floatunsvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

rtx
maybe_gen_pred (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

rtx
maybe_gen_pred (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6)
{
  insn_code code = maybe_code_for_pred (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 7);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_scalar (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == ASHIFT
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_ashlvnx1qi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_ashrvnx1qi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_lshrvnx1qi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_ashlvnx2qi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_ashrvnx2qi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_lshrvnx2qi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_ashlvnx4qi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_ashrvnx4qi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_lshrvnx4qi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_ashlvnx8qi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_ashrvnx8qi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_lshrvnx8qi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_ashlvnx16qi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_ashrvnx16qi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_lshrvnx16qi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_ashlvnx32qi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_ashrvnx32qi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_lshrvnx32qi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_ashlvnx64qi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_ashrvnx64qi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_lshrvnx64qi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_ashlvnx1hi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_ashrvnx1hi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_lshrvnx1hi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_ashlvnx2hi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_ashrvnx2hi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_lshrvnx2hi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_ashlvnx4hi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_ashrvnx4hi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_lshrvnx4hi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_ashlvnx8hi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_ashrvnx8hi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_lshrvnx8hi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_ashlvnx16hi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_ashrvnx16hi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_lshrvnx16hi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_ashlvnx32hi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_ashrvnx32hi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_lshrvnx32hi_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_ashlvnx1si_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_ashrvnx1si_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_lshrvnx1si_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_ashlvnx2si_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_ashrvnx2si_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_lshrvnx2si_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_ashlvnx4si_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_ashrvnx4si_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_lshrvnx4si_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_ashlvnx8si_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_ashrvnx8si_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_lshrvnx8si_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_ashlvnx16si_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_ashrvnx16si_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_lshrvnx16si_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_ashlvnx1di_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_ashrvnx1di_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_lshrvnx1di_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_ashlvnx2di_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_ashrvnx2di_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_lshrvnx2di_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_ashlvnx4di_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_ashrvnx4di_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_lshrvnx4di_scalar;
  if (arg0 == ASHIFT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_ashlvnx8di_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_ashrvnx8di_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_lshrvnx8di_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_addvnx1qi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_andvnx1qi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_iorvnx1qi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_xorvnx1qi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_smaxvnx1qi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_umaxvnx1qi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_sminvnx1qi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_uminvnx1qi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_mulvnx1qi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_addvnx2qi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_andvnx2qi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_iorvnx2qi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_xorvnx2qi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_smaxvnx2qi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_umaxvnx2qi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_sminvnx2qi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_uminvnx2qi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_mulvnx2qi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_addvnx4qi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_andvnx4qi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_iorvnx4qi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_xorvnx4qi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_smaxvnx4qi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_umaxvnx4qi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_sminvnx4qi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_uminvnx4qi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_mulvnx4qi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_addvnx8qi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_andvnx8qi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_iorvnx8qi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_xorvnx8qi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_smaxvnx8qi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_umaxvnx8qi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_sminvnx8qi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_uminvnx8qi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_mulvnx8qi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_addvnx16qi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_andvnx16qi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_iorvnx16qi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_xorvnx16qi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_smaxvnx16qi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_umaxvnx16qi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_sminvnx16qi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_uminvnx16qi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_mulvnx16qi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_addvnx32qi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_andvnx32qi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_iorvnx32qi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_xorvnx32qi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_smaxvnx32qi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_umaxvnx32qi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_sminvnx32qi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_uminvnx32qi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_mulvnx32qi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_addvnx64qi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_andvnx64qi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_iorvnx64qi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_xorvnx64qi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_smaxvnx64qi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_umaxvnx64qi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_sminvnx64qi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_uminvnx64qi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_mulvnx64qi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_addvnx1hi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_andvnx1hi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_iorvnx1hi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_xorvnx1hi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_smaxvnx1hi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_umaxvnx1hi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_sminvnx1hi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_uminvnx1hi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_mulvnx1hi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_addvnx2hi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_andvnx2hi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_iorvnx2hi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_xorvnx2hi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_smaxvnx2hi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_umaxvnx2hi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_sminvnx2hi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_uminvnx2hi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_mulvnx2hi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_addvnx4hi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_andvnx4hi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_iorvnx4hi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_xorvnx4hi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_smaxvnx4hi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_umaxvnx4hi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_sminvnx4hi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_uminvnx4hi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_mulvnx4hi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_addvnx8hi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_andvnx8hi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_iorvnx8hi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_xorvnx8hi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_smaxvnx8hi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_umaxvnx8hi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_sminvnx8hi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_uminvnx8hi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_mulvnx8hi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_addvnx16hi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_andvnx16hi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_iorvnx16hi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_xorvnx16hi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_smaxvnx16hi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_umaxvnx16hi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_sminvnx16hi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_uminvnx16hi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_mulvnx16hi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_addvnx32hi_scalar;
  if (arg0 == AND
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_andvnx32hi_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_iorvnx32hi_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_xorvnx32hi_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_smaxvnx32hi_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_umaxvnx32hi_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_sminvnx32hi_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_uminvnx32hi_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_mulvnx32hi_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_addvnx1si_scalar;
  if (arg0 == AND
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_andvnx1si_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_iorvnx1si_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_xorvnx1si_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_smaxvnx1si_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_umaxvnx1si_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_sminvnx1si_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_uminvnx1si_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_mulvnx1si_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_addvnx2si_scalar;
  if (arg0 == AND
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_andvnx2si_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_iorvnx2si_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_xorvnx2si_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_smaxvnx2si_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_umaxvnx2si_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_sminvnx2si_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_uminvnx2si_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_mulvnx2si_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_addvnx4si_scalar;
  if (arg0 == AND
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_andvnx4si_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_iorvnx4si_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_xorvnx4si_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_smaxvnx4si_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_umaxvnx4si_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_sminvnx4si_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_uminvnx4si_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_mulvnx4si_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_addvnx8si_scalar;
  if (arg0 == AND
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_andvnx8si_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_iorvnx8si_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_xorvnx8si_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_smaxvnx8si_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_umaxvnx8si_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_sminvnx8si_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_uminvnx8si_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_mulvnx8si_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_addvnx16si_scalar;
  if (arg0 == AND
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_andvnx16si_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_iorvnx16si_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_xorvnx16si_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_smaxvnx16si_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_umaxvnx16si_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_sminvnx16si_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_uminvnx16si_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_mulvnx16si_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_subvnx1qi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_divvnx1qi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_udivvnx1qi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_modvnx1qi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_umodvnx1qi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_subvnx2qi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_divvnx2qi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_udivvnx2qi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_modvnx2qi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_umodvnx2qi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_subvnx4qi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_divvnx4qi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_udivvnx4qi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_modvnx4qi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_umodvnx4qi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_subvnx8qi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_divvnx8qi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_udivvnx8qi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_modvnx8qi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_umodvnx8qi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_subvnx16qi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_divvnx16qi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_udivvnx16qi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_modvnx16qi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_umodvnx16qi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_subvnx32qi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_divvnx32qi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_udivvnx32qi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_modvnx32qi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_umodvnx32qi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_subvnx64qi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_divvnx64qi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_udivvnx64qi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_modvnx64qi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_umodvnx64qi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_subvnx1hi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_divvnx1hi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_udivvnx1hi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_modvnx1hi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_umodvnx1hi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_subvnx2hi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_divvnx2hi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_udivvnx2hi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_modvnx2hi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_umodvnx2hi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_subvnx4hi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_divvnx4hi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_udivvnx4hi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_modvnx4hi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_umodvnx4hi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_subvnx8hi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_divvnx8hi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_udivvnx8hi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_modvnx8hi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_umodvnx8hi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_subvnx16hi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_divvnx16hi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_udivvnx16hi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_modvnx16hi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_umodvnx16hi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_subvnx32hi_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_divvnx32hi_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_udivvnx32hi_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_modvnx32hi_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_umodvnx32hi_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_subvnx1si_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_divvnx1si_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_udivvnx1si_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_modvnx1si_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_umodvnx1si_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_subvnx2si_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_divvnx2si_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_udivvnx2si_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_modvnx2si_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_umodvnx2si_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_subvnx4si_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_divvnx4si_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_udivvnx4si_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_modvnx4si_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_umodvnx4si_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_subvnx8si_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_divvnx8si_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_udivvnx8si_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_modvnx8si_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_umodvnx8si_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_subvnx16si_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_divvnx16si_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_udivvnx16si_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_modvnx16si_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_umodvnx16si_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_addvnx1di_scalar;
  if (arg0 == AND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_andvnx1di_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_iorvnx1di_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_xorvnx1di_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_smaxvnx1di_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_umaxvnx1di_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_sminvnx1di_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_uminvnx1di_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_mulvnx1di_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_addvnx2di_scalar;
  if (arg0 == AND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_andvnx2di_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_iorvnx2di_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_xorvnx2di_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_smaxvnx2di_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_umaxvnx2di_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_sminvnx2di_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_uminvnx2di_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_mulvnx2di_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_addvnx4di_scalar;
  if (arg0 == AND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_andvnx4di_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_iorvnx4di_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_xorvnx4di_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_smaxvnx4di_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_umaxvnx4di_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_sminvnx4di_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_uminvnx4di_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_mulvnx4di_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_addvnx8di_scalar;
  if (arg0 == AND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_andvnx8di_scalar;
  if (arg0 == IOR
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_iorvnx8di_scalar;
  if (arg0 == XOR
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_xorvnx8di_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_smaxvnx8di_scalar;
  if (arg0 == UMAX
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_umaxvnx8di_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_sminvnx8di_scalar;
  if (arg0 == UMIN
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_uminvnx8di_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_mulvnx8di_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_subvnx1di_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_divvnx1di_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_udivvnx1di_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_modvnx1di_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_umodvnx1di_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_subvnx2di_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_divvnx2di_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_udivvnx2di_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_modvnx2di_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_umodvnx2di_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_subvnx4di_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_divvnx4di_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_udivvnx4di_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_modvnx4di_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_umodvnx4di_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_subvnx8di_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_divvnx8di_scalar;
  if (arg0 == UDIV
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_udivvnx8di_scalar;
  if (arg0 == MOD
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_modvnx8di_scalar;
  if (arg0 == UMOD
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_umodvnx8di_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_ssaddvnx1qi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_usaddvnx1qi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_ssaddvnx2qi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_usaddvnx2qi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_ssaddvnx4qi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_usaddvnx4qi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_ssaddvnx8qi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_usaddvnx8qi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_ssaddvnx16qi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_usaddvnx16qi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_ssaddvnx32qi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_usaddvnx32qi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_ssaddvnx64qi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_usaddvnx64qi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_ssaddvnx1hi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_usaddvnx1hi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_ssaddvnx2hi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_usaddvnx2hi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_ssaddvnx4hi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_usaddvnx4hi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_ssaddvnx8hi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_usaddvnx8hi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_ssaddvnx16hi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_usaddvnx16hi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_ssaddvnx32hi_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_usaddvnx32hi_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_ssaddvnx1si_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_usaddvnx1si_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_ssaddvnx2si_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_usaddvnx2si_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_ssaddvnx4si_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_usaddvnx4si_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_ssaddvnx8si_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_usaddvnx8si_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_ssaddvnx16si_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_usaddvnx16si_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_sssubvnx1qi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_ussubvnx1qi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_sssubvnx2qi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_ussubvnx2qi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_sssubvnx4qi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_ussubvnx4qi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_sssubvnx8qi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_ussubvnx8qi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_sssubvnx16qi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_ussubvnx16qi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_sssubvnx32qi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_ussubvnx32qi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_sssubvnx64qi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_ussubvnx64qi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_sssubvnx1hi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_ussubvnx1hi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_sssubvnx2hi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_ussubvnx2hi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_sssubvnx4hi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_ussubvnx4hi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_sssubvnx8hi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_ussubvnx8hi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_sssubvnx16hi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_ussubvnx16hi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_sssubvnx32hi_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_ussubvnx32hi_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_sssubvnx1si_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_ussubvnx1si_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_sssubvnx2si_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_ussubvnx2si_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_sssubvnx4si_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_ussubvnx4si_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_sssubvnx8si_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_ussubvnx8si_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_sssubvnx16si_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_ussubvnx16si_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_ssaddvnx1di_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_usaddvnx1di_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_ssaddvnx2di_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_usaddvnx2di_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_ssaddvnx4di_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_usaddvnx4di_scalar;
  if (arg0 == SS_PLUS
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_ssaddvnx8di_scalar;
  if (arg0 == US_PLUS
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_usaddvnx8di_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_sssubvnx1di_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_ussubvnx1di_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_sssubvnx2di_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_ussubvnx2di_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_sssubvnx4di_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_ussubvnx4di_scalar;
  if (arg0 == SS_MINUS
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_sssubvnx8di_scalar;
  if (arg0 == US_MINUS
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_ussubvnx8di_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_addvnx1sf_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_mulvnx1sf_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_smaxvnx1sf_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_sminvnx1sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_addvnx2sf_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_mulvnx2sf_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_smaxvnx2sf_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_sminvnx2sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_addvnx4sf_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_mulvnx4sf_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_smaxvnx4sf_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_sminvnx4sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_addvnx8sf_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_mulvnx8sf_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_smaxvnx8sf_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_sminvnx8sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_addvnx16sf_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_mulvnx16sf_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_smaxvnx16sf_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_sminvnx16sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_addvnx1df_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_mulvnx1df_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_smaxvnx1df_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_sminvnx1df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_addvnx2df_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_mulvnx2df_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_smaxvnx2df_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_sminvnx2df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_addvnx4df_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_mulvnx4df_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_smaxvnx4df_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_sminvnx4df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_addvnx8df_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_mulvnx8df_scalar;
  if (arg0 == SMAX
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_smaxvnx8df_scalar;
  if (arg0 == SMIN
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_sminvnx8df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_subvnx1sf_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_divvnx1sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_subvnx2sf_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_divvnx2sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_subvnx4sf_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_divvnx4sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_subvnx8sf_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_divvnx8sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_subvnx16sf_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_divvnx16sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_subvnx1df_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_divvnx1df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_subvnx2df_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_divvnx2df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_subvnx4df_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_divvnx4df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_subvnx8df_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_divvnx8df_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_scalar (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_sub_reverse_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_subvnx1qi_reverse_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_subvnx2qi_reverse_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_subvnx4qi_reverse_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_subvnx8qi_reverse_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_subvnx16qi_reverse_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_subvnx32qi_reverse_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_subvnx64qi_reverse_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_subvnx1hi_reverse_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_subvnx2hi_reverse_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_subvnx4hi_reverse_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_subvnx8hi_reverse_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_subvnx16hi_reverse_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_subvnx32hi_reverse_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_subvnx1si_reverse_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_subvnx2si_reverse_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_subvnx4si_reverse_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_subvnx8si_reverse_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_subvnx16si_reverse_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_subvnx1di_reverse_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_subvnx2di_reverse_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_subvnx4di_reverse_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_subvnx8di_reverse_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_sub_reverse_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_sub_reverse_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_mulh (int arg0, machine_mode arg1)
{
  if (arg0 == 73
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_mulhvnx1qi;
  if (arg0 == 74
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_mulhuvnx1qi;
  if (arg0 == 75
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_mulhsuvnx1qi;
  if (arg0 == 73
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_mulhvnx2qi;
  if (arg0 == 74
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_mulhuvnx2qi;
  if (arg0 == 75
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_mulhsuvnx2qi;
  if (arg0 == 73
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_mulhvnx4qi;
  if (arg0 == 74
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_mulhuvnx4qi;
  if (arg0 == 75
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_mulhsuvnx4qi;
  if (arg0 == 73
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_mulhvnx8qi;
  if (arg0 == 74
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_mulhuvnx8qi;
  if (arg0 == 75
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_mulhsuvnx8qi;
  if (arg0 == 73
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_mulhvnx16qi;
  if (arg0 == 74
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_mulhuvnx16qi;
  if (arg0 == 75
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_mulhsuvnx16qi;
  if (arg0 == 73
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_mulhvnx32qi;
  if (arg0 == 74
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_mulhuvnx32qi;
  if (arg0 == 75
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_mulhsuvnx32qi;
  if (arg0 == 73
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_mulhvnx64qi;
  if (arg0 == 74
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_mulhuvnx64qi;
  if (arg0 == 75
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_mulhsuvnx64qi;
  if (arg0 == 73
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_mulhvnx1hi;
  if (arg0 == 74
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_mulhuvnx1hi;
  if (arg0 == 75
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_mulhsuvnx1hi;
  if (arg0 == 73
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_mulhvnx2hi;
  if (arg0 == 74
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_mulhuvnx2hi;
  if (arg0 == 75
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_mulhsuvnx2hi;
  if (arg0 == 73
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_mulhvnx4hi;
  if (arg0 == 74
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_mulhuvnx4hi;
  if (arg0 == 75
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_mulhsuvnx4hi;
  if (arg0 == 73
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_mulhvnx8hi;
  if (arg0 == 74
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_mulhuvnx8hi;
  if (arg0 == 75
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_mulhsuvnx8hi;
  if (arg0 == 73
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_mulhvnx16hi;
  if (arg0 == 74
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_mulhuvnx16hi;
  if (arg0 == 75
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_mulhsuvnx16hi;
  if (arg0 == 73
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_mulhvnx32hi;
  if (arg0 == 74
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_mulhuvnx32hi;
  if (arg0 == 75
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_mulhsuvnx32hi;
  if (arg0 == 73
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_mulhvnx1si;
  if (arg0 == 74
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_mulhuvnx1si;
  if (arg0 == 75
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_mulhsuvnx1si;
  if (arg0 == 73
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_mulhvnx2si;
  if (arg0 == 74
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_mulhuvnx2si;
  if (arg0 == 75
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_mulhsuvnx2si;
  if (arg0 == 73
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_mulhvnx4si;
  if (arg0 == 74
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_mulhuvnx4si;
  if (arg0 == 75
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_mulhsuvnx4si;
  if (arg0 == 73
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_mulhvnx8si;
  if (arg0 == 74
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_mulhuvnx8si;
  if (arg0 == 75
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_mulhsuvnx8si;
  if (arg0 == 73
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_mulhvnx16si;
  if (arg0 == 74
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_mulhuvnx16si;
  if (arg0 == 75
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_mulhsuvnx16si;
  if (arg0 == 73
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_mulhvnx1di;
  if (arg0 == 74
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_mulhuvnx1di;
  if (arg0 == 75
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_mulhsuvnx1di;
  if (arg0 == 73
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_mulhvnx2di;
  if (arg0 == 74
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_mulhuvnx2di;
  if (arg0 == 75
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_mulhsuvnx2di;
  if (arg0 == 73
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_mulhvnx4di;
  if (arg0 == 74
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_mulhuvnx4di;
  if (arg0 == 75
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_mulhsuvnx4di;
  if (arg0 == 73
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_mulhvnx8di;
  if (arg0 == 74
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_mulhuvnx8di;
  if (arg0 == 75
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_mulhsuvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_mulh (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_mulh (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_mulh_scalar (int arg0, machine_mode arg1)
{
  if (arg0 == 73
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_mulhvnx1qi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_mulhuvnx1qi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_mulhsuvnx1qi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_mulhvnx2qi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_mulhuvnx2qi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_mulhsuvnx2qi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_mulhvnx4qi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_mulhuvnx4qi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_mulhsuvnx4qi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_mulhvnx8qi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_mulhuvnx8qi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_mulhsuvnx8qi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_mulhvnx16qi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_mulhuvnx16qi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_mulhsuvnx16qi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_mulhvnx32qi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_mulhuvnx32qi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_mulhsuvnx32qi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_mulhvnx64qi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_mulhuvnx64qi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_mulhsuvnx64qi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_mulhvnx1hi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_mulhuvnx1hi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_mulhsuvnx1hi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_mulhvnx2hi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_mulhuvnx2hi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_mulhsuvnx2hi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_mulhvnx4hi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_mulhuvnx4hi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_mulhsuvnx4hi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_mulhvnx8hi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_mulhuvnx8hi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_mulhsuvnx8hi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_mulhvnx16hi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_mulhuvnx16hi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_mulhsuvnx16hi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_mulhvnx32hi_scalar;
  if (arg0 == 74
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_mulhuvnx32hi_scalar;
  if (arg0 == 75
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_mulhsuvnx32hi_scalar;
  if (arg0 == 73
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_mulhvnx1si_scalar;
  if (arg0 == 74
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_mulhuvnx1si_scalar;
  if (arg0 == 75
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_mulhsuvnx1si_scalar;
  if (arg0 == 73
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_mulhvnx2si_scalar;
  if (arg0 == 74
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_mulhuvnx2si_scalar;
  if (arg0 == 75
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_mulhsuvnx2si_scalar;
  if (arg0 == 73
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_mulhvnx4si_scalar;
  if (arg0 == 74
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_mulhuvnx4si_scalar;
  if (arg0 == 75
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_mulhsuvnx4si_scalar;
  if (arg0 == 73
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_mulhvnx8si_scalar;
  if (arg0 == 74
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_mulhuvnx8si_scalar;
  if (arg0 == 75
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_mulhsuvnx8si_scalar;
  if (arg0 == 73
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_mulhvnx16si_scalar;
  if (arg0 == 74
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_mulhuvnx16si_scalar;
  if (arg0 == 75
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_mulhsuvnx16si_scalar;
  if (arg0 == 73
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_mulhvnx1di_scalar;
  if (arg0 == 74
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_mulhuvnx1di_scalar;
  if (arg0 == 75
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_mulhsuvnx1di_scalar;
  if (arg0 == 73
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_mulhvnx2di_scalar;
  if (arg0 == 74
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_mulhuvnx2di_scalar;
  if (arg0 == 75
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_mulhsuvnx2di_scalar;
  if (arg0 == 73
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_mulhvnx4di_scalar;
  if (arg0 == 74
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_mulhuvnx4di_scalar;
  if (arg0 == 75
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_mulhsuvnx4di_scalar;
  if (arg0 == 73
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_mulhvnx8di_scalar;
  if (arg0 == 74
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_mulhuvnx8di_scalar;
  if (arg0 == 75
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_mulhsuvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_mulh_scalar (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_mulh_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_adc (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_adcvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_adcvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_adcvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_adcvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_adcvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_adcvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_adcvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_adcvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_adcvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_adcvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_adcvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_adcvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_adcvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_adcvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_adcvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_adcvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_adcvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_adcvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_adcvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_adcvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_adcvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_adcvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_adc (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_adc (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_sbc (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_sbcvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_sbcvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_sbcvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_sbcvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_sbcvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_sbcvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_sbcvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_sbcvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_sbcvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_sbcvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_sbcvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_sbcvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_sbcvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_sbcvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_sbcvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_sbcvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_sbcvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_sbcvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_sbcvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_sbcvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_sbcvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_sbcvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_sbc (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_sbc (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_adc_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_adcvnx1qi_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_adcvnx2qi_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_adcvnx4qi_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_adcvnx8qi_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_adcvnx16qi_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_adcvnx32qi_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_adcvnx64qi_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_adcvnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_adcvnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_adcvnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_adcvnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_adcvnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_adcvnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_adcvnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_adcvnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_adcvnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_adcvnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_adcvnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_adcvnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_adcvnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_adcvnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_adcvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_adc_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_adc_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_sbc_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_sbcvnx1qi_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_sbcvnx2qi_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_sbcvnx4qi_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_sbcvnx8qi_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_sbcvnx16qi_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_sbcvnx32qi_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_sbcvnx64qi_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_sbcvnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_sbcvnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_sbcvnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_sbcvnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_sbcvnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_sbcvnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_sbcvnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_sbcvnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_sbcvnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_sbcvnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_sbcvnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_sbcvnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_sbcvnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_sbcvnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_sbcvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_sbc_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_sbc_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_madc (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_madcvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_madcvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_madcvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_madcvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_madcvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_madcvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_madcvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_madcvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_madcvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_madcvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_madcvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_madcvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_madcvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_madcvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_madcvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_madcvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_madcvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_madcvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_madcvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_madcvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_madcvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_madcvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_madc (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5)
{
  insn_code code = maybe_code_for_pred_madc (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 6);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_msbc (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_msbcvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_msbcvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_msbcvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_msbcvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_msbcvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_msbcvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_msbcvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_msbcvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_msbcvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_msbcvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_msbcvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_msbcvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_msbcvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_msbcvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_msbcvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_msbcvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_msbcvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_msbcvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_msbcvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_msbcvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_msbcvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_msbcvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_msbc (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5)
{
  insn_code code = maybe_code_for_pred_msbc (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 6);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_madc_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_madcvnx1qi_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_madcvnx2qi_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_madcvnx4qi_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_madcvnx8qi_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_madcvnx16qi_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_madcvnx32qi_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_madcvnx64qi_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_madcvnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_madcvnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_madcvnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_madcvnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_madcvnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_madcvnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_madcvnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_madcvnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_madcvnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_madcvnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_madcvnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_madcvnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_madcvnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_madcvnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_madcvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_madc_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5)
{
  insn_code code = maybe_code_for_pred_madc_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 6);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_msbc_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_msbcvnx1qi_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_msbcvnx2qi_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_msbcvnx4qi_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_msbcvnx8qi_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_msbcvnx16qi_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_msbcvnx32qi_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_msbcvnx64qi_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_msbcvnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_msbcvnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_msbcvnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_msbcvnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_msbcvnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_msbcvnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_msbcvnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_msbcvnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_msbcvnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_msbcvnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_msbcvnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_msbcvnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_msbcvnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_msbcvnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_msbcvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_msbc_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5)
{
  insn_code code = maybe_code_for_pred_msbc_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 6);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_madc_overflow (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_madcvnx1qi_overflow;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_madcvnx2qi_overflow;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_madcvnx4qi_overflow;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_madcvnx8qi_overflow;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_madcvnx16qi_overflow;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_madcvnx32qi_overflow;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_madcvnx64qi_overflow;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_madcvnx1hi_overflow;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_madcvnx2hi_overflow;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_madcvnx4hi_overflow;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_madcvnx8hi_overflow;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_madcvnx16hi_overflow;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_madcvnx32hi_overflow;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_madcvnx1si_overflow;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_madcvnx2si_overflow;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_madcvnx4si_overflow;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_madcvnx8si_overflow;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_madcvnx16si_overflow;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_madcvnx1di_overflow;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_madcvnx2di_overflow;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_madcvnx4di_overflow;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_madcvnx8di_overflow;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_madc_overflow (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)
{
  insn_code code = maybe_code_for_pred_madc_overflow (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 5);
      return GEN_FCN (code) (x0, x1, x2, x3, x4);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_msbc_overflow (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_msbcvnx1qi_overflow;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_msbcvnx2qi_overflow;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_msbcvnx4qi_overflow;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_msbcvnx8qi_overflow;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_msbcvnx16qi_overflow;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_msbcvnx32qi_overflow;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_msbcvnx64qi_overflow;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_msbcvnx1hi_overflow;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_msbcvnx2hi_overflow;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_msbcvnx4hi_overflow;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_msbcvnx8hi_overflow;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_msbcvnx16hi_overflow;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_msbcvnx32hi_overflow;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_msbcvnx1si_overflow;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_msbcvnx2si_overflow;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_msbcvnx4si_overflow;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_msbcvnx8si_overflow;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_msbcvnx16si_overflow;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_msbcvnx1di_overflow;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_msbcvnx2di_overflow;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_msbcvnx4di_overflow;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_msbcvnx8di_overflow;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_msbc_overflow (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)
{
  insn_code code = maybe_code_for_pred_msbc_overflow (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 5);
      return GEN_FCN (code) (x0, x1, x2, x3, x4);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_madc_overflow_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_madcvnx1qi_overflow_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_madcvnx2qi_overflow_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_madcvnx4qi_overflow_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_madcvnx8qi_overflow_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_madcvnx16qi_overflow_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_madcvnx32qi_overflow_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_madcvnx64qi_overflow_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_madcvnx1hi_overflow_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_madcvnx2hi_overflow_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_madcvnx4hi_overflow_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_madcvnx8hi_overflow_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_madcvnx16hi_overflow_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_madcvnx32hi_overflow_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_madcvnx1si_overflow_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_madcvnx2si_overflow_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_madcvnx4si_overflow_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_madcvnx8si_overflow_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_madcvnx16si_overflow_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_madcvnx1di_overflow_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_madcvnx2di_overflow_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_madcvnx4di_overflow_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_madcvnx8di_overflow_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_madc_overflow_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)
{
  insn_code code = maybe_code_for_pred_madc_overflow_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 5);
      return GEN_FCN (code) (x0, x1, x2, x3, x4);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_msbc_overflow_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_msbcvnx1qi_overflow_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_msbcvnx2qi_overflow_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_msbcvnx4qi_overflow_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_msbcvnx8qi_overflow_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_msbcvnx16qi_overflow_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_msbcvnx32qi_overflow_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_msbcvnx64qi_overflow_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_msbcvnx1hi_overflow_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_msbcvnx2hi_overflow_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_msbcvnx4hi_overflow_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_msbcvnx8hi_overflow_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_msbcvnx16hi_overflow_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_msbcvnx32hi_overflow_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_msbcvnx1si_overflow_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_msbcvnx2si_overflow_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_msbcvnx4si_overflow_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_msbcvnx8si_overflow_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_msbcvnx16si_overflow_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_msbcvnx1di_overflow_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_msbcvnx2di_overflow_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_msbcvnx4di_overflow_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_msbcvnx8di_overflow_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_msbc_overflow_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)
{
  insn_code code = maybe_code_for_pred_msbc_overflow_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 5);
      return GEN_FCN (code) (x0, x1, x2, x3, x4);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_vf2 (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_extendvnx1hi_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_zero_extendvnx1hi_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_extendvnx2hi_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_zero_extendvnx2hi_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_extendvnx4hi_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_zero_extendvnx4hi_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_extendvnx8hi_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_zero_extendvnx8hi_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_extendvnx16hi_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_zero_extendvnx16hi_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_extendvnx32hi_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_zero_extendvnx32hi_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_extendvnx1si_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_zero_extendvnx1si_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_extendvnx2si_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_zero_extendvnx2si_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_extendvnx4si_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_zero_extendvnx4si_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_extendvnx8si_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_zero_extendvnx8si_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_extendvnx16si_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_zero_extendvnx16si_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_extendvnx1di_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_zero_extendvnx1di_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_extendvnx2di_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_zero_extendvnx2di_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_extendvnx4di_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_zero_extendvnx4di_vf2;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_extendvnx8di_vf2;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_zero_extendvnx8di_vf2;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_vf2 (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_vf2 (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_vf4 (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_extendvnx1si_vf4;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_zero_extendvnx1si_vf4;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_extendvnx2si_vf4;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_zero_extendvnx2si_vf4;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_extendvnx4si_vf4;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_zero_extendvnx4si_vf4;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_extendvnx8si_vf4;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_zero_extendvnx8si_vf4;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_extendvnx16si_vf4;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_zero_extendvnx16si_vf4;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_extendvnx1di_vf4;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_zero_extendvnx1di_vf4;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_extendvnx2di_vf4;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_zero_extendvnx2di_vf4;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_extendvnx4di_vf4;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_zero_extendvnx4di_vf4;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_extendvnx8di_vf4;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_zero_extendvnx8di_vf4;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_vf4 (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_vf4 (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_vf8 (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_extendvnx1di_vf8;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_zero_extendvnx1di_vf8;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_extendvnx2di_vf8;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_zero_extendvnx2di_vf8;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_extendvnx4di_vf8;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_zero_extendvnx4di_vf8;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_extendvnx8di_vf8;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_zero_extendvnx8di_vf8;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_vf8 (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_vf8 (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_dual_widen (rtx_code arg0, rtx_code arg1, machine_mode arg2)
{
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_dual_widen_addsvnx1hi;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_dual_widen_subsvnx1hi;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_dual_widen_mulsvnx1hi;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_dual_widen_adduvnx1hi;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_dual_widen_subuvnx1hi;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_dual_widen_muluvnx1hi;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_dual_widen_addsvnx2hi;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_dual_widen_subsvnx2hi;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_dual_widen_mulsvnx2hi;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_dual_widen_adduvnx2hi;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_dual_widen_subuvnx2hi;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_dual_widen_muluvnx2hi;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_dual_widen_addsvnx4hi;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_dual_widen_subsvnx4hi;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_dual_widen_mulsvnx4hi;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_dual_widen_adduvnx4hi;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_dual_widen_subuvnx4hi;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_dual_widen_muluvnx4hi;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_dual_widen_addsvnx8hi;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_dual_widen_subsvnx8hi;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_dual_widen_mulsvnx8hi;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_dual_widen_adduvnx8hi;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_dual_widen_subuvnx8hi;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_dual_widen_muluvnx8hi;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_dual_widen_addsvnx16hi;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_dual_widen_subsvnx16hi;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_dual_widen_mulsvnx16hi;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_dual_widen_adduvnx16hi;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_dual_widen_subuvnx16hi;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_dual_widen_muluvnx16hi;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_dual_widen_addsvnx32hi;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_dual_widen_subsvnx32hi;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_dual_widen_mulsvnx32hi;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_dual_widen_adduvnx32hi;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_dual_widen_subuvnx32hi;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_dual_widen_muluvnx32hi;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_dual_widen_addsvnx1si;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_dual_widen_subsvnx1si;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_dual_widen_mulsvnx1si;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_dual_widen_adduvnx1si;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_dual_widen_subuvnx1si;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_dual_widen_muluvnx1si;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_dual_widen_addsvnx2si;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_dual_widen_subsvnx2si;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_dual_widen_mulsvnx2si;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_dual_widen_adduvnx2si;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_dual_widen_subuvnx2si;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_dual_widen_muluvnx2si;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_dual_widen_addsvnx4si;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_dual_widen_subsvnx4si;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_dual_widen_mulsvnx4si;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_dual_widen_adduvnx4si;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_dual_widen_subuvnx4si;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_dual_widen_muluvnx4si;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_dual_widen_addsvnx8si;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_dual_widen_subsvnx8si;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_dual_widen_mulsvnx8si;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_dual_widen_adduvnx8si;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_dual_widen_subuvnx8si;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_dual_widen_muluvnx8si;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_dual_widen_addsvnx16si;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_dual_widen_subsvnx16si;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_dual_widen_mulsvnx16si;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_dual_widen_adduvnx16si;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_dual_widen_subuvnx16si;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_dual_widen_muluvnx16si;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_dual_widen_addsvnx1di;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_dual_widen_subsvnx1di;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_dual_widen_mulsvnx1di;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_dual_widen_adduvnx1di;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_dual_widen_subuvnx1di;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_dual_widen_muluvnx1di;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_dual_widen_addsvnx2di;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_dual_widen_subsvnx2di;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_dual_widen_mulsvnx2di;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_dual_widen_adduvnx2di;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_dual_widen_subuvnx2di;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_dual_widen_muluvnx2di;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_dual_widen_addsvnx4di;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_dual_widen_subsvnx4di;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_dual_widen_mulsvnx4di;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_dual_widen_adduvnx4di;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_dual_widen_subuvnx4di;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_dual_widen_muluvnx4di;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_dual_widen_addsvnx8di;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_dual_widen_subsvnx8di;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_dual_widen_mulsvnx8di;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_dual_widen_adduvnx8di;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_dual_widen_subuvnx8di;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_dual_widen_muluvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_dual_widen (rtx_code arg0, rtx_code arg1, machine_mode arg2, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_dual_widen (arg0, arg1, arg2);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_dual_widen_scalar (rtx_code arg0, rtx_code arg1, machine_mode arg2)
{
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_dual_widen_addsvnx1hi_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_dual_widen_subsvnx1hi_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_dual_widen_mulsvnx1hi_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_dual_widen_adduvnx1hi_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_dual_widen_subuvnx1hi_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_dual_widen_muluvnx1hi_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_dual_widen_addsvnx2hi_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_dual_widen_subsvnx2hi_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_dual_widen_mulsvnx2hi_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_dual_widen_adduvnx2hi_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_dual_widen_subuvnx2hi_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_dual_widen_muluvnx2hi_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_dual_widen_addsvnx4hi_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_dual_widen_subsvnx4hi_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_dual_widen_mulsvnx4hi_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_dual_widen_adduvnx4hi_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_dual_widen_subuvnx4hi_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_dual_widen_muluvnx4hi_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_dual_widen_addsvnx8hi_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_dual_widen_subsvnx8hi_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_dual_widen_mulsvnx8hi_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_dual_widen_adduvnx8hi_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_dual_widen_subuvnx8hi_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_dual_widen_muluvnx8hi_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_dual_widen_addsvnx16hi_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_dual_widen_subsvnx16hi_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_dual_widen_mulsvnx16hi_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_dual_widen_adduvnx16hi_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_dual_widen_subuvnx16hi_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_dual_widen_muluvnx16hi_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_dual_widen_addsvnx32hi_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_dual_widen_subsvnx32hi_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_dual_widen_mulsvnx32hi_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_dual_widen_adduvnx32hi_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_dual_widen_subuvnx32hi_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_dual_widen_muluvnx32hi_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_dual_widen_addsvnx1si_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_dual_widen_subsvnx1si_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_dual_widen_mulsvnx1si_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_dual_widen_adduvnx1si_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_dual_widen_subuvnx1si_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_dual_widen_muluvnx1si_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_dual_widen_addsvnx2si_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_dual_widen_subsvnx2si_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_dual_widen_mulsvnx2si_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_dual_widen_adduvnx2si_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_dual_widen_subuvnx2si_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_dual_widen_muluvnx2si_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_dual_widen_addsvnx4si_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_dual_widen_subsvnx4si_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_dual_widen_mulsvnx4si_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_dual_widen_adduvnx4si_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_dual_widen_subuvnx4si_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_dual_widen_muluvnx4si_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_dual_widen_addsvnx8si_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_dual_widen_subsvnx8si_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_dual_widen_mulsvnx8si_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_dual_widen_adduvnx8si_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_dual_widen_subuvnx8si_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_dual_widen_muluvnx8si_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_dual_widen_addsvnx16si_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_dual_widen_subsvnx16si_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_dual_widen_mulsvnx16si_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_dual_widen_adduvnx16si_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_dual_widen_subuvnx16si_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_dual_widen_muluvnx16si_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_dual_widen_addsvnx1di_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_dual_widen_subsvnx1di_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_dual_widen_mulsvnx1di_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_dual_widen_adduvnx1di_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_dual_widen_subuvnx1di_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_dual_widen_muluvnx1di_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_dual_widen_addsvnx2di_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_dual_widen_subsvnx2di_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_dual_widen_mulsvnx2di_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_dual_widen_adduvnx2di_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_dual_widen_subuvnx2di_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_dual_widen_muluvnx2di_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_dual_widen_addsvnx4di_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_dual_widen_subsvnx4di_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_dual_widen_mulsvnx4di_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_dual_widen_adduvnx4di_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_dual_widen_subuvnx4di_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_dual_widen_muluvnx4di_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_dual_widen_addsvnx8di_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_dual_widen_subsvnx8di_scalar;
  if (arg0 == MULT
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_dual_widen_mulsvnx8di_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_dual_widen_adduvnx8di_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_dual_widen_subuvnx8di_scalar;
  if (arg0 == MULT
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_dual_widen_muluvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_dual_widen_scalar (rtx_code arg0, rtx_code arg1, machine_mode arg2, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_dual_widen_scalar (arg0, arg1, arg2);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_single_widen (rtx_code arg0, rtx_code arg1, machine_mode arg2)
{
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_single_widen_addsvnx1hi;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_single_widen_subsvnx1hi;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_single_widen_adduvnx1hi;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_single_widen_subuvnx1hi;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_single_widen_addsvnx2hi;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_single_widen_subsvnx2hi;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_single_widen_adduvnx2hi;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_single_widen_subuvnx2hi;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_single_widen_addsvnx4hi;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_single_widen_subsvnx4hi;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_single_widen_adduvnx4hi;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_single_widen_subuvnx4hi;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_single_widen_addsvnx8hi;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_single_widen_subsvnx8hi;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_single_widen_adduvnx8hi;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_single_widen_subuvnx8hi;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_single_widen_addsvnx16hi;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_single_widen_subsvnx16hi;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_single_widen_adduvnx16hi;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_single_widen_subuvnx16hi;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_single_widen_addsvnx32hi;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_single_widen_subsvnx32hi;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_single_widen_adduvnx32hi;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_single_widen_subuvnx32hi;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_single_widen_addsvnx1si;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_single_widen_subsvnx1si;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_single_widen_adduvnx1si;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_single_widen_subuvnx1si;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_single_widen_addsvnx2si;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_single_widen_subsvnx2si;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_single_widen_adduvnx2si;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_single_widen_subuvnx2si;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_single_widen_addsvnx4si;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_single_widen_subsvnx4si;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_single_widen_adduvnx4si;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_single_widen_subuvnx4si;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_single_widen_addsvnx8si;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_single_widen_subsvnx8si;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_single_widen_adduvnx8si;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_single_widen_subuvnx8si;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_single_widen_addsvnx16si;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_single_widen_subsvnx16si;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_single_widen_adduvnx16si;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_single_widen_subuvnx16si;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_single_widen_addsvnx1di;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_single_widen_subsvnx1di;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_single_widen_adduvnx1di;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_single_widen_subuvnx1di;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_single_widen_addsvnx2di;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_single_widen_subsvnx2di;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_single_widen_adduvnx2di;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_single_widen_subuvnx2di;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_single_widen_addsvnx4di;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_single_widen_subsvnx4di;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_single_widen_adduvnx4di;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_single_widen_subuvnx4di;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_single_widen_addsvnx8di;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_single_widen_subsvnx8di;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_single_widen_adduvnx8di;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_single_widen_subuvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_single_widen (rtx_code arg0, rtx_code arg1, machine_mode arg2, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_single_widen (arg0, arg1, arg2);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_single_widen_scalar (rtx_code arg0, rtx_code arg1, machine_mode arg2)
{
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_single_widen_addsvnx1hi_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_single_widen_subsvnx1hi_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_single_widen_adduvnx1hi_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_single_widen_subuvnx1hi_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_single_widen_addsvnx2hi_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_single_widen_subsvnx2hi_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_single_widen_adduvnx2hi_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_single_widen_subuvnx2hi_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_single_widen_addsvnx4hi_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_single_widen_subsvnx4hi_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_single_widen_adduvnx4hi_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_single_widen_subuvnx4hi_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_single_widen_addsvnx8hi_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_single_widen_subsvnx8hi_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_single_widen_adduvnx8hi_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_single_widen_subuvnx8hi_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_single_widen_addsvnx16hi_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_single_widen_subsvnx16hi_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_single_widen_adduvnx16hi_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_single_widen_subuvnx16hi_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_single_widen_addsvnx32hi_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_single_widen_subsvnx32hi_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_single_widen_adduvnx32hi_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_single_widen_subuvnx32hi_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_single_widen_addsvnx1si_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_single_widen_subsvnx1si_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_single_widen_adduvnx1si_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_single_widen_subuvnx1si_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_single_widen_addsvnx2si_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_single_widen_subsvnx2si_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_single_widen_adduvnx2si_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_single_widen_subuvnx2si_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_single_widen_addsvnx4si_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_single_widen_subsvnx4si_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_single_widen_adduvnx4si_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_single_widen_subuvnx4si_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_single_widen_addsvnx8si_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_single_widen_subsvnx8si_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_single_widen_adduvnx8si_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_single_widen_subuvnx8si_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_single_widen_addsvnx16si_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_single_widen_subsvnx16si_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_single_widen_adduvnx16si_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_single_widen_subuvnx16si_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_single_widen_addsvnx1di_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_single_widen_subsvnx1di_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_single_widen_adduvnx1di_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_single_widen_subuvnx1di_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_single_widen_addsvnx2di_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_single_widen_subsvnx2di_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_single_widen_adduvnx2di_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_single_widen_subuvnx2di_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_single_widen_addsvnx4di_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_single_widen_subsvnx4di_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_single_widen_adduvnx4di_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_single_widen_subuvnx4di_scalar;
  if (arg0 == PLUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_single_widen_addsvnx8di_scalar;
  if (arg0 == MINUS
      && arg1 == SIGN_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_single_widen_subsvnx8di_scalar;
  if (arg0 == PLUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_single_widen_adduvnx8di_scalar;
  if (arg0 == MINUS
      && arg1 == ZERO_EXTEND
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_single_widen_subuvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_single_widen_scalar (rtx_code arg0, rtx_code arg1, machine_mode arg2, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_single_widen_scalar (arg0, arg1, arg2);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_mulsu (machine_mode arg0)
{
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_widen_mulsuvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_widen_mulsuvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_widen_mulsuvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_widen_mulsuvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_widen_mulsuvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_widen_mulsuvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_widen_mulsuvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_widen_mulsuvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_widen_mulsuvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_widen_mulsuvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_widen_mulsuvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_widen_mulsuvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_widen_mulsuvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_widen_mulsuvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_widen_mulsuvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_mulsu (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_widen_mulsu (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_mulsu_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_widen_mulsuvnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_widen_mulsuvnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_widen_mulsuvnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_widen_mulsuvnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_widen_mulsuvnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_widen_mulsuvnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_widen_mulsuvnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_widen_mulsuvnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_widen_mulsuvnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_widen_mulsuvnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_widen_mulsuvnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_widen_mulsuvnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_widen_mulsuvnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_widen_mulsuvnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_widen_mulsuvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_mulsu_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_widen_mulsu_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_narrow (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_narrow_ashrvnx1hi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_narrow_lshrvnx1hi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_narrow_ashrvnx2hi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_narrow_lshrvnx2hi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_narrow_ashrvnx4hi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_narrow_lshrvnx4hi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_narrow_ashrvnx8hi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_narrow_lshrvnx8hi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_narrow_ashrvnx16hi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_narrow_lshrvnx16hi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_narrow_ashrvnx32hi;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_narrow_lshrvnx32hi;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_narrow_ashrvnx1si;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_narrow_lshrvnx1si;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_narrow_ashrvnx2si;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_narrow_lshrvnx2si;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_narrow_ashrvnx4si;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_narrow_lshrvnx4si;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_narrow_ashrvnx8si;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_narrow_lshrvnx8si;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_narrow_ashrvnx16si;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_narrow_lshrvnx16si;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_narrow_ashrvnx1di;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_narrow_lshrvnx1di;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_narrow_ashrvnx2di;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_narrow_lshrvnx2di;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_narrow_ashrvnx4di;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_narrow_lshrvnx4di;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_narrow_ashrvnx8di;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_narrow_lshrvnx8di;
  if (arg0 == FIX
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_narrow_fix_truncvnx1sf;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_narrow_fixuns_truncvnx1sf;
  if (arg0 == FIX
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_narrow_fix_truncvnx2sf;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_narrow_fixuns_truncvnx2sf;
  if (arg0 == FIX
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_narrow_fix_truncvnx4sf;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_narrow_fixuns_truncvnx4sf;
  if (arg0 == FIX
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_narrow_fix_truncvnx8sf;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_narrow_fixuns_truncvnx8sf;
  if (arg0 == FIX
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_narrow_fix_truncvnx16sf;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_narrow_fixuns_truncvnx16sf;
  if (arg0 == FIX
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_narrow_fix_truncvnx1df;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_narrow_fixuns_truncvnx1df;
  if (arg0 == FIX
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_narrow_fix_truncvnx2df;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_narrow_fixuns_truncvnx2df;
  if (arg0 == FIX
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_narrow_fix_truncvnx4df;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_narrow_fixuns_truncvnx4df;
  if (arg0 == FIX
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_narrow_fix_truncvnx8df;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_narrow_fixuns_truncvnx8df;
  if (arg0 == FLOAT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_narrow_floatvnx1di;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_narrow_floatunsvnx1di;
  if (arg0 == FLOAT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_narrow_floatvnx2di;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_narrow_floatunsvnx2di;
  if (arg0 == FLOAT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_narrow_floatvnx4di;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_narrow_floatunsvnx4di;
  if (arg0 == FLOAT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_narrow_floatvnx8di;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_narrow_floatunsvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_narrow (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_narrow (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

rtx
maybe_gen_pred_narrow (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_narrow (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_narrow_scalar (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_narrow_ashrvnx1hi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_narrow_lshrvnx1hi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_narrow_ashrvnx2hi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_narrow_lshrvnx2hi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_narrow_ashrvnx4hi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_narrow_lshrvnx4hi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_narrow_ashrvnx8hi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_narrow_lshrvnx8hi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_narrow_ashrvnx16hi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_narrow_lshrvnx16hi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_narrow_ashrvnx32hi_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_narrow_lshrvnx32hi_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_narrow_ashrvnx1si_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_narrow_lshrvnx1si_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_narrow_ashrvnx2si_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_narrow_lshrvnx2si_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_narrow_ashrvnx4si_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_narrow_lshrvnx4si_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_narrow_ashrvnx8si_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_narrow_lshrvnx8si_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_narrow_ashrvnx16si_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_narrow_lshrvnx16si_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_narrow_ashrvnx1di_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_narrow_lshrvnx1di_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_narrow_ashrvnx2di_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_narrow_lshrvnx2di_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_narrow_ashrvnx4di_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_narrow_lshrvnx4di_scalar;
  if (arg0 == ASHIFTRT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_narrow_ashrvnx8di_scalar;
  if (arg0 == LSHIFTRT
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_narrow_lshrvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_narrow_scalar (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_narrow_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_trunc (machine_mode arg0)
{
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_truncvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_truncvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_truncvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_truncvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_truncvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_truncvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_truncvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_truncvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_truncvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_truncvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_truncvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_truncvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_truncvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_truncvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_truncvnx8di;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_truncvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_truncvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_truncvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_truncvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_trunc (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_trunc (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred (int arg0, machine_mode arg1)
{
  if (arg0 == 85
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_aadduvnx1qi;
  if (arg0 == 86
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_aaddvnx1qi;
  if (arg0 == 87
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_asubuvnx1qi;
  if (arg0 == 88
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_asubvnx1qi;
  if (arg0 == 89
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_smulvnx1qi;
  if (arg0 == 83
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_ssrlvnx1qi;
  if (arg0 == 84
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_ssravnx1qi;
  if (arg0 == 85
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_aadduvnx2qi;
  if (arg0 == 86
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_aaddvnx2qi;
  if (arg0 == 87
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_asubuvnx2qi;
  if (arg0 == 88
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_asubvnx2qi;
  if (arg0 == 89
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_smulvnx2qi;
  if (arg0 == 83
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_ssrlvnx2qi;
  if (arg0 == 84
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_ssravnx2qi;
  if (arg0 == 85
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_aadduvnx4qi;
  if (arg0 == 86
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_aaddvnx4qi;
  if (arg0 == 87
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_asubuvnx4qi;
  if (arg0 == 88
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_asubvnx4qi;
  if (arg0 == 89
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_smulvnx4qi;
  if (arg0 == 83
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_ssrlvnx4qi;
  if (arg0 == 84
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_ssravnx4qi;
  if (arg0 == 85
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_aadduvnx8qi;
  if (arg0 == 86
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_aaddvnx8qi;
  if (arg0 == 87
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_asubuvnx8qi;
  if (arg0 == 88
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_asubvnx8qi;
  if (arg0 == 89
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_smulvnx8qi;
  if (arg0 == 83
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_ssrlvnx8qi;
  if (arg0 == 84
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_ssravnx8qi;
  if (arg0 == 85
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_aadduvnx16qi;
  if (arg0 == 86
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_aaddvnx16qi;
  if (arg0 == 87
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_asubuvnx16qi;
  if (arg0 == 88
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_asubvnx16qi;
  if (arg0 == 89
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_smulvnx16qi;
  if (arg0 == 83
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_ssrlvnx16qi;
  if (arg0 == 84
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_ssravnx16qi;
  if (arg0 == 85
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_aadduvnx32qi;
  if (arg0 == 86
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_aaddvnx32qi;
  if (arg0 == 87
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_asubuvnx32qi;
  if (arg0 == 88
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_asubvnx32qi;
  if (arg0 == 89
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_smulvnx32qi;
  if (arg0 == 83
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_ssrlvnx32qi;
  if (arg0 == 84
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_ssravnx32qi;
  if (arg0 == 85
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_aadduvnx64qi;
  if (arg0 == 86
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_aaddvnx64qi;
  if (arg0 == 87
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_asubuvnx64qi;
  if (arg0 == 88
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_asubvnx64qi;
  if (arg0 == 89
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_smulvnx64qi;
  if (arg0 == 83
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_ssrlvnx64qi;
  if (arg0 == 84
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_ssravnx64qi;
  if (arg0 == 85
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_aadduvnx1hi;
  if (arg0 == 86
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_aaddvnx1hi;
  if (arg0 == 87
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_asubuvnx1hi;
  if (arg0 == 88
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_asubvnx1hi;
  if (arg0 == 89
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_smulvnx1hi;
  if (arg0 == 83
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_ssrlvnx1hi;
  if (arg0 == 84
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_ssravnx1hi;
  if (arg0 == 85
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_aadduvnx2hi;
  if (arg0 == 86
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_aaddvnx2hi;
  if (arg0 == 87
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_asubuvnx2hi;
  if (arg0 == 88
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_asubvnx2hi;
  if (arg0 == 89
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_smulvnx2hi;
  if (arg0 == 83
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_ssrlvnx2hi;
  if (arg0 == 84
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_ssravnx2hi;
  if (arg0 == 85
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_aadduvnx4hi;
  if (arg0 == 86
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_aaddvnx4hi;
  if (arg0 == 87
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_asubuvnx4hi;
  if (arg0 == 88
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_asubvnx4hi;
  if (arg0 == 89
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_smulvnx4hi;
  if (arg0 == 83
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_ssrlvnx4hi;
  if (arg0 == 84
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_ssravnx4hi;
  if (arg0 == 85
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_aadduvnx8hi;
  if (arg0 == 86
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_aaddvnx8hi;
  if (arg0 == 87
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_asubuvnx8hi;
  if (arg0 == 88
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_asubvnx8hi;
  if (arg0 == 89
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_smulvnx8hi;
  if (arg0 == 83
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_ssrlvnx8hi;
  if (arg0 == 84
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_ssravnx8hi;
  if (arg0 == 85
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_aadduvnx16hi;
  if (arg0 == 86
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_aaddvnx16hi;
  if (arg0 == 87
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_asubuvnx16hi;
  if (arg0 == 88
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_asubvnx16hi;
  if (arg0 == 89
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_smulvnx16hi;
  if (arg0 == 83
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_ssrlvnx16hi;
  if (arg0 == 84
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_ssravnx16hi;
  if (arg0 == 85
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_aadduvnx32hi;
  if (arg0 == 86
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_aaddvnx32hi;
  if (arg0 == 87
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_asubuvnx32hi;
  if (arg0 == 88
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_asubvnx32hi;
  if (arg0 == 89
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_smulvnx32hi;
  if (arg0 == 83
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_ssrlvnx32hi;
  if (arg0 == 84
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_ssravnx32hi;
  if (arg0 == 85
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_aadduvnx1si;
  if (arg0 == 86
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_aaddvnx1si;
  if (arg0 == 87
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_asubuvnx1si;
  if (arg0 == 88
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_asubvnx1si;
  if (arg0 == 89
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_smulvnx1si;
  if (arg0 == 83
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_ssrlvnx1si;
  if (arg0 == 84
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_ssravnx1si;
  if (arg0 == 85
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_aadduvnx2si;
  if (arg0 == 86
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_aaddvnx2si;
  if (arg0 == 87
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_asubuvnx2si;
  if (arg0 == 88
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_asubvnx2si;
  if (arg0 == 89
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_smulvnx2si;
  if (arg0 == 83
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_ssrlvnx2si;
  if (arg0 == 84
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_ssravnx2si;
  if (arg0 == 85
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_aadduvnx4si;
  if (arg0 == 86
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_aaddvnx4si;
  if (arg0 == 87
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_asubuvnx4si;
  if (arg0 == 88
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_asubvnx4si;
  if (arg0 == 89
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_smulvnx4si;
  if (arg0 == 83
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_ssrlvnx4si;
  if (arg0 == 84
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_ssravnx4si;
  if (arg0 == 85
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_aadduvnx8si;
  if (arg0 == 86
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_aaddvnx8si;
  if (arg0 == 87
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_asubuvnx8si;
  if (arg0 == 88
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_asubvnx8si;
  if (arg0 == 89
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_smulvnx8si;
  if (arg0 == 83
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_ssrlvnx8si;
  if (arg0 == 84
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_ssravnx8si;
  if (arg0 == 85
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_aadduvnx16si;
  if (arg0 == 86
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_aaddvnx16si;
  if (arg0 == 87
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_asubuvnx16si;
  if (arg0 == 88
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_asubvnx16si;
  if (arg0 == 89
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_smulvnx16si;
  if (arg0 == 83
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_ssrlvnx16si;
  if (arg0 == 84
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_ssravnx16si;
  if (arg0 == 85
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_aadduvnx1di;
  if (arg0 == 86
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_aaddvnx1di;
  if (arg0 == 87
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_asubuvnx1di;
  if (arg0 == 88
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_asubvnx1di;
  if (arg0 == 89
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_smulvnx1di;
  if (arg0 == 83
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_ssrlvnx1di;
  if (arg0 == 84
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_ssravnx1di;
  if (arg0 == 85
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_aadduvnx2di;
  if (arg0 == 86
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_aaddvnx2di;
  if (arg0 == 87
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_asubuvnx2di;
  if (arg0 == 88
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_asubvnx2di;
  if (arg0 == 89
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_smulvnx2di;
  if (arg0 == 83
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_ssrlvnx2di;
  if (arg0 == 84
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_ssravnx2di;
  if (arg0 == 85
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_aadduvnx4di;
  if (arg0 == 86
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_aaddvnx4di;
  if (arg0 == 87
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_asubuvnx4di;
  if (arg0 == 88
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_asubvnx4di;
  if (arg0 == 89
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_smulvnx4di;
  if (arg0 == 83
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_ssrlvnx4di;
  if (arg0 == 84
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_ssravnx4di;
  if (arg0 == 85
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_aadduvnx8di;
  if (arg0 == 86
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_aaddvnx8di;
  if (arg0 == 87
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_asubuvnx8di;
  if (arg0 == 88
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_asubvnx8di;
  if (arg0 == 89
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_smulvnx8di;
  if (arg0 == 83
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_ssrlvnx8di;
  if (arg0 == 84
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_ssravnx8di;
  if (arg0 == 90
      && arg1 == E_VNx1BImode)
    return CODE_FOR_pred_sbfvnx1bi;
  if (arg0 == 91
      && arg1 == E_VNx1BImode)
    return CODE_FOR_pred_sifvnx1bi;
  if (arg0 == 92
      && arg1 == E_VNx1BImode)
    return CODE_FOR_pred_sofvnx1bi;
  if (arg0 == 90
      && arg1 == E_VNx2BImode)
    return CODE_FOR_pred_sbfvnx2bi;
  if (arg0 == 91
      && arg1 == E_VNx2BImode)
    return CODE_FOR_pred_sifvnx2bi;
  if (arg0 == 92
      && arg1 == E_VNx2BImode)
    return CODE_FOR_pred_sofvnx2bi;
  if (arg0 == 90
      && arg1 == E_VNx4BImode)
    return CODE_FOR_pred_sbfvnx4bi;
  if (arg0 == 91
      && arg1 == E_VNx4BImode)
    return CODE_FOR_pred_sifvnx4bi;
  if (arg0 == 92
      && arg1 == E_VNx4BImode)
    return CODE_FOR_pred_sofvnx4bi;
  if (arg0 == 90
      && arg1 == E_VNx8BImode)
    return CODE_FOR_pred_sbfvnx8bi;
  if (arg0 == 91
      && arg1 == E_VNx8BImode)
    return CODE_FOR_pred_sifvnx8bi;
  if (arg0 == 92
      && arg1 == E_VNx8BImode)
    return CODE_FOR_pred_sofvnx8bi;
  if (arg0 == 90
      && arg1 == E_VNx16BImode)
    return CODE_FOR_pred_sbfvnx16bi;
  if (arg0 == 91
      && arg1 == E_VNx16BImode)
    return CODE_FOR_pred_sifvnx16bi;
  if (arg0 == 92
      && arg1 == E_VNx16BImode)
    return CODE_FOR_pred_sofvnx16bi;
  if (arg0 == 90
      && arg1 == E_VNx32BImode)
    return CODE_FOR_pred_sbfvnx32bi;
  if (arg0 == 91
      && arg1 == E_VNx32BImode)
    return CODE_FOR_pred_sifvnx32bi;
  if (arg0 == 92
      && arg1 == E_VNx32BImode)
    return CODE_FOR_pred_sofvnx32bi;
  if (arg0 == 90
      && arg1 == E_VNx64BImode)
    return CODE_FOR_pred_sbfvnx64bi;
  if (arg0 == 91
      && arg1 == E_VNx64BImode)
    return CODE_FOR_pred_sifvnx64bi;
  if (arg0 == 92
      && arg1 == E_VNx64BImode)
    return CODE_FOR_pred_sofvnx64bi;
  if (arg0 == 97
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_copysignvnx1sf;
  if (arg0 == 98
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_ncopysignvnx1sf;
  if (arg0 == 99
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_xorsignvnx1sf;
  if (arg0 == 97
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_copysignvnx2sf;
  if (arg0 == 98
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_ncopysignvnx2sf;
  if (arg0 == 99
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_xorsignvnx2sf;
  if (arg0 == 97
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_copysignvnx4sf;
  if (arg0 == 98
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_ncopysignvnx4sf;
  if (arg0 == 99
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_xorsignvnx4sf;
  if (arg0 == 97
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_copysignvnx8sf;
  if (arg0 == 98
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_ncopysignvnx8sf;
  if (arg0 == 99
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_xorsignvnx8sf;
  if (arg0 == 97
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_copysignvnx16sf;
  if (arg0 == 98
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_ncopysignvnx16sf;
  if (arg0 == 99
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_xorsignvnx16sf;
  if (arg0 == 97
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_copysignvnx1df;
  if (arg0 == 98
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_ncopysignvnx1df;
  if (arg0 == 99
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_xorsignvnx1df;
  if (arg0 == 97
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_copysignvnx2df;
  if (arg0 == 98
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_ncopysignvnx2df;
  if (arg0 == 99
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_xorsignvnx2df;
  if (arg0 == 97
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_copysignvnx4df;
  if (arg0 == 98
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_ncopysignvnx4df;
  if (arg0 == 99
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_xorsignvnx4df;
  if (arg0 == 97
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_copysignvnx8df;
  if (arg0 == 98
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_ncopysignvnx8df;
  if (arg0 == 99
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_xorsignvnx8df;
  if (arg0 == 94
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_rsqrt7vnx1sf;
  if (arg0 == 95
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_rec7vnx1sf;
  if (arg0 == 94
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_rsqrt7vnx2sf;
  if (arg0 == 95
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_rec7vnx2sf;
  if (arg0 == 94
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_rsqrt7vnx4sf;
  if (arg0 == 95
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_rec7vnx4sf;
  if (arg0 == 94
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_rsqrt7vnx8sf;
  if (arg0 == 95
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_rec7vnx8sf;
  if (arg0 == 94
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_rsqrt7vnx16sf;
  if (arg0 == 95
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_rec7vnx16sf;
  if (arg0 == 94
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_rsqrt7vnx1df;
  if (arg0 == 95
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_rec7vnx1df;
  if (arg0 == 94
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_rsqrt7vnx2df;
  if (arg0 == 95
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_rec7vnx2df;
  if (arg0 == 94
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_rsqrt7vnx4df;
  if (arg0 == 95
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_rec7vnx4df;
  if (arg0 == 94
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_rsqrt7vnx8df;
  if (arg0 == 95
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_rec7vnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

rtx
maybe_gen_pred (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6)
{
  insn_code code = maybe_code_for_pred (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 7);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6);
    }
  else
    return NULL_RTX;
}

rtx
maybe_gen_pred (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_scalar (int arg0, machine_mode arg1)
{
  if (arg0 == 85
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_aadduvnx1qi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_aaddvnx1qi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_asubuvnx1qi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_asubvnx1qi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_smulvnx1qi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_aadduvnx2qi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_aaddvnx2qi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_asubuvnx2qi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_asubvnx2qi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_smulvnx2qi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_aadduvnx4qi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_aaddvnx4qi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_asubuvnx4qi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_asubvnx4qi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_smulvnx4qi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_aadduvnx8qi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_aaddvnx8qi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_asubuvnx8qi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_asubvnx8qi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_smulvnx8qi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_aadduvnx16qi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_aaddvnx16qi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_asubuvnx16qi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_asubvnx16qi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_smulvnx16qi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_aadduvnx32qi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_aaddvnx32qi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_asubuvnx32qi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_asubvnx32qi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_smulvnx32qi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_aadduvnx64qi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_aaddvnx64qi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_asubuvnx64qi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_asubvnx64qi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_smulvnx64qi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_aadduvnx1hi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_aaddvnx1hi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_asubuvnx1hi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_asubvnx1hi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_smulvnx1hi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_aadduvnx2hi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_aaddvnx2hi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_asubuvnx2hi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_asubvnx2hi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_smulvnx2hi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_aadduvnx4hi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_aaddvnx4hi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_asubuvnx4hi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_asubvnx4hi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_smulvnx4hi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_aadduvnx8hi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_aaddvnx8hi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_asubuvnx8hi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_asubvnx8hi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_smulvnx8hi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_aadduvnx16hi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_aaddvnx16hi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_asubuvnx16hi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_asubvnx16hi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_smulvnx16hi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_aadduvnx32hi_scalar;
  if (arg0 == 86
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_aaddvnx32hi_scalar;
  if (arg0 == 87
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_asubuvnx32hi_scalar;
  if (arg0 == 88
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_asubvnx32hi_scalar;
  if (arg0 == 89
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_smulvnx32hi_scalar;
  if (arg0 == 85
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_aadduvnx1si_scalar;
  if (arg0 == 86
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_aaddvnx1si_scalar;
  if (arg0 == 87
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_asubuvnx1si_scalar;
  if (arg0 == 88
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_asubvnx1si_scalar;
  if (arg0 == 89
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_smulvnx1si_scalar;
  if (arg0 == 85
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_aadduvnx2si_scalar;
  if (arg0 == 86
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_aaddvnx2si_scalar;
  if (arg0 == 87
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_asubuvnx2si_scalar;
  if (arg0 == 88
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_asubvnx2si_scalar;
  if (arg0 == 89
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_smulvnx2si_scalar;
  if (arg0 == 85
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_aadduvnx4si_scalar;
  if (arg0 == 86
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_aaddvnx4si_scalar;
  if (arg0 == 87
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_asubuvnx4si_scalar;
  if (arg0 == 88
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_asubvnx4si_scalar;
  if (arg0 == 89
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_smulvnx4si_scalar;
  if (arg0 == 85
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_aadduvnx8si_scalar;
  if (arg0 == 86
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_aaddvnx8si_scalar;
  if (arg0 == 87
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_asubuvnx8si_scalar;
  if (arg0 == 88
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_asubvnx8si_scalar;
  if (arg0 == 89
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_smulvnx8si_scalar;
  if (arg0 == 85
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_aadduvnx16si_scalar;
  if (arg0 == 86
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_aaddvnx16si_scalar;
  if (arg0 == 87
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_asubuvnx16si_scalar;
  if (arg0 == 88
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_asubvnx16si_scalar;
  if (arg0 == 89
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_smulvnx16si_scalar;
  if (arg0 == 83
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_ssrlvnx1qi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_ssravnx1qi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_ssrlvnx2qi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_ssravnx2qi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_ssrlvnx4qi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_ssravnx4qi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_ssrlvnx8qi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_ssravnx8qi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_ssrlvnx16qi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_ssravnx16qi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_ssrlvnx32qi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_ssravnx32qi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_ssrlvnx64qi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_ssravnx64qi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_ssrlvnx1hi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_ssravnx1hi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_ssrlvnx2hi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_ssravnx2hi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_ssrlvnx4hi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_ssravnx4hi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_ssrlvnx8hi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_ssravnx8hi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_ssrlvnx16hi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_ssravnx16hi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_ssrlvnx32hi_scalar;
  if (arg0 == 84
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_ssravnx32hi_scalar;
  if (arg0 == 83
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_ssrlvnx1si_scalar;
  if (arg0 == 84
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_ssravnx1si_scalar;
  if (arg0 == 83
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_ssrlvnx2si_scalar;
  if (arg0 == 84
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_ssravnx2si_scalar;
  if (arg0 == 83
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_ssrlvnx4si_scalar;
  if (arg0 == 84
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_ssravnx4si_scalar;
  if (arg0 == 83
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_ssrlvnx8si_scalar;
  if (arg0 == 84
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_ssravnx8si_scalar;
  if (arg0 == 83
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_ssrlvnx16si_scalar;
  if (arg0 == 84
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_ssravnx16si_scalar;
  if (arg0 == 83
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_ssrlvnx1di_scalar;
  if (arg0 == 84
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_ssravnx1di_scalar;
  if (arg0 == 83
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_ssrlvnx2di_scalar;
  if (arg0 == 84
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_ssravnx2di_scalar;
  if (arg0 == 83
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_ssrlvnx4di_scalar;
  if (arg0 == 84
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_ssravnx4di_scalar;
  if (arg0 == 83
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_ssrlvnx8di_scalar;
  if (arg0 == 84
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_ssravnx8di_scalar;
  if (arg0 == 85
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_aadduvnx1di_scalar;
  if (arg0 == 86
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_aaddvnx1di_scalar;
  if (arg0 == 87
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_asubuvnx1di_scalar;
  if (arg0 == 88
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_asubvnx1di_scalar;
  if (arg0 == 89
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_smulvnx1di_scalar;
  if (arg0 == 85
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_aadduvnx2di_scalar;
  if (arg0 == 86
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_aaddvnx2di_scalar;
  if (arg0 == 87
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_asubuvnx2di_scalar;
  if (arg0 == 88
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_asubvnx2di_scalar;
  if (arg0 == 89
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_smulvnx2di_scalar;
  if (arg0 == 85
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_aadduvnx4di_scalar;
  if (arg0 == 86
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_aaddvnx4di_scalar;
  if (arg0 == 87
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_asubuvnx4di_scalar;
  if (arg0 == 88
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_asubvnx4di_scalar;
  if (arg0 == 89
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_smulvnx4di_scalar;
  if (arg0 == 85
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_aadduvnx8di_scalar;
  if (arg0 == 86
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_aaddvnx8di_scalar;
  if (arg0 == 87
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_asubuvnx8di_scalar;
  if (arg0 == 88
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_asubvnx8di_scalar;
  if (arg0 == 89
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_smulvnx8di_scalar;
  if (arg0 == 97
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_copysignvnx1sf_scalar;
  if (arg0 == 98
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_ncopysignvnx1sf_scalar;
  if (arg0 == 99
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_xorsignvnx1sf_scalar;
  if (arg0 == 97
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_copysignvnx2sf_scalar;
  if (arg0 == 98
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_ncopysignvnx2sf_scalar;
  if (arg0 == 99
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_xorsignvnx2sf_scalar;
  if (arg0 == 97
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_copysignvnx4sf_scalar;
  if (arg0 == 98
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_ncopysignvnx4sf_scalar;
  if (arg0 == 99
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_xorsignvnx4sf_scalar;
  if (arg0 == 97
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_copysignvnx8sf_scalar;
  if (arg0 == 98
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_ncopysignvnx8sf_scalar;
  if (arg0 == 99
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_xorsignvnx8sf_scalar;
  if (arg0 == 97
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_copysignvnx16sf_scalar;
  if (arg0 == 98
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_ncopysignvnx16sf_scalar;
  if (arg0 == 99
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_xorsignvnx16sf_scalar;
  if (arg0 == 97
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_copysignvnx1df_scalar;
  if (arg0 == 98
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_ncopysignvnx1df_scalar;
  if (arg0 == 99
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_xorsignvnx1df_scalar;
  if (arg0 == 97
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_copysignvnx2df_scalar;
  if (arg0 == 98
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_ncopysignvnx2df_scalar;
  if (arg0 == 99
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_xorsignvnx2df_scalar;
  if (arg0 == 97
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_copysignvnx4df_scalar;
  if (arg0 == 98
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_ncopysignvnx4df_scalar;
  if (arg0 == 99
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_xorsignvnx4df_scalar;
  if (arg0 == 97
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_copysignvnx8df_scalar;
  if (arg0 == 98
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_ncopysignvnx8df_scalar;
  if (arg0 == 99
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_xorsignvnx8df_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_scalar (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_narrow_clip (int arg0, machine_mode arg1)
{
  if (arg0 == 81
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_narrow_clipvnx1hi;
  if (arg0 == 82
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_narrow_clipuvnx1hi;
  if (arg0 == 81
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_narrow_clipvnx2hi;
  if (arg0 == 82
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_narrow_clipuvnx2hi;
  if (arg0 == 81
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_narrow_clipvnx4hi;
  if (arg0 == 82
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_narrow_clipuvnx4hi;
  if (arg0 == 81
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_narrow_clipvnx8hi;
  if (arg0 == 82
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_narrow_clipuvnx8hi;
  if (arg0 == 81
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_narrow_clipvnx16hi;
  if (arg0 == 82
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_narrow_clipuvnx16hi;
  if (arg0 == 81
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_narrow_clipvnx32hi;
  if (arg0 == 82
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_narrow_clipuvnx32hi;
  if (arg0 == 81
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_narrow_clipvnx1si;
  if (arg0 == 82
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_narrow_clipuvnx1si;
  if (arg0 == 81
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_narrow_clipvnx2si;
  if (arg0 == 82
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_narrow_clipuvnx2si;
  if (arg0 == 81
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_narrow_clipvnx4si;
  if (arg0 == 82
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_narrow_clipuvnx4si;
  if (arg0 == 81
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_narrow_clipvnx8si;
  if (arg0 == 82
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_narrow_clipuvnx8si;
  if (arg0 == 81
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_narrow_clipvnx16si;
  if (arg0 == 82
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_narrow_clipuvnx16si;
  if (arg0 == 81
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_narrow_clipvnx1di;
  if (arg0 == 82
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_narrow_clipuvnx1di;
  if (arg0 == 81
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_narrow_clipvnx2di;
  if (arg0 == 82
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_narrow_clipuvnx2di;
  if (arg0 == 81
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_narrow_clipvnx4di;
  if (arg0 == 82
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_narrow_clipuvnx4di;
  if (arg0 == 81
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_narrow_clipvnx8di;
  if (arg0 == 82
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_narrow_clipuvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_narrow_clip (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_narrow_clip (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_narrow_clip_scalar (int arg0, machine_mode arg1)
{
  if (arg0 == 81
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_narrow_clipvnx1hi_scalar;
  if (arg0 == 82
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_narrow_clipuvnx1hi_scalar;
  if (arg0 == 81
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_narrow_clipvnx2hi_scalar;
  if (arg0 == 82
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_narrow_clipuvnx2hi_scalar;
  if (arg0 == 81
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_narrow_clipvnx4hi_scalar;
  if (arg0 == 82
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_narrow_clipuvnx4hi_scalar;
  if (arg0 == 81
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_narrow_clipvnx8hi_scalar;
  if (arg0 == 82
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_narrow_clipuvnx8hi_scalar;
  if (arg0 == 81
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_narrow_clipvnx16hi_scalar;
  if (arg0 == 82
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_narrow_clipuvnx16hi_scalar;
  if (arg0 == 81
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_narrow_clipvnx32hi_scalar;
  if (arg0 == 82
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_narrow_clipuvnx32hi_scalar;
  if (arg0 == 81
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_narrow_clipvnx1si_scalar;
  if (arg0 == 82
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_narrow_clipuvnx1si_scalar;
  if (arg0 == 81
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_narrow_clipvnx2si_scalar;
  if (arg0 == 82
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_narrow_clipuvnx2si_scalar;
  if (arg0 == 81
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_narrow_clipvnx4si_scalar;
  if (arg0 == 82
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_narrow_clipuvnx4si_scalar;
  if (arg0 == 81
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_narrow_clipvnx8si_scalar;
  if (arg0 == 82
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_narrow_clipuvnx8si_scalar;
  if (arg0 == 81
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_narrow_clipvnx16si_scalar;
  if (arg0 == 82
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_narrow_clipuvnx16si_scalar;
  if (arg0 == 81
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_narrow_clipvnx1di_scalar;
  if (arg0 == 82
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_narrow_clipuvnx1di_scalar;
  if (arg0 == 81
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_narrow_clipvnx2di_scalar;
  if (arg0 == 82
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_narrow_clipuvnx2di_scalar;
  if (arg0 == 81
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_narrow_clipvnx4di_scalar;
  if (arg0 == 82
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_narrow_clipuvnx4di_scalar;
  if (arg0 == 81
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_narrow_clipvnx8di_scalar;
  if (arg0 == 82
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_narrow_clipuvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_narrow_clip_scalar (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_narrow_clip_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_cmp (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_cmpvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_cmpvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_cmpvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_cmpvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_cmpvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_cmpvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_cmpvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_cmpvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_cmpvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_cmpvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_cmpvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_cmpvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_cmpvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_cmpvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_cmpvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_cmpvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_cmpvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_cmpvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_cmpvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_cmpvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_cmpvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_cmpvnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_cmpvnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_cmpvnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_cmpvnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_cmpvnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_cmpvnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_cmpvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_cmpvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_cmpvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_cmpvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_cmp (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_cmp (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_ltge (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_ltgevnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_ltgevnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_ltgevnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_ltgevnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_ltgevnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_ltgevnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_ltgevnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_ltgevnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_ltgevnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_ltgevnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_ltgevnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_ltgevnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_ltgevnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_ltgevnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_ltgevnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_ltgevnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_ltgevnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_ltgevnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_ltgevnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_ltgevnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_ltgevnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_ltgevnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_ltge (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_ltge (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_cmp_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_cmpvnx1qi_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_cmpvnx2qi_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_cmpvnx4qi_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_cmpvnx8qi_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_cmpvnx16qi_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_cmpvnx32qi_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_cmpvnx64qi_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_cmpvnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_cmpvnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_cmpvnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_cmpvnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_cmpvnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_cmpvnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_cmpvnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_cmpvnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_cmpvnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_cmpvnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_cmpvnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_cmpvnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_cmpvnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_cmpvnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_cmpvnx8di_scalar;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_cmpvnx1sf_scalar;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_cmpvnx2sf_scalar;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_cmpvnx4sf_scalar;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_cmpvnx8sf_scalar;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_cmpvnx16sf_scalar;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_cmpvnx1df_scalar;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_cmpvnx2df_scalar;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_cmpvnx4df_scalar;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_cmpvnx8df_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_cmp_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_cmp_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_eqne_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_eqnevnx1qi_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_eqnevnx2qi_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_eqnevnx4qi_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_eqnevnx8qi_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_eqnevnx16qi_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_eqnevnx32qi_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_eqnevnx64qi_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_eqnevnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_eqnevnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_eqnevnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_eqnevnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_eqnevnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_eqnevnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_eqnevnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_eqnevnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_eqnevnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_eqnevnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_eqnevnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_eqnevnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_eqnevnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_eqnevnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_eqnevnx8di_scalar;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_eqnevnx1sf_scalar;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_eqnevnx2sf_scalar;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_eqnevnx4sf_scalar;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_eqnevnx8sf_scalar;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_eqnevnx16sf_scalar;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_eqnevnx1df_scalar;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_eqnevnx2df_scalar;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_eqnevnx4df_scalar;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_eqnevnx8df_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_eqne_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_eqne_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_ge_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_gevnx1qi_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_gevnx2qi_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_gevnx4qi_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_gevnx8qi_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_gevnx16qi_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_gevnx32qi_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_gevnx64qi_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_gevnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_gevnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_gevnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_gevnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_gevnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_gevnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_gevnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_gevnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_gevnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_gevnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_gevnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_gevnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_gevnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_gevnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_gevnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_ge_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_ge_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_mul_plus (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_mul_plusvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_mul_plusvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_mul_plusvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_mul_plusvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_mul_plusvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_mul_plusvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_mul_plusvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_mul_plusvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_mul_plusvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_mul_plusvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_mul_plusvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_mul_plusvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_mul_plusvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_mul_plusvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_mul_plusvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_mul_plusvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_mul_plusvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_mul_plusvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_mul_plusvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_mul_plusvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_mul_plusvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_mul_plusvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_mul_plus (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8, rtx x9)
{
  insn_code code = maybe_code_for_pred_mul_plus (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 10);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8, x9);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_mul_plus_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_mul_plusvnx1qi_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_mul_plusvnx2qi_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_mul_plusvnx4qi_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_mul_plusvnx8qi_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_mul_plusvnx16qi_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_mul_plusvnx32qi_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_mul_plusvnx64qi_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_mul_plusvnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_mul_plusvnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_mul_plusvnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_mul_plusvnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_mul_plusvnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_mul_plusvnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_mul_plusvnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_mul_plusvnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_mul_plusvnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_mul_plusvnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_mul_plusvnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_mul_plusvnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_mul_plusvnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_mul_plusvnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_mul_plusvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_mul_plus_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8, rtx x9)
{
  insn_code code = maybe_code_for_pred_mul_plus_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 10);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8, x9);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_minus_mul (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_minus_mulvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_minus_mulvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_minus_mulvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_minus_mulvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_minus_mulvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_minus_mulvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_minus_mulvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_minus_mulvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_minus_mulvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_minus_mulvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_minus_mulvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_minus_mulvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_minus_mulvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_minus_mulvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_minus_mulvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_minus_mulvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_minus_mulvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_minus_mulvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_minus_mulvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_minus_mulvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_minus_mulvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_minus_mulvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_minus_mul (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8, rtx x9)
{
  insn_code code = maybe_code_for_pred_minus_mul (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 10);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8, x9);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_minus_mul_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_minus_mulvnx1qi_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_minus_mulvnx2qi_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_minus_mulvnx4qi_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_minus_mulvnx8qi_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_minus_mulvnx16qi_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_minus_mulvnx32qi_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_minus_mulvnx64qi_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_minus_mulvnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_minus_mulvnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_minus_mulvnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_minus_mulvnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_minus_mulvnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_minus_mulvnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_minus_mulvnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_minus_mulvnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_minus_mulvnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_minus_mulvnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_minus_mulvnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_minus_mulvnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_minus_mulvnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_minus_mulvnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_minus_mulvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_minus_mul_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8, rtx x9)
{
  insn_code code = maybe_code_for_pred_minus_mul_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 10);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8, x9);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_mul_plus (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_widen_mul_plussvnx1hi;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_widen_mul_plusuvnx1hi;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_widen_mul_plussvnx2hi;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_widen_mul_plusuvnx2hi;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_widen_mul_plussvnx4hi;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_widen_mul_plusuvnx4hi;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_widen_mul_plussvnx8hi;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_widen_mul_plusuvnx8hi;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_widen_mul_plussvnx16hi;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_widen_mul_plusuvnx16hi;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_widen_mul_plussvnx32hi;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_widen_mul_plusuvnx32hi;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_widen_mul_plussvnx1si;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_widen_mul_plusuvnx1si;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_widen_mul_plussvnx2si;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_widen_mul_plusuvnx2si;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_widen_mul_plussvnx4si;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_widen_mul_plusuvnx4si;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_widen_mul_plussvnx8si;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_widen_mul_plusuvnx8si;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_widen_mul_plussvnx16si;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_widen_mul_plusuvnx16si;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_widen_mul_plussvnx1di;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_widen_mul_plusuvnx1di;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_widen_mul_plussvnx2di;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_widen_mul_plusuvnx2di;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_widen_mul_plussvnx4di;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_widen_mul_plusuvnx4di;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_widen_mul_plussvnx8di;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_widen_mul_plusuvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_mul_plus (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_widen_mul_plus (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_mul_plus_scalar (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_widen_mul_plussvnx1hi_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_widen_mul_plusuvnx1hi_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_widen_mul_plussvnx2hi_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_widen_mul_plusuvnx2hi_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_widen_mul_plussvnx4hi_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_widen_mul_plusuvnx4hi_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_widen_mul_plussvnx8hi_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_widen_mul_plusuvnx8hi_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_widen_mul_plussvnx16hi_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_widen_mul_plusuvnx16hi_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_widen_mul_plussvnx32hi_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_widen_mul_plusuvnx32hi_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_widen_mul_plussvnx1si_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_widen_mul_plusuvnx1si_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_widen_mul_plussvnx2si_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_widen_mul_plusuvnx2si_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_widen_mul_plussvnx4si_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_widen_mul_plusuvnx4si_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_widen_mul_plussvnx8si_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_widen_mul_plusuvnx8si_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_widen_mul_plussvnx16si_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_widen_mul_plusuvnx16si_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_widen_mul_plussvnx1di_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_widen_mul_plusuvnx1di_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_widen_mul_plussvnx2di_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_widen_mul_plusuvnx2di_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_widen_mul_plussvnx4di_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_widen_mul_plusuvnx4di_scalar;
  if (arg0 == SIGN_EXTEND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_widen_mul_plussvnx8di_scalar;
  if (arg0 == ZERO_EXTEND
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_widen_mul_plusuvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_mul_plus_scalar (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_widen_mul_plus_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_mul_plussu (machine_mode arg0)
{
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_widen_mul_plussuvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_widen_mul_plussuvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_widen_mul_plussuvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_widen_mul_plussuvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_widen_mul_plussuvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_widen_mul_plussuvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_widen_mul_plussuvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_widen_mul_plussuvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_widen_mul_plussuvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_widen_mul_plussuvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_widen_mul_plussuvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_widen_mul_plussuvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_widen_mul_plussuvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_widen_mul_plussuvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_widen_mul_plussuvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_mul_plussu (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_widen_mul_plussu (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_mul_plussu_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_widen_mul_plussuvnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_widen_mul_plussuvnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_widen_mul_plussuvnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_widen_mul_plussuvnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_widen_mul_plussuvnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_widen_mul_plussuvnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_widen_mul_plussuvnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_widen_mul_plussuvnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_widen_mul_plussuvnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_widen_mul_plussuvnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_widen_mul_plussuvnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_widen_mul_plussuvnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_widen_mul_plussuvnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_widen_mul_plussuvnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_widen_mul_plussuvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_mul_plussu_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_widen_mul_plussu_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_mul_plusus_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_widen_mul_plususvnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_widen_mul_plususvnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_widen_mul_plususvnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_widen_mul_plususvnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_widen_mul_plususvnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_widen_mul_plususvnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_widen_mul_plususvnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_widen_mul_plususvnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_widen_mul_plususvnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_widen_mul_plususvnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_widen_mul_plususvnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_widen_mul_plususvnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_widen_mul_plususvnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_widen_mul_plususvnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_widen_mul_plususvnx8di_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_mul_plusus_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_widen_mul_plusus_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_n (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == AND
      && arg1 == E_VNx1BImode)
    return CODE_FOR_pred_nandvnx1bi;
  if (arg0 == IOR
      && arg1 == E_VNx1BImode)
    return CODE_FOR_pred_niorvnx1bi;
  if (arg0 == XOR
      && arg1 == E_VNx1BImode)
    return CODE_FOR_pred_nxorvnx1bi;
  if (arg0 == AND
      && arg1 == E_VNx2BImode)
    return CODE_FOR_pred_nandvnx2bi;
  if (arg0 == IOR
      && arg1 == E_VNx2BImode)
    return CODE_FOR_pred_niorvnx2bi;
  if (arg0 == XOR
      && arg1 == E_VNx2BImode)
    return CODE_FOR_pred_nxorvnx2bi;
  if (arg0 == AND
      && arg1 == E_VNx4BImode)
    return CODE_FOR_pred_nandvnx4bi;
  if (arg0 == IOR
      && arg1 == E_VNx4BImode)
    return CODE_FOR_pred_niorvnx4bi;
  if (arg0 == XOR
      && arg1 == E_VNx4BImode)
    return CODE_FOR_pred_nxorvnx4bi;
  if (arg0 == AND
      && arg1 == E_VNx8BImode)
    return CODE_FOR_pred_nandvnx8bi;
  if (arg0 == IOR
      && arg1 == E_VNx8BImode)
    return CODE_FOR_pred_niorvnx8bi;
  if (arg0 == XOR
      && arg1 == E_VNx8BImode)
    return CODE_FOR_pred_nxorvnx8bi;
  if (arg0 == AND
      && arg1 == E_VNx16BImode)
    return CODE_FOR_pred_nandvnx16bi;
  if (arg0 == IOR
      && arg1 == E_VNx16BImode)
    return CODE_FOR_pred_niorvnx16bi;
  if (arg0 == XOR
      && arg1 == E_VNx16BImode)
    return CODE_FOR_pred_nxorvnx16bi;
  if (arg0 == AND
      && arg1 == E_VNx32BImode)
    return CODE_FOR_pred_nandvnx32bi;
  if (arg0 == IOR
      && arg1 == E_VNx32BImode)
    return CODE_FOR_pred_niorvnx32bi;
  if (arg0 == XOR
      && arg1 == E_VNx32BImode)
    return CODE_FOR_pred_nxorvnx32bi;
  if (arg0 == AND
      && arg1 == E_VNx64BImode)
    return CODE_FOR_pred_nandvnx64bi;
  if (arg0 == IOR
      && arg1 == E_VNx64BImode)
    return CODE_FOR_pred_niorvnx64bi;
  if (arg0 == XOR
      && arg1 == E_VNx64BImode)
    return CODE_FOR_pred_nxorvnx64bi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_n (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6)
{
  insn_code code = maybe_code_for_pred_n (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 7);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_not (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == AND
      && arg1 == E_VNx1BImode)
    return CODE_FOR_pred_andnotvnx1bi;
  if (arg0 == IOR
      && arg1 == E_VNx1BImode)
    return CODE_FOR_pred_iornotvnx1bi;
  if (arg0 == AND
      && arg1 == E_VNx2BImode)
    return CODE_FOR_pred_andnotvnx2bi;
  if (arg0 == IOR
      && arg1 == E_VNx2BImode)
    return CODE_FOR_pred_iornotvnx2bi;
  if (arg0 == AND
      && arg1 == E_VNx4BImode)
    return CODE_FOR_pred_andnotvnx4bi;
  if (arg0 == IOR
      && arg1 == E_VNx4BImode)
    return CODE_FOR_pred_iornotvnx4bi;
  if (arg0 == AND
      && arg1 == E_VNx8BImode)
    return CODE_FOR_pred_andnotvnx8bi;
  if (arg0 == IOR
      && arg1 == E_VNx8BImode)
    return CODE_FOR_pred_iornotvnx8bi;
  if (arg0 == AND
      && arg1 == E_VNx16BImode)
    return CODE_FOR_pred_andnotvnx16bi;
  if (arg0 == IOR
      && arg1 == E_VNx16BImode)
    return CODE_FOR_pred_iornotvnx16bi;
  if (arg0 == AND
      && arg1 == E_VNx32BImode)
    return CODE_FOR_pred_andnotvnx32bi;
  if (arg0 == IOR
      && arg1 == E_VNx32BImode)
    return CODE_FOR_pred_iornotvnx32bi;
  if (arg0 == AND
      && arg1 == E_VNx64BImode)
    return CODE_FOR_pred_andnotvnx64bi;
  if (arg0 == IOR
      && arg1 == E_VNx64BImode)
    return CODE_FOR_pred_iornotvnx64bi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_not (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6)
{
  insn_code code = maybe_code_for_pred_not (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 7);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_not (machine_mode arg0)
{
  if (arg0 == E_VNx1BImode)
    return CODE_FOR_pred_notvnx1bi;
  if (arg0 == E_VNx2BImode)
    return CODE_FOR_pred_notvnx2bi;
  if (arg0 == E_VNx4BImode)
    return CODE_FOR_pred_notvnx4bi;
  if (arg0 == E_VNx8BImode)
    return CODE_FOR_pred_notvnx8bi;
  if (arg0 == E_VNx16BImode)
    return CODE_FOR_pred_notvnx16bi;
  if (arg0 == E_VNx32BImode)
    return CODE_FOR_pred_notvnx32bi;
  if (arg0 == E_VNx64BImode)
    return CODE_FOR_pred_notvnx64bi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_not (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5)
{
  insn_code code = maybe_code_for_pred_not (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 6);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_popcount (machine_mode arg0, machine_mode arg1)
{
  if (arg0 == E_VNx1BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_popcountvnx1bisi;
  if (arg0 == E_VNx2BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_popcountvnx2bisi;
  if (arg0 == E_VNx4BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_popcountvnx4bisi;
  if (arg0 == E_VNx8BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_popcountvnx8bisi;
  if (arg0 == E_VNx16BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_popcountvnx16bisi;
  if (arg0 == E_VNx32BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_popcountvnx32bisi;
  if (arg0 == E_VNx64BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_popcountvnx64bisi;
  if (arg0 == E_VNx1BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_popcountvnx1bidi;
  if (arg0 == E_VNx2BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_popcountvnx2bidi;
  if (arg0 == E_VNx4BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_popcountvnx4bidi;
  if (arg0 == E_VNx8BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_popcountvnx8bidi;
  if (arg0 == E_VNx16BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_popcountvnx16bidi;
  if (arg0 == E_VNx32BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_popcountvnx32bidi;
  if (arg0 == E_VNx64BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_popcountvnx64bidi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_popcount (machine_mode arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)
{
  insn_code code = maybe_code_for_pred_popcount (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 5);
      return GEN_FCN (code) (x0, x1, x2, x3, x4);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_ffs (machine_mode arg0, machine_mode arg1)
{
  if (arg0 == E_VNx1BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_ffsvnx1bisi;
  if (arg0 == E_VNx2BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_ffsvnx2bisi;
  if (arg0 == E_VNx4BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_ffsvnx4bisi;
  if (arg0 == E_VNx8BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_ffsvnx8bisi;
  if (arg0 == E_VNx16BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_ffsvnx16bisi;
  if (arg0 == E_VNx32BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_ffsvnx32bisi;
  if (arg0 == E_VNx64BImode
      && arg1 == E_SImode)
    return CODE_FOR_pred_ffsvnx64bisi;
  if (arg0 == E_VNx1BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_ffsvnx1bidi;
  if (arg0 == E_VNx2BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_ffsvnx2bidi;
  if (arg0 == E_VNx4BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_ffsvnx4bidi;
  if (arg0 == E_VNx8BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_ffsvnx8bidi;
  if (arg0 == E_VNx16BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_ffsvnx16bidi;
  if (arg0 == E_VNx32BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_ffsvnx32bidi;
  if (arg0 == E_VNx64BImode
      && arg1 == E_DImode)
    return CODE_FOR_pred_ffsvnx64bidi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_ffs (machine_mode arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)
{
  insn_code code = maybe_code_for_pred_ffs (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 5);
      return GEN_FCN (code) (x0, x1, x2, x3, x4);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_iota (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_iotavnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_iotavnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_iotavnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_iotavnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_iotavnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_iotavnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_iotavnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_iotavnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_iotavnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_iotavnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_iotavnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_iotavnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_iotavnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_iotavnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_iotavnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_iotavnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_iotavnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_iotavnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_iotavnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_iotavnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_iotavnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_iotavnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_iota (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_iota (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_series (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_seriesvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_seriesvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_seriesvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_seriesvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_seriesvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_seriesvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_seriesvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_seriesvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_seriesvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_seriesvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_seriesvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_seriesvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_seriesvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_seriesvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_seriesvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_seriesvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_seriesvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_seriesvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_seriesvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_seriesvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_seriesvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_seriesvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_series (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6)
{
  insn_code code = maybe_code_for_pred_series (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 7);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_reverse_scalar (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == MINUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_subvnx1sf_reverse_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_divvnx1sf_reverse_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_subvnx2sf_reverse_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_divvnx2sf_reverse_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_subvnx4sf_reverse_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_divvnx4sf_reverse_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_subvnx8sf_reverse_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_divvnx8sf_reverse_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_subvnx16sf_reverse_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_divvnx16sf_reverse_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_subvnx1df_reverse_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_divvnx1df_reverse_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_subvnx2df_reverse_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_divvnx2df_reverse_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_subvnx4df_reverse_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_divvnx4df_reverse_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_subvnx8df_reverse_scalar;
  if (arg0 == DIV
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_divvnx8df_reverse_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_reverse_scalar (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_reverse_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_mul (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_mul_addvnx1sf;
  if (arg0 == MINUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_mul_subvnx1sf;
  if (arg0 == PLUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_mul_addvnx2sf;
  if (arg0 == MINUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_mul_subvnx2sf;
  if (arg0 == PLUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_mul_addvnx4sf;
  if (arg0 == MINUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_mul_subvnx4sf;
  if (arg0 == PLUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_mul_addvnx8sf;
  if (arg0 == MINUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_mul_subvnx8sf;
  if (arg0 == PLUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_mul_addvnx16sf;
  if (arg0 == MINUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_mul_subvnx16sf;
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_mul_addvnx1df;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_mul_subvnx1df;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_mul_addvnx2df;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_mul_subvnx2df;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_mul_addvnx4df;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_mul_subvnx4df;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_mul_addvnx8df;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_mul_subvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_mul (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8, rtx x9)
{
  insn_code code = maybe_code_for_pred_mul (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 10);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8, x9);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_mul_scalar (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_mul_addvnx1sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_mul_subvnx1sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_mul_addvnx2sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_mul_subvnx2sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_mul_addvnx4sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_mul_subvnx4sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_mul_addvnx8sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_mul_subvnx8sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_mul_addvnx16sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_mul_subvnx16sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_mul_addvnx1df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_mul_subvnx1df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_mul_addvnx2df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_mul_subvnx2df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_mul_addvnx4df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_mul_subvnx4df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_mul_addvnx8df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_mul_subvnx8df_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_mul_scalar (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8, rtx x9)
{
  insn_code code = maybe_code_for_pred_mul_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 10);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8, x9);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_mul_neg (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_mul_neg_addvnx1sf;
  if (arg0 == MINUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_mul_neg_subvnx1sf;
  if (arg0 == PLUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_mul_neg_addvnx2sf;
  if (arg0 == MINUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_mul_neg_subvnx2sf;
  if (arg0 == PLUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_mul_neg_addvnx4sf;
  if (arg0 == MINUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_mul_neg_subvnx4sf;
  if (arg0 == PLUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_mul_neg_addvnx8sf;
  if (arg0 == MINUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_mul_neg_subvnx8sf;
  if (arg0 == PLUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_mul_neg_addvnx16sf;
  if (arg0 == MINUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_mul_neg_subvnx16sf;
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_mul_neg_addvnx1df;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_mul_neg_subvnx1df;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_mul_neg_addvnx2df;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_mul_neg_subvnx2df;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_mul_neg_addvnx4df;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_mul_neg_subvnx4df;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_mul_neg_addvnx8df;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_mul_neg_subvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_mul_neg (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8, rtx x9)
{
  insn_code code = maybe_code_for_pred_mul_neg (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 10);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8, x9);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_mul_neg_scalar (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_mul_neg_addvnx1sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_mul_neg_subvnx1sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_mul_neg_addvnx2sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_mul_neg_subvnx2sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_mul_neg_addvnx4sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_mul_neg_subvnx4sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_mul_neg_addvnx8sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_mul_neg_subvnx8sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_mul_neg_addvnx16sf_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_mul_neg_subvnx16sf_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_mul_neg_addvnx1df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_mul_neg_subvnx1df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_mul_neg_addvnx2df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_mul_neg_subvnx2df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_mul_neg_addvnx4df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_mul_neg_subvnx4df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_mul_neg_addvnx8df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_mul_neg_subvnx8df_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_mul_neg_scalar (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8, rtx x9)
{
  insn_code code = maybe_code_for_pred_mul_neg_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 10);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8, x9);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_class (machine_mode arg0)
{
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_classvnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_classvnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_classvnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_classvnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_classvnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_classvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_classvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_classvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_classvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_class (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_class (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_dual_widen (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_dual_widen_addvnx1df;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_dual_widen_subvnx1df;
  if (arg0 == MULT
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_dual_widen_mulvnx1df;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_dual_widen_addvnx2df;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_dual_widen_subvnx2df;
  if (arg0 == MULT
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_dual_widen_mulvnx2df;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_dual_widen_addvnx4df;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_dual_widen_subvnx4df;
  if (arg0 == MULT
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_dual_widen_mulvnx4df;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_dual_widen_addvnx8df;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_dual_widen_subvnx8df;
  if (arg0 == MULT
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_dual_widen_mulvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_dual_widen (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_dual_widen (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_dual_widen_scalar (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_dual_widen_addvnx1df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_dual_widen_subvnx1df_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_dual_widen_mulvnx1df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_dual_widen_addvnx2df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_dual_widen_subvnx2df_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_dual_widen_mulvnx2df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_dual_widen_addvnx4df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_dual_widen_subvnx4df_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_dual_widen_mulvnx4df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_dual_widen_addvnx8df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_dual_widen_subvnx8df_scalar;
  if (arg0 == MULT
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_dual_widen_mulvnx8df_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_dual_widen_scalar (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_dual_widen_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_single_widen (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_single_widen_addvnx1df;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_single_widen_subvnx1df;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_single_widen_addvnx2df;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_single_widen_subvnx2df;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_single_widen_addvnx4df;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_single_widen_subvnx4df;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_single_widen_addvnx8df;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_single_widen_subvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_single_widen (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_single_widen (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_single_widen_scalar (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_single_widen_addvnx1df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_single_widen_subvnx1df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_single_widen_addvnx2df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_single_widen_subvnx2df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_single_widen_addvnx4df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_single_widen_subvnx4df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_single_widen_addvnx8df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_single_widen_subvnx8df_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_single_widen_scalar (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_single_widen_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_mul (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_widen_mul_addvnx1df;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_widen_mul_subvnx1df;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_widen_mul_addvnx2df;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_widen_mul_subvnx2df;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_widen_mul_addvnx4df;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_widen_mul_subvnx4df;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_widen_mul_addvnx8df;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_widen_mul_subvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_mul (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_widen_mul (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_mul_scalar (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_widen_mul_addvnx1df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_widen_mul_subvnx1df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_widen_mul_addvnx2df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_widen_mul_subvnx2df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_widen_mul_addvnx4df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_widen_mul_subvnx4df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_widen_mul_addvnx8df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_widen_mul_subvnx8df_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_mul_scalar (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_widen_mul_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_mul_neg (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_widen_mul_neg_addvnx1df;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_widen_mul_neg_subvnx1df;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_widen_mul_neg_addvnx2df;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_widen_mul_neg_subvnx2df;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_widen_mul_neg_addvnx4df;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_widen_mul_neg_subvnx4df;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_widen_mul_neg_addvnx8df;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_widen_mul_neg_subvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_mul_neg (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_widen_mul_neg (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_mul_neg_scalar (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_widen_mul_neg_addvnx1df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_widen_mul_neg_subvnx1df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_widen_mul_neg_addvnx2df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_widen_mul_neg_subvnx2df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_widen_mul_neg_addvnx4df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_widen_mul_neg_subvnx4df_scalar;
  if (arg0 == PLUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_widen_mul_neg_addvnx8df_scalar;
  if (arg0 == MINUS
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_widen_mul_neg_subvnx8df_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_mul_neg_scalar (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_widen_mul_neg_scalar (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_fcvt_x_f (int arg0, machine_mode arg1)
{
  if (arg0 == 100
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_fcvt_x_fvnx1sf;
  if (arg0 == 101
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_fcvt_xu_fvnx1sf;
  if (arg0 == 100
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_fcvt_x_fvnx2sf;
  if (arg0 == 101
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_fcvt_xu_fvnx2sf;
  if (arg0 == 100
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_fcvt_x_fvnx4sf;
  if (arg0 == 101
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_fcvt_xu_fvnx4sf;
  if (arg0 == 100
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_fcvt_x_fvnx8sf;
  if (arg0 == 101
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_fcvt_xu_fvnx8sf;
  if (arg0 == 100
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_fcvt_x_fvnx16sf;
  if (arg0 == 101
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_fcvt_xu_fvnx16sf;
  if (arg0 == 100
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_fcvt_x_fvnx1df;
  if (arg0 == 101
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_fcvt_xu_fvnx1df;
  if (arg0 == 100
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_fcvt_x_fvnx2df;
  if (arg0 == 101
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_fcvt_xu_fvnx2df;
  if (arg0 == 100
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_fcvt_x_fvnx4df;
  if (arg0 == 101
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_fcvt_xu_fvnx4df;
  if (arg0 == 100
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_fcvt_x_fvnx8df;
  if (arg0 == 101
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_fcvt_xu_fvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_fcvt_x_f (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_fcvt_x_f (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_fcvt_x_f (int arg0, machine_mode arg1)
{
  if (arg0 == 100
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_widen_fcvt_x_fvnx1di;
  if (arg0 == 101
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_widen_fcvt_xu_fvnx1di;
  if (arg0 == 100
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_widen_fcvt_x_fvnx2di;
  if (arg0 == 101
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_widen_fcvt_xu_fvnx2di;
  if (arg0 == 100
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_widen_fcvt_x_fvnx4di;
  if (arg0 == 101
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_widen_fcvt_xu_fvnx4di;
  if (arg0 == 100
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_widen_fcvt_x_fvnx8di;
  if (arg0 == 101
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_widen_fcvt_xu_fvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_fcvt_x_f (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_widen_fcvt_x_f (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen (rtx_code arg0, machine_mode arg1)
{
  if (arg0 == FIX
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_widen_fix_truncvnx1di;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_widen_fixuns_truncvnx1di;
  if (arg0 == FIX
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_widen_fix_truncvnx2di;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_widen_fixuns_truncvnx2di;
  if (arg0 == FIX
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_widen_fix_truncvnx4di;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_widen_fixuns_truncvnx4di;
  if (arg0 == FIX
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_widen_fix_truncvnx8di;
  if (arg0 == UNSIGNED_FIX
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_widen_fixuns_truncvnx8di;
  if (arg0 == FLOAT
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_widen_floatvnx1sf;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_widen_floatunsvnx1sf;
  if (arg0 == FLOAT
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_widen_floatvnx2sf;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_widen_floatunsvnx2sf;
  if (arg0 == FLOAT
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_widen_floatvnx4sf;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_widen_floatunsvnx4sf;
  if (arg0 == FLOAT
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_widen_floatvnx8sf;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_widen_floatunsvnx8sf;
  if (arg0 == FLOAT
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_widen_floatvnx16sf;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_widen_floatunsvnx16sf;
  if (arg0 == FLOAT
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_widen_floatvnx1df;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_widen_floatunsvnx1df;
  if (arg0 == FLOAT
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_widen_floatvnx2df;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_widen_floatunsvnx2df;
  if (arg0 == FLOAT
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_widen_floatvnx4df;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_widen_floatunsvnx4df;
  if (arg0 == FLOAT
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_widen_floatvnx8df;
  if (arg0 == UNSIGNED_FLOAT
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_widen_floatunsvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen (rtx_code arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_widen (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_extend (machine_mode arg0)
{
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_extendvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_extendvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_extendvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_extendvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_extend (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_extend (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_narrow_fcvt_x_f (int arg0, machine_mode arg1)
{
  if (arg0 == 100
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_narrow_fcvt_x_fvnx1sf;
  if (arg0 == 101
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_narrow_fcvt_xu_fvnx1sf;
  if (arg0 == 100
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_narrow_fcvt_x_fvnx2sf;
  if (arg0 == 101
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_narrow_fcvt_xu_fvnx2sf;
  if (arg0 == 100
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_narrow_fcvt_x_fvnx4sf;
  if (arg0 == 101
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_narrow_fcvt_xu_fvnx4sf;
  if (arg0 == 100
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_narrow_fcvt_x_fvnx8sf;
  if (arg0 == 101
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_narrow_fcvt_xu_fvnx8sf;
  if (arg0 == 100
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_narrow_fcvt_x_fvnx16sf;
  if (arg0 == 101
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_narrow_fcvt_xu_fvnx16sf;
  if (arg0 == 100
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_narrow_fcvt_x_fvnx1df;
  if (arg0 == 101
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_narrow_fcvt_xu_fvnx1df;
  if (arg0 == 100
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_narrow_fcvt_x_fvnx2df;
  if (arg0 == 101
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_narrow_fcvt_xu_fvnx2df;
  if (arg0 == 100
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_narrow_fcvt_x_fvnx4df;
  if (arg0 == 101
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_narrow_fcvt_xu_fvnx4df;
  if (arg0 == 100
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_narrow_fcvt_x_fvnx8df;
  if (arg0 == 101
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_narrow_fcvt_xu_fvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_narrow_fcvt_x_f (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_narrow_fcvt_x_f (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_rod_trunc (machine_mode arg0)
{
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_rod_truncvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_rod_truncvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_rod_truncvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_rod_truncvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_rod_trunc (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_rod_trunc (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_reduc (rtx_code arg0, machine_mode arg1, machine_mode arg2)
{
  if (arg0 == PLUS
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_sumvnx1qivnx8qi;
  if (arg0 == UMAX
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_maxuvnx1qivnx8qi;
  if (arg0 == SMAX
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_maxvnx1qivnx8qi;
  if (arg0 == UMIN
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_minuvnx1qivnx8qi;
  if (arg0 == SMIN
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_minvnx1qivnx8qi;
  if (arg0 == AND
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_andvnx1qivnx8qi;
  if (arg0 == IOR
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_orvnx1qivnx8qi;
  if (arg0 == XOR
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_xorvnx1qivnx8qi;
  if (arg0 == PLUS
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_sumvnx2qivnx8qi;
  if (arg0 == UMAX
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_maxuvnx2qivnx8qi;
  if (arg0 == SMAX
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_maxvnx2qivnx8qi;
  if (arg0 == UMIN
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_minuvnx2qivnx8qi;
  if (arg0 == SMIN
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_minvnx2qivnx8qi;
  if (arg0 == AND
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_andvnx2qivnx8qi;
  if (arg0 == IOR
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_orvnx2qivnx8qi;
  if (arg0 == XOR
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_xorvnx2qivnx8qi;
  if (arg0 == PLUS
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_sumvnx4qivnx8qi;
  if (arg0 == UMAX
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_maxuvnx4qivnx8qi;
  if (arg0 == SMAX
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_maxvnx4qivnx8qi;
  if (arg0 == UMIN
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_minuvnx4qivnx8qi;
  if (arg0 == SMIN
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_minvnx4qivnx8qi;
  if (arg0 == AND
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_andvnx4qivnx8qi;
  if (arg0 == IOR
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_orvnx4qivnx8qi;
  if (arg0 == XOR
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_xorvnx4qivnx8qi;
  if (arg0 == PLUS
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_sumvnx8qivnx8qi;
  if (arg0 == UMAX
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_maxuvnx8qivnx8qi;
  if (arg0 == SMAX
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_maxvnx8qivnx8qi;
  if (arg0 == UMIN
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_minuvnx8qivnx8qi;
  if (arg0 == SMIN
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_minvnx8qivnx8qi;
  if (arg0 == AND
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_andvnx8qivnx8qi;
  if (arg0 == IOR
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_orvnx8qivnx8qi;
  if (arg0 == XOR
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_xorvnx8qivnx8qi;
  if (arg0 == PLUS
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_sumvnx16qivnx8qi;
  if (arg0 == UMAX
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_maxuvnx16qivnx8qi;
  if (arg0 == SMAX
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_maxvnx16qivnx8qi;
  if (arg0 == UMIN
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_minuvnx16qivnx8qi;
  if (arg0 == SMIN
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_minvnx16qivnx8qi;
  if (arg0 == AND
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_andvnx16qivnx8qi;
  if (arg0 == IOR
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_orvnx16qivnx8qi;
  if (arg0 == XOR
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_xorvnx16qivnx8qi;
  if (arg0 == PLUS
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_sumvnx32qivnx8qi;
  if (arg0 == UMAX
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_maxuvnx32qivnx8qi;
  if (arg0 == SMAX
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_maxvnx32qivnx8qi;
  if (arg0 == UMIN
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_minuvnx32qivnx8qi;
  if (arg0 == SMIN
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_minvnx32qivnx8qi;
  if (arg0 == AND
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_andvnx32qivnx8qi;
  if (arg0 == IOR
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_orvnx32qivnx8qi;
  if (arg0 == XOR
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_xorvnx32qivnx8qi;
  if (arg0 == PLUS
      && arg1 == E_VNx64QImode
      && arg2 == E_VNx64QImode)
    return CODE_FOR_pred_reduc_sumvnx64qivnx8qi;
  if (arg0 == UMAX
      && arg1 == E_VNx64QImode
      && arg2 == E_VNx64QImode)
    return CODE_FOR_pred_reduc_maxuvnx64qivnx8qi;
  if (arg0 == SMAX
      && arg1 == E_VNx64QImode
      && arg2 == E_VNx64QImode)
    return CODE_FOR_pred_reduc_maxvnx64qivnx8qi;
  if (arg0 == UMIN
      && arg1 == E_VNx64QImode
      && arg2 == E_VNx64QImode)
    return CODE_FOR_pred_reduc_minuvnx64qivnx8qi;
  if (arg0 == SMIN
      && arg1 == E_VNx64QImode
      && arg2 == E_VNx64QImode)
    return CODE_FOR_pred_reduc_minvnx64qivnx8qi;
  if (arg0 == AND
      && arg1 == E_VNx64QImode
      && arg2 == E_VNx64QImode)
    return CODE_FOR_pred_reduc_andvnx64qivnx8qi;
  if (arg0 == IOR
      && arg1 == E_VNx64QImode
      && arg2 == E_VNx64QImode)
    return CODE_FOR_pred_reduc_orvnx64qivnx8qi;
  if (arg0 == XOR
      && arg1 == E_VNx64QImode
      && arg2 == E_VNx64QImode)
    return CODE_FOR_pred_reduc_xorvnx64qivnx8qi;
  if (arg0 == PLUS
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_sumvnx1hivnx4hi;
  if (arg0 == UMAX
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_maxuvnx1hivnx4hi;
  if (arg0 == SMAX
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_maxvnx1hivnx4hi;
  if (arg0 == UMIN
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_minuvnx1hivnx4hi;
  if (arg0 == SMIN
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_minvnx1hivnx4hi;
  if (arg0 == AND
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_andvnx1hivnx4hi;
  if (arg0 == IOR
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_orvnx1hivnx4hi;
  if (arg0 == XOR
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_xorvnx1hivnx4hi;
  if (arg0 == PLUS
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_sumvnx2hivnx4hi;
  if (arg0 == UMAX
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_maxuvnx2hivnx4hi;
  if (arg0 == SMAX
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_maxvnx2hivnx4hi;
  if (arg0 == UMIN
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_minuvnx2hivnx4hi;
  if (arg0 == SMIN
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_minvnx2hivnx4hi;
  if (arg0 == AND
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_andvnx2hivnx4hi;
  if (arg0 == IOR
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_orvnx2hivnx4hi;
  if (arg0 == XOR
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_xorvnx2hivnx4hi;
  if (arg0 == PLUS
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_sumvnx4hivnx4hi;
  if (arg0 == UMAX
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_maxuvnx4hivnx4hi;
  if (arg0 == SMAX
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_maxvnx4hivnx4hi;
  if (arg0 == UMIN
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_minuvnx4hivnx4hi;
  if (arg0 == SMIN
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_minvnx4hivnx4hi;
  if (arg0 == AND
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_andvnx4hivnx4hi;
  if (arg0 == IOR
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_orvnx4hivnx4hi;
  if (arg0 == XOR
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_xorvnx4hivnx4hi;
  if (arg0 == PLUS
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_sumvnx8hivnx4hi;
  if (arg0 == UMAX
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_maxuvnx8hivnx4hi;
  if (arg0 == SMAX
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_maxvnx8hivnx4hi;
  if (arg0 == UMIN
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_minuvnx8hivnx4hi;
  if (arg0 == SMIN
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_minvnx8hivnx4hi;
  if (arg0 == AND
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_andvnx8hivnx4hi;
  if (arg0 == IOR
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_orvnx8hivnx4hi;
  if (arg0 == XOR
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_xorvnx8hivnx4hi;
  if (arg0 == PLUS
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_sumvnx16hivnx4hi;
  if (arg0 == UMAX
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_maxuvnx16hivnx4hi;
  if (arg0 == SMAX
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_maxvnx16hivnx4hi;
  if (arg0 == UMIN
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_minuvnx16hivnx4hi;
  if (arg0 == SMIN
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_minvnx16hivnx4hi;
  if (arg0 == AND
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_andvnx16hivnx4hi;
  if (arg0 == IOR
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_orvnx16hivnx4hi;
  if (arg0 == XOR
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_xorvnx16hivnx4hi;
  if (arg0 == PLUS
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_reduc_sumvnx32hivnx4hi;
  if (arg0 == UMAX
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_reduc_maxuvnx32hivnx4hi;
  if (arg0 == SMAX
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_reduc_maxvnx32hivnx4hi;
  if (arg0 == UMIN
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_reduc_minuvnx32hivnx4hi;
  if (arg0 == SMIN
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_reduc_minvnx32hivnx4hi;
  if (arg0 == AND
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_reduc_andvnx32hivnx4hi;
  if (arg0 == IOR
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_reduc_orvnx32hivnx4hi;
  if (arg0 == XOR
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_reduc_xorvnx32hivnx4hi;
  if (arg0 == PLUS
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_sumvnx1sivnx2si;
  if (arg0 == UMAX
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_maxuvnx1sivnx2si;
  if (arg0 == SMAX
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_maxvnx1sivnx2si;
  if (arg0 == UMIN
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_minuvnx1sivnx2si;
  if (arg0 == SMIN
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_minvnx1sivnx2si;
  if (arg0 == AND
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_andvnx1sivnx2si;
  if (arg0 == IOR
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_orvnx1sivnx2si;
  if (arg0 == XOR
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_xorvnx1sivnx2si;
  if (arg0 == PLUS
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_sumvnx2sivnx2si;
  if (arg0 == UMAX
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_maxuvnx2sivnx2si;
  if (arg0 == SMAX
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_maxvnx2sivnx2si;
  if (arg0 == UMIN
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_minuvnx2sivnx2si;
  if (arg0 == SMIN
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_minvnx2sivnx2si;
  if (arg0 == AND
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_andvnx2sivnx2si;
  if (arg0 == IOR
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_orvnx2sivnx2si;
  if (arg0 == XOR
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_xorvnx2sivnx2si;
  if (arg0 == PLUS
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_sumvnx4sivnx2si;
  if (arg0 == UMAX
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_maxuvnx4sivnx2si;
  if (arg0 == SMAX
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_maxvnx4sivnx2si;
  if (arg0 == UMIN
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_minuvnx4sivnx2si;
  if (arg0 == SMIN
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_minvnx4sivnx2si;
  if (arg0 == AND
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_andvnx4sivnx2si;
  if (arg0 == IOR
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_orvnx4sivnx2si;
  if (arg0 == XOR
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_xorvnx4sivnx2si;
  if (arg0 == PLUS
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_sumvnx8sivnx2si;
  if (arg0 == UMAX
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_maxuvnx8sivnx2si;
  if (arg0 == SMAX
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_maxvnx8sivnx2si;
  if (arg0 == UMIN
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_minuvnx8sivnx2si;
  if (arg0 == SMIN
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_minvnx8sivnx2si;
  if (arg0 == AND
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_andvnx8sivnx2si;
  if (arg0 == IOR
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_orvnx8sivnx2si;
  if (arg0 == XOR
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_xorvnx8sivnx2si;
  if (arg0 == PLUS
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_reduc_sumvnx16sivnx2si;
  if (arg0 == UMAX
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_reduc_maxuvnx16sivnx2si;
  if (arg0 == SMAX
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_reduc_maxvnx16sivnx2si;
  if (arg0 == UMIN
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_reduc_minuvnx16sivnx2si;
  if (arg0 == SMIN
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_reduc_minvnx16sivnx2si;
  if (arg0 == AND
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_reduc_andvnx16sivnx2si;
  if (arg0 == IOR
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_reduc_orvnx16sivnx2si;
  if (arg0 == XOR
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_reduc_xorvnx16sivnx2si;
  if (arg0 == PLUS
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_reduc_sumvnx1divnx1DI;
  if (arg0 == UMAX
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_reduc_maxuvnx1divnx1DI;
  if (arg0 == SMAX
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_reduc_maxvnx1divnx1DI;
  if (arg0 == UMIN
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_reduc_minuvnx1divnx1DI;
  if (arg0 == SMIN
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_reduc_minvnx1divnx1DI;
  if (arg0 == AND
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_reduc_andvnx1divnx1DI;
  if (arg0 == IOR
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_reduc_orvnx1divnx1DI;
  if (arg0 == XOR
      && arg1 == E_VNx1DImode
      && arg2 == E_VNx1DImode)
    return CODE_FOR_pred_reduc_xorvnx1divnx1DI;
  if (arg0 == PLUS
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_reduc_sumvnx2divnx1DI;
  if (arg0 == UMAX
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_reduc_maxuvnx2divnx1DI;
  if (arg0 == SMAX
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_reduc_maxvnx2divnx1DI;
  if (arg0 == UMIN
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_reduc_minuvnx2divnx1DI;
  if (arg0 == SMIN
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_reduc_minvnx2divnx1DI;
  if (arg0 == AND
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_reduc_andvnx2divnx1DI;
  if (arg0 == IOR
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_reduc_orvnx2divnx1DI;
  if (arg0 == XOR
      && arg1 == E_VNx2DImode
      && arg2 == E_VNx2DImode)
    return CODE_FOR_pred_reduc_xorvnx2divnx1DI;
  if (arg0 == PLUS
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_reduc_sumvnx4divnx1DI;
  if (arg0 == UMAX
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_reduc_maxuvnx4divnx1DI;
  if (arg0 == SMAX
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_reduc_maxvnx4divnx1DI;
  if (arg0 == UMIN
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_reduc_minuvnx4divnx1DI;
  if (arg0 == SMIN
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_reduc_minvnx4divnx1DI;
  if (arg0 == AND
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_reduc_andvnx4divnx1DI;
  if (arg0 == IOR
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_reduc_orvnx4divnx1DI;
  if (arg0 == XOR
      && arg1 == E_VNx4DImode
      && arg2 == E_VNx4DImode)
    return CODE_FOR_pred_reduc_xorvnx4divnx1DI;
  if (arg0 == PLUS
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_reduc_sumvnx8divnx1DI;
  if (arg0 == UMAX
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_reduc_maxuvnx8divnx1DI;
  if (arg0 == SMAX
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_reduc_maxvnx8divnx1DI;
  if (arg0 == UMIN
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_reduc_minuvnx8divnx1DI;
  if (arg0 == SMIN
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_reduc_minvnx8divnx1DI;
  if (arg0 == AND
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_reduc_andvnx8divnx1DI;
  if (arg0 == IOR
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_reduc_orvnx8divnx1DI;
  if (arg0 == XOR
      && arg1 == E_VNx8DImode
      && arg2 == E_VNx8DImode)
    return CODE_FOR_pred_reduc_xorvnx8divnx1DI;
  if (arg0 == PLUS
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_sumvnx1qivnx4qi;
  if (arg0 == UMAX
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_maxuvnx1qivnx4qi;
  if (arg0 == SMAX
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_maxvnx1qivnx4qi;
  if (arg0 == UMIN
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_minuvnx1qivnx4qi;
  if (arg0 == SMIN
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_minvnx1qivnx4qi;
  if (arg0 == AND
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_andvnx1qivnx4qi;
  if (arg0 == IOR
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_orvnx1qivnx4qi;
  if (arg0 == XOR
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_reduc_xorvnx1qivnx4qi;
  if (arg0 == PLUS
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_sumvnx2qivnx4qi;
  if (arg0 == UMAX
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_maxuvnx2qivnx4qi;
  if (arg0 == SMAX
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_maxvnx2qivnx4qi;
  if (arg0 == UMIN
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_minuvnx2qivnx4qi;
  if (arg0 == SMIN
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_minvnx2qivnx4qi;
  if (arg0 == AND
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_andvnx2qivnx4qi;
  if (arg0 == IOR
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_orvnx2qivnx4qi;
  if (arg0 == XOR
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_reduc_xorvnx2qivnx4qi;
  if (arg0 == PLUS
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_sumvnx4qivnx4qi;
  if (arg0 == UMAX
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_maxuvnx4qivnx4qi;
  if (arg0 == SMAX
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_maxvnx4qivnx4qi;
  if (arg0 == UMIN
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_minuvnx4qivnx4qi;
  if (arg0 == SMIN
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_minvnx4qivnx4qi;
  if (arg0 == AND
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_andvnx4qivnx4qi;
  if (arg0 == IOR
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_orvnx4qivnx4qi;
  if (arg0 == XOR
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_reduc_xorvnx4qivnx4qi;
  if (arg0 == PLUS
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_sumvnx8qivnx4qi;
  if (arg0 == UMAX
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_maxuvnx8qivnx4qi;
  if (arg0 == SMAX
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_maxvnx8qivnx4qi;
  if (arg0 == UMIN
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_minuvnx8qivnx4qi;
  if (arg0 == SMIN
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_minvnx8qivnx4qi;
  if (arg0 == AND
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_andvnx8qivnx4qi;
  if (arg0 == IOR
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_orvnx8qivnx4qi;
  if (arg0 == XOR
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_reduc_xorvnx8qivnx4qi;
  if (arg0 == PLUS
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_sumvnx16qivnx4qi;
  if (arg0 == UMAX
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_maxuvnx16qivnx4qi;
  if (arg0 == SMAX
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_maxvnx16qivnx4qi;
  if (arg0 == UMIN
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_minuvnx16qivnx4qi;
  if (arg0 == SMIN
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_minvnx16qivnx4qi;
  if (arg0 == AND
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_andvnx16qivnx4qi;
  if (arg0 == IOR
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_orvnx16qivnx4qi;
  if (arg0 == XOR
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_reduc_xorvnx16qivnx4qi;
  if (arg0 == PLUS
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_sumvnx32qivnx4qi;
  if (arg0 == UMAX
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_maxuvnx32qivnx4qi;
  if (arg0 == SMAX
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_maxvnx32qivnx4qi;
  if (arg0 == UMIN
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_minuvnx32qivnx4qi;
  if (arg0 == SMIN
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_minvnx32qivnx4qi;
  if (arg0 == AND
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_andvnx32qivnx4qi;
  if (arg0 == IOR
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_orvnx32qivnx4qi;
  if (arg0 == XOR
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_reduc_xorvnx32qivnx4qi;
  if (arg0 == PLUS
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_sumvnx1hivnx2hi;
  if (arg0 == UMAX
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_maxuvnx1hivnx2hi;
  if (arg0 == SMAX
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_maxvnx1hivnx2hi;
  if (arg0 == UMIN
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_minuvnx1hivnx2hi;
  if (arg0 == SMIN
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_minvnx1hivnx2hi;
  if (arg0 == AND
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_andvnx1hivnx2hi;
  if (arg0 == IOR
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_orvnx1hivnx2hi;
  if (arg0 == XOR
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_reduc_xorvnx1hivnx2hi;
  if (arg0 == PLUS
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_sumvnx2hivnx2hi;
  if (arg0 == UMAX
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_maxuvnx2hivnx2hi;
  if (arg0 == SMAX
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_maxvnx2hivnx2hi;
  if (arg0 == UMIN
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_minuvnx2hivnx2hi;
  if (arg0 == SMIN
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_minvnx2hivnx2hi;
  if (arg0 == AND
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_andvnx2hivnx2hi;
  if (arg0 == IOR
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_orvnx2hivnx2hi;
  if (arg0 == XOR
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_reduc_xorvnx2hivnx2hi;
  if (arg0 == PLUS
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_sumvnx4hivnx2hi;
  if (arg0 == UMAX
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_maxuvnx4hivnx2hi;
  if (arg0 == SMAX
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_maxvnx4hivnx2hi;
  if (arg0 == UMIN
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_minuvnx4hivnx2hi;
  if (arg0 == SMIN
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_minvnx4hivnx2hi;
  if (arg0 == AND
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_andvnx4hivnx2hi;
  if (arg0 == IOR
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_orvnx4hivnx2hi;
  if (arg0 == XOR
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_reduc_xorvnx4hivnx2hi;
  if (arg0 == PLUS
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_sumvnx8hivnx2hi;
  if (arg0 == UMAX
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_maxuvnx8hivnx2hi;
  if (arg0 == SMAX
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_maxvnx8hivnx2hi;
  if (arg0 == UMIN
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_minuvnx8hivnx2hi;
  if (arg0 == SMIN
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_minvnx8hivnx2hi;
  if (arg0 == AND
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_andvnx8hivnx2hi;
  if (arg0 == IOR
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_orvnx8hivnx2hi;
  if (arg0 == XOR
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_reduc_xorvnx8hivnx2hi;
  if (arg0 == PLUS
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_sumvnx16hivnx2hi;
  if (arg0 == UMAX
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_maxuvnx16hivnx2hi;
  if (arg0 == SMAX
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_maxvnx16hivnx2hi;
  if (arg0 == UMIN
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_minuvnx16hivnx2hi;
  if (arg0 == SMIN
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_minvnx16hivnx2hi;
  if (arg0 == AND
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_andvnx16hivnx2hi;
  if (arg0 == IOR
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_orvnx16hivnx2hi;
  if (arg0 == XOR
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_reduc_xorvnx16hivnx2hi;
  if (arg0 == PLUS
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_sumvnx1sivnx1si;
  if (arg0 == UMAX
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_maxuvnx1sivnx1si;
  if (arg0 == SMAX
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_maxvnx1sivnx1si;
  if (arg0 == UMIN
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_minuvnx1sivnx1si;
  if (arg0 == SMIN
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_minvnx1sivnx1si;
  if (arg0 == AND
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_andvnx1sivnx1si;
  if (arg0 == IOR
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_orvnx1sivnx1si;
  if (arg0 == XOR
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_reduc_xorvnx1sivnx1si;
  if (arg0 == PLUS
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_sumvnx2sivnx1si;
  if (arg0 == UMAX
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_maxuvnx2sivnx1si;
  if (arg0 == SMAX
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_maxvnx2sivnx1si;
  if (arg0 == UMIN
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_minuvnx2sivnx1si;
  if (arg0 == SMIN
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_minvnx2sivnx1si;
  if (arg0 == AND
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_andvnx2sivnx1si;
  if (arg0 == IOR
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_orvnx2sivnx1si;
  if (arg0 == XOR
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_reduc_xorvnx2sivnx1si;
  if (arg0 == PLUS
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_sumvnx4sivnx1si;
  if (arg0 == UMAX
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_maxuvnx4sivnx1si;
  if (arg0 == SMAX
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_maxvnx4sivnx1si;
  if (arg0 == UMIN
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_minuvnx4sivnx1si;
  if (arg0 == SMIN
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_minvnx4sivnx1si;
  if (arg0 == AND
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_andvnx4sivnx1si;
  if (arg0 == IOR
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_orvnx4sivnx1si;
  if (arg0 == XOR
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_reduc_xorvnx4sivnx1si;
  if (arg0 == PLUS
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_sumvnx8sivnx1si;
  if (arg0 == UMAX
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_maxuvnx8sivnx1si;
  if (arg0 == SMAX
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_maxvnx8sivnx1si;
  if (arg0 == UMIN
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_minuvnx8sivnx1si;
  if (arg0 == SMIN
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_minvnx8sivnx1si;
  if (arg0 == AND
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_andvnx8sivnx1si;
  if (arg0 == IOR
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_orvnx8sivnx1si;
  if (arg0 == XOR
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_reduc_xorvnx8sivnx1si;
  if (arg0 == SMAX
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1SFmode)
    return CODE_FOR_pred_reduc_maxvnx1sfvnx2sf;
  if (arg0 == SMIN
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1SFmode)
    return CODE_FOR_pred_reduc_minvnx1sfvnx2sf;
  if (arg0 == SMAX
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2SFmode)
    return CODE_FOR_pred_reduc_maxvnx2sfvnx2sf;
  if (arg0 == SMIN
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2SFmode)
    return CODE_FOR_pred_reduc_minvnx2sfvnx2sf;
  if (arg0 == SMAX
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4SFmode)
    return CODE_FOR_pred_reduc_maxvnx4sfvnx2sf;
  if (arg0 == SMIN
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4SFmode)
    return CODE_FOR_pred_reduc_minvnx4sfvnx2sf;
  if (arg0 == SMAX
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8SFmode)
    return CODE_FOR_pred_reduc_maxvnx8sfvnx2sf;
  if (arg0 == SMIN
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8SFmode)
    return CODE_FOR_pred_reduc_minvnx8sfvnx2sf;
  if (arg0 == SMAX
      && arg1 == E_VNx16SFmode
      && arg2 == E_VNx16SFmode)
    return CODE_FOR_pred_reduc_maxvnx16sfvnx2sf;
  if (arg0 == SMIN
      && arg1 == E_VNx16SFmode
      && arg2 == E_VNx16SFmode)
    return CODE_FOR_pred_reduc_minvnx16sfvnx2sf;
  if (arg0 == SMAX
      && arg1 == E_VNx1DFmode
      && arg2 == E_VNx1DFmode)
    return CODE_FOR_pred_reduc_maxvnx1dfvnx1df;
  if (arg0 == SMIN
      && arg1 == E_VNx1DFmode
      && arg2 == E_VNx1DFmode)
    return CODE_FOR_pred_reduc_minvnx1dfvnx1df;
  if (arg0 == SMAX
      && arg1 == E_VNx2DFmode
      && arg2 == E_VNx2DFmode)
    return CODE_FOR_pred_reduc_maxvnx2dfvnx1df;
  if (arg0 == SMIN
      && arg1 == E_VNx2DFmode
      && arg2 == E_VNx2DFmode)
    return CODE_FOR_pred_reduc_minvnx2dfvnx1df;
  if (arg0 == SMAX
      && arg1 == E_VNx4DFmode
      && arg2 == E_VNx4DFmode)
    return CODE_FOR_pred_reduc_maxvnx4dfvnx1df;
  if (arg0 == SMIN
      && arg1 == E_VNx4DFmode
      && arg2 == E_VNx4DFmode)
    return CODE_FOR_pred_reduc_minvnx4dfvnx1df;
  if (arg0 == SMAX
      && arg1 == E_VNx8DFmode
      && arg2 == E_VNx8DFmode)
    return CODE_FOR_pred_reduc_maxvnx8dfvnx1df;
  if (arg0 == SMIN
      && arg1 == E_VNx8DFmode
      && arg2 == E_VNx8DFmode)
    return CODE_FOR_pred_reduc_minvnx8dfvnx1df;
  if (arg0 == SMAX
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1SFmode)
    return CODE_FOR_pred_reduc_maxvnx1sfvnx1sf;
  if (arg0 == SMIN
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1SFmode)
    return CODE_FOR_pred_reduc_minvnx1sfvnx1sf;
  if (arg0 == SMAX
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2SFmode)
    return CODE_FOR_pred_reduc_maxvnx2sfvnx1sf;
  if (arg0 == SMIN
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2SFmode)
    return CODE_FOR_pred_reduc_minvnx2sfvnx1sf;
  if (arg0 == SMAX
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4SFmode)
    return CODE_FOR_pred_reduc_maxvnx4sfvnx1sf;
  if (arg0 == SMIN
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4SFmode)
    return CODE_FOR_pred_reduc_minvnx4sfvnx1sf;
  if (arg0 == SMAX
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8SFmode)
    return CODE_FOR_pred_reduc_maxvnx8sfvnx1sf;
  if (arg0 == SMIN
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8SFmode)
    return CODE_FOR_pred_reduc_minvnx8sfvnx1sf;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_reduc (rtx_code arg0, machine_mode arg1, machine_mode arg2, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_reduc (arg0, arg1, arg2);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_widen_reduc_plus (int arg0, machine_mode arg1, machine_mode arg2)
{
  if (arg0 == 104
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx1qivnx4hi;
  if (arg0 == 105
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx1qivnx4hi;
  if (arg0 == 104
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx2qivnx4hi;
  if (arg0 == 105
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx2qivnx4hi;
  if (arg0 == 104
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx4qivnx4hi;
  if (arg0 == 105
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx4qivnx4hi;
  if (arg0 == 104
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx8qivnx4hi;
  if (arg0 == 105
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx8qivnx4hi;
  if (arg0 == 104
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx16qivnx4hi;
  if (arg0 == 105
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx16qivnx4hi;
  if (arg0 == 104
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx32qivnx4hi;
  if (arg0 == 105
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx32qivnx4hi;
  if (arg0 == 104
      && arg1 == E_VNx64QImode
      && arg2 == E_VNx64QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx64qivnx4hi;
  if (arg0 == 105
      && arg1 == E_VNx64QImode
      && arg2 == E_VNx64QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx64qivnx4hi;
  if (arg0 == 104
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_widen_reduc_plusvnx1hivnx2si;
  if (arg0 == 105
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx1hivnx2si;
  if (arg0 == 104
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_widen_reduc_plusvnx2hivnx2si;
  if (arg0 == 105
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx2hivnx2si;
  if (arg0 == 104
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_widen_reduc_plusvnx4hivnx2si;
  if (arg0 == 105
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx4hivnx2si;
  if (arg0 == 104
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_widen_reduc_plusvnx8hivnx2si;
  if (arg0 == 105
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx8hivnx2si;
  if (arg0 == 104
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_widen_reduc_plusvnx16hivnx2si;
  if (arg0 == 105
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx16hivnx2si;
  if (arg0 == 104
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_widen_reduc_plusvnx32hivnx2si;
  if (arg0 == 105
      && arg1 == E_VNx32HImode
      && arg2 == E_VNx32HImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx32hivnx2si;
  if (arg0 == 104
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_widen_reduc_plusvnx1sivnx2di;
  if (arg0 == 105
      && arg1 == E_VNx1SImode
      && arg2 == E_VNx1SImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx1sivnx2di;
  if (arg0 == 104
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_widen_reduc_plusvnx2sivnx2di;
  if (arg0 == 105
      && arg1 == E_VNx2SImode
      && arg2 == E_VNx2SImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx2sivnx2di;
  if (arg0 == 104
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_widen_reduc_plusvnx4sivnx2di;
  if (arg0 == 105
      && arg1 == E_VNx4SImode
      && arg2 == E_VNx4SImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx4sivnx2di;
  if (arg0 == 104
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_widen_reduc_plusvnx8sivnx2di;
  if (arg0 == 105
      && arg1 == E_VNx8SImode
      && arg2 == E_VNx8SImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx8sivnx2di;
  if (arg0 == 104
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_widen_reduc_plusvnx16sivnx2di;
  if (arg0 == 105
      && arg1 == E_VNx16SImode
      && arg2 == E_VNx16SImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx16sivnx2di;
  if (arg0 == 104
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx1qivnx2hi;
  if (arg0 == 105
      && arg1 == E_VNx1QImode
      && arg2 == E_VNx1QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx1qivnx2hi;
  if (arg0 == 104
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx2qivnx2hi;
  if (arg0 == 105
      && arg1 == E_VNx2QImode
      && arg2 == E_VNx2QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx2qivnx2hi;
  if (arg0 == 104
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx4qivnx2hi;
  if (arg0 == 105
      && arg1 == E_VNx4QImode
      && arg2 == E_VNx4QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx4qivnx2hi;
  if (arg0 == 104
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx8qivnx2hi;
  if (arg0 == 105
      && arg1 == E_VNx8QImode
      && arg2 == E_VNx8QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx8qivnx2hi;
  if (arg0 == 104
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx16qivnx2hi;
  if (arg0 == 105
      && arg1 == E_VNx16QImode
      && arg2 == E_VNx16QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx16qivnx2hi;
  if (arg0 == 104
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_widen_reduc_plusvnx32qivnx2hi;
  if (arg0 == 105
      && arg1 == E_VNx32QImode
      && arg2 == E_VNx32QImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx32qivnx2hi;
  if (arg0 == 104
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_widen_reduc_plusvnx1hivnx1si;
  if (arg0 == 105
      && arg1 == E_VNx1HImode
      && arg2 == E_VNx1HImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx1hivnx1si;
  if (arg0 == 104
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_widen_reduc_plusvnx2hivnx1si;
  if (arg0 == 105
      && arg1 == E_VNx2HImode
      && arg2 == E_VNx2HImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx2hivnx1si;
  if (arg0 == 104
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_widen_reduc_plusvnx4hivnx1si;
  if (arg0 == 105
      && arg1 == E_VNx4HImode
      && arg2 == E_VNx4HImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx4hivnx1si;
  if (arg0 == 104
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_widen_reduc_plusvnx8hivnx1si;
  if (arg0 == 105
      && arg1 == E_VNx8HImode
      && arg2 == E_VNx8HImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx8hivnx1si;
  if (arg0 == 104
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_widen_reduc_plusvnx16hivnx1si;
  if (arg0 == 105
      && arg1 == E_VNx16HImode
      && arg2 == E_VNx16HImode)
    return CODE_FOR_pred_widen_reduc_plusuvnx16hivnx1si;
  if (arg0 == 71
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1SFmode)
    return CODE_FOR_pred_widen_reduc_plusovnx1sfvnx1df;
  if (arg0 == 72
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1SFmode)
    return CODE_FOR_pred_widen_reduc_plusuvnx1sfvnx1df;
  if (arg0 == 71
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2SFmode)
    return CODE_FOR_pred_widen_reduc_plusovnx2sfvnx1df;
  if (arg0 == 72
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2SFmode)
    return CODE_FOR_pred_widen_reduc_plusuvnx2sfvnx1df;
  if (arg0 == 71
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4SFmode)
    return CODE_FOR_pred_widen_reduc_plusovnx4sfvnx1df;
  if (arg0 == 72
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4SFmode)
    return CODE_FOR_pred_widen_reduc_plusuvnx4sfvnx1df;
  if (arg0 == 71
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8SFmode)
    return CODE_FOR_pred_widen_reduc_plusovnx8sfvnx1df;
  if (arg0 == 72
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8SFmode)
    return CODE_FOR_pred_widen_reduc_plusuvnx8sfvnx1df;
  if (arg0 == 71
      && arg1 == E_VNx16SFmode
      && arg2 == E_VNx16SFmode)
    return CODE_FOR_pred_widen_reduc_plusovnx16sfvnx1df;
  if (arg0 == 72
      && arg1 == E_VNx16SFmode
      && arg2 == E_VNx16SFmode)
    return CODE_FOR_pred_widen_reduc_plusuvnx16sfvnx1df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_widen_reduc_plus (int arg0, machine_mode arg1, machine_mode arg2, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_widen_reduc_plus (arg0, arg1, arg2);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_reduc_plus (int arg0, machine_mode arg1, machine_mode arg2)
{
  if (arg0 == 71
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1SFmode)
    return CODE_FOR_pred_reduc_plusovnx1sfvnx2sf;
  if (arg0 == 72
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1SFmode)
    return CODE_FOR_pred_reduc_plusuvnx1sfvnx2sf;
  if (arg0 == 71
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2SFmode)
    return CODE_FOR_pred_reduc_plusovnx2sfvnx2sf;
  if (arg0 == 72
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2SFmode)
    return CODE_FOR_pred_reduc_plusuvnx2sfvnx2sf;
  if (arg0 == 71
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4SFmode)
    return CODE_FOR_pred_reduc_plusovnx4sfvnx2sf;
  if (arg0 == 72
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4SFmode)
    return CODE_FOR_pred_reduc_plusuvnx4sfvnx2sf;
  if (arg0 == 71
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8SFmode)
    return CODE_FOR_pred_reduc_plusovnx8sfvnx2sf;
  if (arg0 == 72
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8SFmode)
    return CODE_FOR_pred_reduc_plusuvnx8sfvnx2sf;
  if (arg0 == 71
      && arg1 == E_VNx16SFmode
      && arg2 == E_VNx16SFmode)
    return CODE_FOR_pred_reduc_plusovnx16sfvnx2sf;
  if (arg0 == 72
      && arg1 == E_VNx16SFmode
      && arg2 == E_VNx16SFmode)
    return CODE_FOR_pred_reduc_plusuvnx16sfvnx2sf;
  if (arg0 == 71
      && arg1 == E_VNx1DFmode
      && arg2 == E_VNx1DFmode)
    return CODE_FOR_pred_reduc_plusovnx1dfvnx1df;
  if (arg0 == 72
      && arg1 == E_VNx1DFmode
      && arg2 == E_VNx1DFmode)
    return CODE_FOR_pred_reduc_plusuvnx1dfvnx1df;
  if (arg0 == 71
      && arg1 == E_VNx2DFmode
      && arg2 == E_VNx2DFmode)
    return CODE_FOR_pred_reduc_plusovnx2dfvnx1df;
  if (arg0 == 72
      && arg1 == E_VNx2DFmode
      && arg2 == E_VNx2DFmode)
    return CODE_FOR_pred_reduc_plusuvnx2dfvnx1df;
  if (arg0 == 71
      && arg1 == E_VNx4DFmode
      && arg2 == E_VNx4DFmode)
    return CODE_FOR_pred_reduc_plusovnx4dfvnx1df;
  if (arg0 == 72
      && arg1 == E_VNx4DFmode
      && arg2 == E_VNx4DFmode)
    return CODE_FOR_pred_reduc_plusuvnx4dfvnx1df;
  if (arg0 == 71
      && arg1 == E_VNx8DFmode
      && arg2 == E_VNx8DFmode)
    return CODE_FOR_pred_reduc_plusovnx8dfvnx1df;
  if (arg0 == 72
      && arg1 == E_VNx8DFmode
      && arg2 == E_VNx8DFmode)
    return CODE_FOR_pred_reduc_plusuvnx8dfvnx1df;
  if (arg0 == 71
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1SFmode)
    return CODE_FOR_pred_reduc_plusovnx1sfvnx1sf;
  if (arg0 == 72
      && arg1 == E_VNx1SFmode
      && arg2 == E_VNx1SFmode)
    return CODE_FOR_pred_reduc_plusuvnx1sfvnx1sf;
  if (arg0 == 71
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2SFmode)
    return CODE_FOR_pred_reduc_plusovnx2sfvnx1sf;
  if (arg0 == 72
      && arg1 == E_VNx2SFmode
      && arg2 == E_VNx2SFmode)
    return CODE_FOR_pred_reduc_plusuvnx2sfvnx1sf;
  if (arg0 == 71
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4SFmode)
    return CODE_FOR_pred_reduc_plusovnx4sfvnx1sf;
  if (arg0 == 72
      && arg1 == E_VNx4SFmode
      && arg2 == E_VNx4SFmode)
    return CODE_FOR_pred_reduc_plusuvnx4sfvnx1sf;
  if (arg0 == 71
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8SFmode)
    return CODE_FOR_pred_reduc_plusovnx8sfvnx1sf;
  if (arg0 == 72
      && arg1 == E_VNx8SFmode
      && arg2 == E_VNx8SFmode)
    return CODE_FOR_pred_reduc_plusuvnx8sfvnx1sf;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_reduc_plus (int arg0, machine_mode arg1, machine_mode arg2, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_reduc_plus (arg0, arg1, arg2);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_extract_first (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_extract_firstvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_extract_firstvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_extract_firstvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_extract_firstvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_extract_firstvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_extract_firstvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_extract_firstvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_extract_firstvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_extract_firstvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_extract_firstvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_extract_firstvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_extract_firstvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_extract_firstvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_extract_firstvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_extract_firstvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_extract_firstvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_extract_firstvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_extract_firstvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_extract_firstvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_extract_firstvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_extract_firstvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_extract_firstvnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_extract_firstvnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_extract_firstvnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_extract_firstvnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_extract_firstvnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_extract_firstvnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_extract_firstvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_extract_firstvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_extract_firstvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_extract_firstvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_extract_first (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_pred_extract_first (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 2);
      return GEN_FCN (code) (x0, x1);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_extract_first_trunc (machine_mode arg0)
{
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_extract_first_truncvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_extract_first_truncvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_extract_first_truncvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_extract_first_truncvnx8di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_extract_first_trunc (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_pred_extract_first_trunc (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 2);
      return GEN_FCN (code) (x0, x1);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_slide (int arg0, machine_mode arg1)
{
  if (arg0 == 106
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_slideupvnx1qi;
  if (arg0 == 107
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_slidedownvnx1qi;
  if (arg0 == 106
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_slideupvnx2qi;
  if (arg0 == 107
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_slidedownvnx2qi;
  if (arg0 == 106
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_slideupvnx4qi;
  if (arg0 == 107
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_slidedownvnx4qi;
  if (arg0 == 106
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_slideupvnx8qi;
  if (arg0 == 107
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_slidedownvnx8qi;
  if (arg0 == 106
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_slideupvnx16qi;
  if (arg0 == 107
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_slidedownvnx16qi;
  if (arg0 == 106
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_slideupvnx32qi;
  if (arg0 == 107
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_slidedownvnx32qi;
  if (arg0 == 106
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_slideupvnx64qi;
  if (arg0 == 107
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_slidedownvnx64qi;
  if (arg0 == 106
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_slideupvnx1hi;
  if (arg0 == 107
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_slidedownvnx1hi;
  if (arg0 == 106
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_slideupvnx2hi;
  if (arg0 == 107
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_slidedownvnx2hi;
  if (arg0 == 106
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_slideupvnx4hi;
  if (arg0 == 107
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_slidedownvnx4hi;
  if (arg0 == 106
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_slideupvnx8hi;
  if (arg0 == 107
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_slidedownvnx8hi;
  if (arg0 == 106
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_slideupvnx16hi;
  if (arg0 == 107
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_slidedownvnx16hi;
  if (arg0 == 106
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_slideupvnx32hi;
  if (arg0 == 107
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_slidedownvnx32hi;
  if (arg0 == 106
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_slideupvnx1si;
  if (arg0 == 107
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_slidedownvnx1si;
  if (arg0 == 106
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_slideupvnx2si;
  if (arg0 == 107
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_slidedownvnx2si;
  if (arg0 == 106
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_slideupvnx4si;
  if (arg0 == 107
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_slidedownvnx4si;
  if (arg0 == 106
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_slideupvnx8si;
  if (arg0 == 107
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_slidedownvnx8si;
  if (arg0 == 106
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_slideupvnx16si;
  if (arg0 == 107
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_slidedownvnx16si;
  if (arg0 == 106
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_slideupvnx1di;
  if (arg0 == 107
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_slidedownvnx1di;
  if (arg0 == 106
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_slideupvnx2di;
  if (arg0 == 107
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_slidedownvnx2di;
  if (arg0 == 106
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_slideupvnx4di;
  if (arg0 == 107
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_slidedownvnx4di;
  if (arg0 == 106
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_slideupvnx8di;
  if (arg0 == 107
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_slidedownvnx8di;
  if (arg0 == 106
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_slideupvnx1sf;
  if (arg0 == 107
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_slidedownvnx1sf;
  if (arg0 == 106
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_slideupvnx2sf;
  if (arg0 == 107
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_slidedownvnx2sf;
  if (arg0 == 106
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_slideupvnx4sf;
  if (arg0 == 107
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_slidedownvnx4sf;
  if (arg0 == 106
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_slideupvnx8sf;
  if (arg0 == 107
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_slidedownvnx8sf;
  if (arg0 == 106
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_slideupvnx16sf;
  if (arg0 == 107
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_slidedownvnx16sf;
  if (arg0 == 106
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_slideupvnx1df;
  if (arg0 == 107
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_slidedownvnx1df;
  if (arg0 == 106
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_slideupvnx2df;
  if (arg0 == 107
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_slidedownvnx2df;
  if (arg0 == 106
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_slideupvnx4df;
  if (arg0 == 107
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_slidedownvnx4df;
  if (arg0 == 106
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_slideupvnx8df;
  if (arg0 == 107
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_slidedownvnx8df;
  if (arg0 == 108
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_slide1upvnx1qi;
  if (arg0 == 109
      && arg1 == E_VNx1QImode)
    return CODE_FOR_pred_slide1downvnx1qi;
  if (arg0 == 108
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_slide1upvnx2qi;
  if (arg0 == 109
      && arg1 == E_VNx2QImode)
    return CODE_FOR_pred_slide1downvnx2qi;
  if (arg0 == 108
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_slide1upvnx4qi;
  if (arg0 == 109
      && arg1 == E_VNx4QImode)
    return CODE_FOR_pred_slide1downvnx4qi;
  if (arg0 == 108
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_slide1upvnx8qi;
  if (arg0 == 109
      && arg1 == E_VNx8QImode)
    return CODE_FOR_pred_slide1downvnx8qi;
  if (arg0 == 108
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_slide1upvnx16qi;
  if (arg0 == 109
      && arg1 == E_VNx16QImode)
    return CODE_FOR_pred_slide1downvnx16qi;
  if (arg0 == 108
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_slide1upvnx32qi;
  if (arg0 == 109
      && arg1 == E_VNx32QImode)
    return CODE_FOR_pred_slide1downvnx32qi;
  if (arg0 == 108
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_slide1upvnx64qi;
  if (arg0 == 109
      && arg1 == E_VNx64QImode)
    return CODE_FOR_pred_slide1downvnx64qi;
  if (arg0 == 108
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_slide1upvnx1hi;
  if (arg0 == 109
      && arg1 == E_VNx1HImode)
    return CODE_FOR_pred_slide1downvnx1hi;
  if (arg0 == 108
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_slide1upvnx2hi;
  if (arg0 == 109
      && arg1 == E_VNx2HImode)
    return CODE_FOR_pred_slide1downvnx2hi;
  if (arg0 == 108
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_slide1upvnx4hi;
  if (arg0 == 109
      && arg1 == E_VNx4HImode)
    return CODE_FOR_pred_slide1downvnx4hi;
  if (arg0 == 108
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_slide1upvnx8hi;
  if (arg0 == 109
      && arg1 == E_VNx8HImode)
    return CODE_FOR_pred_slide1downvnx8hi;
  if (arg0 == 108
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_slide1upvnx16hi;
  if (arg0 == 109
      && arg1 == E_VNx16HImode)
    return CODE_FOR_pred_slide1downvnx16hi;
  if (arg0 == 108
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_slide1upvnx32hi;
  if (arg0 == 109
      && arg1 == E_VNx32HImode)
    return CODE_FOR_pred_slide1downvnx32hi;
  if (arg0 == 108
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_slide1upvnx1si;
  if (arg0 == 109
      && arg1 == E_VNx1SImode)
    return CODE_FOR_pred_slide1downvnx1si;
  if (arg0 == 108
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_slide1upvnx2si;
  if (arg0 == 109
      && arg1 == E_VNx2SImode)
    return CODE_FOR_pred_slide1downvnx2si;
  if (arg0 == 108
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_slide1upvnx4si;
  if (arg0 == 109
      && arg1 == E_VNx4SImode)
    return CODE_FOR_pred_slide1downvnx4si;
  if (arg0 == 108
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_slide1upvnx8si;
  if (arg0 == 109
      && arg1 == E_VNx8SImode)
    return CODE_FOR_pred_slide1downvnx8si;
  if (arg0 == 108
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_slide1upvnx16si;
  if (arg0 == 109
      && arg1 == E_VNx16SImode)
    return CODE_FOR_pred_slide1downvnx16si;
  if (arg0 == 108
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_slide1upvnx1di;
  if (arg0 == 109
      && arg1 == E_VNx1DImode)
    return CODE_FOR_pred_slide1downvnx1di;
  if (arg0 == 108
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_slide1upvnx2di;
  if (arg0 == 109
      && arg1 == E_VNx2DImode)
    return CODE_FOR_pred_slide1downvnx2di;
  if (arg0 == 108
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_slide1upvnx4di;
  if (arg0 == 109
      && arg1 == E_VNx4DImode)
    return CODE_FOR_pred_slide1downvnx4di;
  if (arg0 == 108
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_slide1upvnx8di;
  if (arg0 == 109
      && arg1 == E_VNx8DImode)
    return CODE_FOR_pred_slide1downvnx8di;
  if (arg0 == 110
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_slide1upvnx1sf;
  if (arg0 == 111
      && arg1 == E_VNx1SFmode)
    return CODE_FOR_pred_slide1downvnx1sf;
  if (arg0 == 110
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_slide1upvnx2sf;
  if (arg0 == 111
      && arg1 == E_VNx2SFmode)
    return CODE_FOR_pred_slide1downvnx2sf;
  if (arg0 == 110
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_slide1upvnx4sf;
  if (arg0 == 111
      && arg1 == E_VNx4SFmode)
    return CODE_FOR_pred_slide1downvnx4sf;
  if (arg0 == 110
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_slide1upvnx8sf;
  if (arg0 == 111
      && arg1 == E_VNx8SFmode)
    return CODE_FOR_pred_slide1downvnx8sf;
  if (arg0 == 110
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_slide1upvnx16sf;
  if (arg0 == 111
      && arg1 == E_VNx16SFmode)
    return CODE_FOR_pred_slide1downvnx16sf;
  if (arg0 == 110
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_slide1upvnx1df;
  if (arg0 == 111
      && arg1 == E_VNx1DFmode)
    return CODE_FOR_pred_slide1downvnx1df;
  if (arg0 == 110
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_slide1upvnx2df;
  if (arg0 == 111
      && arg1 == E_VNx2DFmode)
    return CODE_FOR_pred_slide1downvnx2df;
  if (arg0 == 110
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_slide1upvnx4df;
  if (arg0 == 111
      && arg1 == E_VNx4DFmode)
    return CODE_FOR_pred_slide1downvnx4df;
  if (arg0 == 110
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_slide1upvnx8df;
  if (arg0 == 111
      && arg1 == E_VNx8DFmode)
    return CODE_FOR_pred_slide1downvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_slide (int arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_slide (arg0, arg1);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_gather (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_gathervnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_gathervnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_gathervnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_gathervnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_gathervnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_gathervnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_gathervnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_gathervnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_gathervnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_gathervnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_gathervnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_gathervnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_gathervnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_gathervnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_gathervnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_gathervnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_gathervnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_gathervnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_gathervnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_gathervnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_gathervnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_gathervnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_gathervnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_gathervnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_gathervnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_gathervnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_gathervnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_gathervnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_gathervnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_gathervnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_gathervnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_gather (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_gather (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_gather_scalar (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_gathervnx1qi_scalar;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_gathervnx2qi_scalar;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_gathervnx4qi_scalar;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_gathervnx8qi_scalar;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_gathervnx16qi_scalar;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_gathervnx32qi_scalar;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_gathervnx64qi_scalar;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_gathervnx1hi_scalar;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_gathervnx2hi_scalar;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_gathervnx4hi_scalar;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_gathervnx8hi_scalar;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_gathervnx16hi_scalar;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_gathervnx32hi_scalar;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_gathervnx1si_scalar;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_gathervnx2si_scalar;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_gathervnx4si_scalar;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_gathervnx8si_scalar;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_gathervnx16si_scalar;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_gathervnx1di_scalar;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_gathervnx2di_scalar;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_gathervnx4di_scalar;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_gathervnx8di_scalar;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_gathervnx1sf_scalar;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_gathervnx2sf_scalar;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_gathervnx4sf_scalar;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_gathervnx8sf_scalar;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_gathervnx16sf_scalar;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_gathervnx1df_scalar;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_gathervnx2df_scalar;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_gathervnx4df_scalar;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_gathervnx8df_scalar;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_gather_scalar (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_gather_scalar (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_gatherei16 (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_gatherei16vnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_gatherei16vnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_gatherei16vnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_gatherei16vnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_gatherei16vnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_gatherei16vnx32qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_gatherei16vnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_gatherei16vnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_gatherei16vnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_gatherei16vnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_gatherei16vnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_gatherei16vnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_gatherei16vnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_gatherei16vnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_gatherei16vnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_gatherei16vnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_gatherei16vnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_gatherei16vnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_gatherei16vnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_gatherei16vnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_gatherei16vnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_gatherei16vnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_gatherei16vnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_gatherei16vnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_gatherei16vnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_gatherei16vnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_gatherei16vnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_gatherei16vnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_gatherei16vnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_gatherei16vnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_gatherei16 (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7, rtx x8)
{
  insn_code code = maybe_code_for_pred_gatherei16 (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 9);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7, x8);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_compress (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_compressvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_compressvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_compressvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_compressvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_compressvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_compressvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_compressvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_compressvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_compressvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_compressvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_compressvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_compressvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_compressvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_compressvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_compressvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_compressvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_compressvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_compressvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_compressvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_compressvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_compressvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_compressvnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_compressvnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_compressvnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_compressvnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_compressvnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_compressvnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_compressvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_compressvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_compressvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_compressvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_compress (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6)
{
  insn_code code = maybe_code_for_pred_compress (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 7);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6);
    }
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_pred_fault_load (machine_mode arg0)
{
  if (arg0 == E_VNx1QImode)
    return CODE_FOR_pred_fault_loadvnx1qi;
  if (arg0 == E_VNx2QImode)
    return CODE_FOR_pred_fault_loadvnx2qi;
  if (arg0 == E_VNx4QImode)
    return CODE_FOR_pred_fault_loadvnx4qi;
  if (arg0 == E_VNx8QImode)
    return CODE_FOR_pred_fault_loadvnx8qi;
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_pred_fault_loadvnx16qi;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_pred_fault_loadvnx32qi;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_pred_fault_loadvnx64qi;
  if (arg0 == E_VNx1HImode)
    return CODE_FOR_pred_fault_loadvnx1hi;
  if (arg0 == E_VNx2HImode)
    return CODE_FOR_pred_fault_loadvnx2hi;
  if (arg0 == E_VNx4HImode)
    return CODE_FOR_pred_fault_loadvnx4hi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_pred_fault_loadvnx8hi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_pred_fault_loadvnx16hi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_pred_fault_loadvnx32hi;
  if (arg0 == E_VNx1SImode)
    return CODE_FOR_pred_fault_loadvnx1si;
  if (arg0 == E_VNx2SImode)
    return CODE_FOR_pred_fault_loadvnx2si;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_pred_fault_loadvnx4si;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_pred_fault_loadvnx8si;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_pred_fault_loadvnx16si;
  if (arg0 == E_VNx1DImode)
    return CODE_FOR_pred_fault_loadvnx1di;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_pred_fault_loadvnx2di;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_pred_fault_loadvnx4di;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_pred_fault_loadvnx8di;
  if (arg0 == E_VNx1SFmode)
    return CODE_FOR_pred_fault_loadvnx1sf;
  if (arg0 == E_VNx2SFmode)
    return CODE_FOR_pred_fault_loadvnx2sf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_pred_fault_loadvnx4sf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_pred_fault_loadvnx8sf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_pred_fault_loadvnx16sf;
  if (arg0 == E_VNx1DFmode)
    return CODE_FOR_pred_fault_loadvnx1df;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_pred_fault_loadvnx2df;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_pred_fault_loadvnx4df;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_pred_fault_loadvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_pred_fault_load (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_pred_fault_load (arg0);
  if (code != CODE_FOR_nothing)
    {
      gcc_assert (insn_data[code].n_generator_args == 8);
      return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
    }
  else
    return NULL_RTX;
}
