(define_conditions [
  (-1 "(TARGET_VECTOR) && (TARGET_FULL_V)")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_VECTOR) && ((TARGET_64BIT && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_FP_32))")
  (0 "(!SMALL_OPERAND (INTVAL (operands[3]))) && (((((TARGET_64BIT) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT))")
  (-1 "TARGET_ZMMUL || TARGET_MUL")
  (-1 "(TARGET_ZKSED) && (!TARGET_64BIT)")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(USE_LOAD_ADDRESS_MACRO (operands[0])) && ((TARGET_64BIT) && (Pmode == DImode))")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && ((TARGET_ZFH || TARGET_ZHINX) && (Pmode == SImode))")
  (-1 "(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx1HImode)
   && register_operand (operands[3], VNx1HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (Pmode == DImode))")
  (-1 "TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1")
  (-1 "TARGET_HARD_FLOAT || TARGET_ZFINX")
  (-1 "(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_MIN_VLEN > 32)")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)")
  (-1 "(TARGET_VECTOR) && ( register_operand (operands[0], VNx4BImode)
   && register_operand (operands[3], VNx4BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (((!TARGET_64BIT) && (TARGET_HARD_FLOAT || TARGET_ZFINX)) && (TARGET_HARD_FLOAT || TARGET_ZFINX))")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "(TARGET_VECTOR) && ( reload_completed)")
  (-1 "(TARGET_ZBS && TARGET_ZBB) && (TARGET_64BIT)")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_64)")
  (-1 "((TARGET_VECTOR && (lra_in_progress || reload_completed)) && (Pmode == DImode)) && ( reload_completed)")
  (-1 "((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (SFmode)) && (TARGET_HARD_FLOAT || TARGET_ZFINX)")
  (-1 "(TARGET_HARD_FLOAT  || TARGET_ZFINX) && ((TARGET_64BIT) && (TARGET_HARD_FLOAT || TARGET_ZFINX))")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (TARGET_ZFH || TARGET_ZHINX)")
  (-1 "TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, false, SImode)")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_SFB_ALU) && (TARGET_64BIT)")
  (-1 "reload_completed")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx8HImode)
   && register_operand (operands[3], VNx8HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8HImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && ((TARGET_64BIT) && (Pmode == SImode))")
  (-1 "TARGET_ZKNE && !TARGET_64BIT")
  (-1 "((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (HFmode)) && (TARGET_ZFH || TARGET_ZHINX)")
  (-1 "TARGET_64BIT && TARGET_ZBA
   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff")
  (-1 "(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (TARGET_HARD_FLOAT || TARGET_ZFINX)")
  (-1 "(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && ( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_64)) && ( register_operand (operands[0], VNx2DImode)
   && register_operand (operands[3], VNx2DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (SImode)) && (!TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (Pmode == SImode))")
  (-1 "(TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (DImode)) && (TARGET_64BIT)")
  (-1 "(TARGET_ZBB) && (TARGET_64BIT)")
  (-1 "(TARGET_VECTOR && TARGET_MIN_VLEN == 32) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_MIN_VLEN > 32)")
  (-1 "Pmode == DImode")
  (-1 "((TARGET_ZBS && TARGET_ZBB) && (TARGET_64BIT)) && ( reload_completed)")
  (-1 "known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode))")
  (-1 "TARGET_DIV")
  (-1 "((TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_MIN_VLEN > 32) && (Pmode == SImode))) && ( reload_completed)")
  (-1 "(TARGET_SFB_ALU) && (!TARGET_64BIT)")
  (-1 "TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0")
  (-1 "TARGET_ZBS && TARGET_64BIT
   && !partial_subreg_p (operands[1])")
  (-1 "!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (((!TARGET_64BIT) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX))")
  (-1 "TARGET_ZBB || TARGET_XTHEADBB")
  (-1 "TARGET_64BIT && TARGET_ZBS
   && clz_hwi (~UINTVAL (operands[2])) > 33")
  (-1 "TARGET_VECTOR && TARGET_64BIT")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)")
  (-1 "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)")
  (-1 "(TARGET_VECTOR) && (Pmode == SImode)")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_VECTOR) && ( register_operand (operands[0], VNx1BImode)
   && register_operand (operands[3], VNx1BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)")
  (-1 "(reload_completed) && (!TARGET_64BIT)")
  (-1 "((TARGET_ZBS) && (TARGET_64BIT)) && ( reload_completed)")
  (-1 "(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32)) && ( register_operand (operands[0], VNx8SFmode)
   && register_operand (operands[3], VNx8SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])) && (TARGET_ZFHMIN)")
  (-1 "(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "(TARGET_ZBKC) && (TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (((TARGET_64BIT) && (TARGET_HARD_FLOAT || TARGET_ZFINX)) && (TARGET_HARD_FLOAT || TARGET_ZFINX))")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_FP_64)")
  (-1 "((TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && (Pmode == DImode))) && ( reload_completed)")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (Pmode == DImode))")
  (-1 "(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1) && ( 1)")
  (-1 "(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)")
  (-1 "(register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)) && (TARGET_MIN_VLEN > 32)")
  (-1 "(riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)) && (Pmode == DImode)")
  (-1 "(TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0) && ( reload_completed)")
  (-1 "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && ((TARGET_ZFHMIN) && (Pmode == DImode))")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(reload_completed) && (TARGET_64BIT)")
  (-1 "riscv_can_use_return_insn ()")
  (-1 "!TARGET_64BIT && TARGET_DOUBLE_FLOAT
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode))")
  (-1 "(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && (TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (TARGET_64BIT))")
  (-1 "TARGET_XTHEADCONDMOV")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (Pmode == SImode))")
  (-1 "(!(p2m1_shift_operand (operands[1], SImode)
     || high_mask_shift_operand (operands[1], SImode))) && ( 1)")
  (-1 "((TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32)) && ( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32QImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "((!TARGET_ZBB) && (TARGET_64BIT)) && ( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0]))")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_MIN_VLEN > 32)")
  (-1 "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
   && th_mempair_operands_p (operands, true, SImode)")
  (-1 "TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])")
  (-1 "(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "(TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)) && (!TARGET_64BIT)")
  (-1 "(TARGET_64BIT && !TARGET_ZBA
   && !(register_operand (operands[1], SImode)
        && reg_or_subregno (operands[1]) == VL_REGNUM)) && ( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0]))")
  (-1 "(TARGET_XTHEADBA
   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)) && (!TARGET_64BIT)")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32)) && ( register_operand (operands[0], VNx1SFmode)
   && register_operand (operands[3], VNx1SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_ZICBOM) && (TARGET_64BIT)")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32)) && ( register_operand (operands[0], VNx2SFmode)
   && register_operand (operands[3], VNx2SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)")
  (-1 "TARGET_XTHEADMAC && TARGET_64BIT")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8QImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx1QImode)
   && register_operand (operands[3], VNx1QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_MIN_VLEN > 32) && (Pmode == DImode))")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "TARGET_HARD_FLOAT
   && (register_operand (operands[0], SFmode)
       || reg_or_0_operand (operands[1], SFmode))")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((TARGET_64BIT) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX))")
  (-1 "(TARGET_XTHEADBA
   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)) && (TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (Pmode == DImode))")
  (-1 "((TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && (TARGET_64BIT)) && ( reload_completed)")
  (-1 "!TARGET_64BIT
   && (register_operand (operands[0], DImode)
       || reg_or_0_operand (operands[1], DImode))")
  (-1 "TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   /* Ensure the mask includes all the bits in SImode.  */
   && ((INTVAL (operands[3]) & (HOST_WIDE_INT_1U << 31)) != 0)")
  (-1 "(TARGET_VECTOR) && (Pmode == DImode)")
  (-1 "(TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && (Pmode == SImode))")
  (-1 "(TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (DImode)) && (TARGET_64BIT)")
  (-1 "(register_operand (operands[0], SImode)
    || reg_or_0_operand (operands[1], SImode))
    && !(register_operand (operands[1], SImode)
         && reg_or_subregno (operands[1]) == VL_REGNUM)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_ZFH || TARGET_ZHINX) && (Pmode == DImode))")
  (-1 "(USE_LOAD_ADDRESS_MACRO (operands[0])) && ((TARGET_64BIT) && (Pmode == SImode))")
  (-1 "(TARGET_ZBS && TARGET_ZBB) && (!TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (Pmode == SImode))")
  (-1 "(USE_LOAD_ADDRESS_MACRO (operands[0])) && (Pmode == SImode)")
  (-1 "(TARGET_VECTOR) && ((TARGET_64BIT && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_FP_64))")
  (-1 "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (Pmode == DImode)")
  (-1 "(TARGET_ZBA) && (!TARGET_64BIT)")
  (-1 "! TARGET_64BIT")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "!TARGET_DOUBLE_FLOAT
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode))")
  (-1 "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV")
  (-1 "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
  (-1 "((TARGET_VECTOR) && (TARGET_VECTOR_ELEN_FP_32)) && ( reload_completed)")
  (-1 "(((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && (((((TARGET_64BIT) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT))) && ( reload_completed)")
  (-1 "TARGET_64BIT && !TARGET_ZBA
   && !(register_operand (operands[1], SImode)
        && reg_or_subregno (operands[1]) == VL_REGNUM)")
  (-1 "TARGET_XTHEADMEMPAIR && TARGET_64BIT
  && th_mempair_operands_p (operands, true, SImode)")
  (-1 "(TARGET_ZBS) && (!TARGET_64BIT)")
  (-1 "(TARGET_VECTOR) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)")
  (-1 "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && ((TARGET_64BIT) && (Pmode == DImode))")
  (-1 "TARGET_ZIFENCEI")
  (-1 "TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))")
  (-1 "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])) && (TARGET_64BIT)")
  (-1 "(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "(TARGET_VECTOR) && (TARGET_MIN_VLEN > 32)")
  (-1 "TARGET_ZKND && TARGET_64BIT")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)")
  (-1 "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT")
  (-1 "register_operand (operands[3], SImode)
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)")
  (-1 "(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, true, DImode)) && (TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (((TARGET_64BIT) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX))")
  (-1 "!(p2m1_shift_operand (operands[1], SImode)
     || high_mask_shift_operand (operands[1], SImode))")
  (-1 "(TARGET_ZKSED) && (TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (((TARGET_64BIT) && (TARGET_ZFH || TARGET_ZHINX)) && (TARGET_ZFH || TARGET_ZHINX))")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "(TARGET_XTHEADBB && (TARGET_64BIT || DImode == SImode)) && (TARGET_64BIT)")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_64)) && ( register_operand (operands[0], VNx8DImode)
   && register_operand (operands[3], VNx8DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "((TARGET_ZBS) && (!TARGET_64BIT)) && ( reload_completed)")
  (-1 "TARGET_ZBKB && !TARGET_64BIT")
  (0 "((!SMALL_OPERAND (INTVAL (operands[3]))) && (((((TARGET_64BIT) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT))) && ( reload_completed)")
  (-1 "((TARGET_VECTOR && (lra_in_progress || reload_completed)) && (Pmode == SImode)) && ( reload_completed)")
  (-1 "!TARGET_ZBB")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx32HImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)")
  (-1 "TARGET_VECTOR")
  (-1 "(TARGET_ZBB || TARGET_XTHEADBB) && (TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (((!TARGET_64BIT) && (TARGET_ZFH || TARGET_ZHINX)) && (TARGET_ZFH || TARGET_ZHINX))")
  (-1 "(TARGET_ZBB || TARGET_ZBKB) && (TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (Pmode == SImode))")
  (-1 "(TARGET_VECTOR) && ((TARGET_64BIT && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_64))")
  (-1 "(TARGET_VECTOR) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN == 32)")
  (-1 "(TARGET_VECTOR) && ((TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32))")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2HImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_ZKSH) && (TARGET_64BIT)")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)")
  (-1 "TARGET_64BIT && TARGET_ZBA")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (Pmode == DImode))")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_64)) && ( register_operand (operands[0], VNx1DImode)
   && register_operand (operands[3], VNx1DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)")
  (-1 "((!(p2m1_shift_operand (operands[1], DImode)
     || high_mask_shift_operand (operands[1], DImode))) && (TARGET_64BIT)) && ( 1)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (Pmode == DImode))")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (DFmode)) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx32QImode)
   && register_operand (operands[3], VNx32QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)")
  (-1 "((TARGET_VECTOR) && (Pmode == SImode)) && ( epilogue_completed)")
  (-1 "(TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
       == GET_MODE_BITSIZE (DImode)-1) && ( 1)")
  (-1 "(TARGET_ZBKB) && (TARGET_64BIT)")
  (-1 "(TARGET_ZBS) && (TARGET_64BIT)")
  (-1 "((TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_64)) && ( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (Pmode == SImode))")
  (-1 "((TARGET_VECTOR) && (TARGET_VECTOR_ELEN_64)) && ( reload_completed)")
  (-1 "TARGET_64BIT
   && (register_operand (operands[0], DImode)
       || reg_or_0_operand (operands[1], DImode))")
  (-1 "((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && (((((TARGET_64BIT) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (!TARGET_64BIT))")
  (-1 "(TARGET_VECTOR) && (TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32)")
  (-1 "(TARGET_ZICBOZ) && (TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT  || TARGET_ZFINX) && ((TARGET_64BIT) && (TARGET_ZFH || TARGET_ZHINX))")
  (-1 "!TARGET_64BIT && TARGET_XTHEADFMV")
  (-1 "(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_64)")
  (-1 "(TARGET_VECTOR && TARGET_MIN_VLEN > 32) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_HARD_FLOAT  || TARGET_ZFINX) && ((TARGET_64BIT) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX))")
  (-1 "TARGET_64BIT
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
       == GET_MODE_BITSIZE (SImode)-1")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_MIN_VLEN > 32)) && ( register_operand (operands[0], VNx64QImode)
   && register_operand (operands[3], VNx64QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB)")
  (-1 "reload_completed
   && riscv_split_64bit_move_p (operands[0], operands[1])")
  (-1 "(!SMALL_OPERAND (INTVAL (operands[3]))) && (TARGET_64BIT)")
  (-1 "TARGET_ZBB || TARGET_ZBKB")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))) && (TARGET_MIN_VLEN > 32)")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && ( register_operand (operands[0], VNx16SFmode)
   && register_operand (operands[3], VNx16SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_VECTOR) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((TARGET_64BIT) && (TARGET_HARD_FLOAT || TARGET_ZFINX))")
  (-1 "((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (HFmode)) && (TARGET_ZFH || TARGET_ZHINX)")
  (-1 "(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_64)")
  (-1 "((TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && ( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))")
  (-1 "(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_64)")
  (-1 "((TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_MIN_VLEN > 32)) && ( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_64)) && ( register_operand (operands[0], VNx4DFmode)
   && register_operand (operands[3], VNx4DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx4SImode)
   && register_operand (operands[3], VNx4SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && (TARGET_64BIT)")
  (-1 "(TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)")
  (-1 "TARGET_64BIT
   && INTVAL (operands[5]) < INTVAL (operands[2])
   && (REGNO (operands[3]) == REGNO (operands[4])
       || peep2_reg_dead_p (3, operands[3]))")
  (-1 "TARGET_64BIT")
  (-1 "(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && ( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))")
  (-1 "(register_operand (operands[3], DImode)
  && GET_MODE_BITSIZE (DImode) > GET_MODE_BITSIZE (Pmode)) && (TARGET_VECTOR_ELEN_64)")
  (-1 "(TARGET_ZICBOP) && (!TARGET_64BIT)")
  (-1 "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && (Pmode == SImode)")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1HImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "TARGET_DIV && TARGET_64BIT")
  (-1 "(TARGET_ZICBOM) && (!TARGET_64BIT)")
  (-1 "TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, true, SImode)")
  (-1 "TARGET_64BIT && TARGET_DOUBLE_FLOAT
   && (register_operand (operands[0], DFmode)
       || reg_or_0_operand (operands[1], DFmode))")
  (-1 "register_operand (operands[3], HImode)
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_64)) && ( register_operand (operands[0], VNx1DFmode)
   && register_operand (operands[3], VNx1DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode))) && (TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx1SImode)
   && register_operand (operands[3], VNx1SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "epilogue_completed")
  (-1 "(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, false, DImode)) && (TARGET_64BIT)")
  (0 "(TARGET_SFB_ALU) && (((((TARGET_64BIT) && (!TARGET_64BIT)) && (!TARGET_64BIT)) && (TARGET_64BIT)) && (TARGET_64BIT))")
  (-1 "TARGET_ZKNH && !TARGET_64BIT")
  (-1 "TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, true, SImode)")
  (-1 "(TARGET_64BIT && !TARGET_ZBA
   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)) && ( reload_completed)")
  (-1 "register_operand (operands[3], QImode)
  && GET_MODE_BITSIZE (QImode) > GET_MODE_BITSIZE (Pmode)")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx16QImode)
   && register_operand (operands[3], VNx16QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_VECTOR) && (((((Pmode == SImode) && (TARGET_MIN_VLEN > 32)) && (TARGET_MIN_VLEN > 32)) && (TARGET_MIN_VLEN > 32)) && (TARGET_MIN_VLEN > 32))")
  (-1 "(!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])) && ((TARGET_ZFHMIN) && (Pmode == SImode))")
  (-1 "(!TARGET_ZBB) && (TARGET_64BIT)")
  (-1 "((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && (!TARGET_64BIT)")
  (-1 "(TARGET_ZBKX) && (TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (Pmode == SImode))")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_64)")
  (-1 "(TARGET_VECTOR) && (((((Pmode == DImode) && (TARGET_MIN_VLEN > 32)) && (TARGET_MIN_VLEN > 32)) && (TARGET_MIN_VLEN > 32)) && (TARGET_MIN_VLEN > 32))")
  (-1 "TARGET_64BIT && !TARGET_ZBA
   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)")
  (-1 "TARGET_VECTOR && TARGET_MIN_VLEN == 32")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_ZFH || TARGET_ZHINX) && (Pmode == DImode))")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_64)")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)")
  (-1 "TARGET_XTHEADMAC")
  (-1 "(TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (SImode)) && (!TARGET_64BIT)")
  (-1 "!TARGET_HARD_FLOAT
   && (register_operand (operands[0], SFmode)
       || reg_or_0_operand (operands[1], SFmode))")
  (-1 "(riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)) && (Pmode == SImode)")
  (-1 "TARGET_ZBB")
  (-1 "(TARGET_SFB_ALU || TARGET_XTHEADCONDMOV) && (TARGET_64BIT)")
  (-1 "((TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && (Pmode == SImode))) && ( reload_completed)")
  (-1 "(TARGET_VECTOR) && ( register_operand (operands[0], VNx32BImode)
   && register_operand (operands[3], VNx32BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)")
  (-1 "TARGET_ATOMIC")
  (-1 "(TARGET_ZKSH) && (!TARGET_64BIT)")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx2SImode)
   && register_operand (operands[3], VNx2SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2]))")
  (-1 "(known_gt (GET_MODE_BITSIZE (HImode), GET_MODE_BITSIZE (Pmode))) && (TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_MIN_VLEN > 32) && (Pmode == SImode))")
  (-1 "(TARGET_ZMMUL || TARGET_MUL) && (TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (TARGET_64BIT))")
  (-1 "((TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)) && ( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)")
  (-1 "(TARGET_VECTOR) && (TARGET_MIN_VLEN == 32)")
  (-1 "(TARGET_ZBA) && (TARGET_64BIT)")
  (-1 "TARGET_64BIT && (INTVAL (operands[2]) & 0x1f) > 0")
  (-1 "(TARGET_VECTOR) && (TARGET_VECTOR_ELEN_FP_64)")
  (0 "((TARGET_64BIT) && (!TARGET_64BIT)) && (!TARGET_64BIT)")
  (-1 "(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (Pmode == SImode)")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((TARGET_64BIT) && (TARGET_ZFH || TARGET_ZHINX))")
  (-1 "(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && (!TARGET_64BIT)")
  (-1 "(TARGET_VECTOR) && ( register_operand (operands[0], VNx16BImode)
   && register_operand (operands[3], VNx16BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)")
  (-1 "((!SMALL_OPERAND (INTVAL (operands[3]))) && (TARGET_64BIT)) && ( reload_completed)")
  (-1 "((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (DFmode)) && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)")
  (-1 "((TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (SFmode)) && (TARGET_HARD_FLOAT || TARGET_ZFINX)")
  (-1 "TARGET_64BIT && TARGET_ZBB")
  (-1 "USE_LOAD_ADDRESS_MACRO (operands[1])")
  (-1 "TARGET_ZBB || (!TARGET_64BIT && TARGET_XTHEADBB)")
  (-1 "(TARGET_VECTOR) && (TARGET_VECTOR_ELEN_64)")
  (-1 "known_gt (GET_MODE_BITSIZE (SImode), GET_MODE_BITSIZE (Pmode))")
  (-1 "(!TARGET_64BIT && TARGET_ZBB) || TARGET_XTHEADBB")
  (-1 "TARGET_ZBS")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_MIN_VLEN > 32)) && ( register_operand (operands[0], VNx16SImode)
   && register_operand (operands[3], VNx16SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(USE_LOAD_ADDRESS_MACRO (operands[1])) && (TARGET_64BIT)")
  (-1 "((TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_64)) && ( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))")
  (0 "(TARGET_64BIT) && (!TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)) && ((TARGET_ZFH || TARGET_ZHINX) && (Pmode == DImode))")
  (-1 "(!(p2m1_shift_operand (operands[1], DImode)
     || high_mask_shift_operand (operands[1], DImode))) && (TARGET_64BIT)")
  (-1 "(TARGET_64BIT && TARGET_ZBA
   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
   && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2]))) && ( reload_completed)")
  (-1 "(TARGET_64BIT && TARGET_ZBS
   && clz_hwi (~UINTVAL (operands[2])) > 33) && ( reload_completed)")
  (-1 "(TARGET_XTHEADBB) && (TARGET_64BIT)")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_64)) && ( register_operand (operands[0], VNx8DFmode)
   && register_operand (operands[3], VNx8DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx4QImode)
   && register_operand (operands[3], VNx4QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "TARGET_ZBKB && TARGET_64BIT")
  (-1 "(TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && (TARGET_64BIT)")
  (-1 "Pmode == SImode")
  (-1 "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_ZKNH) && (!TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (Pmode == DImode))")
  (-1 "((!SMALL_OPERAND (INTVAL (operands[3]))) && (!TARGET_64BIT)) && ( reload_completed)")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx64QImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_MIN_VLEN > 32)")
  (-1 "((TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_64)) && ( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx2QImode)
   && register_operand (operands[3], VNx2QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "((TARGET_ZBS && TARGET_ZBB) && (!TARGET_64BIT)) && ( reload_completed)")
  (-1 "TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])")
  (-1 "SIBLING_CALL_P (insn)")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx16HImode)
   && register_operand (operands[3], VNx16HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_VECTOR && (lra_in_progress || reload_completed)) && (Pmode == DImode)")
  (-1 "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC")
  (-1 "TARGET_ZFHMIN || TARGET_ZHINXMIN")
  (-1 "TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, false, SImode)")
  (-1 "(TARGET_HARD_FLOAT  || TARGET_ZFINX) && (TARGET_ZFH || TARGET_ZHINX)")
  (-1 "known_gt (GET_MODE_BITSIZE (QImode), GET_MODE_BITSIZE (Pmode))")
  (-1 "((TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_FP_32)) && ( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))")
  (-1 "(TARGET_VECTOR) && (TARGET_64BIT && TARGET_MIN_VLEN > 32)")
  (-1 "TARGET_ZFHMIN
   && (register_operand (operands[0], HFmode)
       || reg_or_0_operand (operands[1], HFmode))")
  (-1 "(TARGET_64BIT && (INTVAL (operands[3]) > 0)
    && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))")
  (-1 "(TARGET_ZBKC) && (!TARGET_64BIT)")
  (-1 "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16HImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
   == GET_MODE_BITSIZE (SImode)-1")
  (-1 "(TARGET_XTHEADCONDMOV) && (TARGET_64BIT)")
  (-1 "TARGET_ZKNE && TARGET_64BIT")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)")
  (-1 "(TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32) && (Pmode == DImode))")
  (-1 "(known_gt (GET_MODE_BITSIZE (DImode), GET_MODE_BITSIZE (Pmode))) && (TARGET_VECTOR_ELEN_64)")
  (-1 "!TARGET_64BIT")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_32)) && ( register_operand (operands[0], VNx4SFmode)
   && register_operand (operands[3], VNx4SFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "((TARGET_VECTOR) && (Pmode == DImode)) && ( epilogue_completed)")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1QImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(register_operand (operands[3], SImode)
  && GET_MODE_BITSIZE (SImode) > GET_MODE_BITSIZE (Pmode)) && (TARGET_MIN_VLEN > 32)")
  (-1 "(!SMALL_OPERAND (INTVAL (operands[3]))) && (!TARGET_64BIT)")
  (-1 "TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx2QImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_ZFH || TARGET_ZHINX) && (Pmode == SImode))")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx8QImode)
   && register_operand (operands[3], VNx8QImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "((INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
   == GET_MODE_BITSIZE (SImode)-1) && ( 1)")
  (-1 "(!TARGET_ZBB) && ( reload_completed
   && REG_P (operands[1])
   && !paradoxical_subreg_p (operands[0]))")
  (-1 "TARGET_VECTOR && TARGET_MIN_VLEN > 32")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx8SImode)
   && register_operand (operands[3], VNx8SImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_MIN_VLEN > 32)) && ( register_operand (operands[0], VNx32HImode)
   && register_operand (operands[3], VNx32HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx4HImode)
   && register_operand (operands[3], VNx4HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_FP_64)) && ( register_operand (operands[0], VNx2DFmode)
   && register_operand (operands[3], VNx2DFmode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(register_operand (operands[3], HImode)
  && GET_MODE_BITSIZE (HImode) > GET_MODE_BITSIZE (Pmode)) && (TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_VECTOR) && ( register_operand (operands[0], VNx8BImode)
   && register_operand (operands[3], VNx8BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx16SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32)")
  (-1 "(TARGET_ZBB) && (!TARGET_64BIT)")
  (-1 "((TARGET_VECTOR
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_64)) && ( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))")
  (-1 "((TARGET_VECTOR) && (TARGET_VECTOR_ELEN_FP_64)) && ( reload_completed)")
  (-1 "((TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_MIN_VLEN > 32)) && ( reload_completed
   && !rtx_equal_p (operands[0], operands[5]))")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx16QImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && ( register_operand (operands[0], VNx2HImode)
   && register_operand (operands[3], VNx2HImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "(TARGET_ZBKX) && (!TARGET_64BIT)")
  (-1 "(USE_LOAD_ADDRESS_MACRO (operands[0])) && (Pmode == DImode)")
  (-1 "(TARGET_VECTOR) && ( register_operand (operands[0], VNx2BImode)
   && register_operand (operands[3], VNx2BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)")
  (-1 "((TARGET_VECTOR) && (TARGET_MIN_VLEN > 32)) && ( register_operand (operands[0], VNx64BImode)
   && register_operand (operands[3], VNx64BImode)
   && INTVAL (operands[5]) == riscv_vector::VLMAX)")
  (-1 "TARGET_XTHEADBB && (TARGET_64BIT || SImode == SImode)")
  (-1 "(TARGET_ZBKB) && (!TARGET_64BIT)")
  (-1 "(TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) ||
   (TARGET_ZHINXMIN && TARGET_ZDINX)")
  (-1 "(TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)) && (TARGET_64BIT)")
  (-1 "(register_operand (operands[0], HImode)
    || reg_or_0_operand (operands[1], HImode))")
  (-1 "(((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && (TARGET_64BIT)) && ( reload_completed)")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "(TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
   && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)) && ((TARGET_ZFH || TARGET_ZHINX) && (Pmode == SImode))")
  (-1 "((TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
   || CONST_VECTOR_P (operands[1]))) && (TARGET_VECTOR_ELEN_64)) && ( register_operand (operands[0], VNx4DImode)
   && register_operand (operands[3], VNx4DImode)
   && satisfies_constraint_vu (operands[2])
   && INTVAL (operands[7]) == riscv_vector::VLMAX)")
  (-1 "TARGET_XTHEADBB")
  (-1 "(TARGET_XTHEADMEMPAIR && reload_completed
   && th_mempair_operands_p (operands, false, DImode)) && (TARGET_64BIT)")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx2SImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_ZICBOZ) && (!TARGET_64BIT)")
  (-1 "((TARGET_VECTOR && (lra_in_progress || reload_completed)) && ((TARGET_MIN_VLEN > 32) && (Pmode == DImode))) && ( reload_completed)")
  (-1 "(TARGET_ZICBOP) && (TARGET_64BIT)")
  (-1 "(TARGET_XTHEADMEMPAIR
  && th_mempair_operands_p (operands, true, DImode)) && (TARGET_64BIT)")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4SImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(TARGET_ZBB || TARGET_ZBKB) && (!TARGET_64BIT)")
  (-1 "(((INTVAL (operands[3]) >= 0 || !partial_subreg_p (operands[2]))
    && popcount_hwi (INTVAL (operands[3])) > 1
    && !SMALL_OPERAND (INTVAL (operands[3]))) && (!TARGET_64BIT)) && ( reload_completed)")
  (-1 "(TARGET_VECTOR
   && !rtx_equal_p (operands[2], operands[5])
   && !rtx_equal_p (operands[3], operands[5])
   && !rtx_equal_p (operands[4], operands[5])) && (TARGET_VECTOR_ELEN_64)")
  (-1 "((TARGET_ZBS && !paradoxical_subreg_p (operands[1])) && (!TARGET_64BIT)) && ( reload_completed)")
  (-1 "TARGET_ZKNH && TARGET_64BIT")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4QImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "(register_operand (operands[0], QImode)
    || reg_or_0_operand (operands[1], QImode))")
  (-1 "!TARGET_ZFHMIN
   && (register_operand (operands[0], HFmode)
       || reg_or_0_operand (operands[1], HFmode))")
  (-1 "(TARGET_XTHEADMAC) && (!TARGET_64BIT)")
  (-1 "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ((TARGET_ZFH || TARGET_ZHINX) && (TARGET_64BIT))")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx1DFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_64)")
  (-1 "(TARGET_ATOMIC) && (TARGET_64BIT)")
  (-1 "((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && (TARGET_HARD_FLOAT || TARGET_ZFINX)")
  (-1 "(TARGET_VECTOR && known_le (GET_MODE_SIZE (VNx4DImode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_64)")
  (-1 "((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) && (TARGET_ZFH || TARGET_ZHINX)")
  (-1 "(TARGET_XTHEADBB) && (!TARGET_64BIT)")
  (-1 "TARGET_ZKND && !TARGET_64BIT")
  (-1 "TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx4HImode), BYTES_PER_RISCV_VECTOR)")
  (-1 "TARGET_ZICBOP")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx1SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "(TARGET_VECTOR && known_gt (GET_MODE_SIZE (VNx8SFmode), BYTES_PER_RISCV_VECTOR)) && (TARGET_VECTOR_ELEN_FP_32)")
  (-1 "(TARGET_XTHEADMAC) && (TARGET_64BIT)")
  (-1 "(TARGET_ZKNH) && (TARGET_64BIT)")
])
