/* Generated automatically by the program `genoutput'
   from the machine description file `md'.  */

#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "backend.h"
#include "predict.h"
#include "tree.h"
#include "rtl.h"
#include "flags.h"
#include "alias.h"
#include "varasm.h"
#include "stor-layout.h"
#include "calls.h"
#include "insn-config.h"
#include "expmed.h"
#include "dojump.h"
#include "explow.h"
#include "memmodel.h"
#include "emit-rtl.h"
#include "stmt.h"
#include "expr.h"
#include "insn-codes.h"
#include "tm_p.h"
#include "regs.h"
#include "conditions.h"
#include "insn-attr.h"

#include "recog.h"

#include "diagnostic-core.h"
#include "output.h"
#include "target.h"
#include "tm-constrs.h"

static const char *
output_47 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1089 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
    return "fsqrt.s\t%0,%1";
}
}

static const char *
output_48 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1089 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
    return "fsqrt.d\t%0,%1";
}
}

static const char *
output_49 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1089 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
    return "fsqrt.h\t%0,%1";
}
}

static const char * const output_110[] = {
  "#",
  "lwu\t%0,%1",
};

static const char * const output_111[] = {
  "#",
  "lhu\t%0,%1",
};

static const char * const output_112[] = {
  "#",
  "lhu\t%0,%1",
};

static const char * const output_113[] = {
  "andi\t%0,%1,0xff",
  "lbu\t%0,%1",
};

static const char * const output_114[] = {
  "andi\t%0,%1,0xff",
  "lbu\t%0,%1",
};

static const char * const output_115[] = {
  "andi\t%0,%1,0xff",
  "lbu\t%0,%1",
};

static const char * const output_116[] = {
  "sext.w\t%0,%1",
  "lw\t%0,%1",
};

static const char * const output_117[] = {
  "#",
  "lb\t%0,%1",
};

static const char * const output_118[] = {
  "#",
  "lb\t%0,%1",
};

static const char * const output_119[] = {
  "#",
  "lb\t%0,%1",
};

static const char * const output_120[] = {
  "#",
  "lh\t%0,%1",
};

static const char * const output_121[] = {
  "#",
  "lh\t%0,%1",
};

static const char * const output_122[] = {
  "#",
  "lh\t%0,%1",
};

static const char *
output_126 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1516 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ return riscv_output_move (operands[0], operands[1]); }
}

static const char *
output_127 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1526 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ return riscv_output_move (operands[0], operands[1]); }
}

static const char *
output_178 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1722 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ return riscv_output_move (operands[0], operands[1]); }
}

static const char *
output_179 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1733 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ return riscv_output_move (operands[0], operands[1]); }
}

static const char *
output_180 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1756 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ return riscv_output_move (operands[0], operands[1]); }
}

static const char *
output_181 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1782 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ return riscv_output_move (operands[0], operands[1]); }
}

static const char *
output_186 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1825 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ return riscv_output_move (operands[0], operands[1]); }
}

static const char *
output_187 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1847 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ return riscv_output_move (operands[0], operands[1]); }
}

static const char *
output_188 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1857 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ return riscv_output_move (operands[0], operands[1]); }
}

static const char *
output_189 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1881 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ return riscv_output_move (operands[0], operands[1]); }
}

static const char *
output_190 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1891 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ return riscv_output_move (operands[0], operands[1]); }
}

static const char *
output_191 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1901 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{ return riscv_output_move (operands[0], operands[1]); }
}

static const char *
output_195 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1980 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = GEN_INT (INTVAL (operands[2])
			   & (GET_MODE_BITSIZE (SImode) - 1));

  return "sll%i2%~\t%0,%1,%2";
}
}

static const char *
output_196 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1980 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = GEN_INT (INTVAL (operands[2])
			   & (GET_MODE_BITSIZE (SImode) - 1));

  return "sra%i2%~\t%0,%1,%2";
}
}

static const char *
output_197 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 1980 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = GEN_INT (INTVAL (operands[2])
			   & (GET_MODE_BITSIZE (SImode) - 1));

  return "srl%i2%~\t%0,%1,%2";
}
}

static const char *
output_204 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2035 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = GEN_INT (INTVAL (operands[2])
			   & (GET_MODE_BITSIZE (DImode) - 1));

  return "sll%i2\t%0,%1,%2";
}
}

static const char *
output_205 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2035 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = GEN_INT (INTVAL (operands[2])
			   & (GET_MODE_BITSIZE (DImode) - 1));

  return "sra%i2\t%0,%1,%2";
}
}

static const char *
output_206 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2035 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = GEN_INT (INTVAL (operands[2])
			   & (GET_MODE_BITSIZE (DImode) - 1));

  return "srl%i2\t%0,%1,%2";
}
}

static const char *
output_213 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2091 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);

  return "sll%i2w\t%0,%1,%2";
}
}

static const char *
output_214 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2091 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);

  return "sra%i2w\t%0,%1,%2";
}
}

static const char *
output_215 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2091 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);

  return "srl%i2w\t%0,%1,%2";
}
}

static const char *
output_222 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2152 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);

  return "srliw\t%0,%1,%2";
}
}

static const char *
output_223 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2168 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  return "srliw\t%0,%1,%3";
}
}

static const char *
output_224 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2181 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  return "srliw\t%0,%1,31";
}
}

static const char * const output_243[] = {
  "b%C5\t%1,%z2,1f\t# movcc\n\tmv\t%0,%z4\n1:",
  "b%C5\t%1,%z2,1f\t# movcc\n\tli\t%0,%4\n1:",
};

static const char * const output_244[] = {
  "b%C5\t%1,%z2,1f\t# movcc\n\tmv\t%0,%z4\n1:",
  "b%C5\t%1,%z2,1f\t# movcc\n\tli\t%0,%4\n1:",
};

static const char * const output_245[] = {
  "b%C5\t%1,%z2,1f\t# movcc\n\tmv\t%0,%z4\n1:",
  "b%C5\t%1,%z2,1f\t# movcc\n\tli\t%0,%4\n1:",
};

static const char *
output_280 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2596 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
  return "slt%i2\t%0,%1,%2";
}
}

static const char *
output_281 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2596 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
  return "slt%i2u\t%0,%1,%2";
}
}

static const char *
output_282 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2596 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
  return "slt%i2\t%0,%1,%2";
}
}

static const char *
output_283 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2596 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
  return "slt%i2u\t%0,%1,%2";
}
}

static const char *
output_284 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2596 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
  return "slt%i2\t%0,%1,%2";
}
}

static const char *
output_285 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2596 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
  return "slt%i2u\t%0,%1,%2";
}
}

static const char *
output_292 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 2718 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  return riscv_output_return ();
}
}

static const char * const output_297[] = {
  "jr\t%0",
  "tail\t%0",
  "tail\t%0@plt",
};

static const char * const output_298[] = {
  "jr\t%1",
  "tail\t%1",
  "tail\t%1@plt",
};

static const char * const output_299[] = {
  "jalr\t%0",
  "call\t%0",
  "call\t%0@plt",
};

static const char * const output_300[] = {
  "jalr\t%1",
  "call\t%1",
  "call\t%1@plt",
};

static const char *
output_328 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 3118 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md"
{
  switch (INTVAL (operands[1]))
  {
    case 0: return "prefetch.r\t%a0";
    case 1: return "prefetch.w\t%a0";
    default: gcc_unreachable ();
  }
}
}

static const char * const output_331[] = {
  "zext.w\t%0,%1",
  "lwu\t%0,%1",
};

static const char * const output_353[] = {
  "zext.h\t%0,%1",
  "lhu\t%0,%1",
};

static const char * const output_354[] = {
  "zext.h\t%0,%1",
  "lhu\t%0,%1",
};

static const char * const output_355[] = {
  "sext.b\t%0,%1",
  "lb\t%0,%1",
};

static const char * const output_356[] = {
  "sext.b\t%0,%1",
  "lb\t%0,%1",
};

static const char * const output_357[] = {
  "sext.b\t%0,%1",
  "lb\t%0,%1",
};

static const char * const output_358[] = {
  "sext.h\t%0,%1",
  "lh\t%0,%1",
};

static const char * const output_359[] = {
  "sext.h\t%0,%1",
  "lh\t%0,%1",
};

static const char * const output_360[] = {
  "sext.h\t%0,%1",
  "lh\t%0,%1",
};

static const char * const output_361[] = {
  "zext.h\t%0,%1",
  "lhu\t%0,%1",
};

static const char * const output_362[] = {
  "zext.h\t%0,%1",
  "lhu\t%0,%1",
};

static const char *
output_477 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 54 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    enum memmodel model = (enum memmodel) INTVAL (operands[1]);
    model = memmodel_base (model);
    if (model == MEMMODEL_SEQ_CST)
	return "fence\trw,rw";
    else if (model == MEMMODEL_ACQ_REL)
	return "fence.tso";
    else if (model == MEMMODEL_ACQUIRE)
	return "fence\tr,rw";
    else if (model == MEMMODEL_RELEASE)
	return "fence\trw,w";
    else
	gcc_unreachable ();
  }
}

static const char *
output_478 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 79 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    enum memmodel model = (enum memmodel) INTVAL (operands[2]);
    model = memmodel_base (model);

    if (model == MEMMODEL_SEQ_CST)
      return "fence\trw,rw\n\t"
	     "lw\t%0,%1\n\t"
	     "fence\tr,rw";
    if (model == MEMMODEL_ACQUIRE)
      return "lw\t%0,%1\n\t"
	     "fence\tr,rw";
    else
      return "lw\t%0,%1";
  }
}

static const char *
output_479 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 79 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    enum memmodel model = (enum memmodel) INTVAL (operands[2]);
    model = memmodel_base (model);

    if (model == MEMMODEL_SEQ_CST)
      return "fence\trw,rw\n\t"
	     "ld\t%0,%1\n\t"
	     "fence\tr,rw";
    if (model == MEMMODEL_ACQUIRE)
      return "ld\t%0,%1\n\t"
	     "fence\tr,rw";
    else
      return "ld\t%0,%1";
  }
}

static const char *
output_480 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 105 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    enum memmodel model = (enum memmodel) INTVAL (operands[2]);
    model = memmodel_base (model);

    if (model == MEMMODEL_SEQ_CST)
      return "fence\trw,w\n\t"
	     "sw\t%z1,%0\n\t"
	     "fence\trw,rw";
    if (model == MEMMODEL_RELEASE)
      return "fence\trw,w\n\t"
	     "sw\t%z1,%0";
    else
      return "sw\t%z1,%0";
  }
}

static const char *
output_481 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 105 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    enum memmodel model = (enum memmodel) INTVAL (operands[2]);
    model = memmodel_base (model);

    if (model == MEMMODEL_SEQ_CST)
      return "fence\trw,w\n\t"
	     "sd\t%z1,%0\n\t"
	     "fence\trw,rw";
    if (model == MEMMODEL_RELEASE)
      return "fence\trw,w\n\t"
	     "sd\t%z1,%0";
    else
      return "sd\t%z1,%0";
  }
}

static const char *
output_498 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 162 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    return "1:\n\t"
	   "lr.w%I3\t%0, %1\n\t"
	   "add\t%6, %0, %2\n\t"
	   "and\t%6, %6, %4\n\t"
	   "and\t%7, %0, %5\n\t"
	   "or\t%7, %7, %6\n\t"
	   "sc.w%J3\t%6, %7, %1\n\t"
	   "bnez\t%6, 1b";
  }
}

static const char *
output_499 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 162 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    return "1:\n\t"
	   "lr.w%I3\t%0, %1\n\t"
	   "or\t%6, %0, %2\n\t"
	   "and\t%6, %6, %4\n\t"
	   "and\t%7, %0, %5\n\t"
	   "or\t%7, %7, %6\n\t"
	   "sc.w%J3\t%6, %7, %1\n\t"
	   "bnez\t%6, 1b";
  }
}

static const char *
output_500 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 162 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    return "1:\n\t"
	   "lr.w%I3\t%0, %1\n\t"
	   "xor\t%6, %0, %2\n\t"
	   "and\t%6, %6, %4\n\t"
	   "and\t%7, %0, %5\n\t"
	   "or\t%7, %7, %6\n\t"
	   "sc.w%J3\t%6, %7, %1\n\t"
	   "bnez\t%6, 1b";
  }
}

static const char *
output_501 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 162 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    return "1:\n\t"
	   "lr.w%I3\t%0, %1\n\t"
	   "and\t%6, %0, %2\n\t"
	   "and\t%6, %6, %4\n\t"
	   "and\t%7, %0, %5\n\t"
	   "or\t%7, %7, %6\n\t"
	   "sc.w%J3\t%6, %7, %1\n\t"
	   "bnez\t%6, 1b";
  }
}

static const char *
output_502 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 228 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    return "1:\n\t"
	   "lr.w%I3\t%0, %1\n\t"
	   "and\t%6, %0, %2\n\t"
	   "not\t%6, %6\n\t"
	   "and\t%6, %6, %4\n\t"
	   "and\t%7, %0, %5\n\t"
	   "or\t%7, %7, %6\n\t"
	   "sc.w%J3\t%6, %7, %1\n\t"
	   "bnez\t%6, 1b";
  }
}

static const char *
output_505 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 338 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    return "1:\n\t"
	   "lr.w%I3\t%0, %1\n\t"
	   "and\t%5, %0, %4\n\t"
	   "or\t%5, %5, %2\n\t"
	   "sc.w%J3\t%5, %5, %1\n\t"
	   "bnez\t%5, 1b";
  }
}

static const char *
output_506 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 359 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    enum memmodel model_success = (enum memmodel) INTVAL (operands[4]);
    enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]);
    /* Find the union of the two memory models so we can satisfy both success
       and failure memory models.  */
    operands[5] = GEN_INT (riscv_union_memmodels (model_success, model_failure));
    return "1:\n\t"
	   "lr.w%I5\t%0,%1\n\t"
	   "bne\t%0,%z2,1f\n\t"
	   "sc.w%J5\t%6,%z3,%1\n\t"
	   "bnez\t%6,1b\n\t"
	   "1:";
  }
}

static const char *
output_507 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 359 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    enum memmodel model_success = (enum memmodel) INTVAL (operands[4]);
    enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]);
    /* Find the union of the two memory models so we can satisfy both success
       and failure memory models.  */
    operands[5] = GEN_INT (riscv_union_memmodels (model_success, model_failure));
    return "1:\n\t"
	   "lr.d%I5\t%0,%1\n\t"
	   "bne\t%0,%z2,1f\n\t"
	   "sc.d%J5\t%6,%z3,%1\n\t"
	   "bnez\t%6,1b\n\t"
	   "1:";
  }
}

static const char *
output_508 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 531 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md"
{
    return "1:\n\t"
	   "lr.w%I4\t%0, %1\n\t"
	   "and\t%7, %0, %5\n\t"
	   "bne\t%7, %z2, 1f\n\t"
	   "and\t%7, %0, %6\n\t"
	   "or\t%7, %7, %3\n\t"
	   "sc.w%J4\t%7, %7, %1\n\t"
	   "bnez\t%7, 1b\n\t"
	   "1:";
  }
}

static const char * const output_531[] = {
  "flw\t%0,%1,%2",
  "lw\t%0,%1",
};

static const char * const output_532[] = {
  "fld\t%0,%1,%2",
  "ld\t%0,%1",
};

static const char * const output_533[] = {
  "flh\t%0,%1,%2",
  "lh\t%0,%1",
};

static const char * const output_534[] = {
  "flw\t%0,%1,%2",
  "lw\t%0,%1",
};

static const char * const output_535[] = {
  "fld\t%0,%1,%2",
  "ld\t%0,%1",
};

static const char * const output_536[] = {
  "flh\t%0,%1,%2",
  "lh\t%0,%1",
};

static const char * const output_554[] = {
  "fsw\t%1,%0,%2",
  "sw\t%1,%0,%2",
};

static const char * const output_555[] = {
  "fsd\t%1,%0,%2",
  "sd\t%1,%0,%2",
};

static const char * const output_556[] = {
  "fsh\t%1,%0,%2",
  "sh\t%1,%0,%2",
};

static const char * const output_557[] = {
  "fsw\t%1,%0,%2",
  "sw\t%1,%0,%2",
};

static const char * const output_558[] = {
  "fsd\t%1,%0,%2",
  "sd\t%1,%0,%2",
};

static const char * const output_559[] = {
  "fsh\t%1,%0,%2",
  "sh\t%1,%0,%2",
};

static const char *
output_574 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 40 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{
    bool wform = TARGET_64BIT && (SImode == SImode);
    operands[2] = GEN_INT (INTVAL (operands[2])
                  & (GET_MODE_BITSIZE (SImode) - 1));
    return wform ? "th.srriw\t%0,%1,%2" : "th.srri\t%0,%1,%2";
  }
}

static const char *
output_575 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 40 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{
    bool wform = TARGET_64BIT && (DImode == SImode);
    operands[2] = GEN_INT (INTVAL (operands[2])
                  & (GET_MODE_BITSIZE (DImode) - 1));
    return wform ? "th.srriw\t%0,%1,%2" : "th.srri\t%0,%1,%2";
  }
}

static const char *
output_576 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 55 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{
  operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]) - 1);
  return "th.ext\t%0,%1,%2,%3";
}
}

static const char *
output_577 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 55 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{
  operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]) - 1);
  return "th.ext\t%0,%1,%2,%3";
}
}

static const char *
output_578 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{
  operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]) - 1);
  return "th.extu\t%0,%1,%2,%3";
}
}

static const char *
output_579 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 68 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{
  operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]) - 1);
  return "th.extu\t%0,%1,%2,%3";
}
}

static const char *
output_582 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{
    bool wform = TARGET_64BIT && (SImode == SImode);
    return wform ? "th.revw\t%0,%1" : "th.rev\t%0,%1";
  }
}

static const char *
output_583 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 87 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{
    bool wform = TARGET_64BIT && (DImode == SImode);
    return wform ? "th.revw\t%0,%1" : "th.rev\t%0,%1";
  }
}

static const char *
output_586 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{
  if (which_alternative == 0)
    return "th.mv%C4z\t%0,%z2,%1";

  /* Invert the condition and take else-block.  */
  rtx_code code = GET_CODE (operands[4]);
  code = (code == EQ) ? NE : EQ;
  operands[4] = gen_rtx_fmt_ee (code, VOIDmode, const0_rtx, const0_rtx);
  return "th.mv%C4z\t%0,%z3,%1";
}
}

static const char *
output_587 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{
  if (which_alternative == 0)
    return "th.mv%C4z\t%0,%z2,%1";

  /* Invert the condition and take else-block.  */
  rtx_code code = GET_CODE (operands[4]);
  code = (code == EQ) ? NE : EQ;
  operands[4] = gen_rtx_fmt_ee (code, VOIDmode, const0_rtx, const0_rtx);
  return "th.mv%C4z\t%0,%z3,%1";
}
}

static const char *
output_588 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{
  if (which_alternative == 0)
    return "th.mv%C4z\t%0,%z2,%1";

  /* Invert the condition and take else-block.  */
  rtx_code code = GET_CODE (operands[4]);
  code = (code == EQ) ? NE : EQ;
  operands[4] = gen_rtx_fmt_ee (code, VOIDmode, const0_rtx, const0_rtx);
  return "th.mv%C4z\t%0,%z3,%1";
}
}

static const char *
output_589 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 116 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{
  if (which_alternative == 0)
    return "th.mv%C4z\t%0,%z2,%1";

  /* Invert the condition and take else-block.  */
  rtx_code code = GET_CODE (operands[4]);
  code = (code == EQ) ? NE : EQ;
  operands[4] = gen_rtx_fmt_ee (code, VOIDmode, const0_rtx, const0_rtx);
  return "th.mv%C4z\t%0,%z3,%1";
}
}

static const char * const output_590[] = {
  "th.mvnez\t%0,%z2,%1",
  "th.mveqz\t%0,%z3,%1",
};

static const char * const output_591[] = {
  "th.mvnez\t%0,%z2,%1",
  "th.mveqz\t%0,%z3,%1",
};

static const char * const output_592[] = {
  "th.mvnez\t%0,%z2,%1",
  "th.mveqz\t%0,%z3,%1",
};

static const char * const output_593[] = {
  "th.mvnez\t%0,%z2,%1",
  "th.mveqz\t%0,%z3,%1",
};

static const char *
output_609 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 306 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{ return th_mempair_output_move (operands, true, SImode, UNKNOWN); }
}

static const char *
output_610 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 306 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{ return th_mempair_output_move (operands, true, DImode, UNKNOWN); }
}

static const char *
output_611 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 318 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{ return th_mempair_output_move (operands, false, SImode, UNKNOWN); }
}

static const char *
output_612 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 318 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{ return th_mempair_output_move (operands, false, DImode, UNKNOWN); }
}

static const char *
output_613 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 330 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{ return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); }
}

static const char *
output_614 (rtx *operands ATTRIBUTE_UNUSED, rtx_insn *insn ATTRIBUTE_UNUSED)
{
#line 343 "../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md"
{ return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); }
}

static const char * const output_723[] = {
  "vl%m1re8.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_724[] = {
  "vl%m1re8.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_725[] = {
  "vl%m1re8.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_726[] = {
  "vl%m1re8.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_727[] = {
  "vl%m1re8.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_728[] = {
  "vl%m1re16.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_729[] = {
  "vl%m1re16.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_730[] = {
  "vl%m1re16.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_731[] = {
  "vl%m1re16.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_732[] = {
  "vl%m1re16.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_733[] = {
  "vl%m1re32.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_734[] = {
  "vl%m1re32.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_735[] = {
  "vl%m1re32.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_736[] = {
  "vl%m1re32.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_737[] = {
  "vl%m1re32.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_738[] = {
  "vl%m1re64.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_739[] = {
  "vl%m1re64.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_740[] = {
  "vl%m1re64.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_741[] = {
  "vl%m1re64.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_742[] = {
  "vl%m1re32.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_743[] = {
  "vl%m1re32.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_744[] = {
  "vl%m1re32.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_745[] = {
  "vl%m1re32.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_746[] = {
  "vl%m1re32.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_747[] = {
  "vl%m1re64.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_748[] = {
  "vl%m1re64.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_749[] = {
  "vl%m1re64.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_750[] = {
  "vl%m1re64.v\t%0,%1",
  "vs%m1r.v\t%1,%0",
  "vmv%m1r.v\t%0,%1",
};

static const char * const output_800[] = {
  "vle8.v\t%0,%3%p1",
  "vle8.v\t%0,%3",
  "vle8.v\t%0,%3,%1.t",
  "vse8.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_801[] = {
  "vle8.v\t%0,%3%p1",
  "vle8.v\t%0,%3",
  "vle8.v\t%0,%3,%1.t",
  "vse8.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_802[] = {
  "vle8.v\t%0,%3%p1",
  "vle8.v\t%0,%3",
  "vle8.v\t%0,%3,%1.t",
  "vse8.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_803[] = {
  "vle8.v\t%0,%3%p1",
  "vle8.v\t%0,%3",
  "vle8.v\t%0,%3,%1.t",
  "vse8.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_804[] = {
  "vle8.v\t%0,%3%p1",
  "vle8.v\t%0,%3",
  "vle8.v\t%0,%3,%1.t",
  "vse8.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_805[] = {
  "vle8.v\t%0,%3%p1",
  "vle8.v\t%0,%3",
  "vle8.v\t%0,%3,%1.t",
  "vse8.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_806[] = {
  "vle8.v\t%0,%3%p1",
  "vle8.v\t%0,%3",
  "vle8.v\t%0,%3,%1.t",
  "vse8.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_807[] = {
  "vle16.v\t%0,%3%p1",
  "vle16.v\t%0,%3",
  "vle16.v\t%0,%3,%1.t",
  "vse16.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_808[] = {
  "vle16.v\t%0,%3%p1",
  "vle16.v\t%0,%3",
  "vle16.v\t%0,%3,%1.t",
  "vse16.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_809[] = {
  "vle16.v\t%0,%3%p1",
  "vle16.v\t%0,%3",
  "vle16.v\t%0,%3,%1.t",
  "vse16.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_810[] = {
  "vle16.v\t%0,%3%p1",
  "vle16.v\t%0,%3",
  "vle16.v\t%0,%3,%1.t",
  "vse16.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_811[] = {
  "vle16.v\t%0,%3%p1",
  "vle16.v\t%0,%3",
  "vle16.v\t%0,%3,%1.t",
  "vse16.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_812[] = {
  "vle16.v\t%0,%3%p1",
  "vle16.v\t%0,%3",
  "vle16.v\t%0,%3,%1.t",
  "vse16.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_813[] = {
  "vle32.v\t%0,%3%p1",
  "vle32.v\t%0,%3",
  "vle32.v\t%0,%3,%1.t",
  "vse32.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_814[] = {
  "vle32.v\t%0,%3%p1",
  "vle32.v\t%0,%3",
  "vle32.v\t%0,%3,%1.t",
  "vse32.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_815[] = {
  "vle32.v\t%0,%3%p1",
  "vle32.v\t%0,%3",
  "vle32.v\t%0,%3,%1.t",
  "vse32.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_816[] = {
  "vle32.v\t%0,%3%p1",
  "vle32.v\t%0,%3",
  "vle32.v\t%0,%3,%1.t",
  "vse32.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_817[] = {
  "vle32.v\t%0,%3%p1",
  "vle32.v\t%0,%3",
  "vle32.v\t%0,%3,%1.t",
  "vse32.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_818[] = {
  "vle64.v\t%0,%3%p1",
  "vle64.v\t%0,%3",
  "vle64.v\t%0,%3,%1.t",
  "vse64.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_819[] = {
  "vle64.v\t%0,%3%p1",
  "vle64.v\t%0,%3",
  "vle64.v\t%0,%3,%1.t",
  "vse64.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_820[] = {
  "vle64.v\t%0,%3%p1",
  "vle64.v\t%0,%3",
  "vle64.v\t%0,%3,%1.t",
  "vse64.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_821[] = {
  "vle64.v\t%0,%3%p1",
  "vle64.v\t%0,%3",
  "vle64.v\t%0,%3,%1.t",
  "vse64.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_822[] = {
  "vle32.v\t%0,%3%p1",
  "vle32.v\t%0,%3",
  "vle32.v\t%0,%3,%1.t",
  "vse32.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_823[] = {
  "vle32.v\t%0,%3%p1",
  "vle32.v\t%0,%3",
  "vle32.v\t%0,%3,%1.t",
  "vse32.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_824[] = {
  "vle32.v\t%0,%3%p1",
  "vle32.v\t%0,%3",
  "vle32.v\t%0,%3,%1.t",
  "vse32.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_825[] = {
  "vle32.v\t%0,%3%p1",
  "vle32.v\t%0,%3",
  "vle32.v\t%0,%3,%1.t",
  "vse32.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_826[] = {
  "vle32.v\t%0,%3%p1",
  "vle32.v\t%0,%3",
  "vle32.v\t%0,%3,%1.t",
  "vse32.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_827[] = {
  "vle64.v\t%0,%3%p1",
  "vle64.v\t%0,%3",
  "vle64.v\t%0,%3,%1.t",
  "vse64.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_828[] = {
  "vle64.v\t%0,%3%p1",
  "vle64.v\t%0,%3",
  "vle64.v\t%0,%3,%1.t",
  "vse64.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_829[] = {
  "vle64.v\t%0,%3%p1",
  "vle64.v\t%0,%3",
  "vle64.v\t%0,%3,%1.t",
  "vse64.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_830[] = {
  "vle64.v\t%0,%3%p1",
  "vle64.v\t%0,%3",
  "vle64.v\t%0,%3,%1.t",
  "vse64.v\t%3,%0%p1",
  "vmv.v.v\t%0,%3",
  "vmv.v.v\t%0,%3",
  "vmv.v.i\t%0,%v3",
  "vmv.v.i\t%0,%v3",
};

static const char * const output_862[] = {
  "vlm.v\t%0,%3",
  "vsm.v\t%3,%0",
  "vmmv.m\t%0,%3",
  "vmclr.m\t%0",
  "vmset.m\t%0",
};

static const char * const output_863[] = {
  "vlm.v\t%0,%3",
  "vsm.v\t%3,%0",
  "vmmv.m\t%0,%3",
  "vmclr.m\t%0",
  "vmset.m\t%0",
};

static const char * const output_864[] = {
  "vlm.v\t%0,%3",
  "vsm.v\t%3,%0",
  "vmmv.m\t%0,%3",
  "vmclr.m\t%0",
  "vmset.m\t%0",
};

static const char * const output_865[] = {
  "vlm.v\t%0,%3",
  "vsm.v\t%3,%0",
  "vmmv.m\t%0,%3",
  "vmclr.m\t%0",
  "vmset.m\t%0",
};

static const char * const output_866[] = {
  "vlm.v\t%0,%3",
  "vsm.v\t%3,%0",
  "vmmv.m\t%0,%3",
  "vmclr.m\t%0",
  "vmset.m\t%0",
};

static const char * const output_867[] = {
  "vlm.v\t%0,%3",
  "vsm.v\t%3,%0",
  "vmmv.m\t%0,%3",
  "vmclr.m\t%0",
  "vmset.m\t%0",
};

static const char * const output_868[] = {
  "vlm.v\t%0,%3",
  "vsm.v\t%3,%0",
  "vmmv.m\t%0,%3",
  "vmclr.m\t%0",
  "vmset.m\t%0",
};

static const char * const output_933[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero",
  "vlse8.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_934[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero",
  "vlse8.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_935[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero",
  "vlse8.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_936[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero",
  "vlse8.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_937[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero",
  "vlse8.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_938[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero",
  "vlse8.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_939[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero,%1.t",
  "vlse8.v\t%0,%3,zero",
  "vlse8.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_940[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse16.v\t%0,%3,zero,%1.t",
  "vlse16.v\t%0,%3,zero,%1.t",
  "vlse16.v\t%0,%3,zero",
  "vlse16.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_941[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse16.v\t%0,%3,zero,%1.t",
  "vlse16.v\t%0,%3,zero,%1.t",
  "vlse16.v\t%0,%3,zero",
  "vlse16.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_942[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse16.v\t%0,%3,zero,%1.t",
  "vlse16.v\t%0,%3,zero,%1.t",
  "vlse16.v\t%0,%3,zero",
  "vlse16.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_943[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse16.v\t%0,%3,zero,%1.t",
  "vlse16.v\t%0,%3,zero,%1.t",
  "vlse16.v\t%0,%3,zero",
  "vlse16.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_944[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse16.v\t%0,%3,zero,%1.t",
  "vlse16.v\t%0,%3,zero,%1.t",
  "vlse16.v\t%0,%3,zero",
  "vlse16.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_945[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse16.v\t%0,%3,zero,%1.t",
  "vlse16.v\t%0,%3,zero,%1.t",
  "vlse16.v\t%0,%3,zero",
  "vlse16.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_946[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero",
  "vlse32.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_947[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero",
  "vlse32.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_948[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero",
  "vlse32.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_949[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero",
  "vlse32.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_950[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero",
  "vlse32.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_951[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero",
  "vlse64.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_952[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero",
  "vlse64.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_953[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero",
  "vlse64.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_954[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero",
  "vlse64.v\t%0,%3,zero",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_955[] = {
  "vfmv.v.f\t%0,%3",
  "vfmv.v.f\t%0,%3",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero",
  "vlse32.v\t%0,%3,zero",
  "vfmv.s.f\t%0,%3",
  "vfmv.s.f\t%0,%3",
};

static const char * const output_956[] = {
  "vfmv.v.f\t%0,%3",
  "vfmv.v.f\t%0,%3",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero",
  "vlse32.v\t%0,%3,zero",
  "vfmv.s.f\t%0,%3",
  "vfmv.s.f\t%0,%3",
};

static const char * const output_957[] = {
  "vfmv.v.f\t%0,%3",
  "vfmv.v.f\t%0,%3",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero",
  "vlse32.v\t%0,%3,zero",
  "vfmv.s.f\t%0,%3",
  "vfmv.s.f\t%0,%3",
};

static const char * const output_958[] = {
  "vfmv.v.f\t%0,%3",
  "vfmv.v.f\t%0,%3",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero",
  "vlse32.v\t%0,%3,zero",
  "vfmv.s.f\t%0,%3",
  "vfmv.s.f\t%0,%3",
};

static const char * const output_959[] = {
  "vfmv.v.f\t%0,%3",
  "vfmv.v.f\t%0,%3",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero,%1.t",
  "vlse32.v\t%0,%3,zero",
  "vlse32.v\t%0,%3,zero",
  "vfmv.s.f\t%0,%3",
  "vfmv.s.f\t%0,%3",
};

static const char * const output_960[] = {
  "vfmv.v.f\t%0,%3",
  "vfmv.v.f\t%0,%3",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero",
  "vlse64.v\t%0,%3,zero",
  "vfmv.s.f\t%0,%3",
  "vfmv.s.f\t%0,%3",
};

static const char * const output_961[] = {
  "vfmv.v.f\t%0,%3",
  "vfmv.v.f\t%0,%3",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero",
  "vlse64.v\t%0,%3,zero",
  "vfmv.s.f\t%0,%3",
  "vfmv.s.f\t%0,%3",
};

static const char * const output_962[] = {
  "vfmv.v.f\t%0,%3",
  "vfmv.v.f\t%0,%3",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero",
  "vlse64.v\t%0,%3,zero",
  "vfmv.s.f\t%0,%3",
  "vfmv.s.f\t%0,%3",
};

static const char * const output_963[] = {
  "vfmv.v.f\t%0,%3",
  "vfmv.v.f\t%0,%3",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero,%1.t",
  "vlse64.v\t%0,%3,zero",
  "vlse64.v\t%0,%3,zero",
  "vfmv.s.f\t%0,%3",
  "vfmv.s.f\t%0,%3",
};

static const char * const output_964[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_965[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_966[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_967[] = {
  "vmv.v.x\t%0,%3",
  "vmv.v.x\t%0,%3",
  "vmv.s.x\t%0,%3",
  "vmv.s.x\t%0,%3",
};

static const char * const output_1482[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1483[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1484[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1485[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1486[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1487[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1488[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1489[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1490[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1491[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1492[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1493[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1494[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1495[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1496[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1497[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1498[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1499[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1500[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1501[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1502[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1503[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1504[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1505[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1506[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1507[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1508[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1509[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1510[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1511[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1512[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1513[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1514[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1515[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1516[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1517[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1518[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1519[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1520[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1521[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1522[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1523[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1524[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1525[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1526[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1527[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1528[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1529[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1530[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1531[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1532[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1533[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1534[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1535[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1536[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1537[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1538[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1539[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1540[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1541[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1542[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1543[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1544[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1545[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1546[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1547[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1548[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1549[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1550[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1551[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1552[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1553[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1554[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1555[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1556[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1557[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1558[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1559[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1560[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1561[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1562[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1563[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1564[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1565[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1566[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1567[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1568[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1569[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1570[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1571[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1572[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1573[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1574[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1575[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1576[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1577[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1578[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1579[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1580[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1581[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1582[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1583[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1584[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1585[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1586[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1587[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1588[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1589[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1590[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1591[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1592[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1593[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1594[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1595[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1596[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1597[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1598[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1599[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1600[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1601[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1602[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1603[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1604[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1605[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1606[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1607[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1608[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1609[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1610[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1611[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1612[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1613[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1614[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1615[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1616[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1617[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1618[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1619[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1620[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1621[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1622[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1623[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1624[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1625[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1626[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1627[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1628[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1629[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1630[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1631[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1632[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1633[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1634[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1635[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1636[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1637[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1638[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1639[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1640[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1641[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1642[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1643[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1644[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1645[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1646[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1647[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1648[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1649[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1650[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1651[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1652[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1653[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1654[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1655[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1656[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1657[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1658[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1659[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1660[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1661[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1662[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1663[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1664[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1665[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1666[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1667[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1668[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1669[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1670[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1671[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1672[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1673[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1674[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1675[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1676[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1677[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1678[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1679[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1680[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1681[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1682[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1683[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1684[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1685[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1686[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1687[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1688[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1689[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1690[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1691[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1692[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1693[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1694[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1695[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1696[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1697[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1698[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1699[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1700[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1701[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1702[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1703[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1704[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1705[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1706[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1707[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1708[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1709[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1710[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1711[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1712[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1713[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1714[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1715[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1716[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1717[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1718[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1719[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1720[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1721[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1722[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1723[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1724[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1725[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1726[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1727[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1728[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1729[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1730[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1731[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1732[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1733[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1734[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1735[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1736[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1737[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1738[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1739[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1740[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1741[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1742[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1743[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1744[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1745[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1746[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1747[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1748[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1749[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1750[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1751[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1752[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1753[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1754[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1755[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1756[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1757[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1758[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1759[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1760[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1761[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1762[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1763[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1764[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1765[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1766[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1767[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1768[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1769[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1770[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1771[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1772[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1773[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1774[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1775[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1776[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1777[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1778[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1779[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1780[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1781[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1782[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1783[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1784[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1785[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1786[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1787[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1788[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1789[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1790[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1791[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1792[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1793[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1794[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1795[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1796[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1797[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1798[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1799[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1800[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1801[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1802[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1803[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1804[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1805[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1806[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1807[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1808[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1809[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1810[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1811[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1812[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1813[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1814[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1815[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1816[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1817[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1818[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1819[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1820[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1821[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1822[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1823[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1824[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1825[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1826[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1827[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1828[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1829[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1830[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1831[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1832[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1833[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1834[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1835[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1836[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1837[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1838[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_1839[] = {
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vi\t%0,%3,%v4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
  "vadd.vv\t%0,%3,%4%p1",
};

static const char * const output_1840[] = {
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vsub.vv\t%0,%3,%4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vadd.vi\t%0,%3,%V4%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
  "vrsub.vi\t%0,%4,%v3%p1",
};

static const char * const output_1841[] = {
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vi\t%0,%3,%v4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
  "vand.vv\t%0,%3,%4%p1",
};

static const char * const output_1842[] = {
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vi\t%0,%3,%v4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
  "vor.vv\t%0,%3,%4%p1",
};

static const char * const output_1843[] = {
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vi\t%0,%3,%v4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
  "vxor.vv\t%0,%3,%4%p1",
};

static const char * const output_1844[] = {
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vi\t%0,%3,%v4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
  "vsll.vv\t%0,%3,%4%p1",
};

static const char * const output_1845[] = {
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vi\t%0,%3,%v4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
  "vsra.vv\t%0,%3,%4%p1",
};

static const char * const output_1846[] = {
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vi\t%0,%3,%v4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
  "vsrl.vv\t%0,%3,%4%p1",
};

static const char * const output_1847[] = {
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
  "vmax.vv\t%0,%3,%4%p1",
};

static const char * const output_1848[] = {
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
  "vmaxu.vv\t%0,%3,%4%p1",
};

static const char * const output_1849[] = {
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
  "vmin.vv\t%0,%3,%4%p1",
};

static const char * const output_1850[] = {
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
  "vminu.vv\t%0,%3,%4%p1",
};

static const char * const output_1851[] = {
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
  "vmul.vv\t%0,%3,%4%p1",
};

static const char * const output_1852[] = {
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
  "vdiv.vv\t%0,%3,%4%p1",
};

static const char * const output_1853[] = {
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
  "vdivu.vv\t%0,%3,%4%p1",
};

static const char * const output_1854[] = {
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
  "vrem.vv\t%0,%3,%4%p1",
};

static const char * const output_1855[] = {
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
  "vremu.vv\t%0,%3,%4%p1",
};

static const char * const output_3279[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3280[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3281[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3282[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3283[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3284[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3285[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3286[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3287[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3288[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3289[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3290[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3291[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3292[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3293[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3294[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3295[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3296[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3297[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3298[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3299[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3300[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3301[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3302[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3303[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3304[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3305[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3306[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3307[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3308[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3309[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3310[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3311[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3312[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3313[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3314[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3315[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3316[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3317[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3318[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3319[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3320[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3321[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3322[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3323[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3324[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3325[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3326[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3327[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3328[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3329[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3330[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3331[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3332[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3333[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3334[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3335[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3336[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3337[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3338[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3339[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3340[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3341[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3342[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3343[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3344[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3345[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3346[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3347[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3348[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3349[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3350[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3351[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3352[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3353[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3354[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3355[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3356[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3357[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3358[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3359[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3360[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3361[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3362[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_3363[] = {
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
  "vsadd.vi\t%0,%3,%v4%p1",
};

static const char * const output_3364[] = {
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vssub.vv\t%0,%3,%4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
  "vsadd.vi\t%0,%3,%V4%p1",
};

static const char * const output_3365[] = {
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vv\t%0,%3,%4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
  "vsaddu.vi\t%0,%3,%v4%p1",
};

static const char * const output_3366[] = {
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
  "vssubu.vv\t%0,%3,%4%p1",
};

static const char * const output_4051[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4052[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4053[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4054[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4055[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4056[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4057[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4058[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4059[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4060[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4061[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4062[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4063[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4064[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4065[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4066[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4067[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4068[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4069[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4070[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4071[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4072[] = {
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
  "vmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4073[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4074[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4075[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4076[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4077[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4078[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4079[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4080[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4081[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4082[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4083[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4084[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4085[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4086[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4087[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4088[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4089[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4090[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4091[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4092[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4093[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4094[] = {
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "vmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4095[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4096[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4097[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4098[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4099[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4100[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4101[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4102[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4103[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4104[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4105[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4106[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4107[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4108[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4109[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4110[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4111[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4112[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4113[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4114[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4115[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4116[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4117[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4118[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4119[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4120[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4121[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4122[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4123[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4124[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4125[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4126[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4127[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4128[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4129[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4130[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4131[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4132[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4133[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4134[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4135[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4136[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4137[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4138[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4139[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4140[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4141[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4142[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4143[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4144[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4145[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4146[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4147[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4148[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4149[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4150[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4151[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4152[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4153[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4154[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4155[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4156[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4157[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4158[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4159[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4160[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4161[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4162[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4163[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4164[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4165[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4166[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4167[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4168[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4169[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4170[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4171[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4172[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4173[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4174[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4175[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4176[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4177[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4178[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4179[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4180[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4181[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4182[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4183[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4184[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4185[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4186[] = {
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vx\t%0,%2,%4%p1",
  "vmadd.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%2\n\tvmadd.vx\t%0,%2,%4%p1",
};

static const char * const output_4187[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4188[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4189[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4190[] = {
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "vmacc.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
};

static const char * const output_4191[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4192[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4193[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4194[] = {
  "vmv.v.v\t%0,%4\n\tvmacc.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4195[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4196[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4197[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4198[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4199[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4200[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4201[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4202[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4203[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4204[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4205[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4206[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4207[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4208[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4209[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4210[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4211[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4212[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4213[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4214[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4215[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4216[] = {
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
  "vnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4217[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4218[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4219[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4220[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4221[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4222[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4223[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4224[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4225[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4226[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4227[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4228[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4229[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4230[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4231[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4232[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4233[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4234[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4235[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4236[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4237[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4238[] = {
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "vnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4239[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4240[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4241[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4242[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4243[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4244[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4245[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4246[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4247[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4248[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4249[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4250[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4251[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4252[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4253[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4254[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4255[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4256[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4257[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4258[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4259[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4260[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vv\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
  "#",
};

static const char * const output_4261[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4262[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4263[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4264[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4265[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4266[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4267[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4268[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4269[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4270[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4271[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4272[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4273[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4274[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4275[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4276[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4277[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4278[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4279[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4280[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4281[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4282[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4283[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4284[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4285[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4286[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4287[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4288[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4289[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4290[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4291[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4292[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4293[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4294[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4295[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4296[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4297[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4298[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4299[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4300[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4301[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4302[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4303[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4304[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4305[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4306[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4307[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4308[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4309[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4310[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4311[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4312[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4313[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4314[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4315[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4316[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4317[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4318[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4319[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4320[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4321[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4322[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4323[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4324[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4325[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4326[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4327[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4328[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4329[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4330[] = {
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
  "vnmsub.vx\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvnmsub.vx\t%0,%2,%4%p1",
};

static const char * const output_4331[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4332[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4333[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4334[] = {
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "vnmsac.vx\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
};

static const char * const output_4335[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4336[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4337[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4338[] = {
  "vmv.v.v\t%0,%4\n\tvnmsac.vx\t%0,%2,%3%p1",
  "#",
  "#",
  "#",
};

static const char * const output_4780[] = {
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4781[] = {
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4782[] = {
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4783[] = {
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4784[] = {
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4785[] = {
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4786[] = {
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4787[] = {
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4788[] = {
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4789[] = {
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4790[] = {
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4791[] = {
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4792[] = {
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4793[] = {
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4794[] = {
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4795[] = {
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4796[] = {
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
  "vfmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4797[] = {
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
  "vfmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4798[] = {
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4799[] = {
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4800[] = {
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4801[] = {
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4802[] = {
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4803[] = {
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4804[] = {
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4805[] = {
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4806[] = {
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4807[] = {
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4808[] = {
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4809[] = {
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4810[] = {
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4811[] = {
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4812[] = {
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4813[] = {
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4814[] = {
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "vfmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4815[] = {
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "vfmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4816[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4817[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4818[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4819[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4820[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4821[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4822[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4823[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4824[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4825[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4826[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4827[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4828[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4829[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4830[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4831[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4832[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4833[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4834[] = {
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4835[] = {
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4836[] = {
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4837[] = {
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4838[] = {
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4839[] = {
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4840[] = {
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4841[] = {
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4842[] = {
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4843[] = {
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4844[] = {
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4845[] = {
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4846[] = {
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4847[] = {
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4848[] = {
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4849[] = {
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4850[] = {
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
  "vfmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4851[] = {
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
  "vfmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4852[] = {
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4853[] = {
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4854[] = {
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4855[] = {
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4856[] = {
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4857[] = {
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4858[] = {
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4859[] = {
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4860[] = {
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4861[] = {
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4862[] = {
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4863[] = {
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4864[] = {
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4865[] = {
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4866[] = {
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4867[] = {
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4868[] = {
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "vfmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4869[] = {
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "vfmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4870[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4871[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4872[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4873[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4874[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4875[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4876[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4877[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4878[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4879[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4880[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4881[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4882[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4883[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4884[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4885[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4886[] = {
  "vmv.v.v\t%0,%4\n\tvfmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4887[] = {
  "vmv.v.v\t%0,%4\n\tvfmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4888[] = {
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4889[] = {
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4890[] = {
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4891[] = {
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4892[] = {
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4893[] = {
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4894[] = {
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4895[] = {
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4896[] = {
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4897[] = {
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4898[] = {
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4899[] = {
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4900[] = {
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4901[] = {
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4902[] = {
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4903[] = {
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4904[] = {
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
  "vfnmsub.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmsub.vv\t%0,%3,%4%p1",
};

static const char * const output_4905[] = {
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
  "vfnmadd.vv\t%0,%3,%4%p1",
  "vmv.v.v\t%0,%2\n\tvfnmadd.vv\t%0,%3,%4%p1",
};

static const char * const output_4906[] = {
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4907[] = {
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4908[] = {
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4909[] = {
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4910[] = {
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4911[] = {
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4912[] = {
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4913[] = {
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4914[] = {
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4915[] = {
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4916[] = {
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4917[] = {
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4918[] = {
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4919[] = {
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4920[] = {
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4921[] = {
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4922[] = {
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "vfnmsac.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
};

static const char * const output_4923[] = {
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "vfnmacc.vv\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
};

static const char * const output_4924[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4925[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4926[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4927[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4928[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4929[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4930[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4931[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4932[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4933[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4934[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4935[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4936[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4937[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4938[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4939[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4940[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4941[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vv\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4942[] = {
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4943[] = {
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4944[] = {
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4945[] = {
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4946[] = {
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4947[] = {
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4948[] = {
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4949[] = {
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4950[] = {
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4951[] = {
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4952[] = {
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4953[] = {
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4954[] = {
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4955[] = {
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4956[] = {
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4957[] = {
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4958[] = {
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
  "vfnmsub.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmsub.vf\t%0,%2,%4%p1",
};

static const char * const output_4959[] = {
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
  "vfnmadd.vf\t%0,%2,%4%p1",
  "vmv.v.v\t%0,%3\n\tvfnmadd.vf\t%0,%2,%4%p1",
};

static const char * const output_4960[] = {
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4961[] = {
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4962[] = {
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4963[] = {
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4964[] = {
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4965[] = {
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4966[] = {
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4967[] = {
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4968[] = {
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4969[] = {
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4970[] = {
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4971[] = {
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4972[] = {
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4973[] = {
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4974[] = {
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4975[] = {
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4976[] = {
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "vfnmsac.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
};

static const char * const output_4977[] = {
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "vfnmacc.vf\t%0,%2,%3%p1",
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
};

static const char * const output_4978[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4979[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4980[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4981[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4982[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4983[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4984[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4985[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4986[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4987[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4988[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4989[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4990[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4991[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4992[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4993[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4994[] = {
  "vmv.v.v\t%0,%4\n\tvfnmsac.vf\t%0,%2,%3%p1",
  "#",
};

static const char * const output_4995[] = {
  "vmv.v.v\t%0,%4\n\tvfnmacc.vf\t%0,%2,%3%p1",
  "#",
};



static const struct insn_operand_data operand_data[] = 
{
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "r,I",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "r,I",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "r,I",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "r,I",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    subreg_lowpart_operator,
    "",
    E_SImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    subreg_lowpart_operator,
    "",
    E_SImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    subreg_lowpart_operator,
    "",
    E_SImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    subreg_lowpart_operator,
    "",
    E_SImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "%r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "r,I",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "%r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "r,I",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "r,m",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "r,m",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "r,m",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "r,m",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "r,m",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "r,m",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "r,m",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=f,f,f,m,m,*f,*r,*r,*r,*m",
    E_HFmode,
    0,
    0,
    1,
    1
  },
  {
    move_operand,
    "f,G,m,f,G,*r,*f,*G*r,*m,*r",
    E_HFmode,
    0,
    0,
    1,
    1
  },
  {
    nonimmediate_operand,
    "=f,r,r,m,*f,*r",
    E_HFmode,
    0,
    0,
    1,
    1
  },
  {
    move_operand,
    "f,Gr,m,r,*r,*f",
    E_HFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    symbolic_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    symbolic_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    symbolic_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    symbolic_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    symbolic_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    symbolic_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    symbolic_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    symbolic_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    splittable_const_int_operand,
    "i",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    splittable_const_int_operand,
    "i",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=r,r,r,m,*f,*f,*r,*f,*m,r",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    move_operand,
    "r,i,m,r,*J*r,*m,*f,*f,*f,vp",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    nonimmediate_operand,
    "=r,r,r,m,*f,*f,*r,*f,*m,r",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    move_operand,
    "r,T,m,rJ,*r*J,*m,*f,*f,*f,vp",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    nonimmediate_operand,
    "=r,r,r,m,*f,*f,*r,*m,r",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    move_operand,
    "r,T,m,rJ,*r*J,*m,*f,*f,vp",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    nonimmediate_operand,
    "=r,r,r,m,*f,*r,r",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    move_operand,
    "r,T,m,rJ,*r*J,*f,vp",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "r,I",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "r,I",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=r,r,r,m,*f,*r,r",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    move_operand,
    "r,I,m,rJ,*r*J,*f,vp",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    nonimmediate_operand,
    "=f,f,f,m,m,*f,*r,*r,*r,*m",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    move_operand,
    "f,G,m,f,G,*r,*f,*G*r,*m,*r",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    nonimmediate_operand,
    "=r,r,m",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    move_operand,
    "Gr,m,r",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    nonimmediate_operand,
    "=f,f,f,m,m,*th_f_fmv,*th_r_fmv,*r,*r,*m",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    move_operand,
    "f,G,m,f,G,*th_r_fmv,*th_f_fmv,*r*G,*m,*r",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    nonimmediate_operand,
    "=f,f,f,m,m,*f,*r,*r,*r,*m",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    move_operand,
    "f,G,m,f,G,*r,*f,*r*G,*m,*r",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    nonimmediate_operand,
    "=r,r,m",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    move_operand,
    "rG,m,rG",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "rI",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    subreg_lowpart_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    subreg_lowpart_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "rI",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    subreg_lowpart_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    subreg_lowpart_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "rI",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    subreg_lowpart_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    subreg_lowpart_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    immediate_operand,
    "I",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    immediate_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    shifted_const_arith_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    shifted_const_arith_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    shifted_const_arith_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    shifted_const_arith_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    shifted_const_arith_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    shifted_const_arith_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    shifted_const_arith_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    consecutive_bits_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    consecutive_bits_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    consecutive_bits_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    consecutive_bits_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    consecutive_bits_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    consecutive_bits_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    consecutive_bits_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    consecutive_bits_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    order_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    order_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,0",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    sfb_alu_operand,
    "rJ,IL",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    order_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,0",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    sfb_alu_operand,
    "rJ,IL",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    order_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,0",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    sfb_alu_operand,
    "rJ,IL",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    order_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    branch_on_bit_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    branch_on_bit_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    fp_native_comparison,
    "",
    E_SImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    fp_native_comparison,
    "",
    E_DImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    fp_native_comparison,
    "",
    E_SImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    fp_native_comparison,
    "",
    E_DImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    fp_native_comparison,
    "",
    E_SImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    fp_native_comparison,
    "",
    E_DImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "rI",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "rI",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "rI",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    sle_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    sle_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    sle_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "l",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "l",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "l",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "l",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    call_insn_operand,
    "j,S,U",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    call_insn_operand,
    "j,S,U",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    call_insn_operand,
    "l,S,U",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    gpr_save_operation,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    csr_operand,
    "rK",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "=m",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    memory_operand,
    "=m",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "m",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "m",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    address_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    1
  },
  {
    imm5_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "n",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    address_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    imm5_operand,
    "i",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    address_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    imm5_operand,
    "i",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    imm123_operand,
    "Ds3",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    imm123_operand,
    "Ds3",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    imm123_operand,
    "Ds3",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    consecutive_bits_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    imm123_operand,
    "Ds3",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    immediate_operand,
    "n",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    immediate_operand,
    "I",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    immediate_operand,
    "n",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    immediate_operand,
    "i",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const31_operand,
    "DsS",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const63_operand,
    "DsD",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const31_operand,
    "DsS",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const63_operand,
    "DsD",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    single_bit_mask_operand,
    "DbS",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    single_bit_mask_operand,
    "DbS",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    single_bit_mask_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    not_single_bit_mask_operand,
    "DnS",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    not_single_bit_mask_operand,
    "DnS",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_nottwobits_operand,
    "i",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_nottwobits_operand,
    "i",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    immediate_operand,
    "n",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    immediate_operand,
    "n",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    uimm_extra_bit_or_twobits,
    "i",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    uimm_extra_bit_or_twobits,
    "i",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    not_uimm_extra_bit_or_nottwobits,
    "i",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    not_uimm_extra_bit_or_nottwobits,
    "i",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_twobits_not_arith_operand,
    "i",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    single_bit_mask_operand,
    "i",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_twobits_not_arith_operand,
    "i",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    single_bit_mask_operand,
    "i",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "D03",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "DsA",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "D03",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_BLKmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "A",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "A",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "=A",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "=A",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+A",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+A",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+A",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+A",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+A",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "rI",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "rI",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "rI",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=&r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+A",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+A",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+A",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "rI",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rI",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=&r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+A",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=&r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+A",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=&r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+A",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "rI",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "rI",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f,*r",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=f,*r",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=f,*r",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=f,*r",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=f,*r",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=f,*r",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=f",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,*r",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r,&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,*r",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r,&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,*r",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r,&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,*r",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r,&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,*r",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r,&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,*r",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=r,&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    absolute_symbolic_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "=&r",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "n",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "n",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,0",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "0,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,0",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "0,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,0",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "0,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,0",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "0,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    equality_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "m",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "m",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "m",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "m",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "=m",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "=m",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "=m",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "=m",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "m",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "m",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,?&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "=vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "=vr,m,vr",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "m,vr,vr",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "=&r,&r,X",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    csr_operand,
    "rK",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    csr_operand,
    "rK",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,vr,vd,m,vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm,vmWc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu,vu,vu,0,vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,m,m,vr,vr,vr,viWc0,viWc0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,m,vr,vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu,vu,vu,vu,vu",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,vr,vr,Wc0,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,m,vr,vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu,vu,vu,vu,vu",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,vr,vr,Wc0,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,m,vr,vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu,vu,vu,vu,vu",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,vr,vr,Wc0,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,m,vr,vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu,vu,vu,vu,vu",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,vr,vr,Wc0,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,m,vr,vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu,vu,vu,vu,vu",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,vr,vr,Wc0,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,m,vr,vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu,vu,vu,vu,vu",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,vr,vr,Wc0,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "=vr,m,vr,vr,vr",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1,Wc1,Wc1,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu,vu,vu,vu,vu",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_move_operand,
    "m,vr,vr,Wc0,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vd,vd",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm,vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd,vd,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "r,r,Wdm,Wdm,Wdm,Wdm,r,r",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "f,f,Wdm,Wdm,Wdm,Wdm,f,f",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "f,f,Wdm,Wdm,Wdm,Wdm,f,f",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "f,f,Wdm,Wdm,Wdm,Wdm,f,f",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "f,f,Wdm,Wdm,Wdm,Wdm,f,f",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "f,f,Wdm,Wdm,Wdm,Wdm,f,f",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "f,f,Wdm,Wdm,Wdm,Wdm,f,f",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "f,f,Wdm,Wdm,Wdm,Wdm,f,f",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "f,f,Wdm,Wdm,Wdm,Wdm,f,f",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,vm,vm,Wc1,Wc1,Wb1,Wb1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "f,f,Wdm,Wdm,Wdm,Wdm,f,f",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,Wb1,Wb1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,Wb1,Wb1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,Wb1,Wb1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "Wc1,Wc1,Wb1,Wb1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vd",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,Wc1,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,vu",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_reg_or_0_operand,
    "rJ,rJ,rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+m",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_0_operand,
    "rJ",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,Wc1,vm,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,vu,0,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r,r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    pmode_register_operand,
    "r,r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "r",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "r,r,r,r,K,K,K,K",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vr,&vr,&vr,vd,vr,&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1,vm,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "0,vu,0,vu,vu,vu,vu,0,vu,vu,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_shift_operand,
    "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr,vi,vi,vi,vi",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vr,vr,vj,vj,vj,vj",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vr,vd,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vi,vi",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr,vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "vr,vr,vj,vj",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr,?&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vi,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vi,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vi,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr,?&vr,?&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r,r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_all_trues_mask_operand,
    "Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_undef_operand,
    "vu",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,?&vd,vr,?&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr,0,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,?&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "0",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vr,vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr,&vr,&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1,vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "0,0,0,0,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ,rJ,rJ,rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr,&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "f,f,f,f",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_reg_or_uimm5_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vmWc1,vmWc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=&vr,&vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "vm,vm",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=vd,vd,vr,vr",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "vm,vm,Wc1,Wc1",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "vu,0,vu,0",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "m,m,m,m",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "rK,rK,rK,rK",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "i,i,i,i",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "r,I",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r,r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "r,I",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "rJ",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_TImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    nonimmediate_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    0,
    "",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    general_operand,
    "",
    E_BLKmode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_BLKmode,
    0,
    0,
    1,
    1
  },
  {
    0,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    pmode_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    comparison_operator,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    sfb_alu_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    comparison_operator,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    sfb_alu_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    comparison_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    nonmemory_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    comparison_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    nonmemory_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    comparison_operator,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    nonmemory_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    fp_branch_comparison,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    fp_branch_comparison,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    fp_branch_comparison,
    "",
    E_VOIDmode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    order_operator,
    "",
    E_SImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    nonmemory_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    order_operator,
    "",
    E_SImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    nonmemory_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    fp_scc_comparison,
    "",
    E_SImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    fp_scc_comparison,
    "",
    E_SImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    fp_scc_comparison,
    "",
    E_SImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    general_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    1
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    1
  },
  {
    memory_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    1
  },
  {
    0,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    arith_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "=r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "r",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "",
    E_QImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_0_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_0_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    scratch_operand,
    "",
    E_HImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    memory_operand,
    "+A",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    const_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_any_register_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    general_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_SImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    scratch_operand,
    "",
    E_DImode,
    0,
    0,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    direct_broadcast_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_broadcast_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    direct_broadcast_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    1
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_arith_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ltge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_neg_arith_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    comparison_except_eqge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx64BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx32BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    ge_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx64BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx32BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    signed_order_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx16BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx16BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx1BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx2BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx4BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    1
  },
  {
    equality_operator,
    "",
    E_VNx8BImode,
    0,
    1,
    0,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    vector_length_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx32QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_QImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx64QImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_HImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx32HImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_SImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16SImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_SFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx16SFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx1DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx2DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx4DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_DFmode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_mem_operand,
    "",
    E_VNx8DFmode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx1BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx1DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx2BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx2DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx4BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx4DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    vector_mask_operand,
    "",
    E_VNx8BImode,
    0,
    0,
    1,
    0
  },
  {
    vector_merge_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    1
  },
  {
    register_operand,
    "",
    E_VNx8DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_DImode,
    0,
    0,
    1,
    0
  },
  {
    reg_or_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
  {
    const_int_operand,
    "",
    E_VOIDmode,
    0,
    0,
    1,
    0
  },
};


#if GCC_VERSION >= 2007
__extension__
#endif

const struct insn_data_d insn_data[] = 
{
  /* <internal>:0 */
  {
    "*placeholder_for_nothing",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { 0 },
    &operand_data[0],
    0,
    0,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:461 */
  {
    "addsf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fadd.s\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_addsf3 },
    &operand_data[1],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:461 */
  {
    "adddf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fadd.d\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_adddf3 },
    &operand_data[4],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:461 */
  {
    "addhf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fadd.h\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_addhf3 },
    &operand_data[7],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:470 */
  {
    "addsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "add%i2%~\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_addsi3 },
    &operand_data[10],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:479 */
  {
    "adddi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "add%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_adddi3 },
    &operand_data[13],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:563 */
  {
    "*addsi3_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "add%i2w\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:573 */
  {
    "*addsi3_extended2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "add%i2w\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[19],
    4,
    4,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:592 */
  {
    "subsf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsub.s\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subsf3 },
    &operand_data[1],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:592 */
  {
    "subdf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsub.d\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subdf3 },
    &operand_data[4],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:592 */
  {
    "subhf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsub.h\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subhf3 },
    &operand_data[7],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:601 */
  {
    "subdi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sub\t%0,%z1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subdi3 },
    &operand_data[23],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:610 */
  {
    "subsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sub%~\t%0,%z1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subsi3 },
    &operand_data[26],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:698 */
  {
    "*subsi3_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "subw\t%0,%z1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[29],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:708 */
  {
    "*subsi3_extended2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "subw\t%0,%z1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[32],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:719 */
  {
    "negdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "neg\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_negdi2 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:727 */
  {
    "negsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "neg%~\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_negsi2 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:735 */
  {
    "*negsi2_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "negw\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[40],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:744 */
  {
    "*negsi2_extended2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "negw\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[42],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:762 */
  {
    "mulsf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmul.s\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_mulsf3 },
    &operand_data[1],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:762 */
  {
    "muldf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmul.d\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_muldf3 },
    &operand_data[4],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:762 */
  {
    "mulhf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmul.h\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_mulhf3 },
    &operand_data[7],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:771 */
  {
    "mulsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "mul%~\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_mulsi3 },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:780 */
  {
    "muldi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "mul\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_muldi3 },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:880 */
  {
    "*mulsi3_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "mulw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[51],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:890 */
  {
    "*mulsi3_extended2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "mulw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[54],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:927 */
  {
    "smuldi3_highpart",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "mulh\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_smuldi3_highpart },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:927 */
  {
    "umuldi3_highpart",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "mulhu\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_umuldi3_highpart },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:958 */
  {
    "usmuldi3_highpart",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "mulhsu\t%0,%2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_usmuldi3_highpart },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:988 */
  {
    "smulsi3_highpart",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "mulh\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_smulsi3_highpart },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:988 */
  {
    "umulsi3_highpart",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "mulhu\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_umulsi3_highpart },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1019 */
  {
    "usmulsi3_highpart",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "mulhsu\t%0,%2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_usmulsi3_highpart },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1041 */
  {
    "divsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "div%i2%~\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_divsi3 },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1041 */
  {
    "udivsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "divu%i2%~\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_udivsi3 },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1041 */
  {
    "modsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "rem%i2%~\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_modsi3 },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1041 */
  {
    "umodsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "remu%i2%~\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_umodsi3 },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1050 */
  {
    "divdi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "div%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_divdi3 },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1050 */
  {
    "udivdi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "divu%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_udivdi3 },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1050 */
  {
    "moddi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "rem%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_moddi3 },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1050 */
  {
    "umoddi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "remu%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_umoddi3 },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1059 */
  {
    "*divsi3_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "div%i2w\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[51],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1059 */
  {
    "*udivsi3_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "divu%i2w\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[51],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1059 */
  {
    "*modsi3_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "rem%i2w\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[51],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1059 */
  {
    "*umodsi3_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "remu%i2w\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[51],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1069 */
  {
    "divsf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fdiv.s\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_divsf3 },
    &operand_data[1],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1069 */
  {
    "divdf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fdiv.d\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_divdf3 },
    &operand_data[4],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1069 */
  {
    "divhf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fdiv.h\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_divhf3 },
    &operand_data[7],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1085 */
  {
    "sqrtsf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_47 },
#else
    { 0, 0, output_47 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_sqrtsf2 },
    &operand_data[1],
    2,
    2,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1085 */
  {
    "sqrtdf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_48 },
#else
    { 0, 0, output_48 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_sqrtdf2 },
    &operand_data[4],
    2,
    2,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1085 */
  {
    "sqrthf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_49 },
#else
    { 0, 0, output_49 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_sqrthf2 },
    &operand_data[7],
    2,
    2,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1098 */
  {
    "fmasf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmadd.s\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fmasf4 },
    &operand_data[58],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1098 */
  {
    "fmadf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmadd.d\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fmadf4 },
    &operand_data[62],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1098 */
  {
    "fmahf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmadd.h\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fmahf4 },
    &operand_data[66],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1109 */
  {
    "fmssf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmsub.s\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fmssf4 },
    &operand_data[58],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1109 */
  {
    "fmsdf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmsub.d\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fmsdf4 },
    &operand_data[62],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1109 */
  {
    "fmshf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmsub.h\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fmshf4 },
    &operand_data[66],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1120 */
  {
    "fnmssf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fnmadd.s\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fnmssf4 },
    &operand_data[58],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1120 */
  {
    "fnmsdf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fnmadd.d\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fnmsdf4 },
    &operand_data[62],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1120 */
  {
    "fnmshf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fnmadd.h\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fnmshf4 },
    &operand_data[66],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1132 */
  {
    "fnmasf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fnmsub.s\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fnmasf4 },
    &operand_data[58],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1132 */
  {
    "fnmadf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fnmsub.d\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fnmadf4 },
    &operand_data[62],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1132 */
  {
    "fnmahf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fnmsub.h\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fnmahf4 },
    &operand_data[66],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1144 */
  {
    "*fmasf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmadd.s\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[58],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1144 */
  {
    "*fmadf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmadd.d\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[62],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1144 */
  {
    "*fmahf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmadd.h\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[66],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1157 */
  {
    "*fmssf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmsub.s\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[58],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1157 */
  {
    "*fmsdf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmsub.d\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[62],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1157 */
  {
    "*fmshf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmsub.h\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[66],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1170 */
  {
    "*fnmssf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fnmadd.s\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[58],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1170 */
  {
    "*fnmsdf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fnmadd.d\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[62],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1170 */
  {
    "*fnmshf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fnmadd.h\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[66],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1183 */
  {
    "*fnmasf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fnmsub.s\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[58],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1183 */
  {
    "*fnmadf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fnmsub.d\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[62],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1183 */
  {
    "*fnmahf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fnmsub.h\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[66],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1202 */
  {
    "abssf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fabs.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_abssf2 },
    &operand_data[1],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1202 */
  {
    "absdf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fabs.d\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_absdf2 },
    &operand_data[4],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1202 */
  {
    "abshf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fabs.h\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_abshf2 },
    &operand_data[7],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1210 */
  {
    "copysignsf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsgnj.s\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_copysignsf3 },
    &operand_data[1],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1210 */
  {
    "copysigndf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsgnj.d\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_copysigndf3 },
    &operand_data[4],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1210 */
  {
    "copysignhf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsgnj.h\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_copysignhf3 },
    &operand_data[7],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1220 */
  {
    "negsf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fneg.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_negsf2 },
    &operand_data[1],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1220 */
  {
    "negdf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fneg.d\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_negdf2 },
    &operand_data[4],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1220 */
  {
    "neghf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fneg.h\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_neghf2 },
    &operand_data[7],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1235 */
  {
    "fminsf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmin.s\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fminsf3 },
    &operand_data[1],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1235 */
  {
    "fmindf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmin.d\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fmindf3 },
    &operand_data[4],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1235 */
  {
    "fminhf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmin.h\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fminhf3 },
    &operand_data[7],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1245 */
  {
    "fmaxsf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmax.s\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fmaxsf3 },
    &operand_data[1],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1245 */
  {
    "fmaxdf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmax.d\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fmaxdf3 },
    &operand_data[4],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1245 */
  {
    "fmaxhf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmax.h\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fmaxhf3 },
    &operand_data[7],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1255 */
  {
    "sminsf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmin.s\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_sminsf3 },
    &operand_data[1],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1255 */
  {
    "smindf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmin.d\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_smindf3 },
    &operand_data[4],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1255 */
  {
    "sminhf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmin.h\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_sminhf3 },
    &operand_data[7],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1264 */
  {
    "smaxsf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmax.s\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_smaxsf3 },
    &operand_data[1],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1264 */
  {
    "smaxdf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmax.d\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_smaxdf3 },
    &operand_data[4],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1264 */
  {
    "smaxhf3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmax.h\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_smaxhf3 },
    &operand_data[7],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1284 */
  {
    "andsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "and%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_andsi3 },
    &operand_data[70],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1284 */
  {
    "iorsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "or%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_iorsi3 },
    &operand_data[70],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1284 */
  {
    "xorsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "xor%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_xorsi3 },
    &operand_data[70],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1284 */
  {
    "anddi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "and%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_anddi3 },
    &operand_data[73],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1284 */
  {
    "iordi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "or%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_iordi3 },
    &operand_data[73],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1284 */
  {
    "xordi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "xor%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_xordi3 },
    &operand_data[73],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1293 */
  {
    "*andsi3_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "and%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[70],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1293 */
  {
    "*iorsi3_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "or%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[70],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1293 */
  {
    "*xorsi3_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "xor%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[70],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1302 */
  {
    "one_cmplsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "not\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_one_cmplsi2 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1302 */
  {
    "one_cmpldi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "not\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_one_cmpldi2 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1310 */
  {
    "*one_cmplsi2_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "not\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1325 */
  {
    "truncdfsf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.s.d\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_truncdfsf2 },
    &operand_data[76],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1334 */
  {
    "truncsfhf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.h.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_truncsfhf2 },
    &operand_data[78],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1343 */
  {
    "truncdfhf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.h.d\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_truncdfhf2 },
    &operand_data[80],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1367 */
  {
    "*zero_extendsidi2_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_110 },
#else
    { 0, output_110, 0 },
#endif
    { 0 },
    &operand_data[82],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1394 */
  {
    "*zero_extendhisi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_111 },
#else
    { 0, output_111, 0 },
#endif
    { 0 },
    &operand_data[84],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1394 */
  {
    "*zero_extendhidi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_112 },
#else
    { 0, output_112, 0 },
#endif
    { 0 },
    &operand_data[86],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1416 */
  {
    "zero_extendqihi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_113 },
#else
    { 0, output_113, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_zero_extendqihi2 },
    &operand_data[88],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1416 */
  {
    "zero_extendqisi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_114 },
#else
    { 0, output_114, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_zero_extendqisi2 },
    &operand_data[90],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1416 */
  {
    "zero_extendqidi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_115 },
#else
    { 0, output_115, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_zero_extendqidi2 },
    &operand_data[92],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1434 */
  {
    "extendsidi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_116 },
#else
    { 0, output_116, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extendsidi2 },
    &operand_data[82],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1450 */
  {
    "*extendqihi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_117 },
#else
    { 0, output_117, 0 },
#endif
    { 0 },
    &operand_data[88],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1450 */
  {
    "*extendqisi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_118 },
#else
    { 0, output_118, 0 },
#endif
    { 0 },
    &operand_data[90],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1450 */
  {
    "*extendqidi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_119 },
#else
    { 0, output_119, 0 },
#endif
    { 0 },
    &operand_data[92],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1450 */
  {
    "*extendhihi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_120 },
#else
    { 0, output_120, 0 },
#endif
    { 0 },
    &operand_data[94],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1450 */
  {
    "*extendhisi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_121 },
#else
    { 0, output_121, 0 },
#endif
    { 0 },
    &operand_data[84],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1450 */
  {
    "*extendhidi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_122 },
#else
    { 0, output_122, 0 },
#endif
    { 0 },
    &operand_data[86],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1472 */
  {
    "extendhfsf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.s.h\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extendhfsf2 },
    &operand_data[96],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1481 */
  {
    "extendsfdf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.d.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extendsfdf2 },
    &operand_data[98],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1490 */
  {
    "extendhfdf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.d.h\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extendhfdf2 },
    &operand_data[100],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1510 */
  {
    "*movhf_hardfloat",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_126 },
#else
    { 0, 0, output_126 },
#endif
    { 0 },
    &operand_data[102],
    2,
    2,
    0,
    10,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1520 */
  {
    "*movhf_softfloat",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_127 },
#else
    { 0, 0, output_127 },
#endif
    { 0 },
    &operand_data[104],
    2,
    2,
    0,
    6,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1537 */
  {
    "fix_truncsfsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.w.s %0,%1,rtz",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fix_truncsfsi2 },
    &operand_data[106],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1537 */
  {
    "fix_truncsfdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.l.s %0,%1,rtz",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fix_truncsfdi2 },
    &operand_data[108],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1537 */
  {
    "fix_truncdfsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.w.d %0,%1,rtz",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fix_truncdfsi2 },
    &operand_data[110],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1537 */
  {
    "fix_truncdfdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.l.d %0,%1,rtz",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fix_truncdfdi2 },
    &operand_data[112],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1537 */
  {
    "fix_trunchfsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.w.h %0,%1,rtz",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fix_trunchfsi2 },
    &operand_data[114],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1537 */
  {
    "fix_trunchfdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.l.h %0,%1,rtz",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fix_trunchfdi2 },
    &operand_data[116],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1546 */
  {
    "fixuns_truncsfsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.wu.s %0,%1,rtz",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fixuns_truncsfsi2 },
    &operand_data[106],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1546 */
  {
    "fixuns_truncsfdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.lu.s %0,%1,rtz",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fixuns_truncsfdi2 },
    &operand_data[108],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1546 */
  {
    "fixuns_truncdfsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.wu.d %0,%1,rtz",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fixuns_truncdfsi2 },
    &operand_data[110],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1546 */
  {
    "fixuns_truncdfdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.lu.d %0,%1,rtz",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fixuns_truncdfdi2 },
    &operand_data[112],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1546 */
  {
    "fixuns_trunchfsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.wu.h %0,%1,rtz",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fixuns_trunchfsi2 },
    &operand_data[114],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1546 */
  {
    "fixuns_trunchfdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.lu.h %0,%1,rtz",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fixuns_trunchfdi2 },
    &operand_data[116],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1555 */
  {
    "floatsisf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.s.w\t%0,%z1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_floatsisf2 },
    &operand_data[118],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1555 */
  {
    "floatdisf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.s.l\t%0,%z1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_floatdisf2 },
    &operand_data[120],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1555 */
  {
    "floatsidf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.d.w\t%0,%z1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_floatsidf2 },
    &operand_data[122],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1555 */
  {
    "floatdidf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.d.l\t%0,%z1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_floatdidf2 },
    &operand_data[124],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1555 */
  {
    "floatsihf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.h.w\t%0,%z1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_floatsihf2 },
    &operand_data[126],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1555 */
  {
    "floatdihf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.h.l\t%0,%z1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_floatdihf2 },
    &operand_data[128],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1564 */
  {
    "floatunssisf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.s.wu\t%0,%z1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_floatunssisf2 },
    &operand_data[118],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1564 */
  {
    "floatunsdisf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.s.lu\t%0,%z1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_floatunsdisf2 },
    &operand_data[120],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1564 */
  {
    "floatunssidf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.d.wu\t%0,%z1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_floatunssidf2 },
    &operand_data[122],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1564 */
  {
    "floatunsdidf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.d.lu\t%0,%z1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_floatunsdidf2 },
    &operand_data[124],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1564 */
  {
    "floatunssihf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.h.wu\t%0,%z1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_floatunssihf2 },
    &operand_data[126],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1564 */
  {
    "floatunsdihf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.h.lu\t%0,%z1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_floatunsdihf2 },
    &operand_data[128],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
  {
    "lrintsfsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.w.s %0,%1,dyn",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lrintsfsi2 },
    &operand_data[106],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
  {
    "lroundsfsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.w.s %0,%1,rmm",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lroundsfsi2 },
    &operand_data[106],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
  {
    "lrintsfdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.l.s %0,%1,dyn",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lrintsfdi2 },
    &operand_data[108],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
  {
    "lroundsfdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.l.s %0,%1,rmm",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lroundsfdi2 },
    &operand_data[108],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
  {
    "lrintdfsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.w.d %0,%1,dyn",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lrintdfsi2 },
    &operand_data[110],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
  {
    "lrounddfsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.w.d %0,%1,rmm",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lrounddfsi2 },
    &operand_data[110],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
  {
    "lrintdfdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.l.d %0,%1,dyn",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lrintdfdi2 },
    &operand_data[112],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
  {
    "lrounddfdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.l.d %0,%1,rmm",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lrounddfdi2 },
    &operand_data[112],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
  {
    "lrinthfsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.w.h %0,%1,dyn",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lrinthfsi2 },
    &operand_data[114],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
  {
    "lroundhfsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.w.h %0,%1,rmm",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lroundhfsi2 },
    &operand_data[114],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
  {
    "lrinthfdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.l.h %0,%1,dyn",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lrinthfdi2 },
    &operand_data[116],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1573 */
  {
    "lroundhfdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fcvt.l.h %0,%1,rmm",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lroundhfdi2 },
    &operand_data[116],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1594 */
  {
    "got_loadsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "la\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_got_loadsi },
    &operand_data[130],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1594 */
  {
    "got_loaddi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "la\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_got_loaddi },
    &operand_data[132],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1604 */
  {
    "tls_add_tp_lesi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "add\t%0,%1,%2,%%tprel_add(%3)",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_tls_add_tp_lesi },
    &operand_data[134],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1604 */
  {
    "tls_add_tp_ledi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "add\t%0,%1,%2,%%tprel_add(%3)",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_tls_add_tp_ledi },
    &operand_data[138],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1616 */
  {
    "got_load_tls_gdsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "la.tls.gd\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_got_load_tls_gdsi },
    &operand_data[130],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1616 */
  {
    "got_load_tls_gddi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "la.tls.gd\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_got_load_tls_gddi },
    &operand_data[132],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1626 */
  {
    "got_load_tls_iesi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "la.tls.ie\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_got_load_tls_iesi },
    &operand_data[130],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1626 */
  {
    "got_load_tls_iedi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "la.tls.ie\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_got_load_tls_iedi },
    &operand_data[132],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1636 */
  {
    "auipcsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    ".LA%2: auipc\t%0,%h1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_auipcsi },
    &operand_data[142],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1636 */
  {
    "auipcdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    ".LA%2: auipc\t%0,%h1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_auipcdi },
    &operand_data[145],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1652 */
  {
    "*lowsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "addi\t%0,%1,%R2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[148],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1652 */
  {
    "*lowdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "addi\t%0,%1,%R2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[151],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1691 */
  {
    "*mvconst_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[154],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1691 */
  {
    "*mvconst_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[156],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1716 */
  {
    "*movdi_32bit",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_178 },
#else
    { 0, 0, output_178 },
#endif
    { 0 },
    &operand_data[158],
    2,
    2,
    0,
    10,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1727 */
  {
    "*movdi_64bit",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_179 },
#else
    { 0, 0, output_179 },
#endif
    { 0 },
    &operand_data[160],
    2,
    2,
    0,
    10,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1749 */
  {
    "*movsi_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_180 },
#else
    { 0, 0, output_180 },
#endif
    { 0 },
    &operand_data[162],
    2,
    2,
    0,
    9,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1777 */
  {
    "*movhi_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_181 },
#else
    { 0, 0, output_181 },
#endif
    { 0 },
    &operand_data[164],
    2,
    2,
    0,
    7,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1791 */
  {
    "*addhihi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "add%i2%~\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[166],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1791 */
  {
    "*addsihi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "add%i2%~\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[169],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1800 */
  {
    "*xorhihi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "xor%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[166],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1800 */
  {
    "*xorsihi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "xor%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[169],
    3,
    3,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1820 */
  {
    "*movqi_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_186 },
#else
    { 0, 0, output_186 },
#endif
    { 0 },
    &operand_data[172],
    2,
    2,
    0,
    7,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1841 */
  {
    "*movsf_hardfloat",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_187 },
#else
    { 0, 0, output_187 },
#endif
    { 0 },
    &operand_data[174],
    2,
    2,
    0,
    10,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1851 */
  {
    "*movsf_softfloat",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_188 },
#else
    { 0, 0, output_188 },
#endif
    { 0 },
    &operand_data[176],
    2,
    2,
    0,
    3,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1875 */
  {
    "*movdf_hardfloat_rv32",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_189 },
#else
    { 0, 0, output_189 },
#endif
    { 0 },
    &operand_data[178],
    2,
    2,
    0,
    10,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1885 */
  {
    "*movdf_hardfloat_rv64",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_190 },
#else
    { 0, 0, output_190 },
#endif
    { 0 },
    &operand_data[180],
    2,
    2,
    0,
    10,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1895 */
  {
    "*movdf_softfloat",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_191 },
#else
    { 0, 0, output_191 },
#endif
    { 0 },
    &operand_data[182],
    2,
    2,
    0,
    3,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1947 */
  {
    "fence",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "%|fence%-",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fence },
    &operand_data[0],
    0,
    0,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1952 */
  {
    "fence_i",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fence.i",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fence_i },
    &operand_data[0],
    0,
    0,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1957 */
  {
    "riscv_pause",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "pause",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_pause },
    &operand_data[0],
    0,
    0,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1974 */
  {
    "ashlsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_195 },
#else
    { 0, 0, output_195 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_ashlsi3 },
    &operand_data[184],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1974 */
  {
    "ashrsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_196 },
#else
    { 0, 0, output_196 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_ashrsi3 },
    &operand_data[184],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1974 */
  {
    "lshrsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_197 },
#else
    { 0, 0, output_197 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lshrsi3 },
    &operand_data[184],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1990 */
  {
    "*ashlsi3_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[187],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1990 */
  {
    "*ashrsi3_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[187],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1990 */
  {
    "*lshrsi3_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[187],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2009 */
  {
    "*ashlsi3_mask_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[192],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2009 */
  {
    "*ashrsi3_mask_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[192],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2009 */
  {
    "*lshrsi3_mask_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[192],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2029 */
  {
    "ashldi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_204 },
#else
    { 0, 0, output_204 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_ashldi3 },
    &operand_data[197],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2029 */
  {
    "ashrdi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_205 },
#else
    { 0, 0, output_205 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_ashrdi3 },
    &operand_data[197],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2029 */
  {
    "lshrdi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_206 },
#else
    { 0, 0, output_206 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_lshrdi3 },
    &operand_data[197],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2045 */
  {
    "*ashldi3_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[200],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2045 */
  {
    "*ashrdi3_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[200],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2045 */
  {
    "*lshrdi3_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[200],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2065 */
  {
    "*ashldi3_mask_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[205],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2065 */
  {
    "*ashrdi3_mask_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[205],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2065 */
  {
    "*lshrdi3_mask_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[205],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2085 */
  {
    "*ashlsi3_extend",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_213 },
#else
    { 0, 0, output_213 },
#endif
    { 0 },
    &operand_data[210],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2085 */
  {
    "*ashrsi3_extend",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_214 },
#else
    { 0, 0, output_214 },
#endif
    { 0 },
    &operand_data[210],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2085 */
  {
    "*lshrsi3_extend",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_215 },
#else
    { 0, 0, output_215 },
#endif
    { 0 },
    &operand_data[210],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2100 */
  {
    "*ashlsi3_extend_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[213],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2100 */
  {
    "*ashrsi3_extend_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[213],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2100 */
  {
    "*lshrsi3_extend_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[213],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2122 */
  {
    "*ashlsi3_extend_mask_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[218],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2122 */
  {
    "*ashrsi3_extend_mask_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[218],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2122 */
  {
    "*lshrsi3_extend_mask_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[218],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2146 */
  {
    "*lshrsi3_zero_extend_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_222 },
#else
    { 0, 0, output_222 },
#endif
    { 0 },
    &operand_data[223],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2161 */
  {
    "*lshrsi3_zero_extend_2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_223 },
#else
    { 0, 0, output_223 },
#endif
    { 0 },
    &operand_data[226],
    4,
    4,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2176 */
  {
    "*lshrsi3_zero_extend_3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_224 },
#else
    { 0, 0, output_224 },
#endif
    { 0 },
    &operand_data[40],
    2,
    2,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2230 */
  {
    "zero_extendsidi2_shifted",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_zero_extendsidi2_shifted },
    &operand_data[230],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
  {
    "*branchqi_shiftedarith_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[235],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
  {
    "*branchhi_shiftedarith_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[240],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
  {
    "*branchsi_shiftedarith_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[245],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
  {
    "*branchqi_shiftedarith_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[250],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
  {
    "*branchhi_shiftedarith_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[255],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
  {
    "*branchsi_shiftedarith_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[260],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2257 */
  {
    "*branchdi_shiftedarith_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[265],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
  {
    "*branchqi_shiftedmask_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[270],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
  {
    "*branchhi_shiftedmask_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[275],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
  {
    "*branchsi_shiftedmask_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[280],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
  {
    "*branchdi_shiftedmask_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[285],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
  {
    "*branchqi_shiftedmask_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[290],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
  {
    "*branchhi_shiftedmask_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[295],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
  {
    "*branchsi_shiftedmask_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[300],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2281 */
  {
    "*branchdi_shiftedmask_equals_zero",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[305],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2308 */
  {
    "*branchsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "b%C1\t%2,%z3,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[310],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2308 */
  {
    "*branchdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "b%C1\t%2,%z3,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[314],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2337 */
  {
    "*movsisicc",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_243 },
#else
    { 0, output_243, 0 },
#endif
    { 0 },
    &operand_data[318],
    6,
    6,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2337 */
  {
    "*movsidicc",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_244 },
#else
    { 0, output_244, 0 },
#endif
    { 0 },
    &operand_data[324],
    6,
    6,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2337 */
  {
    "*movdidicc",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_245 },
#else
    { 0, output_245, 0 },
#endif
    { 0 },
    &operand_data[330],
    6,
    6,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2420 */
  {
    "*branch_on_bitsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[336],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2420 */
  {
    "*branch_on_bitdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[341],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2451 */
  {
    "*branch_on_bit_rangesi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[336],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2451 */
  {
    "*branch_on_bit_rangedi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[341],
    4,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2509 */
  {
    "*cstoresfsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "f%C1.s\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[346],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2509 */
  {
    "*cstoresfdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "f%C1.s\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[350],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2509 */
  {
    "*cstoredfsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "f%C1.d\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[354],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2509 */
  {
    "*cstoredfdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "f%C1.d\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[358],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2509 */
  {
    "*cstorehfsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "f%C1.h\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[362],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2509 */
  {
    "*cstorehfdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "f%C1.h\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[366],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2546 */
  {
    "*seq_zero_sisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "seqz\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2546 */
  {
    "*seq_zero_disi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "seqz\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[370],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2546 */
  {
    "*seq_zero_didi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "seqz\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2555 */
  {
    "*sne_zero_sisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "snez\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2555 */
  {
    "*sne_zero_disi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "snez\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[370],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2555 */
  {
    "*sne_zero_didi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "snez\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2564 */
  {
    "*sgt_sisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sgt\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[372],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2564 */
  {
    "*sgtu_sisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sgtu\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[372],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2564 */
  {
    "*sgt_disi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sgt\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[375],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2564 */
  {
    "*sgtu_disi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sgtu\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[375],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2564 */
  {
    "*sgt_didi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sgt\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[378],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2564 */
  {
    "*sgtu_didi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sgtu\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[378],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2573 */
  {
    "*sge_sisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slt%i2\t%0,zero,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2573 */
  {
    "*sgeu_sisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slt%i2u\t%0,zero,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2573 */
  {
    "*sge_disi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slt%i2\t%0,zero,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[370],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2573 */
  {
    "*sgeu_disi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slt%i2u\t%0,zero,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[370],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2573 */
  {
    "*sge_didi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slt%i2\t%0,zero,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2573 */
  {
    "*sgeu_didi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slt%i2u\t%0,zero,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2582 */
  {
    "*slt_sisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slt%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[381],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2582 */
  {
    "*sltu_sisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slt%i2u\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[381],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2582 */
  {
    "*slt_disi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slt%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[384],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2582 */
  {
    "*sltu_disi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slt%i2u\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[384],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2582 */
  {
    "*slt_didi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slt%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[387],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2582 */
  {
    "*sltu_didi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slt%i2u\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[387],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2591 */
  {
    "*sle_sisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_280 },
#else
    { 0, 0, output_280 },
#endif
    { 0 },
    &operand_data[390],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2591 */
  {
    "*sleu_sisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_281 },
#else
    { 0, 0, output_281 },
#endif
    { 0 },
    &operand_data[390],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2591 */
  {
    "*sle_disi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_282 },
#else
    { 0, 0, output_282 },
#endif
    { 0 },
    &operand_data[393],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2591 */
  {
    "*sleu_disi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_283 },
#else
    { 0, 0, output_283 },
#endif
    { 0 },
    &operand_data[393],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2591 */
  {
    "*sle_didi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_284 },
#else
    { 0, 0, output_284 },
#endif
    { 0 },
    &operand_data[396],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2591 */
  {
    "*sleu_didi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_285 },
#else
    { 0, 0, output_285 },
#endif
    { 0 },
    &operand_data[396],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2612 */
  {
    "jump",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "j\t%l0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_jump },
    &operand_data[235],
    1,
    1,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2632 */
  {
    "indirect_jumpsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "jr\t%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_indirect_jumpsi },
    &operand_data[399],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2632 */
  {
    "indirect_jumpdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "jr\t%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_indirect_jumpdi },
    &operand_data[400],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2656 */
  {
    "tablejumpsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "jr\t%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_tablejumpsi },
    &operand_data[401],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2656 */
  {
    "tablejumpdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "jr\t%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_tablejumpdi },
    &operand_data[403],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2684 */
  {
    "blockage",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_blockage },
    &operand_data[0],
    0,
    0,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2715 */
  {
    "simple_return",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_292 },
#else
    { 0, 0, output_292 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_simple_return },
    &operand_data[0],
    0,
    0,
    0,
    0,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2726 */
  {
    "simple_return_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "jr\t%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_simple_return_internal },
    &operand_data[405],
    1,
    1,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2754 */
  {
    "eh_set_lr_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_eh_set_lr_si },
    &operand_data[406],
    1,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2760 */
  {
    "eh_set_lr_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_eh_set_lr_di },
    &operand_data[408],
    1,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2776 */
  {
    "eh_return_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_eh_return_internal },
    &operand_data[0],
    0,
    0,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2803 */
  {
    "sibcall_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_297 },
#else
    { 0, output_297, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_sibcall_internal },
    &operand_data[410],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2825 */
  {
    "sibcall_value_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_298 },
#else
    { 0, output_298, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_sibcall_value_internal },
    &operand_data[411],
    3,
    3,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2848 */
  {
    "call_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_299 },
#else
    { 0, output_299, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_call_internal },
    &operand_data[414],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2871 */
  {
    "call_value_internal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_300 },
#else
    { 0, output_300, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_call_value_internal },
    &operand_data[413],
    3,
    3,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2906 */
  {
    "nop",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "nop",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_nop },
    &operand_data[0],
    0,
    0,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2913 */
  {
    "trap",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "ebreak",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_trap },
    &operand_data[0],
    0,
    0,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2922 */
  {
    "gpr_save",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "call\tt0,__riscv_save_%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_gpr_save },
    &operand_data[416],
    2,
    2,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2929 */
  {
    "gpr_restore",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "tail\t__riscv_restore_%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_gpr_restore },
    &operand_data[190],
    1,
    1,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2934 */
  {
    "gpr_restore_return",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_gpr_restore_return },
    &operand_data[405],
    1,
    1,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2941 */
  {
    "riscv_frflags",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "frflags\t%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_frflags },
    &operand_data[26],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2947 */
  {
    "riscv_fsflags",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsflags\t%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_fsflags },
    &operand_data[418],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2952 */
  {
    "*riscv_fsnvsnansf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "feq.s\tzero,%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[2],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2952 */
  {
    "*riscv_fsnvsnandf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "feq.d\tzero,%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2952 */
  {
    "*riscv_fsnvsnanhf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "feq.h\tzero,%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[8],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2961 */
  {
    "riscv_mret",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "mret",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_mret },
    &operand_data[0],
    0,
    0,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2967 */
  {
    "riscv_sret",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sret",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sret },
    &operand_data[0],
    0,
    0,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2973 */
  {
    "riscv_uret",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "uret",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_uret },
    &operand_data[0],
    0,
    0,
    0,
    0,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2979 */
  {
    "stack_tiesi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_stack_tiesi },
    &operand_data[46],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2979 */
  {
    "stack_tiedi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_stack_tiedi },
    &operand_data[49],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3037 */
  {
    "stack_protect_set_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lw\t%2, %1\n\tsw\t%2, %0\n\tli\t%2, 0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_stack_protect_set_si },
    &operand_data[419],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3037 */
  {
    "stack_protect_set_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "ld\t%2, %1\n\tsd\t%2, %0\n\tli\t%2, 0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_stack_protect_set_di },
    &operand_data[422],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3075 */
  {
    "stack_protect_test_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lw\t%3, %1\n\tlw\t%0, %2\n\txor\t%0, %3, %0\n\tli\t%3, 0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_stack_protect_test_si },
    &operand_data[425],
    3,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3075 */
  {
    "stack_protect_test_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "ld\t%3, %1\n\tld\t%0, %2\n\txor\t%0, %3, %0\n\tli\t%3, 0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_stack_protect_test_di },
    &operand_data[429],
    3,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3085 */
  {
    "riscv_clean_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "cbo.clean\t%a0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_clean_si },
    &operand_data[28],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3085 */
  {
    "riscv_clean_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "cbo.clean\t%a0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_clean_di },
    &operand_data[25],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3092 */
  {
    "riscv_flush_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "cbo.flush\t%a0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_flush_si },
    &operand_data[28],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3092 */
  {
    "riscv_flush_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "cbo.flush\t%a0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_flush_di },
    &operand_data[25],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3099 */
  {
    "riscv_inval_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "cbo.inval\t%a0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_inval_si },
    &operand_data[28],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3099 */
  {
    "riscv_inval_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "cbo.inval\t%a0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_inval_di },
    &operand_data[25],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3106 */
  {
    "riscv_zero_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "cbo.zero\t%a0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_zero_si },
    &operand_data[28],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3106 */
  {
    "riscv_zero_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "cbo.zero\t%a0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_zero_di },
    &operand_data[25],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3113 */
  {
    "prefetch",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_328 },
#else
    { 0, 0, output_328 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_prefetch },
    &operand_data[433],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3127 */
  {
    "riscv_prefetchi_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "prefetch.i\t%a0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_prefetchi_si },
    &operand_data[436],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3127 */
  {
    "riscv_prefetchi_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "prefetch.i\t%a0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_prefetchi_di },
    &operand_data[438],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:22 */
  {
    "*zero_extendsidi2_bitmanip",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_331 },
#else
    { 0, output_331, 0 },
#endif
    { 0 },
    &operand_data[82],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:32 */
  {
    "*shNadd",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sh%2add\t%0,%1,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[440],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:32 */
  {
    "*shNadd",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sh%2add\t%0,%1,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[444],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:91 */
  {
    "*andi_add.uw",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[448],
    5,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:110 */
  {
    "*shNadduw",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sh%2add.uw\t%0,%1,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[454],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:167 */
  {
    "*add.uw",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "add.uw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[218],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:177 */
  {
    "*slliuw",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "slli.uw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[459],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:210 */
  {
    "*and_notsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "andn\t%0,%2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:210 */
  {
    "*ior_notsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "orn\t%0,%2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:210 */
  {
    "*and_notdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "andn\t%0,%2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:210 */
  {
    "*ior_notdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "orn\t%0,%2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:232 */
  {
    "*xor_notsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "xnor\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:232 */
  {
    "*xor_notdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "xnor\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:241 */
  {
    "*clzsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "clz%~\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:241 */
  {
    "*ctzsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "ctz%~\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:241 */
  {
    "*popcountsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "cpop%~\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:249 */
  {
    "*clzdisi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "clzw\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[40],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:249 */
  {
    "*ctzdisi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "ctzw\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[40],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:249 */
  {
    "*popcountdisi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "cpopw\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[40],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:258 */
  {
    "*clzdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "clz\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:258 */
  {
    "*ctzdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "ctz\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:258 */
  {
    "*popcountdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "cpop\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:266 */
  {
    "*zero_extendhisi2_bitmanip",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_353 },
#else
    { 0, output_353, 0 },
#endif
    { 0 },
    &operand_data[84],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:266 */
  {
    "*zero_extendhidi2_bitmanip",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_354 },
#else
    { 0, output_354, 0 },
#endif
    { 0 },
    &operand_data[86],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:276 */
  {
    "*extendqihi2_zbb",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_355 },
#else
    { 0, output_355, 0 },
#endif
    { 0 },
    &operand_data[88],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:276 */
  {
    "*extendqisi2_zbb",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_356 },
#else
    { 0, output_356, 0 },
#endif
    { 0 },
    &operand_data[90],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:276 */
  {
    "*extendqidi2_zbb",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_357 },
#else
    { 0, output_357, 0 },
#endif
    { 0 },
    &operand_data[92],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:276 */
  {
    "*extendhihi2_zbb",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_358 },
#else
    { 0, output_358, 0 },
#endif
    { 0 },
    &operand_data[94],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:276 */
  {
    "*extendhisi2_zbb",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_359 },
#else
    { 0, output_359, 0 },
#endif
    { 0 },
    &operand_data[84],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:276 */
  {
    "*extendhidi2_zbb",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_360 },
#else
    { 0, output_360, 0 },
#endif
    { 0 },
    &operand_data[86],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:287 */
  {
    "*zero_extendhisi2_zbb",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_361 },
#else
    { 0, output_361, 0 },
#endif
    { 0 },
    &operand_data[84],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:287 */
  {
    "*zero_extendhidi2_zbb",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_362 },
#else
    { 0, output_362, 0 },
#endif
    { 0 },
    &operand_data[86],
    2,
    2,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:308 */
  {
    "*rotrsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "ror%i2%~\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[184],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:316 */
  {
    "*rotrdi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "ror%i2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[197],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:324 */
  {
    "*rotrsi3_sext",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "rorw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[463],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:332 */
  {
    "rotlsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "rol%~\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_rotlsi3 },
    &operand_data[466],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:340 */
  {
    "rotldi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "rol\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_rotldi3 },
    &operand_data[469],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:348 */
  {
    "rotlsi3_sext",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "rolw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_rotlsi3_sext },
    &operand_data[463],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:358 */
  {
    "orcbsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "orc.b\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_orcbsi2 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:358 */
  {
    "orcbdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "orc.b\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_orcbdi2 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:374 */
  {
    "*bswapsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "rev8\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:374 */
  {
    "*bswapdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "rev8\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
  {
    "sminsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "min\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_sminsi3 },
    &operand_data[372],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
  {
    "uminsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "minu\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_uminsi3 },
    &operand_data[372],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
  {
    "smaxsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "max\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_smaxsi3 },
    &operand_data[372],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
  {
    "umaxsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "maxu\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_umaxsi3 },
    &operand_data[372],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
  {
    "smindi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "min\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_smindi3 },
    &operand_data[378],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
  {
    "umindi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "minu\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_umindi3 },
    &operand_data[378],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
  {
    "smaxdi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "max\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_smaxdi3 },
    &operand_data[378],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:405 */
  {
    "umaxdi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "maxu\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_umaxdi3 },
    &operand_data[378],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:415 */
  {
    "*minmax",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[472],
    3,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:415 */
  {
    "*minmax",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[472],
    3,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:415 */
  {
    "*minmax",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[472],
    3,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:415 */
  {
    "*minmax",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[472],
    3,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:433 */
  {
    "*bsetsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bset\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[466],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:433 */
  {
    "*bsetdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bset\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[469],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:442 */
  {
    "*bsetsi_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bset\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[477],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:442 */
  {
    "*bsetdi_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bset\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[481],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:453 */
  {
    "*bsetsi_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bset\t%0,x0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[485],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:453 */
  {
    "*bsetdi_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bset\t%0,x0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[487],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:461 */
  {
    "*bsetsi_1_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bset\t%0,x0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[489],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:461 */
  {
    "*bsetdi_1_mask",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bset\t%0,x0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[492],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:471 */
  {
    "*bsetisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bseti\t%0,%1,%S2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[495],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:471 */
  {
    "*bsetidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bseti\t%0,%1,%S2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[498],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:482 */
  {
    "*bsetidisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bseti\t%0,%1,%S2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[501],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:491 */
  {
    "*bclrsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bclr\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[466],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:491 */
  {
    "*bclrdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bclr\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[469],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:500 */
  {
    "*bclrisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bclri\t%0,%1,%T2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[504],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:500 */
  {
    "*bclridi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bclri\t%0,%1,%T2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[507],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:509 */
  {
    "*bclrisi_nottwobits",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[510],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:509 */
  {
    "*bclridi_nottwobits",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[513],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:528 */
  {
    "*bclridisi_nottwobits",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[513],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:546 */
  {
    "*binvsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "binv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[466],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:546 */
  {
    "*binvdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "binv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[469],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:555 */
  {
    "*binvisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "binvi\t%0,%1,%S2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[495],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:555 */
  {
    "*binvidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "binvi\t%0,%1,%S2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[498],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:563 */
  {
    "*bextsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bext\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[466],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:563 */
  {
    "*bextdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bext\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[469],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:576 */
  {
    "*bextsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bext\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:576 */
  {
    "*bextdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bext\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:585 */
  {
    "*bexti",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bexti\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[516],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:585 */
  {
    "*bexti",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "bexti\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[519],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:624 */
  {
    "*iorisi_extrabit",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[522],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:624 */
  {
    "*xorisi_extrabit",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[522],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:624 */
  {
    "*ioridi_extrabit",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[525],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:624 */
  {
    "*xoridi_extrabit",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[525],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:642 */
  {
    "*andisi_extrabit",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[528],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:642 */
  {
    "*andidi_extrabit",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[531],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:660 */
  {
    "*branchsi_mask_twobits_equals_singlebit",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[534],
    5,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:660 */
  {
    "*branchdi_mask_twobits_equals_singlebit",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[541],
    5,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:78 */
  {
    "riscv_brev8_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "brev8\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_brev8_si },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:78 */
  {
    "riscv_brev8_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "brev8\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_brev8_di },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:86 */
  {
    "riscv_zip",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "zip\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_zip },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:94 */
  {
    "riscv_unzip",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "unzip\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_unzip },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:102 */
  {
    "riscv_pack_sihi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "pack\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_pack_sihi },
    &operand_data[548],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:102 */
  {
    "riscv_pack_sisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "pack\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_pack_sisi },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:102 */
  {
    "riscv_pack_dihi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "pack\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_pack_dihi },
    &operand_data[551],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:102 */
  {
    "riscv_pack_disi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "pack\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_pack_disi },
    &operand_data[51],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:111 */
  {
    "riscv_packh_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "packh\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_packh_si },
    &operand_data[554],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:111 */
  {
    "riscv_packh_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "packh\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_packh_di },
    &operand_data[557],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:120 */
  {
    "riscv_packw",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "packw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_packw },
    &operand_data[551],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:131 */
  {
    "riscv_clmul_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "clmul\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_clmul_si },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:131 */
  {
    "riscv_clmul_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "clmul\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_clmul_di },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:140 */
  {
    "riscv_clmulh_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "clmulh\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_clmulh_si },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:140 */
  {
    "riscv_clmulh_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "clmulh\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_clmulh_di },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:151 */
  {
    "riscv_xperm4_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "xperm4\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_xperm4_si },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:151 */
  {
    "riscv_xperm4_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "xperm4\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_xperm4_di },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:160 */
  {
    "riscv_xperm8_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "xperm8\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_xperm8_si },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:160 */
  {
    "riscv_xperm8_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "xperm8\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_xperm8_di },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:171 */
  {
    "riscv_aes32dsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "aes32dsi\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_aes32dsi },
    &operand_data[560],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:181 */
  {
    "riscv_aes32dsmi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "aes32dsmi\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_aes32dsmi },
    &operand_data[560],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:191 */
  {
    "riscv_aes64ds",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "aes64ds\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_aes64ds },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:200 */
  {
    "riscv_aes64dsm",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "aes64dsm\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_aes64dsm },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:209 */
  {
    "riscv_aes64im",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "aes64im\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_aes64im },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:217 */
  {
    "riscv_aes64ks1i",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "aes64ks1i\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_aes64ks1i },
    &operand_data[564],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:226 */
  {
    "riscv_aes64ks2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "aes64ks2\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_aes64ks2 },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:237 */
  {
    "riscv_aes32esi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "aes32esi\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_aes32esi },
    &operand_data[560],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:247 */
  {
    "riscv_aes32esmi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "aes32esmi\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_aes32esmi },
    &operand_data[560],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:257 */
  {
    "riscv_aes64es",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "aes64es\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_aes64es },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:266 */
  {
    "riscv_aes64esm",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "aes64esm\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_aes64esm },
    &operand_data[48],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:277 */
  {
    "riscv_sha256sig0_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha256sig0\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha256sig0_si },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:277 */
  {
    "riscv_sha256sig0_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha256sig0\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha256sig0_di },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:285 */
  {
    "riscv_sha256sig1_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha256sig1\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha256sig1_si },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:285 */
  {
    "riscv_sha256sig1_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha256sig1\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha256sig1_di },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:293 */
  {
    "riscv_sha256sum0_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha256sum0\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha256sum0_si },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:293 */
  {
    "riscv_sha256sum0_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha256sum0\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha256sum0_di },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:301 */
  {
    "riscv_sha256sum1_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha256sum1\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha256sum1_si },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:301 */
  {
    "riscv_sha256sum1_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha256sum1\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha256sum1_di },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:311 */
  {
    "riscv_sha512sig0h",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha512sig0h\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha512sig0h },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:320 */
  {
    "riscv_sha512sig0l",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha512sig0l\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha512sig0l },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:329 */
  {
    "riscv_sha512sig1h",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha512sig1h\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha512sig1h },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:338 */
  {
    "riscv_sha512sig1l",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha512sig1l\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha512sig1l },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:347 */
  {
    "riscv_sha512sum0r",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha512sum0r\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha512sum0r },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:356 */
  {
    "riscv_sha512sum1r",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha512sum1r\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha512sum1r },
    &operand_data[45],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:365 */
  {
    "riscv_sha512sig0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha512sig0\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha512sig0 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:373 */
  {
    "riscv_sha512sig1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha512sig1\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha512sig1 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:381 */
  {
    "riscv_sha512sum0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha512sum0\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha512sum0 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:389 */
  {
    "riscv_sha512sum1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sha512sum1\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sha512sum1 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:399 */
  {
    "riscv_sm3p0_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sm3p0\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sm3p0_si },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:399 */
  {
    "riscv_sm3p0_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sm3p0\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sm3p0_di },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:407 */
  {
    "riscv_sm3p1_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sm3p1\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sm3p1_si },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:407 */
  {
    "riscv_sm3p1_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sm3p1\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sm3p1_di },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:417 */
  {
    "riscv_sm4ed_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sm4ed\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sm4ed_si },
    &operand_data[560],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:417 */
  {
    "riscv_sm4ed_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sm4ed\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sm4ed_di },
    &operand_data[567],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:427 */
  {
    "riscv_sm4ks_si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sm4ks\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sm4ks_si },
    &operand_data[560],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/crypto.md:427 */
  {
    "riscv_sm4ks_di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sm4ks\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_riscv_sm4ks_di },
    &operand_data[567],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:49 */
  {
    "mem_thread_fence_1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_477 },
#else
    { 0, 0, output_477 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_mem_thread_fence_1 },
    &operand_data[571],
    2,
    2,
    1,
    0,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:72 */
  {
    "atomic_loadsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_478 },
#else
    { 0, 0, output_478 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_loadsi },
    &operand_data[573],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:72 */
  {
    "atomic_loaddi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_479 },
#else
    { 0, 0, output_479 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_loaddi },
    &operand_data[576],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:98 */
  {
    "atomic_storesi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_480 },
#else
    { 0, 0, output_480 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_storesi },
    &operand_data[579],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:98 */
  {
    "atomic_storedi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_481 },
#else
    { 0, 0, output_481 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_storedi },
    &operand_data[582],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
  {
    "atomic_addsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoadd.w%A2\tzero,%z1,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_addsi },
    &operand_data[585],
    3,
    3,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
  {
    "atomic_orsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoor.w%A2\tzero,%z1,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_orsi },
    &operand_data[585],
    3,
    3,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
  {
    "atomic_xorsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoxor.w%A2\tzero,%z1,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_xorsi },
    &operand_data[585],
    3,
    3,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
  {
    "atomic_andsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoand.w%A2\tzero,%z1,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_andsi },
    &operand_data[585],
    3,
    3,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
  {
    "atomic_adddi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoadd.d%A2\tzero,%z1,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_adddi },
    &operand_data[588],
    3,
    3,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
  {
    "atomic_ordi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoor.d%A2\tzero,%z1,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_ordi },
    &operand_data[588],
    3,
    3,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
  {
    "atomic_xordi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoxor.d%A2\tzero,%z1,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_xordi },
    &operand_data[588],
    3,
    3,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:122 */
  {
    "atomic_anddi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoand.d%A2\tzero,%z1,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_anddi },
    &operand_data[588],
    3,
    3,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
  {
    "atomic_fetch_addsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoadd.w%A3\t%0,%z2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_addsi },
    &operand_data[591],
    4,
    4,
    2,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
  {
    "atomic_fetch_orsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoor.w%A3\t%0,%z2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_orsi },
    &operand_data[591],
    4,
    4,
    2,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
  {
    "atomic_fetch_xorsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoxor.w%A3\t%0,%z2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_xorsi },
    &operand_data[591],
    4,
    4,
    2,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
  {
    "atomic_fetch_andsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoand.w%A3\t%0,%z2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_andsi },
    &operand_data[591],
    4,
    4,
    2,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
  {
    "atomic_fetch_adddi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoadd.d%A3\t%0,%z2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_adddi },
    &operand_data[595],
    4,
    4,
    2,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
  {
    "atomic_fetch_ordi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoor.d%A3\t%0,%z2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_ordi },
    &operand_data[595],
    4,
    4,
    2,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
  {
    "atomic_fetch_xordi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoxor.d%A3\t%0,%z2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_xordi },
    &operand_data[595],
    4,
    4,
    2,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:134 */
  {
    "atomic_fetch_anddi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoand.d%A3\t%0,%z2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_anddi },
    &operand_data[595],
    4,
    4,
    2,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:148 */
  {
    "subword_atomic_fetch_strong_add",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_498 },
#else
    { 0, 0, output_498 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subword_atomic_fetch_strong_add },
    &operand_data[599],
    6,
    8,
    2,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:148 */
  {
    "subword_atomic_fetch_strong_or",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_499 },
#else
    { 0, 0, output_499 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subword_atomic_fetch_strong_or },
    &operand_data[599],
    6,
    8,
    2,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:148 */
  {
    "subword_atomic_fetch_strong_xor",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_500 },
#else
    { 0, 0, output_500 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subword_atomic_fetch_strong_xor },
    &operand_data[599],
    6,
    8,
    2,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:148 */
  {
    "subword_atomic_fetch_strong_and",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_501 },
#else
    { 0, 0, output_501 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subword_atomic_fetch_strong_and },
    &operand_data[599],
    6,
    8,
    2,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:214 */
  {
    "subword_atomic_fetch_strong_nand",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_502 },
#else
    { 0, 0, output_502 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subword_atomic_fetch_strong_nand },
    &operand_data[599],
    6,
    8,
    2,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:282 */
  {
    "atomic_exchangesi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoswap.w%A3\t%0,%z2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_exchangesi },
    &operand_data[607],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:282 */
  {
    "atomic_exchangedi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "amoswap.d%A3\t%0,%z2,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_exchangedi },
    &operand_data[611],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:327 */
  {
    "subword_atomic_exchange_strong",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_505 },
#else
    { 0, 0, output_505 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subword_atomic_exchange_strong },
    &operand_data[615],
    5,
    6,
    1,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:348 */
  {
    "atomic_cas_value_strongsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_506 },
#else
    { 0, 0, output_506 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_cas_value_strongsi },
    &operand_data[621],
    6,
    7,
    1,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:348 */
  {
    "atomic_cas_value_strongdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_507 },
#else
    { 0, 0, output_507 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_cas_value_strongdi },
    &operand_data[628],
    6,
    7,
    1,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:519 */
  {
    "subword_atomic_cas_strong",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_508 },
#else
    { 0, 0, output_508 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subword_atomic_cas_strong },
    &operand_data[635],
    7,
    8,
    1,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:25 */
  {
    "*local_pic_loadqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lbu\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[643],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:25 */
  {
    "*local_pic_loadhi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lhu\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[645],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:25 */
  {
    "*local_pic_loadsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lw\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[647],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:25 */
  {
    "*local_pic_loaddi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "ld\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[649],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:32 */
  {
    "*local_pic_load_sqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lb\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[645],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:32 */
  {
    "*local_pic_load_sqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lb\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[647],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:32 */
  {
    "*local_pic_load_sqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lb\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[649],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:32 */
  {
    "*local_pic_load_shi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lh\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[645],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:32 */
  {
    "*local_pic_load_shi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lh\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[647],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:32 */
  {
    "*local_pic_load_shi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lh\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[649],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:32 */
  {
    "*local_pic_load_ssi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lw\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[645],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:32 */
  {
    "*local_pic_load_ssi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lw\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[647],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:32 */
  {
    "*local_pic_load_ssi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lw\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[649],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:39 */
  {
    "*local_pic_load_uqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lbu\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[645],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:39 */
  {
    "*local_pic_load_uqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lbu\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[647],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:39 */
  {
    "*local_pic_load_uqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lbu\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[649],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:39 */
  {
    "*local_pic_load_uhi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lhu\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[645],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:39 */
  {
    "*local_pic_load_uhi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lhu\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[647],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:39 */
  {
    "*local_pic_load_uhi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lhu\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[649],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:39 */
  {
    "*local_pic_load_usi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lwu\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[645],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:39 */
  {
    "*local_pic_load_usi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lwu\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[647],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:39 */
  {
    "*local_pic_load_usi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lwu\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[649],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:49 */
  {
    "*local_pic_loadsf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_531 },
#else
    { 0, output_531, 0 },
#endif
    { 0 },
    &operand_data[651],
    2,
    3,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:49 */
  {
    "*local_pic_loaddf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_532 },
#else
    { 0, output_532, 0 },
#endif
    { 0 },
    &operand_data[654],
    2,
    3,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:49 */
  {
    "*local_pic_loadhf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_533 },
#else
    { 0, output_533, 0 },
#endif
    { 0 },
    &operand_data[657],
    2,
    3,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:49 */
  {
    "*local_pic_loadsf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_534 },
#else
    { 0, output_534, 0 },
#endif
    { 0 },
    &operand_data[660],
    2,
    3,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:49 */
  {
    "*local_pic_loaddf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_535 },
#else
    { 0, output_535, 0 },
#endif
    { 0 },
    &operand_data[663],
    2,
    3,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:49 */
  {
    "*local_pic_loadhf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_536 },
#else
    { 0, output_536, 0 },
#endif
    { 0 },
    &operand_data[666],
    2,
    3,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:64 */
  {
    "*local_pic_load_32dsf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "flw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[669],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:64 */
  {
    "*local_pic_load_32ddf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fld\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[672],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:64 */
  {
    "*local_pic_load_32dhf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "flh\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[675],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:64 */
  {
    "*local_pic_load_32dsf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "flw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[678],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:64 */
  {
    "*local_pic_load_32ddf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fld\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[681],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:64 */
  {
    "*local_pic_load_32dhf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "flh\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[684],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:73 */
  {
    "*local_pic_load_sfsf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lw\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[687],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:73 */
  {
    "*local_pic_load_sfdf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "ld\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[689],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:73 */
  {
    "*local_pic_load_sfhf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "lh\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[691],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:83 */
  {
    "*local_pic_storeqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sb\t%z1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[692],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:83 */
  {
    "*local_pic_storehi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sh\t%z1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[695],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:83 */
  {
    "*local_pic_storesi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sw\t%z1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[698],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:83 */
  {
    "*local_pic_storedi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sd\t%z1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[701],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:83 */
  {
    "*local_pic_storeqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sb\t%z1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[704],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:83 */
  {
    "*local_pic_storehi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sh\t%z1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[707],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:83 */
  {
    "*local_pic_storesi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sw\t%z1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[710],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:83 */
  {
    "*local_pic_storedi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sd\t%z1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[713],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:91 */
  {
    "*local_pic_storesf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_554 },
#else
    { 0, output_554, 0 },
#endif
    { 0 },
    &operand_data[716],
    2,
    3,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:91 */
  {
    "*local_pic_storedf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_555 },
#else
    { 0, output_555, 0 },
#endif
    { 0 },
    &operand_data[719],
    2,
    3,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:91 */
  {
    "*local_pic_storehf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_556 },
#else
    { 0, output_556, 0 },
#endif
    { 0 },
    &operand_data[722],
    2,
    3,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:91 */
  {
    "*local_pic_storesf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_557 },
#else
    { 0, output_557, 0 },
#endif
    { 0 },
    &operand_data[725],
    2,
    3,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:91 */
  {
    "*local_pic_storedf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_558 },
#else
    { 0, output_558, 0 },
#endif
    { 0 },
    &operand_data[728],
    2,
    3,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:91 */
  {
    "*local_pic_storehf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_559 },
#else
    { 0, output_559, 0 },
#endif
    { 0 },
    &operand_data[731],
    2,
    3,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:106 */
  {
    "*local_pic_store_32dsf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsw\t%1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[669],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:106 */
  {
    "*local_pic_store_32ddf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsd\t%1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[672],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:106 */
  {
    "*local_pic_store_32dhf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsh\t%1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[675],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:106 */
  {
    "*local_pic_store_32dsf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsw\t%1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[678],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:106 */
  {
    "*local_pic_store_32ddf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsd\t%1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[681],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:106 */
  {
    "*local_pic_store_32dhf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fsh\t%1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[684],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:115 */
  {
    "*local_pic_store_sfsf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sw\t%1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[734],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:115 */
  {
    "*local_pic_store_sfdf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sd\t%1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[737],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:115 */
  {
    "*local_pic_store_sfhf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sh\t%1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[740],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:115 */
  {
    "*local_pic_store_sfsf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sw\t%1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[743],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:115 */
  {
    "*local_pic_store_sfdf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sd\t%1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[746],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/pic.md:115 */
  {
    "*local_pic_store_sfhf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "sh\t%1,%0,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[749],
    2,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:22 */
  {
    "*th_addslsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.addsl\t%0,%3,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[752],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:22 */
  {
    "*th_addsldi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.addsl\t%0,%3,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[756],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:35 */
  {
    "*th_srrisi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_574 },
#else
    { 0, 0, output_574 },
#endif
    { 0 },
    &operand_data[752],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:35 */
  {
    "*th_srridi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_575 },
#else
    { 0, 0, output_575 },
#endif
    { 0 },
    &operand_data[756],
    3,
    3,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:49 */
  {
    "*th_extsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_576 },
#else
    { 0, 0, output_576 },
#endif
    { 0 },
    &operand_data[760],
    4,
    4,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:49 */
  {
    "*th_extdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_577 },
#else
    { 0, 0, output_577 },
#endif
    { 0 },
    &operand_data[226],
    4,
    4,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:62 */
  {
    "*th_extusi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_578 },
#else
    { 0, 0, output_578 },
#endif
    { 0 },
    &operand_data[760],
    4,
    4,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:62 */
  {
    "*th_extudi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_579 },
#else
    { 0, 0, output_579 },
#endif
    { 0 },
    &operand_data[226],
    4,
    4,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:75 */
  {
    "*th_clzsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.ff1\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:75 */
  {
    "*th_clzdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.ff1\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:83 */
  {
    "*th_revsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_582 },
#else
    { 0, 0, output_582 },
#endif
    { 0 },
    &operand_data[38],
    2,
    2,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:83 */
  {
    "*th_revdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_583 },
#else
    { 0, 0, output_583 },
#endif
    { 0 },
    &operand_data[36],
    2,
    2,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:96 */
  {
    "*th_tstsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.tst\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[752],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:96 */
  {
    "*th_tstdi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.tst\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[756],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:107 */
  {
    "*th_cond_movsisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_586 },
#else
    { 0, 0, output_586 },
#endif
    { 0 },
    &operand_data[764],
    5,
    5,
    0,
    2,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:107 */
  {
    "*th_cond_movdisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_587 },
#else
    { 0, 0, output_587 },
#endif
    { 0 },
    &operand_data[769],
    5,
    5,
    0,
    2,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:107 */
  {
    "*th_cond_movsidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_588 },
#else
    { 0, 0, output_588 },
#endif
    { 0 },
    &operand_data[774],
    5,
    5,
    0,
    2,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:107 */
  {
    "*th_cond_movdidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_589 },
#else
    { 0, 0, output_589 },
#endif
    { 0 },
    &operand_data[779],
    5,
    5,
    0,
    2,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:129 */
  {
    "*th_cond_gpr_movsisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_590 },
#else
    { 0, output_590, 0 },
#endif
    { 0 },
    &operand_data[764],
    4,
    4,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:129 */
  {
    "*th_cond_gpr_movdisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_591 },
#else
    { 0, output_591, 0 },
#endif
    { 0 },
    &operand_data[769],
    4,
    4,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:129 */
  {
    "*th_cond_gpr_movsidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_592 },
#else
    { 0, output_592, 0 },
#endif
    { 0 },
    &operand_data[774],
    4,
    4,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:129 */
  {
    "*th_cond_gpr_movdidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_593 },
#else
    { 0, output_593, 0 },
#endif
    { 0 },
    &operand_data[779],
    4,
    4,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:147 */
  {
    "th_fmv_hw_w_x",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmv.w.x\t%0,%2\n\tth.fmv.hw.x\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_th_fmv_hw_w_x },
    &operand_data[784],
    3,
    3,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:157 */
  {
    "th_fmv_x_w",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "fmv.x.w\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_th_fmv_x_w },
    &operand_data[110],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:166 */
  {
    "th_fmv_x_hw",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.fmv.x.hw\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_th_fmv_x_hw },
    &operand_data[110],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:177 */
  {
    "*th_mulasi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.mula\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[787],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:177 */
  {
    "*th_muladi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.mula\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[791],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:188 */
  {
    "*th_mulawsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.mulaw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[795],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:200 */
  {
    "*th_mulawsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.mulaw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[787],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:211 */
  {
    "*th_maddhisi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.mulah\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[799],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:224 */
  {
    "*th_sextw_maddhisi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.mulah\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[803],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:238 */
  {
    "*th_mulssi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.muls\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[787],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:238 */
  {
    "*th_mulsdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.muls\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[791],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:249 */
  {
    "*th_mulswsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.mulsw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[795],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:261 */
  {
    "*th_mulswsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.mulsw\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[787],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:272 */
  {
    "*th_msubhisi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.mulsh\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[799],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:283 */
  {
    "*th_sextw_msubhisi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "th.mulsh\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[803],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:299 */
  {
    "*th_mempair_load_si2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_609 },
#else
    { 0, 0, output_609 },
#endif
    { 0 },
    &operand_data[807],
    4,
    4,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:299 */
  {
    "*th_mempair_load_di2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_610 },
#else
    { 0, 0, output_610 },
#endif
    { 0 },
    &operand_data[811],
    4,
    4,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:311 */
  {
    "*th_mempair_store_si2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_611 },
#else
    { 0, 0, output_611 },
#endif
    { 0 },
    &operand_data[815],
    4,
    4,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:311 */
  {
    "*th_mempair_store_di2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_612 },
#else
    { 0, 0, output_612 },
#endif
    { 0 },
    &operand_data[819],
    4,
    4,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:323 */
  {
    "*th_mempair_load_extendsidi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_613 },
#else
    { 0, 0, output_613 },
#endif
    { 0 },
    &operand_data[823],
    4,
    4,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/thead.md:336 */
  {
    "*th_mempair_load_zero_extendsidi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .function = output_614 },
#else
    { 0, 0, output_614 },
#endif
    { 0 },
    &operand_data[823],
    4,
    4,
    0,
    1,
    3
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx1qi },
    &operand_data[827],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx2qi },
    &operand_data[828],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx4qi },
    &operand_data[829],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx8qi },
    &operand_data[830],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx16qi },
    &operand_data[831],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx32qi },
    &operand_data[832],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx64qi },
    &operand_data[833],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx1hi },
    &operand_data[834],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx2hi },
    &operand_data[835],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx4hi },
    &operand_data[836],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx8hi },
    &operand_data[837],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx16hi },
    &operand_data[838],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx32hi },
    &operand_data[839],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx1si },
    &operand_data[840],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx2si },
    &operand_data[841],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx4si },
    &operand_data[842],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx8si },
    &operand_data[843],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx16si },
    &operand_data[844],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx1di },
    &operand_data[845],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx2di },
    &operand_data[846],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx4di },
    &operand_data[847],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx8di },
    &operand_data[848],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx1sf },
    &operand_data[849],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx2sf },
    &operand_data[850],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx4sf },
    &operand_data[851],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx8sf },
    &operand_data[852],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx16sf },
    &operand_data[853],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx1df },
    &operand_data[854],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx2df },
    &operand_data[855],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx4df },
    &operand_data[856],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:358 */
  {
    "vundefinedvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx8df },
    &operand_data[857],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
  {
    "vundefinedvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx1bi },
    &operand_data[858],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
  {
    "vundefinedvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx2bi },
    &operand_data[859],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
  {
    "vundefinedvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx4bi },
    &operand_data[860],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
  {
    "vundefinedvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx8bi },
    &operand_data[861],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
  {
    "vundefinedvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx16bi },
    &operand_data[862],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
  {
    "vundefinedvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx32bi },
    &operand_data[863],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:364 */
  {
    "vundefinedvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vundefinedvnx64bi },
    &operand_data[864],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[865],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[867],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[869],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[871],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[873],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[875],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[877],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[879],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[881],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[883],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[885],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[887],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[889],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[891],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[893],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[895],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[897],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[899],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[901],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[903],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[905],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[907],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[909],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[911],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:422 */
  {
    "*vlmul_extx2vnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[913],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[915],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[917],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[919],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[921],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[923],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[925],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[927],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[929],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[931],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[933],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[935],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[937],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[939],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[941],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[943],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[945],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[947],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[949],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:435 */
  {
    "*vlmul_extx4vnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[951],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[953],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[955],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[957],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[959],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[961],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[963],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[965],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[967],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[969],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[971],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[973],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[975],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:448 */
  {
    "*vlmul_extx8vnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[977],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
  {
    "*vlmul_extx16vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[979],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
  {
    "*vlmul_extx16vnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[981],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
  {
    "*vlmul_extx16vnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[983],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
  {
    "*vlmul_extx16vnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[985],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
  {
    "*vlmul_extx16vnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[987],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
  {
    "*vlmul_extx16vnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[989],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:461 */
  {
    "*vlmul_extx16vnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[991],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:474 */
  {
    "*vlmul_extx32vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[993],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:474 */
  {
    "*vlmul_extx32vnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[995],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:474 */
  {
    "*vlmul_extx32vnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[997],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:487 */
  {
    "*vlmul_extx64vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[999],
    2,
    2,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:525 */
  {
    "vlmax_avlsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmax_avlsi },
    &operand_data[1001],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:525 */
  {
    "vlmax_avldi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmax_avldi },
    &operand_data[1003],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx4qi_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_723 },
#else
    { 0, output_723, 0 },
#endif
    { 0 },
    &operand_data[1005],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx8qi_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_724 },
#else
    { 0, output_724, 0 },
#endif
    { 0 },
    &operand_data[1007],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx16qi_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_725 },
#else
    { 0, output_725, 0 },
#endif
    { 0 },
    &operand_data[1009],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx32qi_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_726 },
#else
    { 0, output_726, 0 },
#endif
    { 0 },
    &operand_data[1011],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx64qi_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_727 },
#else
    { 0, output_727, 0 },
#endif
    { 0 },
    &operand_data[1013],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx2hi_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_728 },
#else
    { 0, output_728, 0 },
#endif
    { 0 },
    &operand_data[1015],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx4hi_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_729 },
#else
    { 0, output_729, 0 },
#endif
    { 0 },
    &operand_data[1017],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx8hi_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_730 },
#else
    { 0, output_730, 0 },
#endif
    { 0 },
    &operand_data[1019],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx16hi_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_731 },
#else
    { 0, output_731, 0 },
#endif
    { 0 },
    &operand_data[1021],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx32hi_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_732 },
#else
    { 0, output_732, 0 },
#endif
    { 0 },
    &operand_data[1023],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx1si_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_733 },
#else
    { 0, output_733, 0 },
#endif
    { 0 },
    &operand_data[1025],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx2si_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_734 },
#else
    { 0, output_734, 0 },
#endif
    { 0 },
    &operand_data[1027],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx4si_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_735 },
#else
    { 0, output_735, 0 },
#endif
    { 0 },
    &operand_data[1029],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx8si_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_736 },
#else
    { 0, output_736, 0 },
#endif
    { 0 },
    &operand_data[1031],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx16si_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_737 },
#else
    { 0, output_737, 0 },
#endif
    { 0 },
    &operand_data[1033],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx1di_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_738 },
#else
    { 0, output_738, 0 },
#endif
    { 0 },
    &operand_data[1035],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx2di_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_739 },
#else
    { 0, output_739, 0 },
#endif
    { 0 },
    &operand_data[1037],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx4di_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_740 },
#else
    { 0, output_740, 0 },
#endif
    { 0 },
    &operand_data[1039],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx8di_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_741 },
#else
    { 0, output_741, 0 },
#endif
    { 0 },
    &operand_data[1041],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx1sf_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_742 },
#else
    { 0, output_742, 0 },
#endif
    { 0 },
    &operand_data[1043],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx2sf_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_743 },
#else
    { 0, output_743, 0 },
#endif
    { 0 },
    &operand_data[1045],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx4sf_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_744 },
#else
    { 0, output_744, 0 },
#endif
    { 0 },
    &operand_data[1047],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx8sf_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_745 },
#else
    { 0, output_745, 0 },
#endif
    { 0 },
    &operand_data[1049],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx16sf_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_746 },
#else
    { 0, output_746, 0 },
#endif
    { 0 },
    &operand_data[1051],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx1df_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_747 },
#else
    { 0, output_747, 0 },
#endif
    { 0 },
    &operand_data[1053],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx2df_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_748 },
#else
    { 0, output_748, 0 },
#endif
    { 0 },
    &operand_data[1055],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx4df_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_749 },
#else
    { 0, output_749, 0 },
#endif
    { 0 },
    &operand_data[1057],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:602 */
  {
    "*movvnx8df_whole",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_750 },
#else
    { 0, output_750, 0 },
#endif
    { 0 },
    &operand_data[1059],
    2,
    2,
    0,
    3,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:613 */
  {
    "*movvnx1qi_fract",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1061],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:613 */
  {
    "*movvnx2qi_fract",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1063],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:613 */
  {
    "*movvnx4qi_fract",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1065],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:613 */
  {
    "*movvnx1hi_fract",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1067],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:613 */
  {
    "*movvnx2hi_fract",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1069],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:613 */
  {
    "*movvnx1si_fract",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1071],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:613 */
  {
    "*movvnx1sf_fract",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1073],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:630 */
  {
    "*movvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1075],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:630 */
  {
    "*movvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1077],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:630 */
  {
    "*movvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1079],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:630 */
  {
    "*movvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1081],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:630 */
  {
    "*movvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1083],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:630 */
  {
    "*movvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1085],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:630 */
  {
    "*movvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv1r.v\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1087],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx1qisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1089],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx1qidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1092],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx2qisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1095],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx2qidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1098],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx4qisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1101],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx4qidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1104],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx1hisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1107],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx1hidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1110],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx2hisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1113],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx2hidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1116],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx1sisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1119],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx1sidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1122],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx1sfsi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1125],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:654 */
  {
    "*movvnx1sfdi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1128],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx1bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1131],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx2bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1134],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx4bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1137],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx8bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1140],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx16bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1143],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx32bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1146],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx64bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1149],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx1bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1152],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx2bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1155],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx4bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1158],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx8bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1161],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx16bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1164],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx32bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1167],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:674 */
  {
    "*movvnx64bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[1170],
    2,
    3,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:819 */
  {
    "vsetvlsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vsetvlsi },
    &operand_data[1173],
    6,
    6,
    7,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:819 */
  {
    "vsetvldi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vsetvldi },
    &operand_data[1179],
    6,
    6,
    7,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:846 */
  {
    "vsetvl_vtype_change_only",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vsetvl_vtype_change_only },
    &operand_data[1175],
    4,
    4,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:861 */
  {
    "vsetvl_discard_resultsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vsetvl_discard_resultsi },
    &operand_data[1174],
    5,
    5,
    2,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:861 */
  {
    "vsetvl_discard_resultdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vsetvl_discard_resultdi },
    &operand_data[1180],
    5,
    5,
    2,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:883 */
  {
    "vsetvlsi_no_side_effects",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vsetvlsi_no_side_effects },
    &operand_data[1173],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:883 */
  {
    "vsetvldi_no_side_effects",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "#",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vsetvldi_no_side_effects },
    &operand_data[1179],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_800 },
#else
    { 0, output_800, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx1qi },
    &operand_data[1185],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_801 },
#else
    { 0, output_801, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx2qi },
    &operand_data[1193],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_802 },
#else
    { 0, output_802, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx4qi },
    &operand_data[1201],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_803 },
#else
    { 0, output_803, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx8qi },
    &operand_data[1209],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_804 },
#else
    { 0, output_804, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx16qi },
    &operand_data[1217],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_805 },
#else
    { 0, output_805, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx32qi },
    &operand_data[1225],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_806 },
#else
    { 0, output_806, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx64qi },
    &operand_data[1233],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_807 },
#else
    { 0, output_807, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx1hi },
    &operand_data[1241],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_808 },
#else
    { 0, output_808, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx2hi },
    &operand_data[1249],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_809 },
#else
    { 0, output_809, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx4hi },
    &operand_data[1257],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_810 },
#else
    { 0, output_810, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx8hi },
    &operand_data[1265],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_811 },
#else
    { 0, output_811, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx16hi },
    &operand_data[1273],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_812 },
#else
    { 0, output_812, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx32hi },
    &operand_data[1281],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_813 },
#else
    { 0, output_813, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx1si },
    &operand_data[1289],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_814 },
#else
    { 0, output_814, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx2si },
    &operand_data[1297],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_815 },
#else
    { 0, output_815, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx4si },
    &operand_data[1305],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_816 },
#else
    { 0, output_816, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx8si },
    &operand_data[1313],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_817 },
#else
    { 0, output_817, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx16si },
    &operand_data[1321],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_818 },
#else
    { 0, output_818, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx1di },
    &operand_data[1329],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_819 },
#else
    { 0, output_819, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx2di },
    &operand_data[1337],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_820 },
#else
    { 0, output_820, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx4di },
    &operand_data[1345],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_821 },
#else
    { 0, output_821, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx8di },
    &operand_data[1353],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_822 },
#else
    { 0, output_822, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx1sf },
    &operand_data[1361],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_823 },
#else
    { 0, output_823, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx2sf },
    &operand_data[1369],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_824 },
#else
    { 0, output_824, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx4sf },
    &operand_data[1377],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_825 },
#else
    { 0, output_825, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx8sf },
    &operand_data[1385],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_826 },
#else
    { 0, output_826, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx16sf },
    &operand_data[1393],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_827 },
#else
    { 0, output_827, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx1df },
    &operand_data[1401],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_828 },
#else
    { 0, output_828, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx2df },
    &operand_data[1409],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_829 },
#else
    { 0, output_829, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx4df },
    &operand_data[1417],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:971 */
  {
    "pred_movvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_830 },
#else
    { 0, output_830, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx8df },
    &operand_data[1425],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse8.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx1qi },
    &operand_data[1433],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse8.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx2qi },
    &operand_data[1437],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse8.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx4qi },
    &operand_data[1441],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse8.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx8qi },
    &operand_data[1445],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse8.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx16qi },
    &operand_data[1449],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse8.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx32qi },
    &operand_data[1453],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse8.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx64qi },
    &operand_data[1457],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse16.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx1hi },
    &operand_data[1461],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse16.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx2hi },
    &operand_data[1465],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse16.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx4hi },
    &operand_data[1469],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse16.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx8hi },
    &operand_data[1473],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse16.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx16hi },
    &operand_data[1477],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse16.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx32hi },
    &operand_data[1481],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse32.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx1si },
    &operand_data[1485],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse32.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx2si },
    &operand_data[1489],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse32.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx4si },
    &operand_data[1493],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse32.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx8si },
    &operand_data[1497],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse32.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx16si },
    &operand_data[1501],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse64.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx1di },
    &operand_data[1505],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse64.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx2di },
    &operand_data[1509],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse64.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx4di },
    &operand_data[1513],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse64.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx8di },
    &operand_data[1517],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse32.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx1sf },
    &operand_data[1521],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse32.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx2sf },
    &operand_data[1525],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse32.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx4sf },
    &operand_data[1529],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse32.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx8sf },
    &operand_data[1533],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse32.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx16sf },
    &operand_data[1537],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse64.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx1df },
    &operand_data[1541],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse64.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx2df },
    &operand_data[1545],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse64.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx4df },
    &operand_data[1549],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1006 */
  {
    "pred_storevnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vse64.v\t%2,%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx8df },
    &operand_data[1553],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
  {
    "pred_movvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_862 },
#else
    { 0, output_862, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx1bi },
    &operand_data[1557],
    6,
    6,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
  {
    "pred_movvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_863 },
#else
    { 0, output_863, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx2bi },
    &operand_data[1563],
    6,
    6,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
  {
    "pred_movvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_864 },
#else
    { 0, output_864, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx4bi },
    &operand_data[1569],
    6,
    6,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
  {
    "pred_movvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_865 },
#else
    { 0, output_865, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx8bi },
    &operand_data[1575],
    6,
    6,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
  {
    "pred_movvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_866 },
#else
    { 0, output_866, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx16bi },
    &operand_data[1581],
    6,
    6,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
  {
    "pred_movvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_867 },
#else
    { 0, output_867, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx32bi },
    &operand_data[1587],
    6,
    6,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1028 */
  {
    "pred_movvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_868 },
#else
    { 0, output_868, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_movvnx64bi },
    &operand_data[1593],
    6,
    6,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
  {
    "pred_storevnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsm.v\t%2,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx1bi },
    &operand_data[1599],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
  {
    "pred_storevnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsm.v\t%2,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx2bi },
    &operand_data[1603],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
  {
    "pred_storevnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsm.v\t%2,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx4bi },
    &operand_data[1607],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
  {
    "pred_storevnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsm.v\t%2,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx8bi },
    &operand_data[1611],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
  {
    "pred_storevnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsm.v\t%2,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx16bi },
    &operand_data[1615],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
  {
    "pred_storevnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsm.v\t%2,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx32bi },
    &operand_data[1619],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1056 */
  {
    "pred_storevnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsm.v\t%2,%0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_storevnx64bi },
    &operand_data[1623],
    4,
    4,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx1qi },
    &operand_data[1627],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx2qi },
    &operand_data[1635],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx4qi },
    &operand_data[1643],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx8qi },
    &operand_data[1651],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx16qi },
    &operand_data[1659],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx32qi },
    &operand_data[1667],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx64qi },
    &operand_data[1675],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx1hi },
    &operand_data[1683],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx2hi },
    &operand_data[1691],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx4hi },
    &operand_data[1699],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx8hi },
    &operand_data[1707],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx16hi },
    &operand_data[1715],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx32hi },
    &operand_data[1723],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx1si },
    &operand_data[1731],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx2si },
    &operand_data[1739],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx4si },
    &operand_data[1747],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx8si },
    &operand_data[1755],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx16si },
    &operand_data[1763],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx1di },
    &operand_data[1771],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx2di },
    &operand_data[1779],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx4di },
    &operand_data[1787],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx8di },
    &operand_data[1795],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx1sf },
    &operand_data[1803],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx2sf },
    &operand_data[1811],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx4sf },
    &operand_data[1819],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx8sf },
    &operand_data[1827],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx16sf },
    &operand_data[1835],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx1df },
    &operand_data[1843],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx2df },
    &operand_data[1851],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx4df },
    &operand_data[1859],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1073 */
  {
    "pred_mergevnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx8df },
    &operand_data[1867],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx1qi_scalar },
    &operand_data[1875],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx2qi_scalar },
    &operand_data[1883],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx4qi_scalar },
    &operand_data[1891],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx8qi_scalar },
    &operand_data[1899],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx16qi_scalar },
    &operand_data[1907],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx32qi_scalar },
    &operand_data[1915],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx64qi_scalar },
    &operand_data[1923],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx1hi_scalar },
    &operand_data[1931],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx2hi_scalar },
    &operand_data[1939],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx4hi_scalar },
    &operand_data[1947],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx8hi_scalar },
    &operand_data[1955],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx16hi_scalar },
    &operand_data[1963],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx32hi_scalar },
    &operand_data[1971],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx1si_scalar },
    &operand_data[1979],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx2si_scalar },
    &operand_data[1987],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx4si_scalar },
    &operand_data[1995],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx8si_scalar },
    &operand_data[2003],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1092 */
  {
    "pred_mergevnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx16si_scalar },
    &operand_data[2011],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1144 */
  {
    "*pred_mergevnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[2019],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1144 */
  {
    "*pred_mergevnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[2027],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1144 */
  {
    "*pred_mergevnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[2035],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1144 */
  {
    "*pred_mergevnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[2043],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1164 */
  {
    "*pred_mergevnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[2051],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1164 */
  {
    "*pred_mergevnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[2059],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1164 */
  {
    "*pred_mergevnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[2067],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1164 */
  {
    "*pred_mergevnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmerge.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[2075],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_933 },
#else
    { 0, output_933, 0 },
#endif
    { 0 },
    &operand_data[2083],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_934 },
#else
    { 0, output_934, 0 },
#endif
    { 0 },
    &operand_data[2091],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_935 },
#else
    { 0, output_935, 0 },
#endif
    { 0 },
    &operand_data[2099],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_936 },
#else
    { 0, output_936, 0 },
#endif
    { 0 },
    &operand_data[2107],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_937 },
#else
    { 0, output_937, 0 },
#endif
    { 0 },
    &operand_data[2115],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_938 },
#else
    { 0, output_938, 0 },
#endif
    { 0 },
    &operand_data[2123],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_939 },
#else
    { 0, output_939, 0 },
#endif
    { 0 },
    &operand_data[2131],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_940 },
#else
    { 0, output_940, 0 },
#endif
    { 0 },
    &operand_data[2139],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_941 },
#else
    { 0, output_941, 0 },
#endif
    { 0 },
    &operand_data[2147],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_942 },
#else
    { 0, output_942, 0 },
#endif
    { 0 },
    &operand_data[2155],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_943 },
#else
    { 0, output_943, 0 },
#endif
    { 0 },
    &operand_data[2163],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_944 },
#else
    { 0, output_944, 0 },
#endif
    { 0 },
    &operand_data[2171],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_945 },
#else
    { 0, output_945, 0 },
#endif
    { 0 },
    &operand_data[2179],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_946 },
#else
    { 0, output_946, 0 },
#endif
    { 0 },
    &operand_data[2187],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_947 },
#else
    { 0, output_947, 0 },
#endif
    { 0 },
    &operand_data[2195],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_948 },
#else
    { 0, output_948, 0 },
#endif
    { 0 },
    &operand_data[2203],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_949 },
#else
    { 0, output_949, 0 },
#endif
    { 0 },
    &operand_data[2211],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_950 },
#else
    { 0, output_950, 0 },
#endif
    { 0 },
    &operand_data[2219],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_951 },
#else
    { 0, output_951, 0 },
#endif
    { 0 },
    &operand_data[2227],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_952 },
#else
    { 0, output_952, 0 },
#endif
    { 0 },
    &operand_data[2235],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_953 },
#else
    { 0, output_953, 0 },
#endif
    { 0 },
    &operand_data[2243],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1246 */
  {
    "*pred_broadcastvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_954 },
#else
    { 0, output_954, 0 },
#endif
    { 0 },
    &operand_data[2251],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1300 */
  {
    "*pred_broadcastvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_955 },
#else
    { 0, output_955, 0 },
#endif
    { 0 },
    &operand_data[2259],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1300 */
  {
    "*pred_broadcastvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_956 },
#else
    { 0, output_956, 0 },
#endif
    { 0 },
    &operand_data[2267],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1300 */
  {
    "*pred_broadcastvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_957 },
#else
    { 0, output_957, 0 },
#endif
    { 0 },
    &operand_data[2275],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1300 */
  {
    "*pred_broadcastvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_958 },
#else
    { 0, output_958, 0 },
#endif
    { 0 },
    &operand_data[2283],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1300 */
  {
    "*pred_broadcastvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_959 },
#else
    { 0, output_959, 0 },
#endif
    { 0 },
    &operand_data[2291],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1300 */
  {
    "*pred_broadcastvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_960 },
#else
    { 0, output_960, 0 },
#endif
    { 0 },
    &operand_data[2299],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1300 */
  {
    "*pred_broadcastvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_961 },
#else
    { 0, output_961, 0 },
#endif
    { 0 },
    &operand_data[2307],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1300 */
  {
    "*pred_broadcastvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_962 },
#else
    { 0, output_962, 0 },
#endif
    { 0 },
    &operand_data[2315],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1300 */
  {
    "*pred_broadcastvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_963 },
#else
    { 0, output_963, 0 },
#endif
    { 0 },
    &operand_data[2323],
    8,
    8,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1327 */
  {
    "*pred_broadcastvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_964 },
#else
    { 0, output_964, 0 },
#endif
    { 0 },
    &operand_data[2331],
    8,
    8,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1327 */
  {
    "*pred_broadcastvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_965 },
#else
    { 0, output_965, 0 },
#endif
    { 0 },
    &operand_data[2339],
    8,
    8,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1327 */
  {
    "*pred_broadcastvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_966 },
#else
    { 0, output_966, 0 },
#endif
    { 0 },
    &operand_data[2347],
    8,
    8,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1327 */
  {
    "*pred_broadcastvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_967 },
#else
    { 0, output_967, 0 },
#endif
    { 0 },
    &operand_data[2355],
    8,
    8,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse8.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx1qi },
    &operand_data[2363],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse8.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx2qi },
    &operand_data[2371],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse8.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx4qi },
    &operand_data[2379],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse8.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx8qi },
    &operand_data[2387],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse8.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx16qi },
    &operand_data[2395],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse8.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx32qi },
    &operand_data[2403],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse8.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx64qi },
    &operand_data[2411],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse16.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx1hi },
    &operand_data[2419],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse16.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx2hi },
    &operand_data[2427],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse16.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx4hi },
    &operand_data[2435],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse16.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx8hi },
    &operand_data[2443],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse16.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx16hi },
    &operand_data[2451],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse16.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx32hi },
    &operand_data[2459],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse32.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx1si },
    &operand_data[2467],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse32.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx2si },
    &operand_data[2475],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse32.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx4si },
    &operand_data[2483],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse32.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx8si },
    &operand_data[2491],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse32.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx16si },
    &operand_data[2499],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse64.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx1di },
    &operand_data[2507],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse64.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx2di },
    &operand_data[2515],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse64.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx4di },
    &operand_data[2523],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse64.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx8di },
    &operand_data[2531],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse32.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx1sf },
    &operand_data[2539],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse32.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx2sf },
    &operand_data[2547],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse32.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx4sf },
    &operand_data[2555],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse32.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx8sf },
    &operand_data[2563],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse32.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx16sf },
    &operand_data[2571],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse64.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx1df },
    &operand_data[2579],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse64.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx2df },
    &operand_data[2587],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse64.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx4df },
    &operand_data[2595],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1358 */
  {
    "pred_strided_loadvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vlse64.v\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_loadvnx8df },
    &operand_data[2603],
    8,
    8,
    0,
    3,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse8.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx1qi },
    &operand_data[2611],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse8.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx2qi },
    &operand_data[2616],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse8.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx4qi },
    &operand_data[2621],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse8.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx8qi },
    &operand_data[2626],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse8.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx16qi },
    &operand_data[2631],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse8.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx32qi },
    &operand_data[2636],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse8.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx64qi },
    &operand_data[2641],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse16.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx1hi },
    &operand_data[2646],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse16.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx2hi },
    &operand_data[2651],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse16.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx4hi },
    &operand_data[2656],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse16.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx8hi },
    &operand_data[2661],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse16.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx16hi },
    &operand_data[2666],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse16.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx32hi },
    &operand_data[2671],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse32.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx1si },
    &operand_data[2676],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse32.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx2si },
    &operand_data[2681],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse32.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx4si },
    &operand_data[2686],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse32.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx8si },
    &operand_data[2691],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse32.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx16si },
    &operand_data[2696],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse64.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx1di },
    &operand_data[2701],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse64.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx2di },
    &operand_data[2706],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse64.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx4di },
    &operand_data[2711],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse64.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx8di },
    &operand_data[2716],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse32.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx1sf },
    &operand_data[2721],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse32.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx2sf },
    &operand_data[2726],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse32.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx4sf },
    &operand_data[2731],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse32.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx8sf },
    &operand_data[2736],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse32.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx16sf },
    &operand_data[2741],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse64.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx1df },
    &operand_data[2746],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse64.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx2df },
    &operand_data[2751],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse64.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx4df },
    &operand_data[2756],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1377 */
  {
    "pred_strided_storevnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsse64.v\t%3,%0,%z2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_strided_storevnx8df },
    &operand_data[2761],
    5,
    5,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx1qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1qi_same_eew },
    &operand_data[2766],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx1qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1qi_same_eew },
    &operand_data[2766],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx2qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2qi_same_eew },
    &operand_data[2775],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx2qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2qi_same_eew },
    &operand_data[2775],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx4qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4qi_same_eew },
    &operand_data[2784],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx4qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4qi_same_eew },
    &operand_data[2784],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx8qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8qi_same_eew },
    &operand_data[2793],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx8qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8qi_same_eew },
    &operand_data[2793],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx16qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx16qi_same_eew },
    &operand_data[2802],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx16qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx16qi_same_eew },
    &operand_data[2802],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx32qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx32qi_same_eew },
    &operand_data[2811],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx32qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx32qi_same_eew },
    &operand_data[2811],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx64qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx64qi_same_eew },
    &operand_data[2820],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx64qi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx64qi_same_eew },
    &operand_data[2820],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx1hi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1hi_same_eew },
    &operand_data[2829],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx1hi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1hi_same_eew },
    &operand_data[2829],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx2hi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2hi_same_eew },
    &operand_data[2838],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx2hi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2hi_same_eew },
    &operand_data[2838],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx4hi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4hi_same_eew },
    &operand_data[2847],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx4hi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4hi_same_eew },
    &operand_data[2847],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx8hi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8hi_same_eew },
    &operand_data[2856],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx8hi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8hi_same_eew },
    &operand_data[2856],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx16hi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx16hi_same_eew },
    &operand_data[2865],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx16hi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx16hi_same_eew },
    &operand_data[2865],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx32hi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx32hi_same_eew },
    &operand_data[2874],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx32hi_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx32hi_same_eew },
    &operand_data[2874],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx1si_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1si_same_eew },
    &operand_data[2883],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx1si_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1si_same_eew },
    &operand_data[2883],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx2si_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2si_same_eew },
    &operand_data[2892],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx2si_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2si_same_eew },
    &operand_data[2892],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx4si_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4si_same_eew },
    &operand_data[2901],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx4si_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4si_same_eew },
    &operand_data[2901],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx8si_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8si_same_eew },
    &operand_data[2910],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx8si_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8si_same_eew },
    &operand_data[2910],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx16si_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx16si_same_eew },
    &operand_data[2919],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx16si_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx16si_same_eew },
    &operand_data[2919],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx1di_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1di_same_eew },
    &operand_data[2928],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx1di_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1di_same_eew },
    &operand_data[2928],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx2di_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2di_same_eew },
    &operand_data[2937],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx2di_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2di_same_eew },
    &operand_data[2937],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx4di_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4di_same_eew },
    &operand_data[2946],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx4di_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4di_same_eew },
    &operand_data[2946],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx8di_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8di_same_eew },
    &operand_data[2955],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx8di_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8di_same_eew },
    &operand_data[2955],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx1sf_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1sf_same_eew },
    &operand_data[2964],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx1sf_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1sf_same_eew },
    &operand_data[2964],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx2sf_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2sf_same_eew },
    &operand_data[2973],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx2sf_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2sf_same_eew },
    &operand_data[2973],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx4sf_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4sf_same_eew },
    &operand_data[2982],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx4sf_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4sf_same_eew },
    &operand_data[2982],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx8sf_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8sf_same_eew },
    &operand_data[2991],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx8sf_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8sf_same_eew },
    &operand_data[2991],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx16sf_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx16sf_same_eew },
    &operand_data[3000],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx16sf_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx16sf_same_eew },
    &operand_data[3000],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx1df_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1df_same_eew },
    &operand_data[3009],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx1df_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1df_same_eew },
    &operand_data[3009],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx2df_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2df_same_eew },
    &operand_data[3018],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx2df_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2df_same_eew },
    &operand_data[3018],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx4df_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4df_same_eew },
    &operand_data[3027],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx4df_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4df_same_eew },
    &operand_data[3027],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_oloadvnx8df_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8df_same_eew },
    &operand_data[3036],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1402 */
  {
    "pred_indexed_uloadvnx8df_same_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8df_same_eew },
    &operand_data[3036],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx1hi_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1hi_x2_greater_eew },
    &operand_data[3045],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx1hi_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1hi_x2_greater_eew },
    &operand_data[3045],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx2hi_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2hi_x2_greater_eew },
    &operand_data[3054],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx2hi_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2hi_x2_greater_eew },
    &operand_data[3054],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx4hi_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4hi_x2_greater_eew },
    &operand_data[3063],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx4hi_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4hi_x2_greater_eew },
    &operand_data[3063],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx8hi_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8hi_x2_greater_eew },
    &operand_data[3072],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx8hi_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8hi_x2_greater_eew },
    &operand_data[3072],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx16hi_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx16hi_x2_greater_eew },
    &operand_data[3081],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx16hi_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx16hi_x2_greater_eew },
    &operand_data[3081],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx32hi_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx32hi_x2_greater_eew },
    &operand_data[3090],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx32hi_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx32hi_x2_greater_eew },
    &operand_data[3090],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx1si_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1si_x2_greater_eew },
    &operand_data[3099],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx1si_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1si_x2_greater_eew },
    &operand_data[3099],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx2si_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2si_x2_greater_eew },
    &operand_data[3108],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx2si_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2si_x2_greater_eew },
    &operand_data[3108],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx4si_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4si_x2_greater_eew },
    &operand_data[3117],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx4si_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4si_x2_greater_eew },
    &operand_data[3117],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx8si_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8si_x2_greater_eew },
    &operand_data[3126],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx8si_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8si_x2_greater_eew },
    &operand_data[3126],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx16si_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx16si_x2_greater_eew },
    &operand_data[3135],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx16si_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx16si_x2_greater_eew },
    &operand_data[3135],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx1di_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1di_x2_greater_eew },
    &operand_data[3144],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx1di_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1di_x2_greater_eew },
    &operand_data[3144],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx2di_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2di_x2_greater_eew },
    &operand_data[3153],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx2di_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2di_x2_greater_eew },
    &operand_data[3153],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx4di_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4di_x2_greater_eew },
    &operand_data[3162],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx4di_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4di_x2_greater_eew },
    &operand_data[3162],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx8di_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8di_x2_greater_eew },
    &operand_data[3171],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx8di_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8di_x2_greater_eew },
    &operand_data[3171],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx1sf_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1sf_x2_greater_eew },
    &operand_data[3180],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx1sf_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1sf_x2_greater_eew },
    &operand_data[3180],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx2sf_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2sf_x2_greater_eew },
    &operand_data[3189],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx2sf_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2sf_x2_greater_eew },
    &operand_data[3189],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx4sf_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4sf_x2_greater_eew },
    &operand_data[3198],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx4sf_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4sf_x2_greater_eew },
    &operand_data[3198],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx8sf_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8sf_x2_greater_eew },
    &operand_data[3207],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx8sf_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8sf_x2_greater_eew },
    &operand_data[3207],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx16sf_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx16sf_x2_greater_eew },
    &operand_data[3216],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx16sf_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx16sf_x2_greater_eew },
    &operand_data[3216],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx1df_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1df_x2_greater_eew },
    &operand_data[3225],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx1df_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1df_x2_greater_eew },
    &operand_data[3225],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx2df_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2df_x2_greater_eew },
    &operand_data[3234],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx2df_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2df_x2_greater_eew },
    &operand_data[3234],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx4df_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4df_x2_greater_eew },
    &operand_data[3243],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx4df_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4df_x2_greater_eew },
    &operand_data[3243],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_oloadvnx8df_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8df_x2_greater_eew },
    &operand_data[3252],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1424 */
  {
    "pred_indexed_uloadvnx8df_x2_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8df_x2_greater_eew },
    &operand_data[3252],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx1si_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1si_x4_greater_eew },
    &operand_data[3261],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx1si_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1si_x4_greater_eew },
    &operand_data[3261],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx2si_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2si_x4_greater_eew },
    &operand_data[3270],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx2si_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2si_x4_greater_eew },
    &operand_data[3270],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx4si_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4si_x4_greater_eew },
    &operand_data[3279],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx4si_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4si_x4_greater_eew },
    &operand_data[3279],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx8si_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8si_x4_greater_eew },
    &operand_data[3288],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx8si_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8si_x4_greater_eew },
    &operand_data[3288],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx16si_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx16si_x4_greater_eew },
    &operand_data[3297],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx16si_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx16si_x4_greater_eew },
    &operand_data[3297],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx1di_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1di_x4_greater_eew },
    &operand_data[3306],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx1di_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1di_x4_greater_eew },
    &operand_data[3306],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx2di_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2di_x4_greater_eew },
    &operand_data[3315],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx2di_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2di_x4_greater_eew },
    &operand_data[3315],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx4di_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4di_x4_greater_eew },
    &operand_data[3324],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx4di_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4di_x4_greater_eew },
    &operand_data[3324],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx8di_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8di_x4_greater_eew },
    &operand_data[3333],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx8di_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8di_x4_greater_eew },
    &operand_data[3333],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx1sf_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1sf_x4_greater_eew },
    &operand_data[3342],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx1sf_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1sf_x4_greater_eew },
    &operand_data[3342],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx2sf_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2sf_x4_greater_eew },
    &operand_data[3351],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx2sf_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2sf_x4_greater_eew },
    &operand_data[3351],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx4sf_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4sf_x4_greater_eew },
    &operand_data[3360],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx4sf_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4sf_x4_greater_eew },
    &operand_data[3360],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx8sf_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8sf_x4_greater_eew },
    &operand_data[3369],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx8sf_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8sf_x4_greater_eew },
    &operand_data[3369],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx16sf_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx16sf_x4_greater_eew },
    &operand_data[3378],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx16sf_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx16sf_x4_greater_eew },
    &operand_data[3378],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx1df_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1df_x4_greater_eew },
    &operand_data[3387],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx1df_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1df_x4_greater_eew },
    &operand_data[3387],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx2df_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2df_x4_greater_eew },
    &operand_data[3396],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx2df_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2df_x4_greater_eew },
    &operand_data[3396],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx4df_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4df_x4_greater_eew },
    &operand_data[3405],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx4df_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4df_x4_greater_eew },
    &operand_data[3405],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_oloadvnx8df_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8df_x4_greater_eew },
    &operand_data[3414],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1445 */
  {
    "pred_indexed_uloadvnx8df_x4_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8df_x4_greater_eew },
    &operand_data[3414],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_oloadvnx1di_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1di_x8_greater_eew },
    &operand_data[3423],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_uloadvnx1di_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1di_x8_greater_eew },
    &operand_data[3423],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_oloadvnx2di_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2di_x8_greater_eew },
    &operand_data[3432],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_uloadvnx2di_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2di_x8_greater_eew },
    &operand_data[3432],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_oloadvnx4di_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4di_x8_greater_eew },
    &operand_data[3441],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_uloadvnx4di_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4di_x8_greater_eew },
    &operand_data[3441],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_oloadvnx8di_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8di_x8_greater_eew },
    &operand_data[3450],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_uloadvnx8di_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8di_x8_greater_eew },
    &operand_data[3450],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_oloadvnx1df_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1df_x8_greater_eew },
    &operand_data[3459],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_uloadvnx1df_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1df_x8_greater_eew },
    &operand_data[3459],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_oloadvnx2df_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2df_x8_greater_eew },
    &operand_data[3468],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_uloadvnx2df_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2df_x8_greater_eew },
    &operand_data[3468],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_oloadvnx4df_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4df_x8_greater_eew },
    &operand_data[3477],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_uloadvnx4df_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4df_x8_greater_eew },
    &operand_data[3477],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_oloadvnx8df_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8df_x8_greater_eew },
    &operand_data[3486],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1466 */
  {
    "pred_indexed_uloadvnx8df_x8_greater_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei8.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8df_x8_greater_eew },
    &operand_data[3486],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx1qi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1qi_x2_smaller_eew },
    &operand_data[3495],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx1qi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1qi_x2_smaller_eew },
    &operand_data[3495],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx2qi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2qi_x2_smaller_eew },
    &operand_data[3504],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx2qi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2qi_x2_smaller_eew },
    &operand_data[3504],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx4qi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4qi_x2_smaller_eew },
    &operand_data[3513],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx4qi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4qi_x2_smaller_eew },
    &operand_data[3513],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx8qi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8qi_x2_smaller_eew },
    &operand_data[3522],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx8qi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8qi_x2_smaller_eew },
    &operand_data[3522],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx16qi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx16qi_x2_smaller_eew },
    &operand_data[3531],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx16qi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx16qi_x2_smaller_eew },
    &operand_data[3531],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx32qi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx32qi_x2_smaller_eew },
    &operand_data[3540],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx32qi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei16.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx32qi_x2_smaller_eew },
    &operand_data[3540],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx1hi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1hi_x2_smaller_eew },
    &operand_data[3549],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx1hi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1hi_x2_smaller_eew },
    &operand_data[3549],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx2hi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2hi_x2_smaller_eew },
    &operand_data[3558],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx2hi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2hi_x2_smaller_eew },
    &operand_data[3558],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx4hi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4hi_x2_smaller_eew },
    &operand_data[3567],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx4hi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4hi_x2_smaller_eew },
    &operand_data[3567],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx8hi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8hi_x2_smaller_eew },
    &operand_data[3576],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx8hi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8hi_x2_smaller_eew },
    &operand_data[3576],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx16hi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx16hi_x2_smaller_eew },
    &operand_data[3585],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx16hi_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx16hi_x2_smaller_eew },
    &operand_data[3585],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx1si_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1si_x2_smaller_eew },
    &operand_data[3594],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx1si_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1si_x2_smaller_eew },
    &operand_data[3594],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx2si_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2si_x2_smaller_eew },
    &operand_data[3603],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx2si_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2si_x2_smaller_eew },
    &operand_data[3603],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx4si_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4si_x2_smaller_eew },
    &operand_data[3612],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx4si_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4si_x2_smaller_eew },
    &operand_data[3612],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx8si_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8si_x2_smaller_eew },
    &operand_data[3621],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx8si_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8si_x2_smaller_eew },
    &operand_data[3621],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx1sf_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1sf_x2_smaller_eew },
    &operand_data[3630],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx1sf_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1sf_x2_smaller_eew },
    &operand_data[3630],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx2sf_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2sf_x2_smaller_eew },
    &operand_data[3639],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx2sf_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2sf_x2_smaller_eew },
    &operand_data[3639],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx4sf_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4sf_x2_smaller_eew },
    &operand_data[3648],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx4sf_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4sf_x2_smaller_eew },
    &operand_data[3648],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_oloadvnx8sf_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8sf_x2_smaller_eew },
    &operand_data[3657],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1488 */
  {
    "pred_indexed_uloadvnx8sf_x2_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8sf_x2_smaller_eew },
    &operand_data[3657],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_oloadvnx1qi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1qi_x4_smaller_eew },
    &operand_data[3666],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_uloadvnx1qi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1qi_x4_smaller_eew },
    &operand_data[3666],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_oloadvnx2qi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2qi_x4_smaller_eew },
    &operand_data[3675],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_uloadvnx2qi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2qi_x4_smaller_eew },
    &operand_data[3675],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_oloadvnx4qi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4qi_x4_smaller_eew },
    &operand_data[3684],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_uloadvnx4qi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4qi_x4_smaller_eew },
    &operand_data[3684],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_oloadvnx8qi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8qi_x4_smaller_eew },
    &operand_data[3693],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_uloadvnx8qi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8qi_x4_smaller_eew },
    &operand_data[3693],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_oloadvnx16qi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx16qi_x4_smaller_eew },
    &operand_data[3702],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_uloadvnx16qi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei32.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx16qi_x4_smaller_eew },
    &operand_data[3702],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_oloadvnx1hi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1hi_x4_smaller_eew },
    &operand_data[3711],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_uloadvnx1hi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1hi_x4_smaller_eew },
    &operand_data[3711],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_oloadvnx2hi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2hi_x4_smaller_eew },
    &operand_data[3720],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_uloadvnx2hi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2hi_x4_smaller_eew },
    &operand_data[3720],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_oloadvnx4hi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4hi_x4_smaller_eew },
    &operand_data[3729],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_uloadvnx4hi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4hi_x4_smaller_eew },
    &operand_data[3729],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_oloadvnx8hi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8hi_x4_smaller_eew },
    &operand_data[3738],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1509 */
  {
    "pred_indexed_uloadvnx8hi_x4_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8hi_x4_smaller_eew },
    &operand_data[3738],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
  {
    "pred_indexed_oloadvnx1qi_x8_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx1qi_x8_smaller_eew },
    &operand_data[3747],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
  {
    "pred_indexed_uloadvnx1qi_x8_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx1qi_x8_smaller_eew },
    &operand_data[3747],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
  {
    "pred_indexed_oloadvnx2qi_x8_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx2qi_x8_smaller_eew },
    &operand_data[3756],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
  {
    "pred_indexed_uloadvnx2qi_x8_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx2qi_x8_smaller_eew },
    &operand_data[3756],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
  {
    "pred_indexed_oloadvnx4qi_x8_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx4qi_x8_smaller_eew },
    &operand_data[3765],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
  {
    "pred_indexed_uloadvnx4qi_x8_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx4qi_x8_smaller_eew },
    &operand_data[3765],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
  {
    "pred_indexed_oloadvnx8qi_x8_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vloxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_oloadvnx8qi_x8_smaller_eew },
    &operand_data[3774],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1530 */
  {
    "pred_indexed_uloadvnx8qi_x8_smaller_eew",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vluxei64.v\t%0,(%3),%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_uloadvnx8qi_x8_smaller_eew },
    &operand_data[3774],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1qivnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1qivnx1qi },
    &operand_data[3783],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1qivnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1qivnx1qi },
    &operand_data[3783],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1qivnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1qivnx1hi },
    &operand_data[3789],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1qivnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1qivnx1hi },
    &operand_data[3789],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1qivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1qivnx1si },
    &operand_data[3795],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1qivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1qivnx1si },
    &operand_data[3795],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1qivnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1qivnx1di },
    &operand_data[3801],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1qivnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1qivnx1di },
    &operand_data[3801],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1hivnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1hivnx1qi },
    &operand_data[3807],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1hivnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1hivnx1qi },
    &operand_data[3807],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1hivnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1hivnx1hi },
    &operand_data[3813],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1hivnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1hivnx1hi },
    &operand_data[3813],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1hivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1hivnx1si },
    &operand_data[3819],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1hivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1hivnx1si },
    &operand_data[3819],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1hivnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1hivnx1di },
    &operand_data[3825],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1hivnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1hivnx1di },
    &operand_data[3825],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1sivnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1sivnx1qi },
    &operand_data[3831],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1sivnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1sivnx1qi },
    &operand_data[3831],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1sivnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1sivnx1hi },
    &operand_data[3837],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1sivnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1sivnx1hi },
    &operand_data[3837],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1sivnx1si },
    &operand_data[3843],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1sivnx1si },
    &operand_data[3843],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1sivnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1sivnx1di },
    &operand_data[3849],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1sivnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1sivnx1di },
    &operand_data[3849],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1divnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1divnx1qi },
    &operand_data[3855],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1divnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1divnx1qi },
    &operand_data[3855],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1divnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1divnx1hi },
    &operand_data[3861],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1divnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1divnx1hi },
    &operand_data[3861],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1divnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1divnx1si },
    &operand_data[3867],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1divnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1divnx1si },
    &operand_data[3867],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1divnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1divnx1di },
    &operand_data[3873],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1divnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1divnx1di },
    &operand_data[3873],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1sfvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1sfvnx1qi },
    &operand_data[3879],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1sfvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1sfvnx1qi },
    &operand_data[3879],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1sfvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1sfvnx1hi },
    &operand_data[3885],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1sfvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1sfvnx1hi },
    &operand_data[3885],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1sfvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1sfvnx1si },
    &operand_data[3891],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1sfvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1sfvnx1si },
    &operand_data[3891],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1sfvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1sfvnx1di },
    &operand_data[3897],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1sfvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1sfvnx1di },
    &operand_data[3897],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1dfvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1dfvnx1qi },
    &operand_data[3903],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1dfvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1dfvnx1qi },
    &operand_data[3903],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1dfvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1dfvnx1hi },
    &operand_data[3909],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1dfvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1dfvnx1hi },
    &operand_data[3909],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1dfvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1dfvnx1si },
    &operand_data[3915],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1dfvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1dfvnx1si },
    &operand_data[3915],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ostorevnx1dfvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx1dfvnx1di },
    &operand_data[3921],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1551 */
  {
    "pred_indexed_ustorevnx1dfvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx1dfvnx1di },
    &operand_data[3921],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2qivnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2qivnx2qi },
    &operand_data[3927],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2qivnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2qivnx2qi },
    &operand_data[3927],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2hivnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2hivnx2qi },
    &operand_data[3933],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2hivnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2hivnx2qi },
    &operand_data[3933],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2sivnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2sivnx2qi },
    &operand_data[3939],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2sivnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2sivnx2qi },
    &operand_data[3939],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2divnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2divnx2qi },
    &operand_data[3945],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2divnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2divnx2qi },
    &operand_data[3945],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2sfvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2sfvnx2qi },
    &operand_data[3951],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2sfvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2sfvnx2qi },
    &operand_data[3951],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2dfvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2dfvnx2qi },
    &operand_data[3957],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2dfvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2dfvnx2qi },
    &operand_data[3957],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2qivnx2hi },
    &operand_data[3963],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2qivnx2hi },
    &operand_data[3963],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2hivnx2hi },
    &operand_data[3969],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2hivnx2hi },
    &operand_data[3969],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2sivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2sivnx2hi },
    &operand_data[3975],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2sivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2sivnx2hi },
    &operand_data[3975],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2divnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2divnx2hi },
    &operand_data[3981],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2divnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2divnx2hi },
    &operand_data[3981],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2sfvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2sfvnx2hi },
    &operand_data[3987],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2sfvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2sfvnx2hi },
    &operand_data[3987],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2dfvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2dfvnx2hi },
    &operand_data[3993],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2dfvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2dfvnx2hi },
    &operand_data[3993],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2qivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2qivnx2si },
    &operand_data[3999],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2qivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2qivnx2si },
    &operand_data[3999],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2hivnx2si },
    &operand_data[4005],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2hivnx2si },
    &operand_data[4005],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2sivnx2si },
    &operand_data[4011],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2sivnx2si },
    &operand_data[4011],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2divnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2divnx2si },
    &operand_data[4017],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2divnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2divnx2si },
    &operand_data[4017],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2sfvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2sfvnx2si },
    &operand_data[4023],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2sfvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2sfvnx2si },
    &operand_data[4023],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2dfvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2dfvnx2si },
    &operand_data[4029],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2dfvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2dfvnx2si },
    &operand_data[4029],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2qivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2qivnx2di },
    &operand_data[4035],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2qivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2qivnx2di },
    &operand_data[4035],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2hivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2hivnx2di },
    &operand_data[4041],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2hivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2hivnx2di },
    &operand_data[4041],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2sivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2sivnx2di },
    &operand_data[4047],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2sivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2sivnx2di },
    &operand_data[4047],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2divnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2divnx2di },
    &operand_data[4053],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2divnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2divnx2di },
    &operand_data[4053],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2sfvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2sfvnx2di },
    &operand_data[4059],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2sfvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2sfvnx2di },
    &operand_data[4059],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ostorevnx2dfvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx2dfvnx2di },
    &operand_data[4065],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1568 */
  {
    "pred_indexed_ustorevnx2dfvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx2dfvnx2di },
    &operand_data[4065],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4qivnx4qi },
    &operand_data[4071],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4qivnx4qi },
    &operand_data[4071],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4hivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4hivnx4qi },
    &operand_data[4077],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4hivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4hivnx4qi },
    &operand_data[4077],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4sivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4sivnx4qi },
    &operand_data[4083],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4sivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4sivnx4qi },
    &operand_data[4083],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4divnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4divnx4qi },
    &operand_data[4089],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4divnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4divnx4qi },
    &operand_data[4089],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4sfvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4sfvnx4qi },
    &operand_data[4095],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4sfvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4sfvnx4qi },
    &operand_data[4095],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4dfvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4dfvnx4qi },
    &operand_data[4101],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4dfvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4dfvnx4qi },
    &operand_data[4101],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4qivnx4hi },
    &operand_data[4107],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4qivnx4hi },
    &operand_data[4107],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4hivnx4hi },
    &operand_data[4113],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4hivnx4hi },
    &operand_data[4113],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4sivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4sivnx4hi },
    &operand_data[4119],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4sivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4sivnx4hi },
    &operand_data[4119],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4divnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4divnx4hi },
    &operand_data[4125],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4divnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4divnx4hi },
    &operand_data[4125],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4sfvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4sfvnx4hi },
    &operand_data[4131],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4sfvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4sfvnx4hi },
    &operand_data[4131],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4dfvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4dfvnx4hi },
    &operand_data[4137],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4dfvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4dfvnx4hi },
    &operand_data[4137],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4qivnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4qivnx4si },
    &operand_data[4143],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4qivnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4qivnx4si },
    &operand_data[4143],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4hivnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4hivnx4si },
    &operand_data[4149],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4hivnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4hivnx4si },
    &operand_data[4149],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4sivnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4sivnx4si },
    &operand_data[4155],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4sivnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4sivnx4si },
    &operand_data[4155],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4divnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4divnx4si },
    &operand_data[4161],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4divnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4divnx4si },
    &operand_data[4161],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4sfvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4sfvnx4si },
    &operand_data[4167],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4sfvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4sfvnx4si },
    &operand_data[4167],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4dfvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4dfvnx4si },
    &operand_data[4173],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4dfvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4dfvnx4si },
    &operand_data[4173],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4qivnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4qivnx4di },
    &operand_data[4179],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4qivnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4qivnx4di },
    &operand_data[4179],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4hivnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4hivnx4di },
    &operand_data[4185],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4hivnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4hivnx4di },
    &operand_data[4185],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4sivnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4sivnx4di },
    &operand_data[4191],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4sivnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4sivnx4di },
    &operand_data[4191],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4divnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4divnx4di },
    &operand_data[4197],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4divnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4divnx4di },
    &operand_data[4197],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4sfvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4sfvnx4di },
    &operand_data[4203],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4sfvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4sfvnx4di },
    &operand_data[4203],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ostorevnx4dfvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx4dfvnx4di },
    &operand_data[4209],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1585 */
  {
    "pred_indexed_ustorevnx4dfvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx4dfvnx4di },
    &operand_data[4209],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8qivnx8qi },
    &operand_data[4215],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8qivnx8qi },
    &operand_data[4215],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8hivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8hivnx8qi },
    &operand_data[4221],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8hivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8hivnx8qi },
    &operand_data[4221],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8sivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8sivnx8qi },
    &operand_data[4227],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8sivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8sivnx8qi },
    &operand_data[4227],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8divnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8divnx8qi },
    &operand_data[4233],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8divnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8divnx8qi },
    &operand_data[4233],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8sfvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8sfvnx8qi },
    &operand_data[4239],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8sfvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8sfvnx8qi },
    &operand_data[4239],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8dfvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8dfvnx8qi },
    &operand_data[4245],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8dfvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8dfvnx8qi },
    &operand_data[4245],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8qivnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8qivnx8hi },
    &operand_data[4251],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8qivnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8qivnx8hi },
    &operand_data[4251],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8hivnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8hivnx8hi },
    &operand_data[4257],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8hivnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8hivnx8hi },
    &operand_data[4257],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8sivnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8sivnx8hi },
    &operand_data[4263],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8sivnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8sivnx8hi },
    &operand_data[4263],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8divnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8divnx8hi },
    &operand_data[4269],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8divnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8divnx8hi },
    &operand_data[4269],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8sfvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8sfvnx8hi },
    &operand_data[4275],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8sfvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8sfvnx8hi },
    &operand_data[4275],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8dfvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8dfvnx8hi },
    &operand_data[4281],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8dfvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8dfvnx8hi },
    &operand_data[4281],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8qivnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8qivnx8si },
    &operand_data[4287],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8qivnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8qivnx8si },
    &operand_data[4287],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8hivnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8hivnx8si },
    &operand_data[4293],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8hivnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8hivnx8si },
    &operand_data[4293],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8sivnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8sivnx8si },
    &operand_data[4299],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8sivnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8sivnx8si },
    &operand_data[4299],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8divnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8divnx8si },
    &operand_data[4305],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8divnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8divnx8si },
    &operand_data[4305],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8sfvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8sfvnx8si },
    &operand_data[4311],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8sfvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8sfvnx8si },
    &operand_data[4311],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8dfvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8dfvnx8si },
    &operand_data[4317],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8dfvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8dfvnx8si },
    &operand_data[4317],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8qivnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8qivnx8di },
    &operand_data[4323],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8qivnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8qivnx8di },
    &operand_data[4323],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8hivnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8hivnx8di },
    &operand_data[4329],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8hivnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8hivnx8di },
    &operand_data[4329],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8sivnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8sivnx8di },
    &operand_data[4335],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8sivnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8sivnx8di },
    &operand_data[4335],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8divnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8divnx8di },
    &operand_data[4341],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8divnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8divnx8di },
    &operand_data[4341],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8sfvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8sfvnx8di },
    &operand_data[4347],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8sfvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8sfvnx8di },
    &operand_data[4347],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ostorevnx8dfvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx8dfvnx8di },
    &operand_data[4353],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1602 */
  {
    "pred_indexed_ustorevnx8dfvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei64.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx8dfvnx8di },
    &operand_data[4353],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ostorevnx16qivnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx16qivnx16qi },
    &operand_data[4359],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ustorevnx16qivnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx16qivnx16qi },
    &operand_data[4359],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ostorevnx16hivnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx16hivnx16qi },
    &operand_data[4365],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ustorevnx16hivnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx16hivnx16qi },
    &operand_data[4365],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ostorevnx16sivnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx16sivnx16qi },
    &operand_data[4371],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ustorevnx16sivnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx16sivnx16qi },
    &operand_data[4371],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ostorevnx16sfvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx16sfvnx16qi },
    &operand_data[4377],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ustorevnx16sfvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx16sfvnx16qi },
    &operand_data[4377],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ostorevnx16qivnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx16qivnx16hi },
    &operand_data[4383],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ustorevnx16qivnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx16qivnx16hi },
    &operand_data[4383],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ostorevnx16hivnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx16hivnx16hi },
    &operand_data[4389],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ustorevnx16hivnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx16hivnx16hi },
    &operand_data[4389],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ostorevnx16sivnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx16sivnx16hi },
    &operand_data[4395],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ustorevnx16sivnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx16sivnx16hi },
    &operand_data[4395],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ostorevnx16sfvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx16sfvnx16hi },
    &operand_data[4401],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ustorevnx16sfvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx16sfvnx16hi },
    &operand_data[4401],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ostorevnx16qivnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx16qivnx16si },
    &operand_data[4407],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ustorevnx16qivnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx16qivnx16si },
    &operand_data[4407],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ostorevnx16hivnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx16hivnx16si },
    &operand_data[4413],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ustorevnx16hivnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx16hivnx16si },
    &operand_data[4413],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ostorevnx16sivnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx16sivnx16si },
    &operand_data[4419],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ustorevnx16sivnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx16sivnx16si },
    &operand_data[4419],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ostorevnx16sfvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx16sfvnx16si },
    &operand_data[4425],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1619 */
  {
    "pred_indexed_ustorevnx16sfvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei32.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx16sfvnx16si },
    &operand_data[4425],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
  {
    "pred_indexed_ostorevnx32qivnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx32qivnx32qi },
    &operand_data[4431],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
  {
    "pred_indexed_ustorevnx32qivnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx32qivnx32qi },
    &operand_data[4431],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
  {
    "pred_indexed_ostorevnx32qivnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx32qivnx32hi },
    &operand_data[4437],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
  {
    "pred_indexed_ustorevnx32qivnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx32qivnx32hi },
    &operand_data[4437],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
  {
    "pred_indexed_ostorevnx32hivnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx32hivnx32qi },
    &operand_data[4443],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
  {
    "pred_indexed_ustorevnx32hivnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx32hivnx32qi },
    &operand_data[4443],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
  {
    "pred_indexed_ostorevnx32hivnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx32hivnx32hi },
    &operand_data[4449],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1636 */
  {
    "pred_indexed_ustorevnx32hivnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei16.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx32hivnx32hi },
    &operand_data[4449],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1653 */
  {
    "pred_indexed_ostorevnx64qivnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsoxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ostorevnx64qivnx64qi },
    &operand_data[4455],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1653 */
  {
    "pred_indexed_ustorevnx64qivnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsuxei8.v\t%3,(%1),%2%p0",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_indexed_ustorevnx64qivnx64qi },
    &operand_data[4455],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1482 },
#else
    { 0, output_1482, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx1qi },
    &operand_data[4461],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1483 },
#else
    { 0, output_1483, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1qi },
    &operand_data[4470],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1484 },
#else
    { 0, output_1484, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx1qi },
    &operand_data[4461],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1485 },
#else
    { 0, output_1485, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx1qi },
    &operand_data[4461],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1486 },
#else
    { 0, output_1486, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx1qi },
    &operand_data[4461],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1487 },
#else
    { 0, output_1487, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx1qi },
    &operand_data[4479],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1488 },
#else
    { 0, output_1488, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx1qi },
    &operand_data[4479],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1489 },
#else
    { 0, output_1489, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx1qi },
    &operand_data[4479],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1490 },
#else
    { 0, output_1490, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx1qi },
    &operand_data[4488],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1491 },
#else
    { 0, output_1491, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx1qi },
    &operand_data[4488],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1492 },
#else
    { 0, output_1492, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx1qi },
    &operand_data[4488],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1493 },
#else
    { 0, output_1493, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx1qi },
    &operand_data[4488],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1494 },
#else
    { 0, output_1494, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx1qi },
    &operand_data[4488],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1495 },
#else
    { 0, output_1495, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1qi },
    &operand_data[4488],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1496 },
#else
    { 0, output_1496, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx1qi },
    &operand_data[4488],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1497 },
#else
    { 0, output_1497, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx1qi },
    &operand_data[4488],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1498 },
#else
    { 0, output_1498, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx1qi },
    &operand_data[4488],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1499 },
#else
    { 0, output_1499, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx2qi },
    &operand_data[4497],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1500 },
#else
    { 0, output_1500, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2qi },
    &operand_data[4506],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1501 },
#else
    { 0, output_1501, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx2qi },
    &operand_data[4497],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1502 },
#else
    { 0, output_1502, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx2qi },
    &operand_data[4497],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1503 },
#else
    { 0, output_1503, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx2qi },
    &operand_data[4497],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1504 },
#else
    { 0, output_1504, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx2qi },
    &operand_data[4515],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1505 },
#else
    { 0, output_1505, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx2qi },
    &operand_data[4515],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1506 },
#else
    { 0, output_1506, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx2qi },
    &operand_data[4515],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1507 },
#else
    { 0, output_1507, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx2qi },
    &operand_data[4524],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1508 },
#else
    { 0, output_1508, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx2qi },
    &operand_data[4524],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1509 },
#else
    { 0, output_1509, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx2qi },
    &operand_data[4524],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1510 },
#else
    { 0, output_1510, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx2qi },
    &operand_data[4524],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1511 },
#else
    { 0, output_1511, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx2qi },
    &operand_data[4524],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1512 },
#else
    { 0, output_1512, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2qi },
    &operand_data[4524],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1513 },
#else
    { 0, output_1513, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx2qi },
    &operand_data[4524],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1514 },
#else
    { 0, output_1514, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx2qi },
    &operand_data[4524],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1515 },
#else
    { 0, output_1515, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx2qi },
    &operand_data[4524],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1516 },
#else
    { 0, output_1516, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx4qi },
    &operand_data[4533],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1517 },
#else
    { 0, output_1517, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4qi },
    &operand_data[4542],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1518 },
#else
    { 0, output_1518, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx4qi },
    &operand_data[4533],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1519 },
#else
    { 0, output_1519, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx4qi },
    &operand_data[4533],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1520 },
#else
    { 0, output_1520, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx4qi },
    &operand_data[4533],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1521 },
#else
    { 0, output_1521, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx4qi },
    &operand_data[4551],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1522 },
#else
    { 0, output_1522, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx4qi },
    &operand_data[4551],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1523 },
#else
    { 0, output_1523, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx4qi },
    &operand_data[4551],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1524 },
#else
    { 0, output_1524, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx4qi },
    &operand_data[4560],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1525 },
#else
    { 0, output_1525, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx4qi },
    &operand_data[4560],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1526 },
#else
    { 0, output_1526, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx4qi },
    &operand_data[4560],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1527 },
#else
    { 0, output_1527, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx4qi },
    &operand_data[4560],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1528 },
#else
    { 0, output_1528, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx4qi },
    &operand_data[4560],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1529 },
#else
    { 0, output_1529, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4qi },
    &operand_data[4560],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1530 },
#else
    { 0, output_1530, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx4qi },
    &operand_data[4560],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1531 },
#else
    { 0, output_1531, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx4qi },
    &operand_data[4560],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1532 },
#else
    { 0, output_1532, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx4qi },
    &operand_data[4560],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1533 },
#else
    { 0, output_1533, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx8qi },
    &operand_data[4569],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1534 },
#else
    { 0, output_1534, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8qi },
    &operand_data[4578],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1535 },
#else
    { 0, output_1535, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx8qi },
    &operand_data[4569],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1536 },
#else
    { 0, output_1536, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx8qi },
    &operand_data[4569],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1537 },
#else
    { 0, output_1537, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx8qi },
    &operand_data[4569],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1538 },
#else
    { 0, output_1538, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx8qi },
    &operand_data[4587],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1539 },
#else
    { 0, output_1539, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx8qi },
    &operand_data[4587],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1540 },
#else
    { 0, output_1540, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx8qi },
    &operand_data[4587],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1541 },
#else
    { 0, output_1541, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx8qi },
    &operand_data[4596],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1542 },
#else
    { 0, output_1542, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx8qi },
    &operand_data[4596],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1543 },
#else
    { 0, output_1543, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx8qi },
    &operand_data[4596],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1544 },
#else
    { 0, output_1544, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx8qi },
    &operand_data[4596],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1545 },
#else
    { 0, output_1545, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx8qi },
    &operand_data[4596],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1546 },
#else
    { 0, output_1546, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8qi },
    &operand_data[4596],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1547 },
#else
    { 0, output_1547, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx8qi },
    &operand_data[4596],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1548 },
#else
    { 0, output_1548, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx8qi },
    &operand_data[4596],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1549 },
#else
    { 0, output_1549, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx8qi },
    &operand_data[4596],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1550 },
#else
    { 0, output_1550, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx16qi },
    &operand_data[4605],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1551 },
#else
    { 0, output_1551, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx16qi },
    &operand_data[4614],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1552 },
#else
    { 0, output_1552, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx16qi },
    &operand_data[4605],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1553 },
#else
    { 0, output_1553, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx16qi },
    &operand_data[4605],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1554 },
#else
    { 0, output_1554, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx16qi },
    &operand_data[4605],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1555 },
#else
    { 0, output_1555, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx16qi },
    &operand_data[4623],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1556 },
#else
    { 0, output_1556, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx16qi },
    &operand_data[4623],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1557 },
#else
    { 0, output_1557, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx16qi },
    &operand_data[4623],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1558 },
#else
    { 0, output_1558, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx16qi },
    &operand_data[4632],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1559 },
#else
    { 0, output_1559, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx16qi },
    &operand_data[4632],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1560 },
#else
    { 0, output_1560, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx16qi },
    &operand_data[4632],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1561 },
#else
    { 0, output_1561, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx16qi },
    &operand_data[4632],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1562 },
#else
    { 0, output_1562, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx16qi },
    &operand_data[4632],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1563 },
#else
    { 0, output_1563, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx16qi },
    &operand_data[4632],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1564 },
#else
    { 0, output_1564, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx16qi },
    &operand_data[4632],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1565 },
#else
    { 0, output_1565, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx16qi },
    &operand_data[4632],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1566 },
#else
    { 0, output_1566, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx16qi },
    &operand_data[4632],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1567 },
#else
    { 0, output_1567, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx32qi },
    &operand_data[4641],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1568 },
#else
    { 0, output_1568, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx32qi },
    &operand_data[4650],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1569 },
#else
    { 0, output_1569, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx32qi },
    &operand_data[4641],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1570 },
#else
    { 0, output_1570, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx32qi },
    &operand_data[4641],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1571 },
#else
    { 0, output_1571, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx32qi },
    &operand_data[4641],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1572 },
#else
    { 0, output_1572, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx32qi },
    &operand_data[4659],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1573 },
#else
    { 0, output_1573, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx32qi },
    &operand_data[4659],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1574 },
#else
    { 0, output_1574, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx32qi },
    &operand_data[4659],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1575 },
#else
    { 0, output_1575, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx32qi },
    &operand_data[4668],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1576 },
#else
    { 0, output_1576, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx32qi },
    &operand_data[4668],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1577 },
#else
    { 0, output_1577, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx32qi },
    &operand_data[4668],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1578 },
#else
    { 0, output_1578, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx32qi },
    &operand_data[4668],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1579 },
#else
    { 0, output_1579, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx32qi },
    &operand_data[4668],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1580 },
#else
    { 0, output_1580, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx32qi },
    &operand_data[4668],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1581 },
#else
    { 0, output_1581, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx32qi },
    &operand_data[4668],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1582 },
#else
    { 0, output_1582, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx32qi },
    &operand_data[4668],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1583 },
#else
    { 0, output_1583, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx32qi },
    &operand_data[4668],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1584 },
#else
    { 0, output_1584, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx64qi },
    &operand_data[4677],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1585 },
#else
    { 0, output_1585, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx64qi },
    &operand_data[4686],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1586 },
#else
    { 0, output_1586, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx64qi },
    &operand_data[4677],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1587 },
#else
    { 0, output_1587, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx64qi },
    &operand_data[4677],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1588 },
#else
    { 0, output_1588, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx64qi },
    &operand_data[4677],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1589 },
#else
    { 0, output_1589, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx64qi },
    &operand_data[4695],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1590 },
#else
    { 0, output_1590, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx64qi },
    &operand_data[4695],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1591 },
#else
    { 0, output_1591, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx64qi },
    &operand_data[4695],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1592 },
#else
    { 0, output_1592, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx64qi },
    &operand_data[4704],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1593 },
#else
    { 0, output_1593, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx64qi },
    &operand_data[4704],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1594 },
#else
    { 0, output_1594, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx64qi },
    &operand_data[4704],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1595 },
#else
    { 0, output_1595, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx64qi },
    &operand_data[4704],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1596 },
#else
    { 0, output_1596, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx64qi },
    &operand_data[4704],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1597 },
#else
    { 0, output_1597, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx64qi },
    &operand_data[4704],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1598 },
#else
    { 0, output_1598, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx64qi },
    &operand_data[4704],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1599 },
#else
    { 0, output_1599, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx64qi },
    &operand_data[4704],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1600 },
#else
    { 0, output_1600, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx64qi },
    &operand_data[4704],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1601 },
#else
    { 0, output_1601, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx1hi },
    &operand_data[4713],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1602 },
#else
    { 0, output_1602, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1hi },
    &operand_data[4722],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1603 },
#else
    { 0, output_1603, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx1hi },
    &operand_data[4713],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1604 },
#else
    { 0, output_1604, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx1hi },
    &operand_data[4713],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1605 },
#else
    { 0, output_1605, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx1hi },
    &operand_data[4713],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1606 },
#else
    { 0, output_1606, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx1hi },
    &operand_data[4731],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1607 },
#else
    { 0, output_1607, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx1hi },
    &operand_data[4731],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1608 },
#else
    { 0, output_1608, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx1hi },
    &operand_data[4731],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1609 },
#else
    { 0, output_1609, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx1hi },
    &operand_data[4740],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1610 },
#else
    { 0, output_1610, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx1hi },
    &operand_data[4740],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1611 },
#else
    { 0, output_1611, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx1hi },
    &operand_data[4740],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1612 },
#else
    { 0, output_1612, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx1hi },
    &operand_data[4740],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1613 },
#else
    { 0, output_1613, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx1hi },
    &operand_data[4740],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1614 },
#else
    { 0, output_1614, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1hi },
    &operand_data[4740],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1615 },
#else
    { 0, output_1615, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx1hi },
    &operand_data[4740],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1616 },
#else
    { 0, output_1616, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx1hi },
    &operand_data[4740],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1617 },
#else
    { 0, output_1617, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx1hi },
    &operand_data[4740],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1618 },
#else
    { 0, output_1618, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx2hi },
    &operand_data[4749],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1619 },
#else
    { 0, output_1619, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2hi },
    &operand_data[4758],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1620 },
#else
    { 0, output_1620, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx2hi },
    &operand_data[4749],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1621 },
#else
    { 0, output_1621, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx2hi },
    &operand_data[4749],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1622 },
#else
    { 0, output_1622, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx2hi },
    &operand_data[4749],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1623 },
#else
    { 0, output_1623, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx2hi },
    &operand_data[4767],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1624 },
#else
    { 0, output_1624, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx2hi },
    &operand_data[4767],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1625 },
#else
    { 0, output_1625, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx2hi },
    &operand_data[4767],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1626 },
#else
    { 0, output_1626, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx2hi },
    &operand_data[4776],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1627 },
#else
    { 0, output_1627, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx2hi },
    &operand_data[4776],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1628 },
#else
    { 0, output_1628, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx2hi },
    &operand_data[4776],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1629 },
#else
    { 0, output_1629, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx2hi },
    &operand_data[4776],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1630 },
#else
    { 0, output_1630, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx2hi },
    &operand_data[4776],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1631 },
#else
    { 0, output_1631, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2hi },
    &operand_data[4776],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1632 },
#else
    { 0, output_1632, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx2hi },
    &operand_data[4776],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1633 },
#else
    { 0, output_1633, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx2hi },
    &operand_data[4776],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1634 },
#else
    { 0, output_1634, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx2hi },
    &operand_data[4776],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1635 },
#else
    { 0, output_1635, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx4hi },
    &operand_data[4785],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1636 },
#else
    { 0, output_1636, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4hi },
    &operand_data[4794],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1637 },
#else
    { 0, output_1637, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx4hi },
    &operand_data[4785],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1638 },
#else
    { 0, output_1638, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx4hi },
    &operand_data[4785],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1639 },
#else
    { 0, output_1639, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx4hi },
    &operand_data[4785],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1640 },
#else
    { 0, output_1640, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx4hi },
    &operand_data[4803],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1641 },
#else
    { 0, output_1641, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx4hi },
    &operand_data[4803],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1642 },
#else
    { 0, output_1642, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx4hi },
    &operand_data[4803],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1643 },
#else
    { 0, output_1643, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx4hi },
    &operand_data[4812],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1644 },
#else
    { 0, output_1644, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx4hi },
    &operand_data[4812],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1645 },
#else
    { 0, output_1645, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx4hi },
    &operand_data[4812],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1646 },
#else
    { 0, output_1646, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx4hi },
    &operand_data[4812],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1647 },
#else
    { 0, output_1647, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx4hi },
    &operand_data[4812],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1648 },
#else
    { 0, output_1648, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4hi },
    &operand_data[4812],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1649 },
#else
    { 0, output_1649, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx4hi },
    &operand_data[4812],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1650 },
#else
    { 0, output_1650, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx4hi },
    &operand_data[4812],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1651 },
#else
    { 0, output_1651, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx4hi },
    &operand_data[4812],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1652 },
#else
    { 0, output_1652, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx8hi },
    &operand_data[4821],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1653 },
#else
    { 0, output_1653, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8hi },
    &operand_data[4830],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1654 },
#else
    { 0, output_1654, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx8hi },
    &operand_data[4821],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1655 },
#else
    { 0, output_1655, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx8hi },
    &operand_data[4821],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1656 },
#else
    { 0, output_1656, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx8hi },
    &operand_data[4821],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1657 },
#else
    { 0, output_1657, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx8hi },
    &operand_data[4839],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1658 },
#else
    { 0, output_1658, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx8hi },
    &operand_data[4839],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1659 },
#else
    { 0, output_1659, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx8hi },
    &operand_data[4839],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1660 },
#else
    { 0, output_1660, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx8hi },
    &operand_data[4848],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1661 },
#else
    { 0, output_1661, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx8hi },
    &operand_data[4848],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1662 },
#else
    { 0, output_1662, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx8hi },
    &operand_data[4848],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1663 },
#else
    { 0, output_1663, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx8hi },
    &operand_data[4848],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1664 },
#else
    { 0, output_1664, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx8hi },
    &operand_data[4848],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1665 },
#else
    { 0, output_1665, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8hi },
    &operand_data[4848],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1666 },
#else
    { 0, output_1666, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx8hi },
    &operand_data[4848],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1667 },
#else
    { 0, output_1667, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx8hi },
    &operand_data[4848],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1668 },
#else
    { 0, output_1668, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx8hi },
    &operand_data[4848],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1669 },
#else
    { 0, output_1669, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx16hi },
    &operand_data[4857],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1670 },
#else
    { 0, output_1670, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx16hi },
    &operand_data[4866],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1671 },
#else
    { 0, output_1671, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx16hi },
    &operand_data[4857],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1672 },
#else
    { 0, output_1672, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx16hi },
    &operand_data[4857],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1673 },
#else
    { 0, output_1673, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx16hi },
    &operand_data[4857],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1674 },
#else
    { 0, output_1674, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx16hi },
    &operand_data[4875],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1675 },
#else
    { 0, output_1675, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx16hi },
    &operand_data[4875],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1676 },
#else
    { 0, output_1676, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx16hi },
    &operand_data[4875],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1677 },
#else
    { 0, output_1677, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx16hi },
    &operand_data[4884],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1678 },
#else
    { 0, output_1678, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx16hi },
    &operand_data[4884],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1679 },
#else
    { 0, output_1679, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx16hi },
    &operand_data[4884],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1680 },
#else
    { 0, output_1680, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx16hi },
    &operand_data[4884],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1681 },
#else
    { 0, output_1681, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx16hi },
    &operand_data[4884],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1682 },
#else
    { 0, output_1682, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx16hi },
    &operand_data[4884],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1683 },
#else
    { 0, output_1683, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx16hi },
    &operand_data[4884],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1684 },
#else
    { 0, output_1684, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx16hi },
    &operand_data[4884],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1685 },
#else
    { 0, output_1685, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx16hi },
    &operand_data[4884],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1686 },
#else
    { 0, output_1686, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx32hi },
    &operand_data[4893],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1687 },
#else
    { 0, output_1687, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx32hi },
    &operand_data[4902],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1688 },
#else
    { 0, output_1688, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx32hi },
    &operand_data[4893],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1689 },
#else
    { 0, output_1689, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx32hi },
    &operand_data[4893],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1690 },
#else
    { 0, output_1690, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx32hi },
    &operand_data[4893],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1691 },
#else
    { 0, output_1691, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx32hi },
    &operand_data[4911],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1692 },
#else
    { 0, output_1692, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx32hi },
    &operand_data[4911],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1693 },
#else
    { 0, output_1693, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx32hi },
    &operand_data[4911],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1694 },
#else
    { 0, output_1694, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx32hi },
    &operand_data[4920],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1695 },
#else
    { 0, output_1695, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx32hi },
    &operand_data[4920],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1696 },
#else
    { 0, output_1696, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx32hi },
    &operand_data[4920],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1697 },
#else
    { 0, output_1697, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx32hi },
    &operand_data[4920],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1698 },
#else
    { 0, output_1698, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx32hi },
    &operand_data[4920],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1699 },
#else
    { 0, output_1699, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx32hi },
    &operand_data[4920],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1700 },
#else
    { 0, output_1700, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx32hi },
    &operand_data[4920],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1701 },
#else
    { 0, output_1701, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx32hi },
    &operand_data[4920],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1702 },
#else
    { 0, output_1702, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx32hi },
    &operand_data[4920],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1703 },
#else
    { 0, output_1703, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx1si },
    &operand_data[4929],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1704 },
#else
    { 0, output_1704, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1si },
    &operand_data[4938],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1705 },
#else
    { 0, output_1705, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx1si },
    &operand_data[4929],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1706 },
#else
    { 0, output_1706, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx1si },
    &operand_data[4929],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1707 },
#else
    { 0, output_1707, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx1si },
    &operand_data[4929],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1708 },
#else
    { 0, output_1708, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx1si },
    &operand_data[4947],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1709 },
#else
    { 0, output_1709, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx1si },
    &operand_data[4947],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1710 },
#else
    { 0, output_1710, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx1si },
    &operand_data[4947],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1711 },
#else
    { 0, output_1711, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx1si },
    &operand_data[4956],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1712 },
#else
    { 0, output_1712, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx1si },
    &operand_data[4956],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1713 },
#else
    { 0, output_1713, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx1si },
    &operand_data[4956],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1714 },
#else
    { 0, output_1714, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx1si },
    &operand_data[4956],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1715 },
#else
    { 0, output_1715, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx1si },
    &operand_data[4956],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1716 },
#else
    { 0, output_1716, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1si },
    &operand_data[4956],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1717 },
#else
    { 0, output_1717, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx1si },
    &operand_data[4956],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1718 },
#else
    { 0, output_1718, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx1si },
    &operand_data[4956],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1719 },
#else
    { 0, output_1719, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx1si },
    &operand_data[4956],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1720 },
#else
    { 0, output_1720, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx2si },
    &operand_data[4965],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1721 },
#else
    { 0, output_1721, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2si },
    &operand_data[4974],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1722 },
#else
    { 0, output_1722, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx2si },
    &operand_data[4965],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1723 },
#else
    { 0, output_1723, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx2si },
    &operand_data[4965],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1724 },
#else
    { 0, output_1724, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx2si },
    &operand_data[4965],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1725 },
#else
    { 0, output_1725, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx2si },
    &operand_data[4983],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1726 },
#else
    { 0, output_1726, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx2si },
    &operand_data[4983],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1727 },
#else
    { 0, output_1727, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx2si },
    &operand_data[4983],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1728 },
#else
    { 0, output_1728, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx2si },
    &operand_data[4992],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1729 },
#else
    { 0, output_1729, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx2si },
    &operand_data[4992],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1730 },
#else
    { 0, output_1730, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx2si },
    &operand_data[4992],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1731 },
#else
    { 0, output_1731, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx2si },
    &operand_data[4992],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1732 },
#else
    { 0, output_1732, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx2si },
    &operand_data[4992],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1733 },
#else
    { 0, output_1733, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2si },
    &operand_data[4992],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1734 },
#else
    { 0, output_1734, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx2si },
    &operand_data[4992],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1735 },
#else
    { 0, output_1735, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx2si },
    &operand_data[4992],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1736 },
#else
    { 0, output_1736, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx2si },
    &operand_data[4992],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1737 },
#else
    { 0, output_1737, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx4si },
    &operand_data[5001],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1738 },
#else
    { 0, output_1738, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4si },
    &operand_data[5010],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1739 },
#else
    { 0, output_1739, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx4si },
    &operand_data[5001],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1740 },
#else
    { 0, output_1740, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx4si },
    &operand_data[5001],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1741 },
#else
    { 0, output_1741, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx4si },
    &operand_data[5001],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1742 },
#else
    { 0, output_1742, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx4si },
    &operand_data[5019],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1743 },
#else
    { 0, output_1743, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx4si },
    &operand_data[5019],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1744 },
#else
    { 0, output_1744, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx4si },
    &operand_data[5019],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1745 },
#else
    { 0, output_1745, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx4si },
    &operand_data[5028],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1746 },
#else
    { 0, output_1746, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx4si },
    &operand_data[5028],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1747 },
#else
    { 0, output_1747, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx4si },
    &operand_data[5028],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1748 },
#else
    { 0, output_1748, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx4si },
    &operand_data[5028],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1749 },
#else
    { 0, output_1749, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx4si },
    &operand_data[5028],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1750 },
#else
    { 0, output_1750, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4si },
    &operand_data[5028],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1751 },
#else
    { 0, output_1751, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx4si },
    &operand_data[5028],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1752 },
#else
    { 0, output_1752, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx4si },
    &operand_data[5028],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1753 },
#else
    { 0, output_1753, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx4si },
    &operand_data[5028],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1754 },
#else
    { 0, output_1754, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx8si },
    &operand_data[5037],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1755 },
#else
    { 0, output_1755, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8si },
    &operand_data[5046],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1756 },
#else
    { 0, output_1756, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx8si },
    &operand_data[5037],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1757 },
#else
    { 0, output_1757, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx8si },
    &operand_data[5037],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1758 },
#else
    { 0, output_1758, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx8si },
    &operand_data[5037],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1759 },
#else
    { 0, output_1759, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx8si },
    &operand_data[5055],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1760 },
#else
    { 0, output_1760, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx8si },
    &operand_data[5055],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1761 },
#else
    { 0, output_1761, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx8si },
    &operand_data[5055],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1762 },
#else
    { 0, output_1762, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx8si },
    &operand_data[5064],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1763 },
#else
    { 0, output_1763, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx8si },
    &operand_data[5064],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1764 },
#else
    { 0, output_1764, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx8si },
    &operand_data[5064],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1765 },
#else
    { 0, output_1765, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx8si },
    &operand_data[5064],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1766 },
#else
    { 0, output_1766, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx8si },
    &operand_data[5064],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1767 },
#else
    { 0, output_1767, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8si },
    &operand_data[5064],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1768 },
#else
    { 0, output_1768, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx8si },
    &operand_data[5064],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1769 },
#else
    { 0, output_1769, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx8si },
    &operand_data[5064],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1770 },
#else
    { 0, output_1770, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx8si },
    &operand_data[5064],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1771 },
#else
    { 0, output_1771, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx16si },
    &operand_data[5073],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1772 },
#else
    { 0, output_1772, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx16si },
    &operand_data[5082],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1773 },
#else
    { 0, output_1773, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx16si },
    &operand_data[5073],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1774 },
#else
    { 0, output_1774, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx16si },
    &operand_data[5073],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1775 },
#else
    { 0, output_1775, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx16si },
    &operand_data[5073],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1776 },
#else
    { 0, output_1776, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx16si },
    &operand_data[5091],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1777 },
#else
    { 0, output_1777, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx16si },
    &operand_data[5091],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1778 },
#else
    { 0, output_1778, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx16si },
    &operand_data[5091],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1779 },
#else
    { 0, output_1779, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx16si },
    &operand_data[5100],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1780 },
#else
    { 0, output_1780, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx16si },
    &operand_data[5100],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1781 },
#else
    { 0, output_1781, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx16si },
    &operand_data[5100],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1782 },
#else
    { 0, output_1782, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx16si },
    &operand_data[5100],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1783 },
#else
    { 0, output_1783, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx16si },
    &operand_data[5100],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1784 },
#else
    { 0, output_1784, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx16si },
    &operand_data[5100],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1785 },
#else
    { 0, output_1785, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx16si },
    &operand_data[5100],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1786 },
#else
    { 0, output_1786, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx16si },
    &operand_data[5100],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1787 },
#else
    { 0, output_1787, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx16si },
    &operand_data[5100],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1788 },
#else
    { 0, output_1788, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx1di },
    &operand_data[5109],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1789 },
#else
    { 0, output_1789, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1di },
    &operand_data[5118],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1790 },
#else
    { 0, output_1790, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx1di },
    &operand_data[5109],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1791 },
#else
    { 0, output_1791, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx1di },
    &operand_data[5109],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1792 },
#else
    { 0, output_1792, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx1di },
    &operand_data[5109],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1793 },
#else
    { 0, output_1793, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx1di },
    &operand_data[5127],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1794 },
#else
    { 0, output_1794, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx1di },
    &operand_data[5127],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1795 },
#else
    { 0, output_1795, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx1di },
    &operand_data[5127],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1796 },
#else
    { 0, output_1796, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx1di },
    &operand_data[5136],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1797 },
#else
    { 0, output_1797, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx1di },
    &operand_data[5136],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1798 },
#else
    { 0, output_1798, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx1di },
    &operand_data[5136],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1799 },
#else
    { 0, output_1799, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx1di },
    &operand_data[5136],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1800 },
#else
    { 0, output_1800, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx1di },
    &operand_data[5136],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1801 },
#else
    { 0, output_1801, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1di },
    &operand_data[5136],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1802 },
#else
    { 0, output_1802, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx1di },
    &operand_data[5136],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1803 },
#else
    { 0, output_1803, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx1di },
    &operand_data[5136],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1804 },
#else
    { 0, output_1804, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx1di },
    &operand_data[5136],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1805 },
#else
    { 0, output_1805, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx2di },
    &operand_data[5145],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1806 },
#else
    { 0, output_1806, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2di },
    &operand_data[5154],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1807 },
#else
    { 0, output_1807, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx2di },
    &operand_data[5145],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1808 },
#else
    { 0, output_1808, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx2di },
    &operand_data[5145],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1809 },
#else
    { 0, output_1809, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx2di },
    &operand_data[5145],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1810 },
#else
    { 0, output_1810, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx2di },
    &operand_data[5163],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1811 },
#else
    { 0, output_1811, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx2di },
    &operand_data[5163],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1812 },
#else
    { 0, output_1812, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx2di },
    &operand_data[5163],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1813 },
#else
    { 0, output_1813, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx2di },
    &operand_data[5172],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1814 },
#else
    { 0, output_1814, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx2di },
    &operand_data[5172],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1815 },
#else
    { 0, output_1815, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx2di },
    &operand_data[5172],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1816 },
#else
    { 0, output_1816, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx2di },
    &operand_data[5172],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1817 },
#else
    { 0, output_1817, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx2di },
    &operand_data[5172],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1818 },
#else
    { 0, output_1818, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2di },
    &operand_data[5172],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1819 },
#else
    { 0, output_1819, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx2di },
    &operand_data[5172],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1820 },
#else
    { 0, output_1820, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx2di },
    &operand_data[5172],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1821 },
#else
    { 0, output_1821, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx2di },
    &operand_data[5172],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1822 },
#else
    { 0, output_1822, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx4di },
    &operand_data[5181],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1823 },
#else
    { 0, output_1823, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4di },
    &operand_data[5190],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1824 },
#else
    { 0, output_1824, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx4di },
    &operand_data[5181],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1825 },
#else
    { 0, output_1825, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx4di },
    &operand_data[5181],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1826 },
#else
    { 0, output_1826, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx4di },
    &operand_data[5181],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1827 },
#else
    { 0, output_1827, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx4di },
    &operand_data[5199],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1828 },
#else
    { 0, output_1828, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx4di },
    &operand_data[5199],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1829 },
#else
    { 0, output_1829, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx4di },
    &operand_data[5199],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1830 },
#else
    { 0, output_1830, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx4di },
    &operand_data[5208],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1831 },
#else
    { 0, output_1831, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx4di },
    &operand_data[5208],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1832 },
#else
    { 0, output_1832, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx4di },
    &operand_data[5208],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1833 },
#else
    { 0, output_1833, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx4di },
    &operand_data[5208],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1834 },
#else
    { 0, output_1834, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx4di },
    &operand_data[5208],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1835 },
#else
    { 0, output_1835, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4di },
    &operand_data[5208],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1836 },
#else
    { 0, output_1836, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx4di },
    &operand_data[5208],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1837 },
#else
    { 0, output_1837, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx4di },
    &operand_data[5208],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1838 },
#else
    { 0, output_1838, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx4di },
    &operand_data[5208],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_addvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1839 },
#else
    { 0, output_1839, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx8di },
    &operand_data[5217],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_subvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1840 },
#else
    { 0, output_1840, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8di },
    &operand_data[5226],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_andvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1841 },
#else
    { 0, output_1841, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx8di },
    &operand_data[5217],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_iorvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1842 },
#else
    { 0, output_1842, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx8di },
    &operand_data[5217],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_xorvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1843 },
#else
    { 0, output_1843, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx8di },
    &operand_data[5217],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashlvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1844 },
#else
    { 0, output_1844, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx8di },
    &operand_data[5235],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_ashrvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1845 },
#else
    { 0, output_1845, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx8di },
    &operand_data[5235],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_lshrvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1846 },
#else
    { 0, output_1846, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx8di },
    &operand_data[5235],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_smaxvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1847 },
#else
    { 0, output_1847, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx8di },
    &operand_data[5244],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umaxvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1848 },
#else
    { 0, output_1848, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx8di },
    &operand_data[5244],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_sminvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1849 },
#else
    { 0, output_1849, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx8di },
    &operand_data[5244],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_uminvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1850 },
#else
    { 0, output_1850, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx8di },
    &operand_data[5244],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_mulvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1851 },
#else
    { 0, output_1851, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx8di },
    &operand_data[5244],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_divvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1852 },
#else
    { 0, output_1852, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8di },
    &operand_data[5244],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_udivvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1853 },
#else
    { 0, output_1853, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx8di },
    &operand_data[5244],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_modvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1854 },
#else
    { 0, output_1854, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx8di },
    &operand_data[5244],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1683 */
  {
    "pred_umodvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_1855 },
#else
    { 0, output_1855, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx8di },
    &operand_data[5244],
    9,
    9,
    0,
    12,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx1qi_scalar },
    &operand_data[5253],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx1qi_scalar },
    &operand_data[5253],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx1qi_scalar },
    &operand_data[5253],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx2qi_scalar },
    &operand_data[5262],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx2qi_scalar },
    &operand_data[5262],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx2qi_scalar },
    &operand_data[5262],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx4qi_scalar },
    &operand_data[5271],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx4qi_scalar },
    &operand_data[5271],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx4qi_scalar },
    &operand_data[5271],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx8qi_scalar },
    &operand_data[5280],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx8qi_scalar },
    &operand_data[5280],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx8qi_scalar },
    &operand_data[5280],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx16qi_scalar },
    &operand_data[5289],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx16qi_scalar },
    &operand_data[5289],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx16qi_scalar },
    &operand_data[5289],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx32qi_scalar },
    &operand_data[5298],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx32qi_scalar },
    &operand_data[5298],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx32qi_scalar },
    &operand_data[5298],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx64qi_scalar },
    &operand_data[5307],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx64qi_scalar },
    &operand_data[5307],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx64qi_scalar },
    &operand_data[5307],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx1hi_scalar },
    &operand_data[5316],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx1hi_scalar },
    &operand_data[5316],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx1hi_scalar },
    &operand_data[5316],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx2hi_scalar },
    &operand_data[5325],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx2hi_scalar },
    &operand_data[5325],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx2hi_scalar },
    &operand_data[5325],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx4hi_scalar },
    &operand_data[5334],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx4hi_scalar },
    &operand_data[5334],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx4hi_scalar },
    &operand_data[5334],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx8hi_scalar },
    &operand_data[5343],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx8hi_scalar },
    &operand_data[5343],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx8hi_scalar },
    &operand_data[5343],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx16hi_scalar },
    &operand_data[5352],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx16hi_scalar },
    &operand_data[5352],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx16hi_scalar },
    &operand_data[5352],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx32hi_scalar },
    &operand_data[5361],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx32hi_scalar },
    &operand_data[5361],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx32hi_scalar },
    &operand_data[5361],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx1si_scalar },
    &operand_data[5370],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx1si_scalar },
    &operand_data[5370],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx1si_scalar },
    &operand_data[5370],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx2si_scalar },
    &operand_data[5379],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx2si_scalar },
    &operand_data[5379],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx2si_scalar },
    &operand_data[5379],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx4si_scalar },
    &operand_data[5388],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx4si_scalar },
    &operand_data[5388],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx4si_scalar },
    &operand_data[5388],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx8si_scalar },
    &operand_data[5397],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx8si_scalar },
    &operand_data[5397],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx8si_scalar },
    &operand_data[5397],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx16si_scalar },
    &operand_data[5406],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx16si_scalar },
    &operand_data[5406],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx16si_scalar },
    &operand_data[5406],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx1di_scalar },
    &operand_data[5415],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx1di_scalar },
    &operand_data[5415],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx1di_scalar },
    &operand_data[5415],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx2di_scalar },
    &operand_data[5424],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx2di_scalar },
    &operand_data[5424],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx2di_scalar },
    &operand_data[5424],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx4di_scalar },
    &operand_data[5433],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx4di_scalar },
    &operand_data[5433],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx4di_scalar },
    &operand_data[5433],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashlvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsll.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashlvnx8di_scalar },
    &operand_data[5442],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_ashrvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ashrvnx8di_scalar },
    &operand_data[5442],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1719 */
  {
    "pred_lshrvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_lshrvnx8di_scalar },
    &operand_data[5442],
    9,
    9,
    0,
    8,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_addvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_andvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_iorvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_xorvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_smaxvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_umaxvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_sminvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_uminvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1740 */
  {
    "pred_mulvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_subvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_divvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_udivvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_modvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1761 */
  {
    "pred_umodvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx1qi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1qi_reverse_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx2qi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2qi_reverse_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx4qi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4qi_reverse_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx8qi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8qi_reverse_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx16qi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx16qi_reverse_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx32qi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx32qi_reverse_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx64qi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx64qi_reverse_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx1hi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1hi_reverse_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx2hi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2hi_reverse_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx4hi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4hi_reverse_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx8hi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8hi_reverse_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx16hi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx16hi_reverse_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx32hi_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx32hi_reverse_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx1si_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1si_reverse_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx2si_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2si_reverse_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx4si_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4si_reverse_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx8si_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8si_reverse_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1782 */
  {
    "pred_subvnx16si_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx16si_reverse_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_addvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_andvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_iorvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_xorvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_smaxvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_umaxvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_sminvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_uminvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_mulvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_addvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_andvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_iorvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_xorvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_smaxvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_umaxvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_sminvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_uminvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_mulvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_addvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_andvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_iorvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_xorvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_smaxvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_umaxvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_sminvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_uminvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_mulvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_addvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_andvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_iorvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_xorvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_smaxvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_umaxvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_sminvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_uminvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1838 */
  {
    "*pred_mulvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_addvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_andvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_iorvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_xorvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_smaxvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_umaxvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_sminvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_uminvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_mulvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_addvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_andvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_iorvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_xorvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_smaxvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_umaxvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_sminvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_uminvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_mulvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_addvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_andvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_iorvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_xorvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_smaxvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_umaxvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_sminvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_uminvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_mulvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_addvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_andvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vand.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_iorvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_xorvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vxor.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_smaxvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmax.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_umaxvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmaxu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_sminvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmin.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_uminvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vminu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1859 */
  {
    "*pred_mulvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_subvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_divvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_udivvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_modvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_umodvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_subvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_divvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_udivvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_modvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_umodvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_subvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_divvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_udivvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_modvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_umodvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_subvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_divvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_udivvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_modvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1914 */
  {
    "*pred_umodvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_subvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_divvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_udivvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_modvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_umodvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_subvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_divvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_udivvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_modvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_umodvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_subvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_divvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_udivvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_modvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_umodvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_subvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_divvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdiv.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_udivvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vdivu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_modvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrem.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1935 */
  {
    "*pred_umodvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vremu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1990 */
  {
    "*pred_subvnx1di_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1990 */
  {
    "*pred_subvnx2di_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1990 */
  {
    "*pred_subvnx4di_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1990 */
  {
    "*pred_subvnx8di_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2011 */
  {
    "*pred_subvnx1di_extended_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2011 */
  {
    "*pred_subvnx2di_extended_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2011 */
  {
    "*pred_subvnx4di_extended_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2011 */
  {
    "*pred_subvnx8di_extended_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx1qi },
    &operand_data[5685],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx1qi },
    &operand_data[5685],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx1qi },
    &operand_data[5685],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx2qi },
    &operand_data[5694],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx2qi },
    &operand_data[5694],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx2qi },
    &operand_data[5694],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx4qi },
    &operand_data[5703],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx4qi },
    &operand_data[5703],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx4qi },
    &operand_data[5703],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx8qi },
    &operand_data[5712],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx8qi },
    &operand_data[5712],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx8qi },
    &operand_data[5712],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx16qi },
    &operand_data[5721],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx16qi },
    &operand_data[5721],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx16qi },
    &operand_data[5721],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx32qi },
    &operand_data[5730],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx32qi },
    &operand_data[5730],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx32qi },
    &operand_data[5730],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx64qi },
    &operand_data[5739],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx64qi },
    &operand_data[5739],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx64qi },
    &operand_data[5739],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx1hi },
    &operand_data[5748],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx1hi },
    &operand_data[5748],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx1hi },
    &operand_data[5748],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx2hi },
    &operand_data[5757],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx2hi },
    &operand_data[5757],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx2hi },
    &operand_data[5757],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx4hi },
    &operand_data[5766],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx4hi },
    &operand_data[5766],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx4hi },
    &operand_data[5766],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx8hi },
    &operand_data[5775],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx8hi },
    &operand_data[5775],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx8hi },
    &operand_data[5775],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx16hi },
    &operand_data[5784],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx16hi },
    &operand_data[5784],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx16hi },
    &operand_data[5784],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx32hi },
    &operand_data[5793],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx32hi },
    &operand_data[5793],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx32hi },
    &operand_data[5793],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx1si },
    &operand_data[5802],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx1si },
    &operand_data[5802],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx1si },
    &operand_data[5802],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx2si },
    &operand_data[5811],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx2si },
    &operand_data[5811],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx2si },
    &operand_data[5811],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx4si },
    &operand_data[5820],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx4si },
    &operand_data[5820],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx4si },
    &operand_data[5820],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx8si },
    &operand_data[5829],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx8si },
    &operand_data[5829],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx8si },
    &operand_data[5829],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx16si },
    &operand_data[5838],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx16si },
    &operand_data[5838],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx16si },
    &operand_data[5838],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx1di },
    &operand_data[5847],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx1di },
    &operand_data[5847],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx1di },
    &operand_data[5847],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx2di },
    &operand_data[5856],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx2di },
    &operand_data[5856],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx2di },
    &operand_data[5856],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx4di },
    &operand_data[5865],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx4di },
    &operand_data[5865],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx4di },
    &operand_data[5865],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx8di },
    &operand_data[5874],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhuvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx8di },
    &operand_data[5874],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2034 */
  {
    "pred_mulhsuvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx8di },
    &operand_data[5874],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx1qi_scalar },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx2qi_scalar },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx4qi_scalar },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx8qi_scalar },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx16qi_scalar },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx32qi_scalar },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx64qi_scalar },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx1hi_scalar },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx2hi_scalar },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx4hi_scalar },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx8hi_scalar },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx16hi_scalar },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx32hi_scalar },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx1si_scalar },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx2si_scalar },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx4si_scalar },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx8si_scalar },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhuvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2054 */
  {
    "pred_mulhsuvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx16si_scalar },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2108 */
  {
    "*pred_mulhvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2108 */
  {
    "*pred_mulhuvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2108 */
  {
    "*pred_mulhsuvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2108 */
  {
    "*pred_mulhvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2108 */
  {
    "*pred_mulhuvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2108 */
  {
    "*pred_mulhsuvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2108 */
  {
    "*pred_mulhvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2108 */
  {
    "*pred_mulhuvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2108 */
  {
    "*pred_mulhsuvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2108 */
  {
    "*pred_mulhvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2108 */
  {
    "*pred_mulhuvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2108 */
  {
    "*pred_mulhsuvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2129 */
  {
    "*pred_mulhvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2129 */
  {
    "*pred_mulhuvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2129 */
  {
    "*pred_mulhsuvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2129 */
  {
    "*pred_mulhvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2129 */
  {
    "*pred_mulhuvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2129 */
  {
    "*pred_mulhsuvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2129 */
  {
    "*pred_mulhvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2129 */
  {
    "*pred_mulhuvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2129 */
  {
    "*pred_mulhsuvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2129 */
  {
    "*pred_mulhvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulh.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2129 */
  {
    "*pred_mulhuvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2129 */
  {
    "*pred_mulhsuvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmulhsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx1qi },
    &operand_data[1627],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx2qi },
    &operand_data[1635],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx4qi },
    &operand_data[1643],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx8qi },
    &operand_data[1651],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx16qi },
    &operand_data[1659],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx32qi },
    &operand_data[1667],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx64qi },
    &operand_data[1675],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx1hi },
    &operand_data[1683],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx2hi },
    &operand_data[1691],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx4hi },
    &operand_data[1699],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx8hi },
    &operand_data[1707],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx16hi },
    &operand_data[1715],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx32hi },
    &operand_data[1723],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx1si },
    &operand_data[1731],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx2si },
    &operand_data[1739],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx4si },
    &operand_data[1747],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx8si },
    &operand_data[1755],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx16si },
    &operand_data[1763],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx1di },
    &operand_data[1771],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx2di },
    &operand_data[1779],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx4di },
    &operand_data[1787],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2152 */
  {
    "pred_adcvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.v%o3m\t%0,%2,%v3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx8di },
    &operand_data[1795],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx1qi },
    &operand_data[5883],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx2qi },
    &operand_data[5891],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx4qi },
    &operand_data[5899],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx8qi },
    &operand_data[5907],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx16qi },
    &operand_data[5915],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx32qi },
    &operand_data[5923],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx64qi },
    &operand_data[5931],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx1hi },
    &operand_data[5939],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx2hi },
    &operand_data[5947],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx4hi },
    &operand_data[5955],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx8hi },
    &operand_data[5963],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx16hi },
    &operand_data[5971],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx32hi },
    &operand_data[5979],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx1si },
    &operand_data[5987],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx2si },
    &operand_data[5995],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx4si },
    &operand_data[6003],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx8si },
    &operand_data[6011],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx16si },
    &operand_data[6019],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx1di },
    &operand_data[6027],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx2di },
    &operand_data[6035],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx4di },
    &operand_data[6043],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2176 */
  {
    "pred_sbcvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vvm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx8di },
    &operand_data[6051],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx1qi_scalar },
    &operand_data[1875],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx2qi_scalar },
    &operand_data[1883],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx4qi_scalar },
    &operand_data[1891],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx8qi_scalar },
    &operand_data[1899],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx16qi_scalar },
    &operand_data[1907],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx32qi_scalar },
    &operand_data[1915],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx64qi_scalar },
    &operand_data[1923],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx1hi_scalar },
    &operand_data[1931],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx2hi_scalar },
    &operand_data[1939],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx4hi_scalar },
    &operand_data[1947],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx8hi_scalar },
    &operand_data[1955],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx16hi_scalar },
    &operand_data[1963],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx32hi_scalar },
    &operand_data[1971],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx1si_scalar },
    &operand_data[1979],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx2si_scalar },
    &operand_data[1987],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx4si_scalar },
    &operand_data[1995],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx8si_scalar },
    &operand_data[2003],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2200 */
  {
    "pred_adcvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx16si_scalar },
    &operand_data[2011],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx1qi_scalar },
    &operand_data[6059],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx2qi_scalar },
    &operand_data[6067],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx4qi_scalar },
    &operand_data[6075],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx8qi_scalar },
    &operand_data[6083],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx16qi_scalar },
    &operand_data[6091],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx32qi_scalar },
    &operand_data[6099],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx64qi_scalar },
    &operand_data[6107],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx1hi_scalar },
    &operand_data[6115],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx2hi_scalar },
    &operand_data[6123],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx4hi_scalar },
    &operand_data[6131],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx8hi_scalar },
    &operand_data[6139],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx16hi_scalar },
    &operand_data[6147],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx32hi_scalar },
    &operand_data[6155],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx1si_scalar },
    &operand_data[6163],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx2si_scalar },
    &operand_data[6171],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx4si_scalar },
    &operand_data[6179],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx8si_scalar },
    &operand_data[6187],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2225 */
  {
    "pred_sbcvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx16si_scalar },
    &operand_data[6195],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2283 */
  {
    "*pred_adcvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6203],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2283 */
  {
    "*pred_adcvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6211],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2283 */
  {
    "*pred_adcvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6219],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2283 */
  {
    "*pred_adcvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6227],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2308 */
  {
    "*pred_adcvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6235],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2308 */
  {
    "*pred_adcvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6243],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2308 */
  {
    "*pred_adcvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6251],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2308 */
  {
    "*pred_adcvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vadc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6259],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2367 */
  {
    "*pred_sbcvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6203],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2367 */
  {
    "*pred_sbcvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6211],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2367 */
  {
    "*pred_sbcvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6219],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2367 */
  {
    "*pred_sbcvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6227],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2392 */
  {
    "*pred_sbcvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6235],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2392 */
  {
    "*pred_sbcvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6243],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2392 */
  {
    "*pred_sbcvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6251],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2392 */
  {
    "*pred_sbcvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsbc.vxm\t%0,%2,%z3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6259],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1qi },
    &operand_data[6267],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2qi },
    &operand_data[6273],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4qi },
    &operand_data[6279],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8qi },
    &operand_data[6285],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx16qi },
    &operand_data[6291],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx32qi },
    &operand_data[6297],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx64qi },
    &operand_data[6303],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1hi },
    &operand_data[6309],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2hi },
    &operand_data[6315],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4hi },
    &operand_data[6321],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8hi },
    &operand_data[6327],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx16hi },
    &operand_data[6333],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx32hi },
    &operand_data[6339],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1si },
    &operand_data[6345],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2si },
    &operand_data[6351],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4si },
    &operand_data[6357],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8si },
    &operand_data[6363],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx16si },
    &operand_data[6369],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1di },
    &operand_data[6375],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2di },
    &operand_data[6381],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4di },
    &operand_data[6387],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2418 */
  {
    "pred_madcvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2m\t%0,%1,%v2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8di },
    &operand_data[6393],
    6,
    6,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1qi },
    &operand_data[6399],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2qi },
    &operand_data[6405],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4qi },
    &operand_data[6411],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8qi },
    &operand_data[6417],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx16qi },
    &operand_data[6423],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx32qi },
    &operand_data[6429],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx64qi },
    &operand_data[6435],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1hi },
    &operand_data[6441],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2hi },
    &operand_data[6447],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4hi },
    &operand_data[6453],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8hi },
    &operand_data[6459],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx16hi },
    &operand_data[6465],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx32hi },
    &operand_data[6471],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1si },
    &operand_data[6477],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2si },
    &operand_data[6483],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4si },
    &operand_data[6489],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8si },
    &operand_data[6495],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx16si },
    &operand_data[6501],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1di },
    &operand_data[6507],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2di },
    &operand_data[6513],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4di },
    &operand_data[6519],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2437 */
  {
    "pred_msbcvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vvm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8di },
    &operand_data[6525],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1qi_scalar },
    &operand_data[6531],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2qi_scalar },
    &operand_data[6537],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4qi_scalar },
    &operand_data[6543],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8qi_scalar },
    &operand_data[6549],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx16qi_scalar },
    &operand_data[6555],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx32qi_scalar },
    &operand_data[6561],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx64qi_scalar },
    &operand_data[6567],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1hi_scalar },
    &operand_data[6573],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2hi_scalar },
    &operand_data[6579],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4hi_scalar },
    &operand_data[6585],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8hi_scalar },
    &operand_data[6591],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx16hi_scalar },
    &operand_data[6597],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx32hi_scalar },
    &operand_data[6603],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1si_scalar },
    &operand_data[6609],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2si_scalar },
    &operand_data[6615],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4si_scalar },
    &operand_data[6621],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8si_scalar },
    &operand_data[6627],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2456 */
  {
    "pred_madcvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx16si_scalar },
    &operand_data[6633],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1qi_scalar },
    &operand_data[6639],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2qi_scalar },
    &operand_data[6645],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4qi_scalar },
    &operand_data[6651],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8qi_scalar },
    &operand_data[6657],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx16qi_scalar },
    &operand_data[6663],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx32qi_scalar },
    &operand_data[6669],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx64qi_scalar },
    &operand_data[6675],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1hi_scalar },
    &operand_data[6681],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2hi_scalar },
    &operand_data[6687],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4hi_scalar },
    &operand_data[6693],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8hi_scalar },
    &operand_data[6699],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx16hi_scalar },
    &operand_data[6705],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx32hi_scalar },
    &operand_data[6711],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1si_scalar },
    &operand_data[6717],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2si_scalar },
    &operand_data[6723],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4si_scalar },
    &operand_data[6729],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8si_scalar },
    &operand_data[6735],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2476 */
  {
    "pred_msbcvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx16si_scalar },
    &operand_data[6741],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2525 */
  {
    "*pred_madcvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6747],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2525 */
  {
    "*pred_madcvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6753],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2525 */
  {
    "*pred_madcvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6759],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2525 */
  {
    "*pred_madcvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6765],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2545 */
  {
    "*pred_madcvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6771],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2545 */
  {
    "*pred_madcvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6777],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2545 */
  {
    "*pred_madcvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6783],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2545 */
  {
    "*pred_madcvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6789],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2595 */
  {
    "*pred_msbcvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6747],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2595 */
  {
    "*pred_msbcvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6753],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2595 */
  {
    "*pred_msbcvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6759],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2595 */
  {
    "*pred_msbcvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6765],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2615 */
  {
    "*pred_msbcvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6771],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2615 */
  {
    "*pred_msbcvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6777],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2615 */
  {
    "*pred_msbcvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6783],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2615 */
  {
    "*pred_msbcvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vxm\t%0,%1,%z2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[6789],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx1qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1qi_overflow },
    &operand_data[6795],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx2qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2qi_overflow },
    &operand_data[6800],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx4qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4qi_overflow },
    &operand_data[6805],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx8qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8qi_overflow },
    &operand_data[6810],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx16qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx16qi_overflow },
    &operand_data[6815],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx32qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx32qi_overflow },
    &operand_data[6820],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx64qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx64qi_overflow },
    &operand_data[6825],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx1hi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1hi_overflow },
    &operand_data[6830],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx2hi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2hi_overflow },
    &operand_data[6835],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx4hi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4hi_overflow },
    &operand_data[6840],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx8hi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8hi_overflow },
    &operand_data[6845],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx16hi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx16hi_overflow },
    &operand_data[6850],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx32hi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx32hi_overflow },
    &operand_data[6855],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx1si_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1si_overflow },
    &operand_data[6860],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx2si_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2si_overflow },
    &operand_data[6865],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx4si_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4si_overflow },
    &operand_data[6870],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx8si_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8si_overflow },
    &operand_data[6875],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx16si_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx16si_overflow },
    &operand_data[6880],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx1di_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1di_overflow },
    &operand_data[6885],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx2di_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2di_overflow },
    &operand_data[6890],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx4di_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4di_overflow },
    &operand_data[6895],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2636 */
  {
    "pred_madcvnx8di_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.v%o2\t%0,%1,%v2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8di_overflow },
    &operand_data[6900],
    5,
    5,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx1qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1qi_overflow },
    &operand_data[6905],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx2qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2qi_overflow },
    &operand_data[6910],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx4qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4qi_overflow },
    &operand_data[6915],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx8qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8qi_overflow },
    &operand_data[6920],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx16qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx16qi_overflow },
    &operand_data[6925],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx32qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx32qi_overflow },
    &operand_data[6930],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx64qi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx64qi_overflow },
    &operand_data[6935],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx1hi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1hi_overflow },
    &operand_data[6940],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx2hi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2hi_overflow },
    &operand_data[6945],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx4hi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4hi_overflow },
    &operand_data[6950],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx8hi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8hi_overflow },
    &operand_data[6955],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx16hi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx16hi_overflow },
    &operand_data[6960],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx32hi_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx32hi_overflow },
    &operand_data[6965],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx1si_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1si_overflow },
    &operand_data[6970],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx2si_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2si_overflow },
    &operand_data[6975],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx4si_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4si_overflow },
    &operand_data[6980],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx8si_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8si_overflow },
    &operand_data[6985],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx16si_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx16si_overflow },
    &operand_data[6990],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx1di_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1di_overflow },
    &operand_data[6995],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx2di_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2di_overflow },
    &operand_data[7000],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx4di_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4di_overflow },
    &operand_data[7005],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2654 */
  {
    "pred_msbcvnx8di_overflow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vv\t%0,%1,%2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8di_overflow },
    &operand_data[7010],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx1qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1qi_overflow_scalar },
    &operand_data[7015],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx2qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2qi_overflow_scalar },
    &operand_data[7020],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx4qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4qi_overflow_scalar },
    &operand_data[7025],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx8qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8qi_overflow_scalar },
    &operand_data[7030],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx16qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx16qi_overflow_scalar },
    &operand_data[7035],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx32qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx32qi_overflow_scalar },
    &operand_data[7040],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx64qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx64qi_overflow_scalar },
    &operand_data[7045],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx1hi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1hi_overflow_scalar },
    &operand_data[7050],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx2hi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2hi_overflow_scalar },
    &operand_data[7055],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx4hi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4hi_overflow_scalar },
    &operand_data[7060],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx8hi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8hi_overflow_scalar },
    &operand_data[7065],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx16hi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx16hi_overflow_scalar },
    &operand_data[7070],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx32hi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx32hi_overflow_scalar },
    &operand_data[7075],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx1si_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1si_overflow_scalar },
    &operand_data[7080],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx2si_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2si_overflow_scalar },
    &operand_data[7085],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx4si_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4si_overflow_scalar },
    &operand_data[7090],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx8si_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8si_overflow_scalar },
    &operand_data[7095],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2672 */
  {
    "pred_madcvnx16si_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx16si_overflow_scalar },
    &operand_data[7100],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx1qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1qi_overflow_scalar },
    &operand_data[7015],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx2qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2qi_overflow_scalar },
    &operand_data[7020],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx4qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4qi_overflow_scalar },
    &operand_data[7025],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx8qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8qi_overflow_scalar },
    &operand_data[7030],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx16qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx16qi_overflow_scalar },
    &operand_data[7035],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx32qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx32qi_overflow_scalar },
    &operand_data[7040],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx64qi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx64qi_overflow_scalar },
    &operand_data[7045],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx1hi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1hi_overflow_scalar },
    &operand_data[7050],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx2hi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2hi_overflow_scalar },
    &operand_data[7055],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx4hi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4hi_overflow_scalar },
    &operand_data[7060],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx8hi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8hi_overflow_scalar },
    &operand_data[7065],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx16hi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx16hi_overflow_scalar },
    &operand_data[7070],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx32hi_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx32hi_overflow_scalar },
    &operand_data[7075],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx1si_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1si_overflow_scalar },
    &operand_data[7080],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx2si_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2si_overflow_scalar },
    &operand_data[7085],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx4si_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4si_overflow_scalar },
    &operand_data[7090],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx8si_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8si_overflow_scalar },
    &operand_data[7095],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2691 */
  {
    "pred_msbcvnx16si_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx16si_overflow_scalar },
    &operand_data[7100],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2738 */
  {
    "*pred_madcvnx1di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7105],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2738 */
  {
    "*pred_madcvnx2di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7110],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2738 */
  {
    "*pred_madcvnx4di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7115],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2738 */
  {
    "*pred_madcvnx8di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7120],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2757 */
  {
    "*pred_madcvnx1di_overflow_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7125],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2757 */
  {
    "*pred_madcvnx2di_overflow_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7130],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2757 */
  {
    "*pred_madcvnx4di_overflow_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7135],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2757 */
  {
    "*pred_madcvnx8di_overflow_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmadc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7140],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2805 */
  {
    "*pred_msbcvnx1di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7105],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2805 */
  {
    "*pred_msbcvnx2di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7110],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2805 */
  {
    "*pred_msbcvnx4di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7115],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2805 */
  {
    "*pred_msbcvnx8di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7120],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2824 */
  {
    "*pred_msbcvnx1di_overflow_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7125],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2824 */
  {
    "*pred_msbcvnx2di_overflow_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7130],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2824 */
  {
    "*pred_msbcvnx4di_overflow_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7135],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2824 */
  {
    "*pred_msbcvnx8di_overflow_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbc.vx\t%0,%1,%z2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[7140],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx1qi },
    &operand_data[7145],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx1qi },
    &operand_data[7145],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx2qi },
    &operand_data[7153],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx2qi },
    &operand_data[7153],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx4qi },
    &operand_data[7161],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx4qi },
    &operand_data[7161],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx8qi },
    &operand_data[7169],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx8qi },
    &operand_data[7169],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx16qi },
    &operand_data[7177],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx16qi },
    &operand_data[7177],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx32qi },
    &operand_data[7185],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx32qi },
    &operand_data[7185],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx64qi },
    &operand_data[7193],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx64qi },
    &operand_data[7193],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx1hi },
    &operand_data[7201],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx1hi },
    &operand_data[7201],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx2hi },
    &operand_data[7209],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx2hi },
    &operand_data[7209],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx4hi },
    &operand_data[7217],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx4hi },
    &operand_data[7217],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx8hi },
    &operand_data[7225],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx8hi },
    &operand_data[7225],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx16hi },
    &operand_data[7233],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx16hi },
    &operand_data[7233],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx32hi },
    &operand_data[7241],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx32hi },
    &operand_data[7241],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx1si },
    &operand_data[7249],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx1si },
    &operand_data[7249],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx2si },
    &operand_data[7257],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx2si },
    &operand_data[7257],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx4si },
    &operand_data[7265],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx4si },
    &operand_data[7265],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx8si },
    &operand_data[7273],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx8si },
    &operand_data[7273],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx16si },
    &operand_data[7281],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx16si },
    &operand_data[7281],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx1di },
    &operand_data[7289],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx1di },
    &operand_data[7289],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx2di },
    &operand_data[7297],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx2di },
    &operand_data[7297],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx4di },
    &operand_data[7305],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx4di },
    &operand_data[7305],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_negvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx8di },
    &operand_data[7313],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2851 */
  {
    "pred_one_cmplvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnot.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_one_cmplvnx8di },
    &operand_data[7313],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx1hi_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx1hi_vf2 },
    &operand_data[7321],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx1hi_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx1hi_vf2 },
    &operand_data[7321],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx2hi_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx2hi_vf2 },
    &operand_data[7329],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx2hi_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx2hi_vf2 },
    &operand_data[7329],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx4hi_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx4hi_vf2 },
    &operand_data[7337],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx4hi_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx4hi_vf2 },
    &operand_data[7337],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx8hi_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx8hi_vf2 },
    &operand_data[7345],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx8hi_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx8hi_vf2 },
    &operand_data[7345],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx16hi_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx16hi_vf2 },
    &operand_data[7353],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx16hi_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx16hi_vf2 },
    &operand_data[7353],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx32hi_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx32hi_vf2 },
    &operand_data[7361],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx32hi_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx32hi_vf2 },
    &operand_data[7361],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx1si_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx1si_vf2 },
    &operand_data[7369],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx1si_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx1si_vf2 },
    &operand_data[7369],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx2si_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx2si_vf2 },
    &operand_data[7377],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx2si_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx2si_vf2 },
    &operand_data[7377],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx4si_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx4si_vf2 },
    &operand_data[7385],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx4si_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx4si_vf2 },
    &operand_data[7385],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx8si_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx8si_vf2 },
    &operand_data[7393],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx8si_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx8si_vf2 },
    &operand_data[7393],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx16si_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx16si_vf2 },
    &operand_data[7401],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx16si_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx16si_vf2 },
    &operand_data[7401],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx1di_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx1di_vf2 },
    &operand_data[7409],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx1di_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx1di_vf2 },
    &operand_data[7409],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx2di_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx2di_vf2 },
    &operand_data[7417],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx2di_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx2di_vf2 },
    &operand_data[7417],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx4di_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx4di_vf2 },
    &operand_data[7425],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx4di_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx4di_vf2 },
    &operand_data[7425],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_extendvnx8di_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx8di_vf2 },
    &operand_data[7433],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2884 */
  {
    "pred_zero_extendvnx8di_vf2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf2\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx8di_vf2 },
    &operand_data[7433],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_extendvnx1si_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx1si_vf4 },
    &operand_data[7441],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_zero_extendvnx1si_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx1si_vf4 },
    &operand_data[7441],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_extendvnx2si_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx2si_vf4 },
    &operand_data[7449],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_zero_extendvnx2si_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx2si_vf4 },
    &operand_data[7449],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_extendvnx4si_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx4si_vf4 },
    &operand_data[7457],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_zero_extendvnx4si_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx4si_vf4 },
    &operand_data[7457],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_extendvnx8si_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx8si_vf4 },
    &operand_data[7465],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_zero_extendvnx8si_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx8si_vf4 },
    &operand_data[7465],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_extendvnx16si_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx16si_vf4 },
    &operand_data[7473],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_zero_extendvnx16si_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx16si_vf4 },
    &operand_data[7473],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_extendvnx1di_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx1di_vf4 },
    &operand_data[7481],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_zero_extendvnx1di_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx1di_vf4 },
    &operand_data[7481],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_extendvnx2di_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx2di_vf4 },
    &operand_data[7489],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_zero_extendvnx2di_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx2di_vf4 },
    &operand_data[7489],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_extendvnx4di_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx4di_vf4 },
    &operand_data[7497],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_zero_extendvnx4di_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx4di_vf4 },
    &operand_data[7497],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_extendvnx8di_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx8di_vf4 },
    &operand_data[7505],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2904 */
  {
    "pred_zero_extendvnx8di_vf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf4\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx8di_vf4 },
    &operand_data[7505],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
  {
    "pred_extendvnx1di_vf8",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf8\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx1di_vf8 },
    &operand_data[7513],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
  {
    "pred_zero_extendvnx1di_vf8",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf8\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx1di_vf8 },
    &operand_data[7513],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
  {
    "pred_extendvnx2di_vf8",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf8\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx2di_vf8 },
    &operand_data[7521],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
  {
    "pred_zero_extendvnx2di_vf8",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf8\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx2di_vf8 },
    &operand_data[7521],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
  {
    "pred_extendvnx4di_vf8",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf8\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx4di_vf8 },
    &operand_data[7529],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
  {
    "pred_zero_extendvnx4di_vf8",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf8\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx4di_vf8 },
    &operand_data[7529],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
  {
    "pred_extendvnx8di_vf8",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsext.vf8\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx8di_vf8 },
    &operand_data[7537],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2924 */
  {
    "pred_zero_extendvnx8di_vf8",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vzext.vf8\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx8di_vf8 },
    &operand_data[7537],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx1hi },
    &operand_data[7545],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx1hi },
    &operand_data[7545],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx1hi },
    &operand_data[7545],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx1hi },
    &operand_data[7545],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx1hi },
    &operand_data[7545],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx1hi },
    &operand_data[7545],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx2hi },
    &operand_data[7554],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx2hi },
    &operand_data[7554],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx2hi },
    &operand_data[7554],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx2hi },
    &operand_data[7554],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx2hi },
    &operand_data[7554],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx2hi },
    &operand_data[7554],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx4hi },
    &operand_data[7563],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx4hi },
    &operand_data[7563],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx4hi },
    &operand_data[7563],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx4hi },
    &operand_data[7563],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx4hi },
    &operand_data[7563],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx4hi },
    &operand_data[7563],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx8hi },
    &operand_data[7572],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx8hi },
    &operand_data[7572],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx8hi },
    &operand_data[7572],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx8hi },
    &operand_data[7572],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx8hi },
    &operand_data[7572],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx8hi },
    &operand_data[7572],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx16hi },
    &operand_data[7581],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx16hi },
    &operand_data[7581],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx16hi },
    &operand_data[7581],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx16hi },
    &operand_data[7581],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx16hi },
    &operand_data[7581],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx16hi },
    &operand_data[7581],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx32hi },
    &operand_data[7590],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx32hi },
    &operand_data[7590],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx32hi },
    &operand_data[7590],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx32hi },
    &operand_data[7590],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx32hi },
    &operand_data[7590],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx32hi },
    &operand_data[7590],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx1si },
    &operand_data[7599],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx1si },
    &operand_data[7599],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx1si },
    &operand_data[7599],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx1si },
    &operand_data[7599],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx1si },
    &operand_data[7599],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx1si },
    &operand_data[7599],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx2si },
    &operand_data[7608],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx2si },
    &operand_data[7608],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx2si },
    &operand_data[7608],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx2si },
    &operand_data[7608],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx2si },
    &operand_data[7608],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx2si },
    &operand_data[7608],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx4si },
    &operand_data[7617],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx4si },
    &operand_data[7617],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx4si },
    &operand_data[7617],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx4si },
    &operand_data[7617],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx4si },
    &operand_data[7617],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx4si },
    &operand_data[7617],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx8si },
    &operand_data[7626],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx8si },
    &operand_data[7626],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx8si },
    &operand_data[7626],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx8si },
    &operand_data[7626],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx8si },
    &operand_data[7626],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx8si },
    &operand_data[7626],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx16si },
    &operand_data[7635],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx16si },
    &operand_data[7635],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx16si },
    &operand_data[7635],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx16si },
    &operand_data[7635],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx16si },
    &operand_data[7635],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx16si },
    &operand_data[7635],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx1di },
    &operand_data[7644],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx1di },
    &operand_data[7644],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx1di },
    &operand_data[7644],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx1di },
    &operand_data[7644],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx1di },
    &operand_data[7644],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx1di },
    &operand_data[7644],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx2di },
    &operand_data[7653],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx2di },
    &operand_data[7653],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx2di },
    &operand_data[7653],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx2di },
    &operand_data[7653],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx2di },
    &operand_data[7653],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx2di },
    &operand_data[7653],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx4di },
    &operand_data[7662],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx4di },
    &operand_data[7662],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx4di },
    &operand_data[7662],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx4di },
    &operand_data[7662],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx4di },
    &operand_data[7662],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx4di },
    &operand_data[7662],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_addsvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx8di },
    &operand_data[7671],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subsvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx8di },
    &operand_data[7671],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_mulsvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx8di },
    &operand_data[7671],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_adduvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx8di },
    &operand_data[7671],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_subuvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx8di },
    &operand_data[7671],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2944 */
  {
    "pred_dual_widen_muluvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx8di },
    &operand_data[7671],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx1hi_scalar },
    &operand_data[7680],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx1hi_scalar },
    &operand_data[7680],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx1hi_scalar },
    &operand_data[7680],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx1hi_scalar },
    &operand_data[7680],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx1hi_scalar },
    &operand_data[7680],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx1hi_scalar },
    &operand_data[7680],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx2hi_scalar },
    &operand_data[7689],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx2hi_scalar },
    &operand_data[7689],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx2hi_scalar },
    &operand_data[7689],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx2hi_scalar },
    &operand_data[7689],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx2hi_scalar },
    &operand_data[7689],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx2hi_scalar },
    &operand_data[7689],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx4hi_scalar },
    &operand_data[7698],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx4hi_scalar },
    &operand_data[7698],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx4hi_scalar },
    &operand_data[7698],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx4hi_scalar },
    &operand_data[7698],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx4hi_scalar },
    &operand_data[7698],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx4hi_scalar },
    &operand_data[7698],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx8hi_scalar },
    &operand_data[7707],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx8hi_scalar },
    &operand_data[7707],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx8hi_scalar },
    &operand_data[7707],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx8hi_scalar },
    &operand_data[7707],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx8hi_scalar },
    &operand_data[7707],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx8hi_scalar },
    &operand_data[7707],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx16hi_scalar },
    &operand_data[7716],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx16hi_scalar },
    &operand_data[7716],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx16hi_scalar },
    &operand_data[7716],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx16hi_scalar },
    &operand_data[7716],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx16hi_scalar },
    &operand_data[7716],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx16hi_scalar },
    &operand_data[7716],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx32hi_scalar },
    &operand_data[7725],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx32hi_scalar },
    &operand_data[7725],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx32hi_scalar },
    &operand_data[7725],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx32hi_scalar },
    &operand_data[7725],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx32hi_scalar },
    &operand_data[7725],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx32hi_scalar },
    &operand_data[7725],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx1si_scalar },
    &operand_data[7734],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx1si_scalar },
    &operand_data[7734],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx1si_scalar },
    &operand_data[7734],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx1si_scalar },
    &operand_data[7734],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx1si_scalar },
    &operand_data[7734],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx1si_scalar },
    &operand_data[7734],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx2si_scalar },
    &operand_data[7743],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx2si_scalar },
    &operand_data[7743],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx2si_scalar },
    &operand_data[7743],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx2si_scalar },
    &operand_data[7743],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx2si_scalar },
    &operand_data[7743],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx2si_scalar },
    &operand_data[7743],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx4si_scalar },
    &operand_data[7752],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx4si_scalar },
    &operand_data[7752],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx4si_scalar },
    &operand_data[7752],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx4si_scalar },
    &operand_data[7752],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx4si_scalar },
    &operand_data[7752],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx4si_scalar },
    &operand_data[7752],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx8si_scalar },
    &operand_data[7761],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx8si_scalar },
    &operand_data[7761],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx8si_scalar },
    &operand_data[7761],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx8si_scalar },
    &operand_data[7761],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx8si_scalar },
    &operand_data[7761],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx8si_scalar },
    &operand_data[7761],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx16si_scalar },
    &operand_data[7770],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx16si_scalar },
    &operand_data[7770],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx16si_scalar },
    &operand_data[7770],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx16si_scalar },
    &operand_data[7770],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx16si_scalar },
    &operand_data[7770],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx16si_scalar },
    &operand_data[7770],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx1di_scalar },
    &operand_data[7779],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx1di_scalar },
    &operand_data[7779],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx1di_scalar },
    &operand_data[7779],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx1di_scalar },
    &operand_data[7779],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx1di_scalar },
    &operand_data[7779],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx1di_scalar },
    &operand_data[7779],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx2di_scalar },
    &operand_data[7788],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx2di_scalar },
    &operand_data[7788],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx2di_scalar },
    &operand_data[7788],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx2di_scalar },
    &operand_data[7788],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx2di_scalar },
    &operand_data[7788],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx2di_scalar },
    &operand_data[7788],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx4di_scalar },
    &operand_data[7797],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx4di_scalar },
    &operand_data[7797],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx4di_scalar },
    &operand_data[7797],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx4di_scalar },
    &operand_data[7797],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx4di_scalar },
    &operand_data[7797],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx4di_scalar },
    &operand_data[7797],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_addsvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addsvnx8di_scalar },
    &operand_data[7806],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subsvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subsvnx8di_scalar },
    &operand_data[7806],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_mulsvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulsvnx8di_scalar },
    &operand_data[7806],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_adduvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_adduvnx8di_scalar },
    &operand_data[7806],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_subuvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subuvnx8di_scalar },
    &operand_data[7806],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2966 */
  {
    "pred_dual_widen_muluvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_muluvnx8di_scalar },
    &operand_data[7806],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx1hi },
    &operand_data[7815],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx1hi },
    &operand_data[7815],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx1hi },
    &operand_data[7815],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx1hi },
    &operand_data[7815],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx2hi },
    &operand_data[7824],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx2hi },
    &operand_data[7824],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx2hi },
    &operand_data[7824],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx2hi },
    &operand_data[7824],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx4hi },
    &operand_data[7833],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx4hi },
    &operand_data[7833],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx4hi },
    &operand_data[7833],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx4hi },
    &operand_data[7833],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx8hi },
    &operand_data[7842],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx8hi },
    &operand_data[7842],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx8hi },
    &operand_data[7842],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx8hi },
    &operand_data[7842],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx16hi },
    &operand_data[7851],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx16hi },
    &operand_data[7851],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx16hi },
    &operand_data[7851],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx16hi },
    &operand_data[7851],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx32hi },
    &operand_data[7860],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx32hi },
    &operand_data[7860],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx32hi },
    &operand_data[7860],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx32hi },
    &operand_data[7860],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx1si },
    &operand_data[7869],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx1si },
    &operand_data[7869],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx1si },
    &operand_data[7869],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx1si },
    &operand_data[7869],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx2si },
    &operand_data[7878],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx2si },
    &operand_data[7878],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx2si },
    &operand_data[7878],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx2si },
    &operand_data[7878],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx4si },
    &operand_data[7887],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx4si },
    &operand_data[7887],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx4si },
    &operand_data[7887],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx4si },
    &operand_data[7887],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx8si },
    &operand_data[7896],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx8si },
    &operand_data[7896],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx8si },
    &operand_data[7896],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx8si },
    &operand_data[7896],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx16si },
    &operand_data[7905],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx16si },
    &operand_data[7905],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx16si },
    &operand_data[7905],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx16si },
    &operand_data[7905],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx1di },
    &operand_data[7914],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx1di },
    &operand_data[7914],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx1di },
    &operand_data[7914],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx1di },
    &operand_data[7914],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx2di },
    &operand_data[7923],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx2di },
    &operand_data[7923],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx2di },
    &operand_data[7923],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx2di },
    &operand_data[7923],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx4di },
    &operand_data[7932],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx4di },
    &operand_data[7932],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx4di },
    &operand_data[7932],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx4di },
    &operand_data[7932],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_addsvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx8di },
    &operand_data[7941],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subsvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx8di },
    &operand_data[7941],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_adduvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx8di },
    &operand_data[7941],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2989 */
  {
    "pred_single_widen_subuvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx8di },
    &operand_data[7941],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx1hi_scalar },
    &operand_data[7950],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx1hi_scalar },
    &operand_data[7950],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx1hi_scalar },
    &operand_data[7950],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx1hi_scalar },
    &operand_data[7950],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx2hi_scalar },
    &operand_data[7959],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx2hi_scalar },
    &operand_data[7959],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx2hi_scalar },
    &operand_data[7959],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx2hi_scalar },
    &operand_data[7959],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx4hi_scalar },
    &operand_data[7968],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx4hi_scalar },
    &operand_data[7968],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx4hi_scalar },
    &operand_data[7968],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx4hi_scalar },
    &operand_data[7968],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx8hi_scalar },
    &operand_data[7977],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx8hi_scalar },
    &operand_data[7977],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx8hi_scalar },
    &operand_data[7977],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx8hi_scalar },
    &operand_data[7977],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx16hi_scalar },
    &operand_data[7986],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx16hi_scalar },
    &operand_data[7986],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx16hi_scalar },
    &operand_data[7986],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx16hi_scalar },
    &operand_data[7986],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx32hi_scalar },
    &operand_data[7995],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx32hi_scalar },
    &operand_data[7995],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx32hi_scalar },
    &operand_data[7995],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx32hi_scalar },
    &operand_data[7995],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx1si_scalar },
    &operand_data[8004],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx1si_scalar },
    &operand_data[8004],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx1si_scalar },
    &operand_data[8004],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx1si_scalar },
    &operand_data[8004],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx2si_scalar },
    &operand_data[8013],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx2si_scalar },
    &operand_data[8013],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx2si_scalar },
    &operand_data[8013],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx2si_scalar },
    &operand_data[8013],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx4si_scalar },
    &operand_data[8022],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx4si_scalar },
    &operand_data[8022],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx4si_scalar },
    &operand_data[8022],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx4si_scalar },
    &operand_data[8022],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx8si_scalar },
    &operand_data[8031],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx8si_scalar },
    &operand_data[8031],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx8si_scalar },
    &operand_data[8031],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx8si_scalar },
    &operand_data[8031],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx16si_scalar },
    &operand_data[8040],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx16si_scalar },
    &operand_data[8040],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx16si_scalar },
    &operand_data[8040],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx16si_scalar },
    &operand_data[8040],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx1di_scalar },
    &operand_data[8049],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx1di_scalar },
    &operand_data[8049],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx1di_scalar },
    &operand_data[8049],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx1di_scalar },
    &operand_data[8049],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx2di_scalar },
    &operand_data[8058],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx2di_scalar },
    &operand_data[8058],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx2di_scalar },
    &operand_data[8058],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx2di_scalar },
    &operand_data[8058],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx4di_scalar },
    &operand_data[8067],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx4di_scalar },
    &operand_data[8067],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx4di_scalar },
    &operand_data[8067],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx4di_scalar },
    &operand_data[8067],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_addsvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwadd.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addsvnx8di_scalar },
    &operand_data[8076],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subsvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsub.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subsvnx8di_scalar },
    &operand_data[8076],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_adduvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwaddu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_adduvnx8di_scalar },
    &operand_data[8076],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3010 */
  {
    "pred_single_widen_subuvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwsubu.wx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subuvnx8di_scalar },
    &operand_data[8076],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx1hi },
    &operand_data[7545],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx2hi },
    &operand_data[7554],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx4hi },
    &operand_data[7563],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx8hi },
    &operand_data[7572],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx16hi },
    &operand_data[7581],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx32hi },
    &operand_data[7590],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx1si },
    &operand_data[7599],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx2si },
    &operand_data[7608],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx4si },
    &operand_data[7617],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx8si },
    &operand_data[7626],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx16si },
    &operand_data[7635],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx1di },
    &operand_data[7644],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx2di },
    &operand_data[7653],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx4di },
    &operand_data[7662],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3032 */
  {
    "pred_widen_mulsuvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx8di },
    &operand_data[7671],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx1hi_scalar },
    &operand_data[7680],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx2hi_scalar },
    &operand_data[7689],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx4hi_scalar },
    &operand_data[7698],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx8hi_scalar },
    &operand_data[7707],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx16hi_scalar },
    &operand_data[7716],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx32hi_scalar },
    &operand_data[7725],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx1si_scalar },
    &operand_data[7734],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx2si_scalar },
    &operand_data[7743],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx4si_scalar },
    &operand_data[7752],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx8si_scalar },
    &operand_data[7761],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx16si_scalar },
    &operand_data[7770],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx1di_scalar },
    &operand_data[7779],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx2di_scalar },
    &operand_data[7788],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx4di_scalar },
    &operand_data[7797],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3054 */
  {
    "pred_widen_mulsuvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmulsu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mulsuvnx8di_scalar },
    &operand_data[7806],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx1hi },
    &operand_data[7321],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx1hi },
    &operand_data[7321],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx2hi },
    &operand_data[7329],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx2hi },
    &operand_data[7329],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx4hi },
    &operand_data[7337],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx4hi },
    &operand_data[7337],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx8hi },
    &operand_data[7345],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx8hi },
    &operand_data[7345],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx16hi },
    &operand_data[7353],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx16hi },
    &operand_data[7353],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx32hi },
    &operand_data[7361],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx32hi },
    &operand_data[7361],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx1si },
    &operand_data[7369],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx1si },
    &operand_data[7369],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx2si },
    &operand_data[7377],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx2si },
    &operand_data[7377],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx4si },
    &operand_data[7385],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx4si },
    &operand_data[7385],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx8si },
    &operand_data[7393],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx8si },
    &operand_data[7393],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx16si },
    &operand_data[7401],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx16si },
    &operand_data[7401],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx1di },
    &operand_data[7409],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx1di },
    &operand_data[7409],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx2di },
    &operand_data[7417],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx2di },
    &operand_data[7417],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx4di },
    &operand_data[7425],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx4di },
    &operand_data[7425],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_extendvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvt.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx8di },
    &operand_data[7433],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3078 */
  {
    "pred_zero_extendvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwcvtu.x.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_zero_extendvnx8di },
    &operand_data[7433],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx1hi },
    &operand_data[8085],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx1hi },
    &operand_data[8085],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx2hi },
    &operand_data[8094],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx2hi },
    &operand_data[8094],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx4hi },
    &operand_data[8103],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx4hi },
    &operand_data[8103],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx8hi },
    &operand_data[8112],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx8hi },
    &operand_data[8112],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx16hi },
    &operand_data[8121],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx16hi },
    &operand_data[8121],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx32hi },
    &operand_data[8130],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx32hi },
    &operand_data[8130],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx1si },
    &operand_data[8139],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx1si },
    &operand_data[8139],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx2si },
    &operand_data[8148],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx2si },
    &operand_data[8148],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx4si },
    &operand_data[8157],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx4si },
    &operand_data[8157],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx8si },
    &operand_data[8166],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx8si },
    &operand_data[8166],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx16si },
    &operand_data[8175],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx16si },
    &operand_data[8175],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx1di },
    &operand_data[8184],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx1di },
    &operand_data[8184],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx2di },
    &operand_data[8193],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx2di },
    &operand_data[8193],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx4di },
    &operand_data[8202],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx4di },
    &operand_data[8202],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_ashrvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx8di },
    &operand_data[8211],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3114 */
  {
    "pred_narrow_lshrvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx8di },
    &operand_data[8211],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx1hi_scalar },
    &operand_data[8220],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx1hi_scalar },
    &operand_data[8220],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx2hi_scalar },
    &operand_data[8229],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx2hi_scalar },
    &operand_data[8229],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx4hi_scalar },
    &operand_data[8238],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx4hi_scalar },
    &operand_data[8238],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx8hi_scalar },
    &operand_data[8247],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx8hi_scalar },
    &operand_data[8247],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx16hi_scalar },
    &operand_data[8256],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx16hi_scalar },
    &operand_data[8256],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx32hi_scalar },
    &operand_data[8265],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx32hi_scalar },
    &operand_data[8265],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx1si_scalar },
    &operand_data[8274],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx1si_scalar },
    &operand_data[8274],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx2si_scalar },
    &operand_data[8283],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx2si_scalar },
    &operand_data[8283],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx4si_scalar },
    &operand_data[8292],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx4si_scalar },
    &operand_data[8292],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx8si_scalar },
    &operand_data[8301],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx8si_scalar },
    &operand_data[8301],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx16si_scalar },
    &operand_data[8310],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx16si_scalar },
    &operand_data[8310],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx1di_scalar },
    &operand_data[8319],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx1di_scalar },
    &operand_data[8319],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx2di_scalar },
    &operand_data[8328],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx2di_scalar },
    &operand_data[8328],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx4di_scalar },
    &operand_data[8337],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx4di_scalar },
    &operand_data[8337],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_ashrvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsra.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_ashrvnx8di_scalar },
    &operand_data[8346],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3135 */
  {
    "pred_narrow_lshrvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnsrl.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_lshrvnx8di_scalar },
    &operand_data[8346],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx1hi },
    &operand_data[8355],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx2hi },
    &operand_data[8363],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx4hi },
    &operand_data[8371],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx8hi },
    &operand_data[8379],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx16hi },
    &operand_data[8387],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx32hi },
    &operand_data[8395],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx1si },
    &operand_data[8403],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx2si },
    &operand_data[8411],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx4si },
    &operand_data[8419],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx8si },
    &operand_data[8427],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx16si },
    &operand_data[8435],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx1di },
    &operand_data[8443],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx2di },
    &operand_data[8451],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx4di },
    &operand_data[8459],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3157 */
  {
    "pred_truncvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vncvt.x.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx8di },
    &operand_data[8467],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3279 },
#else
    { 0, output_3279, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx1qi },
    &operand_data[8475],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3280 },
#else
    { 0, output_3280, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx1qi },
    &operand_data[8484],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3281 },
#else
    { 0, output_3281, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx1qi },
    &operand_data[8475],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3282 },
#else
    { 0, output_3282, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx1qi },
    &operand_data[8493],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3283 },
#else
    { 0, output_3283, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx2qi },
    &operand_data[8502],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3284 },
#else
    { 0, output_3284, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx2qi },
    &operand_data[8511],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3285 },
#else
    { 0, output_3285, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx2qi },
    &operand_data[8502],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3286 },
#else
    { 0, output_3286, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx2qi },
    &operand_data[8520],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3287 },
#else
    { 0, output_3287, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx4qi },
    &operand_data[8529],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3288 },
#else
    { 0, output_3288, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx4qi },
    &operand_data[8538],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3289 },
#else
    { 0, output_3289, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx4qi },
    &operand_data[8529],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3290 },
#else
    { 0, output_3290, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx4qi },
    &operand_data[8547],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3291 },
#else
    { 0, output_3291, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx8qi },
    &operand_data[8556],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3292 },
#else
    { 0, output_3292, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx8qi },
    &operand_data[8565],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3293 },
#else
    { 0, output_3293, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx8qi },
    &operand_data[8556],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3294 },
#else
    { 0, output_3294, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx8qi },
    &operand_data[8574],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3295 },
#else
    { 0, output_3295, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx16qi },
    &operand_data[8583],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3296 },
#else
    { 0, output_3296, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx16qi },
    &operand_data[8592],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3297 },
#else
    { 0, output_3297, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx16qi },
    &operand_data[8583],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3298 },
#else
    { 0, output_3298, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx16qi },
    &operand_data[8601],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3299 },
#else
    { 0, output_3299, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx32qi },
    &operand_data[8610],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3300 },
#else
    { 0, output_3300, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx32qi },
    &operand_data[8619],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3301 },
#else
    { 0, output_3301, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx32qi },
    &operand_data[8610],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3302 },
#else
    { 0, output_3302, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx32qi },
    &operand_data[8628],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3303 },
#else
    { 0, output_3303, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx64qi },
    &operand_data[8637],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3304 },
#else
    { 0, output_3304, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx64qi },
    &operand_data[8646],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3305 },
#else
    { 0, output_3305, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx64qi },
    &operand_data[8637],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3306 },
#else
    { 0, output_3306, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx64qi },
    &operand_data[8655],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3307 },
#else
    { 0, output_3307, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx1hi },
    &operand_data[8664],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3308 },
#else
    { 0, output_3308, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx1hi },
    &operand_data[8673],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3309 },
#else
    { 0, output_3309, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx1hi },
    &operand_data[8664],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3310 },
#else
    { 0, output_3310, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx1hi },
    &operand_data[8682],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3311 },
#else
    { 0, output_3311, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx2hi },
    &operand_data[8691],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3312 },
#else
    { 0, output_3312, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx2hi },
    &operand_data[8700],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3313 },
#else
    { 0, output_3313, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx2hi },
    &operand_data[8691],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3314 },
#else
    { 0, output_3314, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx2hi },
    &operand_data[8709],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3315 },
#else
    { 0, output_3315, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx4hi },
    &operand_data[8718],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3316 },
#else
    { 0, output_3316, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx4hi },
    &operand_data[8727],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3317 },
#else
    { 0, output_3317, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx4hi },
    &operand_data[8718],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3318 },
#else
    { 0, output_3318, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx4hi },
    &operand_data[8736],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3319 },
#else
    { 0, output_3319, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx8hi },
    &operand_data[8745],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3320 },
#else
    { 0, output_3320, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx8hi },
    &operand_data[8754],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3321 },
#else
    { 0, output_3321, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx8hi },
    &operand_data[8745],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3322 },
#else
    { 0, output_3322, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx8hi },
    &operand_data[8763],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3323 },
#else
    { 0, output_3323, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx16hi },
    &operand_data[8772],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3324 },
#else
    { 0, output_3324, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx16hi },
    &operand_data[8781],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3325 },
#else
    { 0, output_3325, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx16hi },
    &operand_data[8772],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3326 },
#else
    { 0, output_3326, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx16hi },
    &operand_data[8790],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3327 },
#else
    { 0, output_3327, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx32hi },
    &operand_data[8799],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3328 },
#else
    { 0, output_3328, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx32hi },
    &operand_data[8808],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3329 },
#else
    { 0, output_3329, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx32hi },
    &operand_data[8799],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3330 },
#else
    { 0, output_3330, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx32hi },
    &operand_data[8817],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3331 },
#else
    { 0, output_3331, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx1si },
    &operand_data[8826],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3332 },
#else
    { 0, output_3332, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx1si },
    &operand_data[8835],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3333 },
#else
    { 0, output_3333, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx1si },
    &operand_data[8826],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3334 },
#else
    { 0, output_3334, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx1si },
    &operand_data[8844],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3335 },
#else
    { 0, output_3335, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx2si },
    &operand_data[8853],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3336 },
#else
    { 0, output_3336, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx2si },
    &operand_data[8862],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3337 },
#else
    { 0, output_3337, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx2si },
    &operand_data[8853],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3338 },
#else
    { 0, output_3338, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx2si },
    &operand_data[8871],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3339 },
#else
    { 0, output_3339, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx4si },
    &operand_data[8880],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3340 },
#else
    { 0, output_3340, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx4si },
    &operand_data[8889],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3341 },
#else
    { 0, output_3341, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx4si },
    &operand_data[8880],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3342 },
#else
    { 0, output_3342, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx4si },
    &operand_data[8898],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3343 },
#else
    { 0, output_3343, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx8si },
    &operand_data[8907],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3344 },
#else
    { 0, output_3344, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx8si },
    &operand_data[8916],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3345 },
#else
    { 0, output_3345, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx8si },
    &operand_data[8907],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3346 },
#else
    { 0, output_3346, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx8si },
    &operand_data[8925],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3347 },
#else
    { 0, output_3347, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx16si },
    &operand_data[8934],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3348 },
#else
    { 0, output_3348, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx16si },
    &operand_data[8943],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3349 },
#else
    { 0, output_3349, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx16si },
    &operand_data[8934],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3350 },
#else
    { 0, output_3350, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx16si },
    &operand_data[8952],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3351 },
#else
    { 0, output_3351, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx1di },
    &operand_data[8961],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3352 },
#else
    { 0, output_3352, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx1di },
    &operand_data[8970],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3353 },
#else
    { 0, output_3353, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx1di },
    &operand_data[8961],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3354 },
#else
    { 0, output_3354, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx1di },
    &operand_data[8979],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3355 },
#else
    { 0, output_3355, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx2di },
    &operand_data[8988],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3356 },
#else
    { 0, output_3356, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx2di },
    &operand_data[8997],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3357 },
#else
    { 0, output_3357, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx2di },
    &operand_data[8988],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3358 },
#else
    { 0, output_3358, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx2di },
    &operand_data[9006],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3359 },
#else
    { 0, output_3359, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx4di },
    &operand_data[9015],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3360 },
#else
    { 0, output_3360, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx4di },
    &operand_data[9024],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3361 },
#else
    { 0, output_3361, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx4di },
    &operand_data[9015],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3362 },
#else
    { 0, output_3362, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx4di },
    &operand_data[9033],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ssaddvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3363 },
#else
    { 0, output_3363, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx8di },
    &operand_data[9042],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_sssubvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3364 },
#else
    { 0, output_3364, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx8di },
    &operand_data[9051],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_usaddvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3365 },
#else
    { 0, output_3365, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx8di },
    &operand_data[9042],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3192 */
  {
    "pred_ussubvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_3366 },
#else
    { 0, output_3366, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx8di },
    &operand_data[9060],
    9,
    9,
    0,
    8,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx1qi_scalar },
    &operand_data[9069],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx1qi_scalar },
    &operand_data[9069],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx2qi_scalar },
    &operand_data[9078],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx2qi_scalar },
    &operand_data[9078],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx4qi_scalar },
    &operand_data[9087],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx4qi_scalar },
    &operand_data[9087],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx8qi_scalar },
    &operand_data[9096],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx8qi_scalar },
    &operand_data[9096],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx16qi_scalar },
    &operand_data[9105],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx16qi_scalar },
    &operand_data[9105],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx32qi_scalar },
    &operand_data[9114],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx32qi_scalar },
    &operand_data[9114],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx64qi_scalar },
    &operand_data[9123],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx64qi_scalar },
    &operand_data[9123],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx1hi_scalar },
    &operand_data[9132],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx1hi_scalar },
    &operand_data[9132],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx2hi_scalar },
    &operand_data[9141],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx2hi_scalar },
    &operand_data[9141],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx4hi_scalar },
    &operand_data[9150],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx4hi_scalar },
    &operand_data[9150],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx8hi_scalar },
    &operand_data[9159],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx8hi_scalar },
    &operand_data[9159],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx16hi_scalar },
    &operand_data[9168],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx16hi_scalar },
    &operand_data[9168],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx32hi_scalar },
    &operand_data[9177],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx32hi_scalar },
    &operand_data[9177],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx1si_scalar },
    &operand_data[9186],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx1si_scalar },
    &operand_data[9186],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx2si_scalar },
    &operand_data[9195],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx2si_scalar },
    &operand_data[9195],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx4si_scalar },
    &operand_data[9204],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx4si_scalar },
    &operand_data[9204],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx8si_scalar },
    &operand_data[9213],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx8si_scalar },
    &operand_data[9213],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_ssaddvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx16si_scalar },
    &operand_data[9222],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3221 */
  {
    "pred_usaddvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx16si_scalar },
    &operand_data[9222],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx1qi_scalar },
    &operand_data[9069],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx1qi_scalar },
    &operand_data[9069],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx2qi_scalar },
    &operand_data[9078],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx2qi_scalar },
    &operand_data[9078],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx4qi_scalar },
    &operand_data[9087],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx4qi_scalar },
    &operand_data[9087],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx8qi_scalar },
    &operand_data[9096],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx8qi_scalar },
    &operand_data[9096],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx16qi_scalar },
    &operand_data[9105],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx16qi_scalar },
    &operand_data[9105],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx32qi_scalar },
    &operand_data[9114],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx32qi_scalar },
    &operand_data[9114],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx64qi_scalar },
    &operand_data[9123],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx64qi_scalar },
    &operand_data[9123],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx1hi_scalar },
    &operand_data[9132],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx1hi_scalar },
    &operand_data[9132],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx2hi_scalar },
    &operand_data[9141],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx2hi_scalar },
    &operand_data[9141],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx4hi_scalar },
    &operand_data[9150],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx4hi_scalar },
    &operand_data[9150],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx8hi_scalar },
    &operand_data[9159],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx8hi_scalar },
    &operand_data[9159],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx16hi_scalar },
    &operand_data[9168],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx16hi_scalar },
    &operand_data[9168],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx32hi_scalar },
    &operand_data[9177],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx32hi_scalar },
    &operand_data[9177],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx1si_scalar },
    &operand_data[9186],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx1si_scalar },
    &operand_data[9186],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx2si_scalar },
    &operand_data[9195],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx2si_scalar },
    &operand_data[9195],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx4si_scalar },
    &operand_data[9204],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx4si_scalar },
    &operand_data[9204],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx8si_scalar },
    &operand_data[9213],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx8si_scalar },
    &operand_data[9213],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_sssubvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx16si_scalar },
    &operand_data[9222],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3242 */
  {
    "pred_ussubvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx16si_scalar },
    &operand_data[9222],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3296 */
  {
    "*pred_ssaddvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9231],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3296 */
  {
    "*pred_usaddvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9231],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3296 */
  {
    "*pred_ssaddvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9240],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3296 */
  {
    "*pred_usaddvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9240],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3296 */
  {
    "*pred_ssaddvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9249],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3296 */
  {
    "*pred_usaddvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9249],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3296 */
  {
    "*pred_ssaddvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9258],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3296 */
  {
    "*pred_usaddvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9258],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3317 */
  {
    "*pred_ssaddvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9267],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3317 */
  {
    "*pred_usaddvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9267],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3317 */
  {
    "*pred_ssaddvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9276],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3317 */
  {
    "*pred_usaddvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9276],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3317 */
  {
    "*pred_ssaddvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9285],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3317 */
  {
    "*pred_usaddvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9285],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3317 */
  {
    "*pred_ssaddvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsadd.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9294],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3317 */
  {
    "*pred_usaddvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsaddu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9294],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3372 */
  {
    "*pred_sssubvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9231],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3372 */
  {
    "*pred_ussubvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9231],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3372 */
  {
    "*pred_sssubvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9240],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3372 */
  {
    "*pred_ussubvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9240],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3372 */
  {
    "*pred_sssubvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9249],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3372 */
  {
    "*pred_ussubvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9249],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3372 */
  {
    "*pred_sssubvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9258],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3372 */
  {
    "*pred_ussubvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9258],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3393 */
  {
    "*pred_sssubvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9267],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3393 */
  {
    "*pred_ussubvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9267],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3393 */
  {
    "*pred_sssubvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9276],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3393 */
  {
    "*pred_ussubvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9276],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3393 */
  {
    "*pred_sssubvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9285],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3393 */
  {
    "*pred_ussubvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9285],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3393 */
  {
    "*pred_sssubvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssub.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9294],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3393 */
  {
    "*pred_ussubvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssubu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9294],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx1qi },
    &operand_data[5685],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx1qi },
    &operand_data[5685],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx1qi },
    &operand_data[5685],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx1qi },
    &operand_data[5685],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx1qi },
    &operand_data[5685],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx1qi },
    &operand_data[5685],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx1qi },
    &operand_data[5685],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx2qi },
    &operand_data[5694],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx2qi },
    &operand_data[5694],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx2qi },
    &operand_data[5694],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx2qi },
    &operand_data[5694],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx2qi },
    &operand_data[5694],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx2qi },
    &operand_data[5694],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx2qi },
    &operand_data[5694],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx4qi },
    &operand_data[5703],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx4qi },
    &operand_data[5703],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx4qi },
    &operand_data[5703],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx4qi },
    &operand_data[5703],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx4qi },
    &operand_data[5703],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx4qi },
    &operand_data[5703],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx4qi },
    &operand_data[5703],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx8qi },
    &operand_data[5712],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx8qi },
    &operand_data[5712],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx8qi },
    &operand_data[5712],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx8qi },
    &operand_data[5712],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx8qi },
    &operand_data[5712],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx8qi },
    &operand_data[5712],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx8qi },
    &operand_data[5712],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx16qi },
    &operand_data[5721],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx16qi },
    &operand_data[5721],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx16qi },
    &operand_data[5721],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx16qi },
    &operand_data[5721],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx16qi },
    &operand_data[5721],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx16qi },
    &operand_data[5721],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx16qi },
    &operand_data[5721],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx32qi },
    &operand_data[5730],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx32qi },
    &operand_data[5730],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx32qi },
    &operand_data[5730],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx32qi },
    &operand_data[5730],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx32qi },
    &operand_data[5730],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx32qi },
    &operand_data[5730],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx32qi },
    &operand_data[5730],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx64qi },
    &operand_data[5739],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx64qi },
    &operand_data[5739],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx64qi },
    &operand_data[5739],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx64qi },
    &operand_data[5739],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx64qi },
    &operand_data[5739],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx64qi },
    &operand_data[5739],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx64qi },
    &operand_data[5739],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx1hi },
    &operand_data[5748],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx1hi },
    &operand_data[5748],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx1hi },
    &operand_data[5748],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx1hi },
    &operand_data[5748],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx1hi },
    &operand_data[5748],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx1hi },
    &operand_data[5748],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx1hi },
    &operand_data[5748],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx2hi },
    &operand_data[5757],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx2hi },
    &operand_data[5757],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx2hi },
    &operand_data[5757],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx2hi },
    &operand_data[5757],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx2hi },
    &operand_data[5757],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx2hi },
    &operand_data[5757],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx2hi },
    &operand_data[5757],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx4hi },
    &operand_data[5766],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx4hi },
    &operand_data[5766],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx4hi },
    &operand_data[5766],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx4hi },
    &operand_data[5766],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx4hi },
    &operand_data[5766],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx4hi },
    &operand_data[5766],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx4hi },
    &operand_data[5766],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx8hi },
    &operand_data[5775],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx8hi },
    &operand_data[5775],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx8hi },
    &operand_data[5775],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx8hi },
    &operand_data[5775],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx8hi },
    &operand_data[5775],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx8hi },
    &operand_data[5775],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx8hi },
    &operand_data[5775],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx16hi },
    &operand_data[5784],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx16hi },
    &operand_data[5784],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx16hi },
    &operand_data[5784],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx16hi },
    &operand_data[5784],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx16hi },
    &operand_data[5784],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx16hi },
    &operand_data[5784],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx16hi },
    &operand_data[5784],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx32hi },
    &operand_data[5793],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx32hi },
    &operand_data[5793],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx32hi },
    &operand_data[5793],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx32hi },
    &operand_data[5793],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx32hi },
    &operand_data[5793],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx32hi },
    &operand_data[5793],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx32hi },
    &operand_data[5793],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx1si },
    &operand_data[5802],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx1si },
    &operand_data[5802],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx1si },
    &operand_data[5802],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx1si },
    &operand_data[5802],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx1si },
    &operand_data[5802],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx1si },
    &operand_data[5802],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx1si },
    &operand_data[5802],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx2si },
    &operand_data[5811],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx2si },
    &operand_data[5811],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx2si },
    &operand_data[5811],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx2si },
    &operand_data[5811],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx2si },
    &operand_data[5811],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx2si },
    &operand_data[5811],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx2si },
    &operand_data[5811],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx4si },
    &operand_data[5820],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx4si },
    &operand_data[5820],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx4si },
    &operand_data[5820],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx4si },
    &operand_data[5820],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx4si },
    &operand_data[5820],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx4si },
    &operand_data[5820],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx4si },
    &operand_data[5820],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx8si },
    &operand_data[5829],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx8si },
    &operand_data[5829],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx8si },
    &operand_data[5829],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx8si },
    &operand_data[5829],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx8si },
    &operand_data[5829],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx8si },
    &operand_data[5829],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx8si },
    &operand_data[5829],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx16si },
    &operand_data[5838],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx16si },
    &operand_data[5838],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx16si },
    &operand_data[5838],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx16si },
    &operand_data[5838],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx16si },
    &operand_data[5838],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx16si },
    &operand_data[5838],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx16si },
    &operand_data[5838],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx1di },
    &operand_data[5847],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx1di },
    &operand_data[5847],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx1di },
    &operand_data[5847],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx1di },
    &operand_data[5847],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx1di },
    &operand_data[5847],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx1di },
    &operand_data[5847],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx1di },
    &operand_data[5847],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx2di },
    &operand_data[5856],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx2di },
    &operand_data[5856],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx2di },
    &operand_data[5856],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx2di },
    &operand_data[5856],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx2di },
    &operand_data[5856],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx2di },
    &operand_data[5856],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx2di },
    &operand_data[5856],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx4di },
    &operand_data[5865],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx4di },
    &operand_data[5865],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx4di },
    &operand_data[5865],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx4di },
    &operand_data[5865],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx4di },
    &operand_data[5865],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx4di },
    &operand_data[5865],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx4di },
    &operand_data[5865],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aadduvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx8di },
    &operand_data[5874],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_aaddvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx8di },
    &operand_data[5874],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubuvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx8di },
    &operand_data[5874],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_asubvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx8di },
    &operand_data[5874],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_smulvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx8di },
    &operand_data[5874],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssrlvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx8di },
    &operand_data[5874],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3415 */
  {
    "pred_ssravnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx8di },
    &operand_data[5874],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx1qi_scalar },
    &operand_data[9303],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx1qi_scalar },
    &operand_data[9303],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx1qi_scalar },
    &operand_data[9303],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx1qi_scalar },
    &operand_data[9303],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx1qi_scalar },
    &operand_data[9303],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx2qi_scalar },
    &operand_data[9312],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx2qi_scalar },
    &operand_data[9312],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx2qi_scalar },
    &operand_data[9312],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx2qi_scalar },
    &operand_data[9312],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx2qi_scalar },
    &operand_data[9312],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx4qi_scalar },
    &operand_data[9321],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx4qi_scalar },
    &operand_data[9321],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx4qi_scalar },
    &operand_data[9321],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx4qi_scalar },
    &operand_data[9321],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx4qi_scalar },
    &operand_data[9321],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx8qi_scalar },
    &operand_data[9330],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx8qi_scalar },
    &operand_data[9330],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx8qi_scalar },
    &operand_data[9330],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx8qi_scalar },
    &operand_data[9330],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx8qi_scalar },
    &operand_data[9330],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx16qi_scalar },
    &operand_data[9339],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx16qi_scalar },
    &operand_data[9339],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx16qi_scalar },
    &operand_data[9339],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx16qi_scalar },
    &operand_data[9339],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx16qi_scalar },
    &operand_data[9339],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx32qi_scalar },
    &operand_data[9348],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx32qi_scalar },
    &operand_data[9348],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx32qi_scalar },
    &operand_data[9348],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx32qi_scalar },
    &operand_data[9348],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx32qi_scalar },
    &operand_data[9348],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx64qi_scalar },
    &operand_data[9357],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx64qi_scalar },
    &operand_data[9357],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx64qi_scalar },
    &operand_data[9357],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx64qi_scalar },
    &operand_data[9357],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx64qi_scalar },
    &operand_data[9357],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx1hi_scalar },
    &operand_data[9366],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx1hi_scalar },
    &operand_data[9366],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx1hi_scalar },
    &operand_data[9366],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx1hi_scalar },
    &operand_data[9366],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx1hi_scalar },
    &operand_data[9366],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx2hi_scalar },
    &operand_data[9375],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx2hi_scalar },
    &operand_data[9375],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx2hi_scalar },
    &operand_data[9375],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx2hi_scalar },
    &operand_data[9375],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx2hi_scalar },
    &operand_data[9375],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx4hi_scalar },
    &operand_data[9384],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx4hi_scalar },
    &operand_data[9384],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx4hi_scalar },
    &operand_data[9384],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx4hi_scalar },
    &operand_data[9384],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx4hi_scalar },
    &operand_data[9384],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx8hi_scalar },
    &operand_data[9393],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx8hi_scalar },
    &operand_data[9393],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx8hi_scalar },
    &operand_data[9393],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx8hi_scalar },
    &operand_data[9393],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx8hi_scalar },
    &operand_data[9393],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx16hi_scalar },
    &operand_data[9402],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx16hi_scalar },
    &operand_data[9402],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx16hi_scalar },
    &operand_data[9402],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx16hi_scalar },
    &operand_data[9402],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx16hi_scalar },
    &operand_data[9402],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx32hi_scalar },
    &operand_data[9411],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx32hi_scalar },
    &operand_data[9411],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx32hi_scalar },
    &operand_data[9411],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx32hi_scalar },
    &operand_data[9411],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx32hi_scalar },
    &operand_data[9411],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx1si_scalar },
    &operand_data[9420],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx1si_scalar },
    &operand_data[9420],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx1si_scalar },
    &operand_data[9420],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx1si_scalar },
    &operand_data[9420],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx1si_scalar },
    &operand_data[9420],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx2si_scalar },
    &operand_data[9429],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx2si_scalar },
    &operand_data[9429],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx2si_scalar },
    &operand_data[9429],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx2si_scalar },
    &operand_data[9429],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx2si_scalar },
    &operand_data[9429],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx4si_scalar },
    &operand_data[9438],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx4si_scalar },
    &operand_data[9438],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx4si_scalar },
    &operand_data[9438],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx4si_scalar },
    &operand_data[9438],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx4si_scalar },
    &operand_data[9438],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx8si_scalar },
    &operand_data[9447],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx8si_scalar },
    &operand_data[9447],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx8si_scalar },
    &operand_data[9447],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx8si_scalar },
    &operand_data[9447],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx8si_scalar },
    &operand_data[9447],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aadduvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx16si_scalar },
    &operand_data[9456],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_aaddvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx16si_scalar },
    &operand_data[9456],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubuvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx16si_scalar },
    &operand_data[9456],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_asubvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx16si_scalar },
    &operand_data[9456],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3436 */
  {
    "pred_smulvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx16si_scalar },
    &operand_data[9456],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx1qi_scalar },
    &operand_data[9465],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx1qi_scalar },
    &operand_data[9465],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx2qi_scalar },
    &operand_data[9474],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx2qi_scalar },
    &operand_data[9474],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx4qi_scalar },
    &operand_data[9483],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx4qi_scalar },
    &operand_data[9483],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx8qi_scalar },
    &operand_data[9492],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx8qi_scalar },
    &operand_data[9492],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx16qi_scalar },
    &operand_data[9501],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx16qi_scalar },
    &operand_data[9501],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx32qi_scalar },
    &operand_data[9510],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx32qi_scalar },
    &operand_data[9510],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx64qi_scalar },
    &operand_data[9519],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx64qi_scalar },
    &operand_data[9519],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx1hi_scalar },
    &operand_data[9528],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx1hi_scalar },
    &operand_data[9528],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx2hi_scalar },
    &operand_data[9537],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx2hi_scalar },
    &operand_data[9537],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx4hi_scalar },
    &operand_data[9546],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx4hi_scalar },
    &operand_data[9546],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx8hi_scalar },
    &operand_data[9555],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx8hi_scalar },
    &operand_data[9555],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx16hi_scalar },
    &operand_data[9564],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx16hi_scalar },
    &operand_data[9564],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx32hi_scalar },
    &operand_data[9573],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx32hi_scalar },
    &operand_data[9573],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx1si_scalar },
    &operand_data[9582],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx1si_scalar },
    &operand_data[9582],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx2si_scalar },
    &operand_data[9591],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx2si_scalar },
    &operand_data[9591],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx4si_scalar },
    &operand_data[9600],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx4si_scalar },
    &operand_data[9600],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx8si_scalar },
    &operand_data[9609],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx8si_scalar },
    &operand_data[9609],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx16si_scalar },
    &operand_data[9618],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx16si_scalar },
    &operand_data[9618],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx1di_scalar },
    &operand_data[9627],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx1di_scalar },
    &operand_data[9627],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx2di_scalar },
    &operand_data[9636],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx2di_scalar },
    &operand_data[9636],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx4di_scalar },
    &operand_data[9645],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx4di_scalar },
    &operand_data[9645],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssrlvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssrl.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssrlvnx8di_scalar },
    &operand_data[9654],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3456 */
  {
    "pred_ssravnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vssra.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssravnx8di_scalar },
    &operand_data[9654],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_aadduvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9663],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_aaddvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9663],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_asubuvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9663],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_asubvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9663],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_smulvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9663],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_aadduvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9672],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_aaddvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9672],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_asubuvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9672],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_asubvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9672],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_smulvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9672],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_aadduvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9681],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_aaddvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9681],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_asubuvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9681],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_asubvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9681],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_smulvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9681],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_aadduvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9690],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_aaddvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9690],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_asubuvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9690],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_asubvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9690],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3510 */
  {
    "*pred_smulvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9690],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_aadduvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9699],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_aaddvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9699],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_asubuvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9699],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_asubvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9699],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_smulvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9699],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_aadduvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9708],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_aaddvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9708],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_asubuvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9708],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_asubvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9708],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_smulvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9708],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_aadduvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9717],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_aaddvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9717],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_asubuvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9717],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_asubvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9717],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_smulvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9717],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_aadduvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaaddu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9726],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_aaddvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vaadd.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9726],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_asubuvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasubu.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9726],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_asubvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vasub.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9726],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3530 */
  {
    "*pred_smulvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vsmul.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9726],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx1hi },
    &operand_data[8085],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx1hi },
    &operand_data[8085],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx2hi },
    &operand_data[8094],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx2hi },
    &operand_data[8094],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx4hi },
    &operand_data[8103],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx4hi },
    &operand_data[8103],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx8hi },
    &operand_data[8112],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx8hi },
    &operand_data[8112],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx16hi },
    &operand_data[8121],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx16hi },
    &operand_data[8121],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx32hi },
    &operand_data[8130],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx32hi },
    &operand_data[8130],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx1si },
    &operand_data[8139],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx1si },
    &operand_data[8139],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx2si },
    &operand_data[8148],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx2si },
    &operand_data[8148],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx4si },
    &operand_data[8157],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx4si },
    &operand_data[8157],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx8si },
    &operand_data[8166],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx8si },
    &operand_data[8166],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx16si },
    &operand_data[8175],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx16si },
    &operand_data[8175],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx1di },
    &operand_data[8184],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx1di },
    &operand_data[8184],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx2di },
    &operand_data[8193],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx2di },
    &operand_data[8193],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx4di },
    &operand_data[8202],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx4di },
    &operand_data[8202],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx8di },
    &operand_data[8211],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3552 */
  {
    "pred_narrow_clipuvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%v4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx8di },
    &operand_data[8211],
    9,
    9,
    0,
    12,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx1hi_scalar },
    &operand_data[8220],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx1hi_scalar },
    &operand_data[8220],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx2hi_scalar },
    &operand_data[8229],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx2hi_scalar },
    &operand_data[8229],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx4hi_scalar },
    &operand_data[8238],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx4hi_scalar },
    &operand_data[8238],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx8hi_scalar },
    &operand_data[8247],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx8hi_scalar },
    &operand_data[8247],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx16hi_scalar },
    &operand_data[8256],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx16hi_scalar },
    &operand_data[8256],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx32hi_scalar },
    &operand_data[8265],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx32hi_scalar },
    &operand_data[8265],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx1si_scalar },
    &operand_data[8274],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx1si_scalar },
    &operand_data[8274],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx2si_scalar },
    &operand_data[8283],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx2si_scalar },
    &operand_data[8283],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx4si_scalar },
    &operand_data[8292],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx4si_scalar },
    &operand_data[8292],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx8si_scalar },
    &operand_data[8301],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx8si_scalar },
    &operand_data[8301],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx16si_scalar },
    &operand_data[8310],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx16si_scalar },
    &operand_data[8310],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx1di_scalar },
    &operand_data[8319],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx1di_scalar },
    &operand_data[8319],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx2di_scalar },
    &operand_data[8328],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx2di_scalar },
    &operand_data[8328],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx4di_scalar },
    &operand_data[8337],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx4di_scalar },
    &operand_data[8337],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclip.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipvnx8di_scalar },
    &operand_data[8346],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3572 */
  {
    "pred_narrow_clipuvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vnclipu.w%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_clipuvnx8di_scalar },
    &operand_data[8346],
    9,
    9,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9735],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9744],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9753],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9762],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9771],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9780],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9789],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9798],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9807],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9816],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9825],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9834],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9843],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9852],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9861],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9870],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9879],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9888],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9897],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9906],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9915],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3617 */
  {
    "*pred_cmpvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9924],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx1qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9933],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx2qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9942],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx4qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9951],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx8qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9960],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx16qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9969],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx32qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9978],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx64qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9987],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx1hi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[9996],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx2hi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10005],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx4hi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10014],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx8hi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10023],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx16hi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10032],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx32hi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10041],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx1si_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10050],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx2si_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10059],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx4si_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10068],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx8si_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10077],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx16si_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10086],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx1di_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10095],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx2di_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10104],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx4di_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10113],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3637 */
  {
    "*pred_cmpvnx8di_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10122],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10131],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10140],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10149],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10158],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10167],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10176],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10185],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10194],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10203],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10212],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10221],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10230],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10239],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10248],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10257],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10266],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10275],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10284],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10293],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10302],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10311],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3674 */
  {
    "*pred_ltgevnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10320],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx1qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10329],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx2qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10338],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx4qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10347],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx8qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10356],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx16qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10365],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx32qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10374],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx64qi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10383],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx1hi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10392],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx2hi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10401],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx4hi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10410],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx8hi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10419],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx16hi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10428],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx32hi_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10437],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx1si_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10446],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx2si_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10455],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx4si_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10464],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx8si_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10473],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx16si_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10482],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx1di_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10491],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx2di_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10500],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx4di_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10509],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3694 */
  {
    "*pred_ltgevnx8di_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.v%o5\t%0,%4,%v5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10518],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10527],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10536],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10545],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10554],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10563],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10572],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10581],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10590],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10599],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10608],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10617],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10626],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10635],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10644],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10653],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10662],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10671],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3732 */
  {
    "*pred_cmpvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10680],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx1qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10689],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx2qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10698],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx4qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10707],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx8qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10716],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx16qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10725],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx32qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10734],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx64qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10743],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx1hi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10752],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx2hi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10761],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx4hi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10770],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx8hi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10779],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx16hi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10788],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx32hi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10797],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx1si_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10806],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx2si_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10815],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx4si_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10824],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx8si_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10833],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3753 */
  {
    "*pred_cmpvnx16si_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10842],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10851],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10860],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10869],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10878],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10887],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10896],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10905],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10914],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10923],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10932],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10941],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10950],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10959],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10968],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10977],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10986],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[10995],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3792 */
  {
    "*pred_eqnevnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11004],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx1qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11013],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx2qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11022],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx4qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11031],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx8qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11040],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx16qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11049],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx32qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11058],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx64qi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11067],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx1hi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11076],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx2hi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11085],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx4hi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11094],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx8hi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11103],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx16hi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11112],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx32hi_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11121],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx1si_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11130],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx2si_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11139],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx4si_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11148],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx8si_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11157],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3813 */
  {
    "*pred_eqnevnx16si_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11166],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3909 */
  {
    "*pred_cmpvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11175],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3909 */
  {
    "*pred_cmpvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11184],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3909 */
  {
    "*pred_cmpvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11193],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3909 */
  {
    "*pred_cmpvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11202],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3930 */
  {
    "*pred_cmpvnx1di_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11211],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3930 */
  {
    "*pred_cmpvnx2di_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11220],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3930 */
  {
    "*pred_cmpvnx4di_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11229],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3930 */
  {
    "*pred_cmpvnx8di_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11238],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3951 */
  {
    "*pred_eqnevnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11247],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3951 */
  {
    "*pred_eqnevnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11256],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3951 */
  {
    "*pred_eqnevnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11265],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3951 */
  {
    "*pred_eqnevnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11274],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3972 */
  {
    "*pred_eqnevnx1di_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11283],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3972 */
  {
    "*pred_eqnevnx2di_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11292],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3972 */
  {
    "*pred_eqnevnx4di_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11301],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3972 */
  {
    "*pred_eqnevnx8di_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11310],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3993 */
  {
    "*pred_cmpvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11319],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3993 */
  {
    "*pred_cmpvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11328],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3993 */
  {
    "*pred_cmpvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11337],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3993 */
  {
    "*pred_cmpvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11346],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4014 */
  {
    "*pred_cmpvnx1di_extended_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11355],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4014 */
  {
    "*pred_cmpvnx2di_extended_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11364],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4014 */
  {
    "*pred_cmpvnx4di_extended_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11373],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4014 */
  {
    "*pred_cmpvnx8di_extended_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11382],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4036 */
  {
    "*pred_eqnevnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11391],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4036 */
  {
    "*pred_eqnevnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11400],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4036 */
  {
    "*pred_eqnevnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11409],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4036 */
  {
    "*pred_eqnevnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11418],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4057 */
  {
    "*pred_eqnevnx1di_extended_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11427],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4057 */
  {
    "*pred_eqnevnx2di_extended_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11436],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4057 */
  {
    "*pred_eqnevnx4di_extended_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11445],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4057 */
  {
    "*pred_eqnevnx8di_extended_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vms%B3.vx\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[11454],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4051 },
#else
    { 0, output_4051, 0 },
#endif
    { 0 },
    &operand_data[11463],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4052 },
#else
    { 0, output_4052, 0 },
#endif
    { 0 },
    &operand_data[11472],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4053 },
#else
    { 0, output_4053, 0 },
#endif
    { 0 },
    &operand_data[11481],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4054 },
#else
    { 0, output_4054, 0 },
#endif
    { 0 },
    &operand_data[11490],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4055 },
#else
    { 0, output_4055, 0 },
#endif
    { 0 },
    &operand_data[11499],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4056 },
#else
    { 0, output_4056, 0 },
#endif
    { 0 },
    &operand_data[11508],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4057 },
#else
    { 0, output_4057, 0 },
#endif
    { 0 },
    &operand_data[11517],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4058 },
#else
    { 0, output_4058, 0 },
#endif
    { 0 },
    &operand_data[11526],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4059 },
#else
    { 0, output_4059, 0 },
#endif
    { 0 },
    &operand_data[11535],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4060 },
#else
    { 0, output_4060, 0 },
#endif
    { 0 },
    &operand_data[11544],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4061 },
#else
    { 0, output_4061, 0 },
#endif
    { 0 },
    &operand_data[11553],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4062 },
#else
    { 0, output_4062, 0 },
#endif
    { 0 },
    &operand_data[11562],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4063 },
#else
    { 0, output_4063, 0 },
#endif
    { 0 },
    &operand_data[11571],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4064 },
#else
    { 0, output_4064, 0 },
#endif
    { 0 },
    &operand_data[11580],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4065 },
#else
    { 0, output_4065, 0 },
#endif
    { 0 },
    &operand_data[11589],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4066 },
#else
    { 0, output_4066, 0 },
#endif
    { 0 },
    &operand_data[11598],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4067 },
#else
    { 0, output_4067, 0 },
#endif
    { 0 },
    &operand_data[11607],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4068 },
#else
    { 0, output_4068, 0 },
#endif
    { 0 },
    &operand_data[11616],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4069 },
#else
    { 0, output_4069, 0 },
#endif
    { 0 },
    &operand_data[11625],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4070 },
#else
    { 0, output_4070, 0 },
#endif
    { 0 },
    &operand_data[11634],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4071 },
#else
    { 0, output_4071, 0 },
#endif
    { 0 },
    &operand_data[11643],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4228 */
  {
    "*pred_maddvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4072 },
#else
    { 0, output_4072, 0 },
#endif
    { 0 },
    &operand_data[11652],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4073 },
#else
    { 0, output_4073, 0 },
#endif
    { 0 },
    &operand_data[11661],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4074 },
#else
    { 0, output_4074, 0 },
#endif
    { 0 },
    &operand_data[11670],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4075 },
#else
    { 0, output_4075, 0 },
#endif
    { 0 },
    &operand_data[11679],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4076 },
#else
    { 0, output_4076, 0 },
#endif
    { 0 },
    &operand_data[11688],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4077 },
#else
    { 0, output_4077, 0 },
#endif
    { 0 },
    &operand_data[11697],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4078 },
#else
    { 0, output_4078, 0 },
#endif
    { 0 },
    &operand_data[11706],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4079 },
#else
    { 0, output_4079, 0 },
#endif
    { 0 },
    &operand_data[11715],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4080 },
#else
    { 0, output_4080, 0 },
#endif
    { 0 },
    &operand_data[11724],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4081 },
#else
    { 0, output_4081, 0 },
#endif
    { 0 },
    &operand_data[11733],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4082 },
#else
    { 0, output_4082, 0 },
#endif
    { 0 },
    &operand_data[11742],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4083 },
#else
    { 0, output_4083, 0 },
#endif
    { 0 },
    &operand_data[11751],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4084 },
#else
    { 0, output_4084, 0 },
#endif
    { 0 },
    &operand_data[11760],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4085 },
#else
    { 0, output_4085, 0 },
#endif
    { 0 },
    &operand_data[11769],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4086 },
#else
    { 0, output_4086, 0 },
#endif
    { 0 },
    &operand_data[11778],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4087 },
#else
    { 0, output_4087, 0 },
#endif
    { 0 },
    &operand_data[11787],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4088 },
#else
    { 0, output_4088, 0 },
#endif
    { 0 },
    &operand_data[11796],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4089 },
#else
    { 0, output_4089, 0 },
#endif
    { 0 },
    &operand_data[11805],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4090 },
#else
    { 0, output_4090, 0 },
#endif
    { 0 },
    &operand_data[11814],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4091 },
#else
    { 0, output_4091, 0 },
#endif
    { 0 },
    &operand_data[11823],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4092 },
#else
    { 0, output_4092, 0 },
#endif
    { 0 },
    &operand_data[11832],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4093 },
#else
    { 0, output_4093, 0 },
#endif
    { 0 },
    &operand_data[11841],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4259 */
  {
    "*pred_maccvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4094 },
#else
    { 0, output_4094, 0 },
#endif
    { 0 },
    &operand_data[11850],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4095 },
#else
    { 0, output_4095, 0 },
#endif
    { 0 },
    &operand_data[11859],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4096 },
#else
    { 0, output_4096, 0 },
#endif
    { 0 },
    &operand_data[11869],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4097 },
#else
    { 0, output_4097, 0 },
#endif
    { 0 },
    &operand_data[11879],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4098 },
#else
    { 0, output_4098, 0 },
#endif
    { 0 },
    &operand_data[11889],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4099 },
#else
    { 0, output_4099, 0 },
#endif
    { 0 },
    &operand_data[11899],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4100 },
#else
    { 0, output_4100, 0 },
#endif
    { 0 },
    &operand_data[11909],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4101 },
#else
    { 0, output_4101, 0 },
#endif
    { 0 },
    &operand_data[11919],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4102 },
#else
    { 0, output_4102, 0 },
#endif
    { 0 },
    &operand_data[11929],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4103 },
#else
    { 0, output_4103, 0 },
#endif
    { 0 },
    &operand_data[11939],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4104 },
#else
    { 0, output_4104, 0 },
#endif
    { 0 },
    &operand_data[11949],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4105 },
#else
    { 0, output_4105, 0 },
#endif
    { 0 },
    &operand_data[11959],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4106 },
#else
    { 0, output_4106, 0 },
#endif
    { 0 },
    &operand_data[11969],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4107 },
#else
    { 0, output_4107, 0 },
#endif
    { 0 },
    &operand_data[11979],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4108 },
#else
    { 0, output_4108, 0 },
#endif
    { 0 },
    &operand_data[11989],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4109 },
#else
    { 0, output_4109, 0 },
#endif
    { 0 },
    &operand_data[11999],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4110 },
#else
    { 0, output_4110, 0 },
#endif
    { 0 },
    &operand_data[12009],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4111 },
#else
    { 0, output_4111, 0 },
#endif
    { 0 },
    &operand_data[12019],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4112 },
#else
    { 0, output_4112, 0 },
#endif
    { 0 },
    &operand_data[12029],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4113 },
#else
    { 0, output_4113, 0 },
#endif
    { 0 },
    &operand_data[12039],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4114 },
#else
    { 0, output_4114, 0 },
#endif
    { 0 },
    &operand_data[12049],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4115 },
#else
    { 0, output_4115, 0 },
#endif
    { 0 },
    &operand_data[12059],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4290 */
  {
    "*pred_mul_plusvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4116 },
#else
    { 0, output_4116, 0 },
#endif
    { 0 },
    &operand_data[12069],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4117 },
#else
    { 0, output_4117, 0 },
#endif
    { 0 },
    &operand_data[12079],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4118 },
#else
    { 0, output_4118, 0 },
#endif
    { 0 },
    &operand_data[12088],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4119 },
#else
    { 0, output_4119, 0 },
#endif
    { 0 },
    &operand_data[12097],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4120 },
#else
    { 0, output_4120, 0 },
#endif
    { 0 },
    &operand_data[12106],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4121 },
#else
    { 0, output_4121, 0 },
#endif
    { 0 },
    &operand_data[12115],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4122 },
#else
    { 0, output_4122, 0 },
#endif
    { 0 },
    &operand_data[12124],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4123 },
#else
    { 0, output_4123, 0 },
#endif
    { 0 },
    &operand_data[12133],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4124 },
#else
    { 0, output_4124, 0 },
#endif
    { 0 },
    &operand_data[12142],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4125 },
#else
    { 0, output_4125, 0 },
#endif
    { 0 },
    &operand_data[12151],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4126 },
#else
    { 0, output_4126, 0 },
#endif
    { 0 },
    &operand_data[12160],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4127 },
#else
    { 0, output_4127, 0 },
#endif
    { 0 },
    &operand_data[12169],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4128 },
#else
    { 0, output_4128, 0 },
#endif
    { 0 },
    &operand_data[12178],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4129 },
#else
    { 0, output_4129, 0 },
#endif
    { 0 },
    &operand_data[12187],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4130 },
#else
    { 0, output_4130, 0 },
#endif
    { 0 },
    &operand_data[12196],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4131 },
#else
    { 0, output_4131, 0 },
#endif
    { 0 },
    &operand_data[12205],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4132 },
#else
    { 0, output_4132, 0 },
#endif
    { 0 },
    &operand_data[12214],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4133 },
#else
    { 0, output_4133, 0 },
#endif
    { 0 },
    &operand_data[12223],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4134 },
#else
    { 0, output_4134, 0 },
#endif
    { 0 },
    &operand_data[12232],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4135 },
#else
    { 0, output_4135, 0 },
#endif
    { 0 },
    &operand_data[12241],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4136 },
#else
    { 0, output_4136, 0 },
#endif
    { 0 },
    &operand_data[12250],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4137 },
#else
    { 0, output_4137, 0 },
#endif
    { 0 },
    &operand_data[12259],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4364 */
  {
    "*pred_maddvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4138 },
#else
    { 0, output_4138, 0 },
#endif
    { 0 },
    &operand_data[12268],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4139 },
#else
    { 0, output_4139, 0 },
#endif
    { 0 },
    &operand_data[12277],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4140 },
#else
    { 0, output_4140, 0 },
#endif
    { 0 },
    &operand_data[12286],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4141 },
#else
    { 0, output_4141, 0 },
#endif
    { 0 },
    &operand_data[12295],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4142 },
#else
    { 0, output_4142, 0 },
#endif
    { 0 },
    &operand_data[12304],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4143 },
#else
    { 0, output_4143, 0 },
#endif
    { 0 },
    &operand_data[12313],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4144 },
#else
    { 0, output_4144, 0 },
#endif
    { 0 },
    &operand_data[12322],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4145 },
#else
    { 0, output_4145, 0 },
#endif
    { 0 },
    &operand_data[12331],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4146 },
#else
    { 0, output_4146, 0 },
#endif
    { 0 },
    &operand_data[12340],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4147 },
#else
    { 0, output_4147, 0 },
#endif
    { 0 },
    &operand_data[12349],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4148 },
#else
    { 0, output_4148, 0 },
#endif
    { 0 },
    &operand_data[12358],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4149 },
#else
    { 0, output_4149, 0 },
#endif
    { 0 },
    &operand_data[12367],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4150 },
#else
    { 0, output_4150, 0 },
#endif
    { 0 },
    &operand_data[12376],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4151 },
#else
    { 0, output_4151, 0 },
#endif
    { 0 },
    &operand_data[12385],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4152 },
#else
    { 0, output_4152, 0 },
#endif
    { 0 },
    &operand_data[12394],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4153 },
#else
    { 0, output_4153, 0 },
#endif
    { 0 },
    &operand_data[12403],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4154 },
#else
    { 0, output_4154, 0 },
#endif
    { 0 },
    &operand_data[12412],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4155 },
#else
    { 0, output_4155, 0 },
#endif
    { 0 },
    &operand_data[12421],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4156 },
#else
    { 0, output_4156, 0 },
#endif
    { 0 },
    &operand_data[12430],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4157 },
#else
    { 0, output_4157, 0 },
#endif
    { 0 },
    &operand_data[12439],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4158 },
#else
    { 0, output_4158, 0 },
#endif
    { 0 },
    &operand_data[12448],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4159 },
#else
    { 0, output_4159, 0 },
#endif
    { 0 },
    &operand_data[12457],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4396 */
  {
    "*pred_maccvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4160 },
#else
    { 0, output_4160, 0 },
#endif
    { 0 },
    &operand_data[12466],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4161 },
#else
    { 0, output_4161, 0 },
#endif
    { 0 },
    &operand_data[12475],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4162 },
#else
    { 0, output_4162, 0 },
#endif
    { 0 },
    &operand_data[12485],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4163 },
#else
    { 0, output_4163, 0 },
#endif
    { 0 },
    &operand_data[12495],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4164 },
#else
    { 0, output_4164, 0 },
#endif
    { 0 },
    &operand_data[12505],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4165 },
#else
    { 0, output_4165, 0 },
#endif
    { 0 },
    &operand_data[12515],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4166 },
#else
    { 0, output_4166, 0 },
#endif
    { 0 },
    &operand_data[12525],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4167 },
#else
    { 0, output_4167, 0 },
#endif
    { 0 },
    &operand_data[12535],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4168 },
#else
    { 0, output_4168, 0 },
#endif
    { 0 },
    &operand_data[12545],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4169 },
#else
    { 0, output_4169, 0 },
#endif
    { 0 },
    &operand_data[12555],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4170 },
#else
    { 0, output_4170, 0 },
#endif
    { 0 },
    &operand_data[12565],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4171 },
#else
    { 0, output_4171, 0 },
#endif
    { 0 },
    &operand_data[12575],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4172 },
#else
    { 0, output_4172, 0 },
#endif
    { 0 },
    &operand_data[12585],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4173 },
#else
    { 0, output_4173, 0 },
#endif
    { 0 },
    &operand_data[12595],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4174 },
#else
    { 0, output_4174, 0 },
#endif
    { 0 },
    &operand_data[12605],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4175 },
#else
    { 0, output_4175, 0 },
#endif
    { 0 },
    &operand_data[12615],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4176 },
#else
    { 0, output_4176, 0 },
#endif
    { 0 },
    &operand_data[12625],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4177 },
#else
    { 0, output_4177, 0 },
#endif
    { 0 },
    &operand_data[12635],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4178 },
#else
    { 0, output_4178, 0 },
#endif
    { 0 },
    &operand_data[12645],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4179 },
#else
    { 0, output_4179, 0 },
#endif
    { 0 },
    &operand_data[12655],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4180 },
#else
    { 0, output_4180, 0 },
#endif
    { 0 },
    &operand_data[12665],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4181 },
#else
    { 0, output_4181, 0 },
#endif
    { 0 },
    &operand_data[12675],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4428 */
  {
    "*pred_mul_plusvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4182 },
#else
    { 0, output_4182, 0 },
#endif
    { 0 },
    &operand_data[12685],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4510 */
  {
    "*pred_maddvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4183 },
#else
    { 0, output_4183, 0 },
#endif
    { 0 },
    &operand_data[12695],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4510 */
  {
    "*pred_maddvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4184 },
#else
    { 0, output_4184, 0 },
#endif
    { 0 },
    &operand_data[12704],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4510 */
  {
    "*pred_maddvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4185 },
#else
    { 0, output_4185, 0 },
#endif
    { 0 },
    &operand_data[12713],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4510 */
  {
    "*pred_maddvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4186 },
#else
    { 0, output_4186, 0 },
#endif
    { 0 },
    &operand_data[12722],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4543 */
  {
    "*pred_maccvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4187 },
#else
    { 0, output_4187, 0 },
#endif
    { 0 },
    &operand_data[12731],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4543 */
  {
    "*pred_maccvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4188 },
#else
    { 0, output_4188, 0 },
#endif
    { 0 },
    &operand_data[12740],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4543 */
  {
    "*pred_maccvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4189 },
#else
    { 0, output_4189, 0 },
#endif
    { 0 },
    &operand_data[12749],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4543 */
  {
    "*pred_maccvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4190 },
#else
    { 0, output_4190, 0 },
#endif
    { 0 },
    &operand_data[12758],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4576 */
  {
    "*pred_mul_plusvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4191 },
#else
    { 0, output_4191, 0 },
#endif
    { 0 },
    &operand_data[12767],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4576 */
  {
    "*pred_mul_plusvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4192 },
#else
    { 0, output_4192, 0 },
#endif
    { 0 },
    &operand_data[12777],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4576 */
  {
    "*pred_mul_plusvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4193 },
#else
    { 0, output_4193, 0 },
#endif
    { 0 },
    &operand_data[12787],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4576 */
  {
    "*pred_mul_plusvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4194 },
#else
    { 0, output_4194, 0 },
#endif
    { 0 },
    &operand_data[12797],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4195 },
#else
    { 0, output_4195, 0 },
#endif
    { 0 },
    &operand_data[11463],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4196 },
#else
    { 0, output_4196, 0 },
#endif
    { 0 },
    &operand_data[11472],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4197 },
#else
    { 0, output_4197, 0 },
#endif
    { 0 },
    &operand_data[11481],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4198 },
#else
    { 0, output_4198, 0 },
#endif
    { 0 },
    &operand_data[11490],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4199 },
#else
    { 0, output_4199, 0 },
#endif
    { 0 },
    &operand_data[11499],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4200 },
#else
    { 0, output_4200, 0 },
#endif
    { 0 },
    &operand_data[11508],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4201 },
#else
    { 0, output_4201, 0 },
#endif
    { 0 },
    &operand_data[11517],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4202 },
#else
    { 0, output_4202, 0 },
#endif
    { 0 },
    &operand_data[11526],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4203 },
#else
    { 0, output_4203, 0 },
#endif
    { 0 },
    &operand_data[11535],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4204 },
#else
    { 0, output_4204, 0 },
#endif
    { 0 },
    &operand_data[11544],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4205 },
#else
    { 0, output_4205, 0 },
#endif
    { 0 },
    &operand_data[11553],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4206 },
#else
    { 0, output_4206, 0 },
#endif
    { 0 },
    &operand_data[11562],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4207 },
#else
    { 0, output_4207, 0 },
#endif
    { 0 },
    &operand_data[11571],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4208 },
#else
    { 0, output_4208, 0 },
#endif
    { 0 },
    &operand_data[11580],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4209 },
#else
    { 0, output_4209, 0 },
#endif
    { 0 },
    &operand_data[11589],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4210 },
#else
    { 0, output_4210, 0 },
#endif
    { 0 },
    &operand_data[11598],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4211 },
#else
    { 0, output_4211, 0 },
#endif
    { 0 },
    &operand_data[11607],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4212 },
#else
    { 0, output_4212, 0 },
#endif
    { 0 },
    &operand_data[11616],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4213 },
#else
    { 0, output_4213, 0 },
#endif
    { 0 },
    &operand_data[11625],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4214 },
#else
    { 0, output_4214, 0 },
#endif
    { 0 },
    &operand_data[11634],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4215 },
#else
    { 0, output_4215, 0 },
#endif
    { 0 },
    &operand_data[11643],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4649 */
  {
    "*pred_nmsubvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4216 },
#else
    { 0, output_4216, 0 },
#endif
    { 0 },
    &operand_data[11652],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4217 },
#else
    { 0, output_4217, 0 },
#endif
    { 0 },
    &operand_data[11661],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4218 },
#else
    { 0, output_4218, 0 },
#endif
    { 0 },
    &operand_data[11670],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4219 },
#else
    { 0, output_4219, 0 },
#endif
    { 0 },
    &operand_data[11679],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4220 },
#else
    { 0, output_4220, 0 },
#endif
    { 0 },
    &operand_data[11688],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4221 },
#else
    { 0, output_4221, 0 },
#endif
    { 0 },
    &operand_data[11697],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4222 },
#else
    { 0, output_4222, 0 },
#endif
    { 0 },
    &operand_data[11706],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4223 },
#else
    { 0, output_4223, 0 },
#endif
    { 0 },
    &operand_data[11715],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4224 },
#else
    { 0, output_4224, 0 },
#endif
    { 0 },
    &operand_data[11724],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4225 },
#else
    { 0, output_4225, 0 },
#endif
    { 0 },
    &operand_data[11733],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4226 },
#else
    { 0, output_4226, 0 },
#endif
    { 0 },
    &operand_data[11742],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4227 },
#else
    { 0, output_4227, 0 },
#endif
    { 0 },
    &operand_data[11751],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4228 },
#else
    { 0, output_4228, 0 },
#endif
    { 0 },
    &operand_data[11760],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4229 },
#else
    { 0, output_4229, 0 },
#endif
    { 0 },
    &operand_data[11769],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4230 },
#else
    { 0, output_4230, 0 },
#endif
    { 0 },
    &operand_data[11778],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4231 },
#else
    { 0, output_4231, 0 },
#endif
    { 0 },
    &operand_data[11787],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4232 },
#else
    { 0, output_4232, 0 },
#endif
    { 0 },
    &operand_data[11796],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4233 },
#else
    { 0, output_4233, 0 },
#endif
    { 0 },
    &operand_data[11805],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4234 },
#else
    { 0, output_4234, 0 },
#endif
    { 0 },
    &operand_data[11814],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4235 },
#else
    { 0, output_4235, 0 },
#endif
    { 0 },
    &operand_data[11823],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4236 },
#else
    { 0, output_4236, 0 },
#endif
    { 0 },
    &operand_data[11832],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4237 },
#else
    { 0, output_4237, 0 },
#endif
    { 0 },
    &operand_data[11841],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4680 */
  {
    "*pred_nmsacvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4238 },
#else
    { 0, output_4238, 0 },
#endif
    { 0 },
    &operand_data[11850],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4239 },
#else
    { 0, output_4239, 0 },
#endif
    { 0 },
    &operand_data[11859],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4240 },
#else
    { 0, output_4240, 0 },
#endif
    { 0 },
    &operand_data[11869],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4241 },
#else
    { 0, output_4241, 0 },
#endif
    { 0 },
    &operand_data[11879],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4242 },
#else
    { 0, output_4242, 0 },
#endif
    { 0 },
    &operand_data[11889],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4243 },
#else
    { 0, output_4243, 0 },
#endif
    { 0 },
    &operand_data[11899],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4244 },
#else
    { 0, output_4244, 0 },
#endif
    { 0 },
    &operand_data[11909],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4245 },
#else
    { 0, output_4245, 0 },
#endif
    { 0 },
    &operand_data[11919],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4246 },
#else
    { 0, output_4246, 0 },
#endif
    { 0 },
    &operand_data[11929],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4247 },
#else
    { 0, output_4247, 0 },
#endif
    { 0 },
    &operand_data[11939],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4248 },
#else
    { 0, output_4248, 0 },
#endif
    { 0 },
    &operand_data[11949],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4249 },
#else
    { 0, output_4249, 0 },
#endif
    { 0 },
    &operand_data[11959],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4250 },
#else
    { 0, output_4250, 0 },
#endif
    { 0 },
    &operand_data[11969],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4251 },
#else
    { 0, output_4251, 0 },
#endif
    { 0 },
    &operand_data[11979],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4252 },
#else
    { 0, output_4252, 0 },
#endif
    { 0 },
    &operand_data[11989],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4253 },
#else
    { 0, output_4253, 0 },
#endif
    { 0 },
    &operand_data[11999],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4254 },
#else
    { 0, output_4254, 0 },
#endif
    { 0 },
    &operand_data[12009],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4255 },
#else
    { 0, output_4255, 0 },
#endif
    { 0 },
    &operand_data[12019],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4256 },
#else
    { 0, output_4256, 0 },
#endif
    { 0 },
    &operand_data[12029],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4257 },
#else
    { 0, output_4257, 0 },
#endif
    { 0 },
    &operand_data[12039],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4258 },
#else
    { 0, output_4258, 0 },
#endif
    { 0 },
    &operand_data[12049],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4259 },
#else
    { 0, output_4259, 0 },
#endif
    { 0 },
    &operand_data[12059],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4711 */
  {
    "*pred_minus_mulvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4260 },
#else
    { 0, output_4260, 0 },
#endif
    { 0 },
    &operand_data[12069],
    10,
    10,
    0,
    5,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4261 },
#else
    { 0, output_4261, 0 },
#endif
    { 0 },
    &operand_data[12079],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4262 },
#else
    { 0, output_4262, 0 },
#endif
    { 0 },
    &operand_data[12088],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4263 },
#else
    { 0, output_4263, 0 },
#endif
    { 0 },
    &operand_data[12097],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4264 },
#else
    { 0, output_4264, 0 },
#endif
    { 0 },
    &operand_data[12106],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4265 },
#else
    { 0, output_4265, 0 },
#endif
    { 0 },
    &operand_data[12115],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4266 },
#else
    { 0, output_4266, 0 },
#endif
    { 0 },
    &operand_data[12124],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4267 },
#else
    { 0, output_4267, 0 },
#endif
    { 0 },
    &operand_data[12133],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4268 },
#else
    { 0, output_4268, 0 },
#endif
    { 0 },
    &operand_data[12142],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4269 },
#else
    { 0, output_4269, 0 },
#endif
    { 0 },
    &operand_data[12151],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4270 },
#else
    { 0, output_4270, 0 },
#endif
    { 0 },
    &operand_data[12160],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4271 },
#else
    { 0, output_4271, 0 },
#endif
    { 0 },
    &operand_data[12169],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4272 },
#else
    { 0, output_4272, 0 },
#endif
    { 0 },
    &operand_data[12178],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4273 },
#else
    { 0, output_4273, 0 },
#endif
    { 0 },
    &operand_data[12187],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4274 },
#else
    { 0, output_4274, 0 },
#endif
    { 0 },
    &operand_data[12196],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4275 },
#else
    { 0, output_4275, 0 },
#endif
    { 0 },
    &operand_data[12205],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4276 },
#else
    { 0, output_4276, 0 },
#endif
    { 0 },
    &operand_data[12214],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4277 },
#else
    { 0, output_4277, 0 },
#endif
    { 0 },
    &operand_data[12223],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4278 },
#else
    { 0, output_4278, 0 },
#endif
    { 0 },
    &operand_data[12232],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4279 },
#else
    { 0, output_4279, 0 },
#endif
    { 0 },
    &operand_data[12241],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4280 },
#else
    { 0, output_4280, 0 },
#endif
    { 0 },
    &operand_data[12250],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4281 },
#else
    { 0, output_4281, 0 },
#endif
    { 0 },
    &operand_data[12259],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4785 */
  {
    "*pred_nmsubvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4282 },
#else
    { 0, output_4282, 0 },
#endif
    { 0 },
    &operand_data[12268],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4283 },
#else
    { 0, output_4283, 0 },
#endif
    { 0 },
    &operand_data[12277],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4284 },
#else
    { 0, output_4284, 0 },
#endif
    { 0 },
    &operand_data[12286],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4285 },
#else
    { 0, output_4285, 0 },
#endif
    { 0 },
    &operand_data[12295],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4286 },
#else
    { 0, output_4286, 0 },
#endif
    { 0 },
    &operand_data[12304],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4287 },
#else
    { 0, output_4287, 0 },
#endif
    { 0 },
    &operand_data[12313],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4288 },
#else
    { 0, output_4288, 0 },
#endif
    { 0 },
    &operand_data[12322],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4289 },
#else
    { 0, output_4289, 0 },
#endif
    { 0 },
    &operand_data[12331],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4290 },
#else
    { 0, output_4290, 0 },
#endif
    { 0 },
    &operand_data[12340],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4291 },
#else
    { 0, output_4291, 0 },
#endif
    { 0 },
    &operand_data[12349],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4292 },
#else
    { 0, output_4292, 0 },
#endif
    { 0 },
    &operand_data[12358],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4293 },
#else
    { 0, output_4293, 0 },
#endif
    { 0 },
    &operand_data[12367],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4294 },
#else
    { 0, output_4294, 0 },
#endif
    { 0 },
    &operand_data[12376],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4295 },
#else
    { 0, output_4295, 0 },
#endif
    { 0 },
    &operand_data[12385],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4296 },
#else
    { 0, output_4296, 0 },
#endif
    { 0 },
    &operand_data[12394],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4297 },
#else
    { 0, output_4297, 0 },
#endif
    { 0 },
    &operand_data[12403],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4298 },
#else
    { 0, output_4298, 0 },
#endif
    { 0 },
    &operand_data[12412],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4299 },
#else
    { 0, output_4299, 0 },
#endif
    { 0 },
    &operand_data[12421],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4300 },
#else
    { 0, output_4300, 0 },
#endif
    { 0 },
    &operand_data[12430],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4301 },
#else
    { 0, output_4301, 0 },
#endif
    { 0 },
    &operand_data[12439],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4302 },
#else
    { 0, output_4302, 0 },
#endif
    { 0 },
    &operand_data[12448],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4303 },
#else
    { 0, output_4303, 0 },
#endif
    { 0 },
    &operand_data[12457],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4817 */
  {
    "*pred_nmsacvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4304 },
#else
    { 0, output_4304, 0 },
#endif
    { 0 },
    &operand_data[12466],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4305 },
#else
    { 0, output_4305, 0 },
#endif
    { 0 },
    &operand_data[12475],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4306 },
#else
    { 0, output_4306, 0 },
#endif
    { 0 },
    &operand_data[12485],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4307 },
#else
    { 0, output_4307, 0 },
#endif
    { 0 },
    &operand_data[12495],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4308 },
#else
    { 0, output_4308, 0 },
#endif
    { 0 },
    &operand_data[12505],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4309 },
#else
    { 0, output_4309, 0 },
#endif
    { 0 },
    &operand_data[12515],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4310 },
#else
    { 0, output_4310, 0 },
#endif
    { 0 },
    &operand_data[12525],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4311 },
#else
    { 0, output_4311, 0 },
#endif
    { 0 },
    &operand_data[12535],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4312 },
#else
    { 0, output_4312, 0 },
#endif
    { 0 },
    &operand_data[12545],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4313 },
#else
    { 0, output_4313, 0 },
#endif
    { 0 },
    &operand_data[12555],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4314 },
#else
    { 0, output_4314, 0 },
#endif
    { 0 },
    &operand_data[12565],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4315 },
#else
    { 0, output_4315, 0 },
#endif
    { 0 },
    &operand_data[12575],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4316 },
#else
    { 0, output_4316, 0 },
#endif
    { 0 },
    &operand_data[12585],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4317 },
#else
    { 0, output_4317, 0 },
#endif
    { 0 },
    &operand_data[12595],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4318 },
#else
    { 0, output_4318, 0 },
#endif
    { 0 },
    &operand_data[12605],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4319 },
#else
    { 0, output_4319, 0 },
#endif
    { 0 },
    &operand_data[12615],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4320 },
#else
    { 0, output_4320, 0 },
#endif
    { 0 },
    &operand_data[12625],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4321 },
#else
    { 0, output_4321, 0 },
#endif
    { 0 },
    &operand_data[12635],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4322 },
#else
    { 0, output_4322, 0 },
#endif
    { 0 },
    &operand_data[12645],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4323 },
#else
    { 0, output_4323, 0 },
#endif
    { 0 },
    &operand_data[12655],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4324 },
#else
    { 0, output_4324, 0 },
#endif
    { 0 },
    &operand_data[12665],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4325 },
#else
    { 0, output_4325, 0 },
#endif
    { 0 },
    &operand_data[12675],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4849 */
  {
    "*pred_minus_mulvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4326 },
#else
    { 0, output_4326, 0 },
#endif
    { 0 },
    &operand_data[12685],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4931 */
  {
    "*pred_nmsubvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4327 },
#else
    { 0, output_4327, 0 },
#endif
    { 0 },
    &operand_data[12695],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4931 */
  {
    "*pred_nmsubvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4328 },
#else
    { 0, output_4328, 0 },
#endif
    { 0 },
    &operand_data[12704],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4931 */
  {
    "*pred_nmsubvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4329 },
#else
    { 0, output_4329, 0 },
#endif
    { 0 },
    &operand_data[12713],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4931 */
  {
    "*pred_nmsubvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4330 },
#else
    { 0, output_4330, 0 },
#endif
    { 0 },
    &operand_data[12722],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4964 */
  {
    "*pred_nmsacvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4331 },
#else
    { 0, output_4331, 0 },
#endif
    { 0 },
    &operand_data[12731],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4964 */
  {
    "*pred_nmsacvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4332 },
#else
    { 0, output_4332, 0 },
#endif
    { 0 },
    &operand_data[12740],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4964 */
  {
    "*pred_nmsacvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4333 },
#else
    { 0, output_4333, 0 },
#endif
    { 0 },
    &operand_data[12749],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4964 */
  {
    "*pred_nmsacvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4334 },
#else
    { 0, output_4334, 0 },
#endif
    { 0 },
    &operand_data[12758],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4997 */
  {
    "*pred_minus_mulvnx1di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4335 },
#else
    { 0, output_4335, 0 },
#endif
    { 0 },
    &operand_data[12767],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4997 */
  {
    "*pred_minus_mulvnx2di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4336 },
#else
    { 0, output_4336, 0 },
#endif
    { 0 },
    &operand_data[12777],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4997 */
  {
    "*pred_minus_mulvnx4di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4337 },
#else
    { 0, output_4337, 0 },
#endif
    { 0 },
    &operand_data[12787],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4997 */
  {
    "*pred_minus_mulvnx8di_extended_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4338 },
#else
    { 0, output_4338, 0 },
#endif
    { 0 },
    &operand_data[12797],
    10,
    10,
    0,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx1hi },
    &operand_data[12807],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx1hi },
    &operand_data[12807],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx2hi },
    &operand_data[12816],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx2hi },
    &operand_data[12816],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx4hi },
    &operand_data[12825],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx4hi },
    &operand_data[12825],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx8hi },
    &operand_data[12834],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx8hi },
    &operand_data[12834],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx16hi },
    &operand_data[12843],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx16hi },
    &operand_data[12843],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx32hi },
    &operand_data[12852],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx32hi },
    &operand_data[12852],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx1si },
    &operand_data[12861],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx1si },
    &operand_data[12861],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx2si },
    &operand_data[12870],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx2si },
    &operand_data[12870],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx4si },
    &operand_data[12879],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx4si },
    &operand_data[12879],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx8si },
    &operand_data[12888],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx8si },
    &operand_data[12888],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx16si },
    &operand_data[12897],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx16si },
    &operand_data[12897],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx1di },
    &operand_data[12906],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx1di },
    &operand_data[12906],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx2di },
    &operand_data[12915],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx2di },
    &operand_data[12915],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx4di },
    &operand_data[12924],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx4di },
    &operand_data[12924],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plussvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx8di },
    &operand_data[12933],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5052 */
  {
    "pred_widen_mul_plusuvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx8di },
    &operand_data[12933],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx1hi_scalar },
    &operand_data[12942],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx1hi_scalar },
    &operand_data[12942],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx2hi_scalar },
    &operand_data[12951],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx2hi_scalar },
    &operand_data[12951],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx4hi_scalar },
    &operand_data[12960],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx4hi_scalar },
    &operand_data[12960],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx8hi_scalar },
    &operand_data[12969],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx8hi_scalar },
    &operand_data[12969],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx16hi_scalar },
    &operand_data[12978],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx16hi_scalar },
    &operand_data[12978],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx32hi_scalar },
    &operand_data[12987],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx32hi_scalar },
    &operand_data[12987],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx1si_scalar },
    &operand_data[12996],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx1si_scalar },
    &operand_data[12996],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx2si_scalar },
    &operand_data[13005],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx2si_scalar },
    &operand_data[13005],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx4si_scalar },
    &operand_data[13014],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx4si_scalar },
    &operand_data[13014],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx8si_scalar },
    &operand_data[13023],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx8si_scalar },
    &operand_data[13023],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx16si_scalar },
    &operand_data[13032],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx16si_scalar },
    &operand_data[13032],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx1di_scalar },
    &operand_data[13041],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx1di_scalar },
    &operand_data[13041],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx2di_scalar },
    &operand_data[13050],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx2di_scalar },
    &operand_data[13050],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx4di_scalar },
    &operand_data[13059],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx4di_scalar },
    &operand_data[13059],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plussvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmacc.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussvnx8di_scalar },
    &operand_data[13068],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5076 */
  {
    "pred_widen_mul_plusuvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plusuvnx8di_scalar },
    &operand_data[13068],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx1hi },
    &operand_data[12807],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx2hi },
    &operand_data[12816],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx4hi },
    &operand_data[12825],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx8hi },
    &operand_data[12834],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx16hi },
    &operand_data[12843],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx32hi },
    &operand_data[12852],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx1si },
    &operand_data[12861],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx2si },
    &operand_data[12870],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx4si },
    &operand_data[12879],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx8si },
    &operand_data[12888],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx16si },
    &operand_data[12897],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx1di },
    &operand_data[12906],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx2di },
    &operand_data[12915],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx4di },
    &operand_data[12924],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5101 */
  {
    "pred_widen_mul_plussuvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx8di },
    &operand_data[12933],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx1hi_scalar },
    &operand_data[12942],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx2hi_scalar },
    &operand_data[12951],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx4hi_scalar },
    &operand_data[12960],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx8hi_scalar },
    &operand_data[12969],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx16hi_scalar },
    &operand_data[12978],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx32hi_scalar },
    &operand_data[12987],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx1si_scalar },
    &operand_data[12996],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx2si_scalar },
    &operand_data[13005],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx4si_scalar },
    &operand_data[13014],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx8si_scalar },
    &operand_data[13023],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx16si_scalar },
    &operand_data[13032],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx1di_scalar },
    &operand_data[13041],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx2di_scalar },
    &operand_data[13050],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx4di_scalar },
    &operand_data[13059],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5125 */
  {
    "pred_widen_mul_plussuvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccsu.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plussuvnx8di_scalar },
    &operand_data[13068],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx1hi_scalar },
    &operand_data[12942],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx2hi_scalar },
    &operand_data[12951],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx4hi_scalar },
    &operand_data[12960],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx8hi_scalar },
    &operand_data[12969],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx16hi_scalar },
    &operand_data[12978],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx32hi_scalar },
    &operand_data[12987],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx1si_scalar },
    &operand_data[12996],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx2si_scalar },
    &operand_data[13005],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx4si_scalar },
    &operand_data[13014],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx8si_scalar },
    &operand_data[13023],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx16si_scalar },
    &operand_data[13032],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx1di_scalar },
    &operand_data[13041],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx2di_scalar },
    &operand_data[13050],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx4di_scalar },
    &operand_data[13059],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5150 */
  {
    "pred_widen_mul_plususvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwmaccus.vx\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_plususvnx8di_scalar },
    &operand_data[13068],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_andvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx1bi },
    &operand_data[13077],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_iorvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx1bi },
    &operand_data[13077],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_xorvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx1bi },
    &operand_data[13077],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_andvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx2bi },
    &operand_data[13084],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_iorvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx2bi },
    &operand_data[13084],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_xorvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx2bi },
    &operand_data[13084],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_andvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx4bi },
    &operand_data[13091],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_iorvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx4bi },
    &operand_data[13091],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_xorvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx4bi },
    &operand_data[13091],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_andvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx8bi },
    &operand_data[13098],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_iorvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx8bi },
    &operand_data[13098],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_xorvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx8bi },
    &operand_data[13098],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_andvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx16bi },
    &operand_data[13105],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_iorvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx16bi },
    &operand_data[13105],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_xorvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx16bi },
    &operand_data[13105],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_andvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx32bi },
    &operand_data[13112],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_iorvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx32bi },
    &operand_data[13112],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_xorvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx32bi },
    &operand_data[13112],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_andvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx64bi },
    &operand_data[13119],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_iorvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx64bi },
    &operand_data[13119],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5192 */
  {
    "pred_xorvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx64bi },
    &operand_data[13119],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nandvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nandvnx1bi },
    &operand_data[13077],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_niorvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_niorvnx1bi },
    &operand_data[13077],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nxorvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nxorvnx1bi },
    &operand_data[13077],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nandvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nandvnx2bi },
    &operand_data[13084],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_niorvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_niorvnx2bi },
    &operand_data[13084],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nxorvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nxorvnx2bi },
    &operand_data[13084],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nandvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nandvnx4bi },
    &operand_data[13091],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_niorvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_niorvnx4bi },
    &operand_data[13091],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nxorvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nxorvnx4bi },
    &operand_data[13091],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nandvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nandvnx8bi },
    &operand_data[13098],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_niorvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_niorvnx8bi },
    &operand_data[13098],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nxorvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nxorvnx8bi },
    &operand_data[13098],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nandvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nandvnx16bi },
    &operand_data[13105],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_niorvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_niorvnx16bi },
    &operand_data[13105],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nxorvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nxorvnx16bi },
    &operand_data[13105],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nandvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nandvnx32bi },
    &operand_data[13112],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_niorvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_niorvnx32bi },
    &operand_data[13112],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nxorvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nxorvnx32bi },
    &operand_data[13112],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nandvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnand.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nandvnx64bi },
    &operand_data[13119],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_niorvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_niorvnx64bi },
    &operand_data[13119],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5212 */
  {
    "pred_nxorvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmxnor.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_nxorvnx64bi },
    &operand_data[13119],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_andnotvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmandn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andnotvnx1bi },
    &operand_data[13077],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_iornotvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmorn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iornotvnx1bi },
    &operand_data[13077],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_andnotvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmandn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andnotvnx2bi },
    &operand_data[13084],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_iornotvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmorn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iornotvnx2bi },
    &operand_data[13084],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_andnotvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmandn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andnotvnx4bi },
    &operand_data[13091],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_iornotvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmorn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iornotvnx4bi },
    &operand_data[13091],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_andnotvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmandn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andnotvnx8bi },
    &operand_data[13098],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_iornotvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmorn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iornotvnx8bi },
    &operand_data[13098],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_andnotvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmandn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andnotvnx16bi },
    &operand_data[13105],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_iornotvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmorn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iornotvnx16bi },
    &operand_data[13105],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_andnotvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmandn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andnotvnx32bi },
    &operand_data[13112],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_iornotvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmorn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iornotvnx32bi },
    &operand_data[13112],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_andnotvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmandn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andnotvnx64bi },
    &operand_data[13119],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5233 */
  {
    "pred_iornotvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmorn.mm\t%0,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iornotvnx64bi },
    &operand_data[13119],
    7,
    7,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
  {
    "pred_notvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnot.m\t%0,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_notvnx1bi },
    &operand_data[13126],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
  {
    "pred_notvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnot.m\t%0,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_notvnx2bi },
    &operand_data[13132],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
  {
    "pred_notvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnot.m\t%0,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_notvnx4bi },
    &operand_data[13138],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
  {
    "pred_notvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnot.m\t%0,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_notvnx8bi },
    &operand_data[13144],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
  {
    "pred_notvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnot.m\t%0,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_notvnx16bi },
    &operand_data[13150],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
  {
    "pred_notvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnot.m\t%0,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_notvnx32bi },
    &operand_data[13156],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5254 */
  {
    "pred_notvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmnot.m\t%0,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_notvnx64bi },
    &operand_data[13162],
    6,
    6,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx1bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx1bisi },
    &operand_data[13168],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx2bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx2bisi },
    &operand_data[13173],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx4bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx4bisi },
    &operand_data[13178],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx8bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx8bisi },
    &operand_data[13183],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx16bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx16bisi },
    &operand_data[13188],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx32bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx32bisi },
    &operand_data[13193],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx64bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx64bisi },
    &operand_data[13198],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx1bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx1bidi },
    &operand_data[13203],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx2bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx2bidi },
    &operand_data[13208],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx4bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx4bidi },
    &operand_data[13213],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx8bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx8bidi },
    &operand_data[13218],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx16bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx16bidi },
    &operand_data[13223],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx32bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx32bidi },
    &operand_data[13228],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5273 */
  {
    "pred_popcountvnx64bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcpop.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_popcountvnx64bidi },
    &operand_data[13233],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx1bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx1bisi },
    &operand_data[13168],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx2bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx2bisi },
    &operand_data[13173],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx4bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx4bisi },
    &operand_data[13178],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx8bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx8bisi },
    &operand_data[13183],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx16bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx16bisi },
    &operand_data[13188],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx32bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx32bisi },
    &operand_data[13193],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx64bisi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx64bisi },
    &operand_data[13198],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx1bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx1bidi },
    &operand_data[13203],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx2bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx2bidi },
    &operand_data[13208],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx4bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx4bidi },
    &operand_data[13213],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx8bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx8bidi },
    &operand_data[13218],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx16bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx16bidi },
    &operand_data[13223],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx32bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx32bidi },
    &operand_data[13228],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5289 */
  {
    "pred_ffsvnx64bidi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfirst.m\t%0,%2%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ffsvnx64bidi },
    &operand_data[13233],
    5,
    5,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sbfvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbf.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbfvnx1bi },
    &operand_data[13238],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sifvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsif.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sifvnx1bi },
    &operand_data[13238],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sofvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsof.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sofvnx1bi },
    &operand_data[13238],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sbfvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbf.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbfvnx2bi },
    &operand_data[13245],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sifvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsif.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sifvnx2bi },
    &operand_data[13245],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sofvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsof.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sofvnx2bi },
    &operand_data[13245],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sbfvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbf.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbfvnx4bi },
    &operand_data[13252],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sifvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsif.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sifvnx4bi },
    &operand_data[13252],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sofvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsof.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sofvnx4bi },
    &operand_data[13252],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sbfvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbf.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbfvnx8bi },
    &operand_data[13259],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sifvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsif.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sifvnx8bi },
    &operand_data[13259],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sofvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsof.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sofvnx8bi },
    &operand_data[13259],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sbfvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbf.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbfvnx16bi },
    &operand_data[13266],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sifvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsif.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sifvnx16bi },
    &operand_data[13266],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sofvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsof.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sofvnx16bi },
    &operand_data[13266],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sbfvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbf.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbfvnx32bi },
    &operand_data[13273],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sifvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsif.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sifvnx32bi },
    &operand_data[13273],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sofvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsof.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sofvnx32bi },
    &operand_data[13273],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sbfvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsbf.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbfvnx64bi },
    &operand_data[13280],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sifvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsif.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sifvnx64bi },
    &operand_data[13280],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5307 */
  {
    "pred_sofvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmsof.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sofvnx64bi },
    &operand_data[13280],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx1qi },
    &operand_data[13287],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx2qi },
    &operand_data[13295],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx4qi },
    &operand_data[13303],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx8qi },
    &operand_data[13311],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx16qi },
    &operand_data[13319],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx32qi },
    &operand_data[13327],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx64qi },
    &operand_data[13335],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx1hi },
    &operand_data[13343],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx2hi },
    &operand_data[13351],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx4hi },
    &operand_data[13359],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx8hi },
    &operand_data[13367],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx16hi },
    &operand_data[13375],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx32hi },
    &operand_data[13383],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx1si },
    &operand_data[13391],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx2si },
    &operand_data[13399],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx4si },
    &operand_data[13407],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx8si },
    &operand_data[13415],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx16si },
    &operand_data[13423],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx1di },
    &operand_data[13431],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx2di },
    &operand_data[13439],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx4di },
    &operand_data[13447],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5325 */
  {
    "pred_iotavnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "viota.m\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iotavnx8di },
    &operand_data[13455],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx1qi },
    &operand_data[13463],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx2qi },
    &operand_data[13470],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx4qi },
    &operand_data[13477],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx8qi },
    &operand_data[13484],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx16qi },
    &operand_data[13491],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx32qi },
    &operand_data[13498],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx64qi },
    &operand_data[13505],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx1hi },
    &operand_data[13512],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx2hi },
    &operand_data[13519],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx4hi },
    &operand_data[13526],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx8hi },
    &operand_data[13533],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx16hi },
    &operand_data[13540],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx32hi },
    &operand_data[13547],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx1si },
    &operand_data[13554],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx2si },
    &operand_data[13561],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx4si },
    &operand_data[13568],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx8si },
    &operand_data[13575],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx16si },
    &operand_data[13582],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx1di },
    &operand_data[13589],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx2di },
    &operand_data[13596],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx4di },
    &operand_data[13603],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5344 */
  {
    "pred_seriesvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vid.v\t%0%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_seriesvnx8di },
    &operand_data[13610],
    7,
    7,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_addvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx1sf },
    &operand_data[13617],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_mulvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx1sf },
    &operand_data[13617],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_smaxvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx1sf },
    &operand_data[13617],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_sminvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx1sf },
    &operand_data[13617],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_subvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1sf },
    &operand_data[13617],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_divvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1sf },
    &operand_data[13617],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_addvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx2sf },
    &operand_data[13626],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_mulvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx2sf },
    &operand_data[13626],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_smaxvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx2sf },
    &operand_data[13626],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_sminvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx2sf },
    &operand_data[13626],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_subvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2sf },
    &operand_data[13626],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_divvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2sf },
    &operand_data[13626],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_addvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx4sf },
    &operand_data[13635],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_mulvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx4sf },
    &operand_data[13635],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_smaxvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx4sf },
    &operand_data[13635],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_sminvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx4sf },
    &operand_data[13635],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_subvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4sf },
    &operand_data[13635],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_divvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4sf },
    &operand_data[13635],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_addvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx8sf },
    &operand_data[13644],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_mulvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx8sf },
    &operand_data[13644],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_smaxvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx8sf },
    &operand_data[13644],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_sminvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx8sf },
    &operand_data[13644],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_subvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8sf },
    &operand_data[13644],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_divvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8sf },
    &operand_data[13644],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_addvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx16sf },
    &operand_data[13653],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_mulvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx16sf },
    &operand_data[13653],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_smaxvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx16sf },
    &operand_data[13653],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_sminvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx16sf },
    &operand_data[13653],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_subvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx16sf },
    &operand_data[13653],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_divvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx16sf },
    &operand_data[13653],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_addvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx1df },
    &operand_data[13662],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_mulvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx1df },
    &operand_data[13662],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_smaxvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx1df },
    &operand_data[13662],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_sminvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx1df },
    &operand_data[13662],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_subvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1df },
    &operand_data[13662],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_divvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1df },
    &operand_data[13662],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_addvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx2df },
    &operand_data[13671],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_mulvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx2df },
    &operand_data[13671],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_smaxvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx2df },
    &operand_data[13671],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_sminvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx2df },
    &operand_data[13671],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_subvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2df },
    &operand_data[13671],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_divvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2df },
    &operand_data[13671],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_addvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx4df },
    &operand_data[13680],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_mulvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx4df },
    &operand_data[13680],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_smaxvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx4df },
    &operand_data[13680],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_sminvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx4df },
    &operand_data[13680],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_subvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4df },
    &operand_data[13680],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_divvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4df },
    &operand_data[13680],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_addvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx8df },
    &operand_data[13689],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_mulvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx8df },
    &operand_data[13689],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_smaxvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx8df },
    &operand_data[13689],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_sminvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx8df },
    &operand_data[13689],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_subvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8df },
    &operand_data[13689],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5372 */
  {
    "pred_divvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8df },
    &operand_data[13689],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_addvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx1sf_scalar },
    &operand_data[13698],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_mulvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx1sf_scalar },
    &operand_data[13698],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_smaxvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx1sf_scalar },
    &operand_data[13698],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_sminvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx1sf_scalar },
    &operand_data[13698],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_addvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx2sf_scalar },
    &operand_data[13707],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_mulvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx2sf_scalar },
    &operand_data[13707],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_smaxvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx2sf_scalar },
    &operand_data[13707],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_sminvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx2sf_scalar },
    &operand_data[13707],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_addvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx4sf_scalar },
    &operand_data[13716],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_mulvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx4sf_scalar },
    &operand_data[13716],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_smaxvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx4sf_scalar },
    &operand_data[13716],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_sminvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx4sf_scalar },
    &operand_data[13716],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_addvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx8sf_scalar },
    &operand_data[13725],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_mulvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx8sf_scalar },
    &operand_data[13725],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_smaxvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx8sf_scalar },
    &operand_data[13725],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_sminvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx8sf_scalar },
    &operand_data[13725],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_addvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx16sf_scalar },
    &operand_data[13734],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_mulvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx16sf_scalar },
    &operand_data[13734],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_smaxvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx16sf_scalar },
    &operand_data[13734],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_sminvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx16sf_scalar },
    &operand_data[13734],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_addvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx1df_scalar },
    &operand_data[13743],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_mulvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx1df_scalar },
    &operand_data[13743],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_smaxvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx1df_scalar },
    &operand_data[13743],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_sminvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx1df_scalar },
    &operand_data[13743],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_addvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx2df_scalar },
    &operand_data[13752],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_mulvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx2df_scalar },
    &operand_data[13752],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_smaxvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx2df_scalar },
    &operand_data[13752],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_sminvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx2df_scalar },
    &operand_data[13752],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_addvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx4df_scalar },
    &operand_data[13761],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_mulvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx4df_scalar },
    &operand_data[13761],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_smaxvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx4df_scalar },
    &operand_data[13761],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_sminvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx4df_scalar },
    &operand_data[13761],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_addvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx8df_scalar },
    &operand_data[13770],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_mulvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx8df_scalar },
    &operand_data[13770],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_smaxvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmax.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx8df_scalar },
    &operand_data[13770],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5392 */
  {
    "pred_sminvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmin.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx8df_scalar },
    &operand_data[13770],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_subvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1sf_scalar },
    &operand_data[13698],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_divvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1sf_scalar },
    &operand_data[13698],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_subvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2sf_scalar },
    &operand_data[13707],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_divvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2sf_scalar },
    &operand_data[13707],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_subvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4sf_scalar },
    &operand_data[13716],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_divvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4sf_scalar },
    &operand_data[13716],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_subvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8sf_scalar },
    &operand_data[13725],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_divvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8sf_scalar },
    &operand_data[13725],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_subvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx16sf_scalar },
    &operand_data[13734],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_divvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx16sf_scalar },
    &operand_data[13734],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_subvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1df_scalar },
    &operand_data[13743],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_divvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1df_scalar },
    &operand_data[13743],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_subvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2df_scalar },
    &operand_data[13752],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_divvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2df_scalar },
    &operand_data[13752],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_subvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4df_scalar },
    &operand_data[13761],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_divvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4df_scalar },
    &operand_data[13761],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_subvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8df_scalar },
    &operand_data[13770],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5413 */
  {
    "pred_divvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8df_scalar },
    &operand_data[13770],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_subvnx1sf_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1sf_reverse_scalar },
    &operand_data[13698],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_divvnx1sf_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1sf_reverse_scalar },
    &operand_data[13698],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_subvnx2sf_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2sf_reverse_scalar },
    &operand_data[13707],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_divvnx2sf_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2sf_reverse_scalar },
    &operand_data[13707],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_subvnx4sf_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4sf_reverse_scalar },
    &operand_data[13716],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_divvnx4sf_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4sf_reverse_scalar },
    &operand_data[13716],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_subvnx8sf_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8sf_reverse_scalar },
    &operand_data[13725],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_divvnx8sf_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8sf_reverse_scalar },
    &operand_data[13725],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_subvnx16sf_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx16sf_reverse_scalar },
    &operand_data[13734],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_divvnx16sf_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx16sf_reverse_scalar },
    &operand_data[13734],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_subvnx1df_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1df_reverse_scalar },
    &operand_data[13743],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_divvnx1df_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1df_reverse_scalar },
    &operand_data[13743],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_subvnx2df_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2df_reverse_scalar },
    &operand_data[13752],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_divvnx2df_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2df_reverse_scalar },
    &operand_data[13752],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_subvnx4df_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4df_reverse_scalar },
    &operand_data[13761],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_divvnx4df_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4df_reverse_scalar },
    &operand_data[13761],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_subvnx8df_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8df_reverse_scalar },
    &operand_data[13770],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5434 */
  {
    "pred_divvnx8df_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrdiv.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8df_reverse_scalar },
    &operand_data[13770],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_copysignvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx1sf },
    &operand_data[13617],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_ncopysignvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx1sf },
    &operand_data[13617],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_xorsignvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx1sf },
    &operand_data[13617],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_copysignvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx2sf },
    &operand_data[13626],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_ncopysignvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx2sf },
    &operand_data[13626],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_xorsignvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx2sf },
    &operand_data[13626],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_copysignvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx4sf },
    &operand_data[13635],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_ncopysignvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx4sf },
    &operand_data[13635],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_xorsignvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx4sf },
    &operand_data[13635],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_copysignvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx8sf },
    &operand_data[13644],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_ncopysignvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx8sf },
    &operand_data[13644],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_xorsignvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx8sf },
    &operand_data[13644],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_copysignvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx16sf },
    &operand_data[13653],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_ncopysignvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx16sf },
    &operand_data[13653],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_xorsignvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx16sf },
    &operand_data[13653],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_copysignvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx1df },
    &operand_data[13662],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_ncopysignvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx1df },
    &operand_data[13662],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_xorsignvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx1df },
    &operand_data[13662],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_copysignvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx2df },
    &operand_data[13671],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_ncopysignvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx2df },
    &operand_data[13671],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_xorsignvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx2df },
    &operand_data[13671],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_copysignvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx4df },
    &operand_data[13680],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_ncopysignvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx4df },
    &operand_data[13680],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_xorsignvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx4df },
    &operand_data[13680],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_copysignvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx8df },
    &operand_data[13689],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_ncopysignvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx8df },
    &operand_data[13689],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5455 */
  {
    "pred_xorsignvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx8df },
    &operand_data[13689],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_copysignvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx1sf_scalar },
    &operand_data[13698],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_ncopysignvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx1sf_scalar },
    &operand_data[13698],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_xorsignvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx1sf_scalar },
    &operand_data[13698],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_copysignvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx2sf_scalar },
    &operand_data[13707],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_ncopysignvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx2sf_scalar },
    &operand_data[13707],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_xorsignvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx2sf_scalar },
    &operand_data[13707],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_copysignvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx4sf_scalar },
    &operand_data[13716],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_ncopysignvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx4sf_scalar },
    &operand_data[13716],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_xorsignvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx4sf_scalar },
    &operand_data[13716],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_copysignvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx8sf_scalar },
    &operand_data[13725],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_ncopysignvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx8sf_scalar },
    &operand_data[13725],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_xorsignvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx8sf_scalar },
    &operand_data[13725],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_copysignvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx16sf_scalar },
    &operand_data[13734],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_ncopysignvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx16sf_scalar },
    &operand_data[13734],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_xorsignvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx16sf_scalar },
    &operand_data[13734],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_copysignvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx1df_scalar },
    &operand_data[13743],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_ncopysignvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx1df_scalar },
    &operand_data[13743],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_xorsignvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx1df_scalar },
    &operand_data[13743],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_copysignvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx2df_scalar },
    &operand_data[13752],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_ncopysignvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx2df_scalar },
    &operand_data[13752],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_xorsignvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx2df_scalar },
    &operand_data[13752],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_copysignvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx4df_scalar },
    &operand_data[13761],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_ncopysignvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx4df_scalar },
    &operand_data[13761],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_xorsignvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx4df_scalar },
    &operand_data[13761],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_copysignvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnj.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_copysignvnx8df_scalar },
    &operand_data[13770],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_ncopysignvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjn.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ncopysignvnx8df_scalar },
    &operand_data[13770],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5475 */
  {
    "pred_xorsignvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsgnjx.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorsignvnx8df_scalar },
    &operand_data[13770],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_maddvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4780 },
#else
    { 0, output_4780, 0 },
#endif
    { 0 },
    &operand_data[13779],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_msubvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4781 },
#else
    { 0, output_4781, 0 },
#endif
    { 0 },
    &operand_data[13779],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_maddvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4782 },
#else
    { 0, output_4782, 0 },
#endif
    { 0 },
    &operand_data[13788],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_msubvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4783 },
#else
    { 0, output_4783, 0 },
#endif
    { 0 },
    &operand_data[13788],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_maddvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4784 },
#else
    { 0, output_4784, 0 },
#endif
    { 0 },
    &operand_data[13797],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_msubvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4785 },
#else
    { 0, output_4785, 0 },
#endif
    { 0 },
    &operand_data[13797],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_maddvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4786 },
#else
    { 0, output_4786, 0 },
#endif
    { 0 },
    &operand_data[13806],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_msubvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4787 },
#else
    { 0, output_4787, 0 },
#endif
    { 0 },
    &operand_data[13806],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_maddvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4788 },
#else
    { 0, output_4788, 0 },
#endif
    { 0 },
    &operand_data[13815],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_msubvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4789 },
#else
    { 0, output_4789, 0 },
#endif
    { 0 },
    &operand_data[13815],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_maddvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4790 },
#else
    { 0, output_4790, 0 },
#endif
    { 0 },
    &operand_data[13824],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_msubvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4791 },
#else
    { 0, output_4791, 0 },
#endif
    { 0 },
    &operand_data[13824],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_maddvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4792 },
#else
    { 0, output_4792, 0 },
#endif
    { 0 },
    &operand_data[13833],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_msubvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4793 },
#else
    { 0, output_4793, 0 },
#endif
    { 0 },
    &operand_data[13833],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_maddvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4794 },
#else
    { 0, output_4794, 0 },
#endif
    { 0 },
    &operand_data[13842],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_msubvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4795 },
#else
    { 0, output_4795, 0 },
#endif
    { 0 },
    &operand_data[13842],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_maddvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4796 },
#else
    { 0, output_4796, 0 },
#endif
    { 0 },
    &operand_data[13851],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5528 */
  {
    "*pred_msubvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4797 },
#else
    { 0, output_4797, 0 },
#endif
    { 0 },
    &operand_data[13851],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_maccvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4798 },
#else
    { 0, output_4798, 0 },
#endif
    { 0 },
    &operand_data[13860],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_msacvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4799 },
#else
    { 0, output_4799, 0 },
#endif
    { 0 },
    &operand_data[13860],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_maccvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4800 },
#else
    { 0, output_4800, 0 },
#endif
    { 0 },
    &operand_data[13869],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_msacvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4801 },
#else
    { 0, output_4801, 0 },
#endif
    { 0 },
    &operand_data[13869],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_maccvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4802 },
#else
    { 0, output_4802, 0 },
#endif
    { 0 },
    &operand_data[13878],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_msacvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4803 },
#else
    { 0, output_4803, 0 },
#endif
    { 0 },
    &operand_data[13878],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_maccvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4804 },
#else
    { 0, output_4804, 0 },
#endif
    { 0 },
    &operand_data[13887],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_msacvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4805 },
#else
    { 0, output_4805, 0 },
#endif
    { 0 },
    &operand_data[13887],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_maccvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4806 },
#else
    { 0, output_4806, 0 },
#endif
    { 0 },
    &operand_data[13896],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_msacvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4807 },
#else
    { 0, output_4807, 0 },
#endif
    { 0 },
    &operand_data[13896],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_maccvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4808 },
#else
    { 0, output_4808, 0 },
#endif
    { 0 },
    &operand_data[13905],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_msacvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4809 },
#else
    { 0, output_4809, 0 },
#endif
    { 0 },
    &operand_data[13905],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_maccvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4810 },
#else
    { 0, output_4810, 0 },
#endif
    { 0 },
    &operand_data[13914],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_msacvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4811 },
#else
    { 0, output_4811, 0 },
#endif
    { 0 },
    &operand_data[13914],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_maccvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4812 },
#else
    { 0, output_4812, 0 },
#endif
    { 0 },
    &operand_data[13923],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_msacvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4813 },
#else
    { 0, output_4813, 0 },
#endif
    { 0 },
    &operand_data[13923],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_maccvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4814 },
#else
    { 0, output_4814, 0 },
#endif
    { 0 },
    &operand_data[13932],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5559 */
  {
    "*pred_msacvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4815 },
#else
    { 0, output_4815, 0 },
#endif
    { 0 },
    &operand_data[13932],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_addvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4816 },
#else
    { 0, output_4816, 0 },
#endif
    { 0 },
    &operand_data[13941],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_subvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4817 },
#else
    { 0, output_4817, 0 },
#endif
    { 0 },
    &operand_data[13941],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_addvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4818 },
#else
    { 0, output_4818, 0 },
#endif
    { 0 },
    &operand_data[13951],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_subvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4819 },
#else
    { 0, output_4819, 0 },
#endif
    { 0 },
    &operand_data[13951],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_addvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4820 },
#else
    { 0, output_4820, 0 },
#endif
    { 0 },
    &operand_data[13961],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_subvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4821 },
#else
    { 0, output_4821, 0 },
#endif
    { 0 },
    &operand_data[13961],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_addvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4822 },
#else
    { 0, output_4822, 0 },
#endif
    { 0 },
    &operand_data[13971],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_subvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4823 },
#else
    { 0, output_4823, 0 },
#endif
    { 0 },
    &operand_data[13971],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_addvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4824 },
#else
    { 0, output_4824, 0 },
#endif
    { 0 },
    &operand_data[13981],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_subvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4825 },
#else
    { 0, output_4825, 0 },
#endif
    { 0 },
    &operand_data[13981],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_addvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4826 },
#else
    { 0, output_4826, 0 },
#endif
    { 0 },
    &operand_data[13991],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_subvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4827 },
#else
    { 0, output_4827, 0 },
#endif
    { 0 },
    &operand_data[13991],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_addvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4828 },
#else
    { 0, output_4828, 0 },
#endif
    { 0 },
    &operand_data[14001],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_subvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4829 },
#else
    { 0, output_4829, 0 },
#endif
    { 0 },
    &operand_data[14001],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_addvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4830 },
#else
    { 0, output_4830, 0 },
#endif
    { 0 },
    &operand_data[14011],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_subvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4831 },
#else
    { 0, output_4831, 0 },
#endif
    { 0 },
    &operand_data[14011],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_addvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4832 },
#else
    { 0, output_4832, 0 },
#endif
    { 0 },
    &operand_data[14021],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5590 */
  {
    "*pred_mul_subvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4833 },
#else
    { 0, output_4833, 0 },
#endif
    { 0 },
    &operand_data[14021],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_maddvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4834 },
#else
    { 0, output_4834, 0 },
#endif
    { 0 },
    &operand_data[14031],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_msubvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4835 },
#else
    { 0, output_4835, 0 },
#endif
    { 0 },
    &operand_data[14031],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_maddvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4836 },
#else
    { 0, output_4836, 0 },
#endif
    { 0 },
    &operand_data[14040],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_msubvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4837 },
#else
    { 0, output_4837, 0 },
#endif
    { 0 },
    &operand_data[14040],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_maddvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4838 },
#else
    { 0, output_4838, 0 },
#endif
    { 0 },
    &operand_data[14049],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_msubvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4839 },
#else
    { 0, output_4839, 0 },
#endif
    { 0 },
    &operand_data[14049],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_maddvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4840 },
#else
    { 0, output_4840, 0 },
#endif
    { 0 },
    &operand_data[14058],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_msubvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4841 },
#else
    { 0, output_4841, 0 },
#endif
    { 0 },
    &operand_data[14058],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_maddvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4842 },
#else
    { 0, output_4842, 0 },
#endif
    { 0 },
    &operand_data[14067],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_msubvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4843 },
#else
    { 0, output_4843, 0 },
#endif
    { 0 },
    &operand_data[14067],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_maddvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4844 },
#else
    { 0, output_4844, 0 },
#endif
    { 0 },
    &operand_data[14076],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_msubvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4845 },
#else
    { 0, output_4845, 0 },
#endif
    { 0 },
    &operand_data[14076],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_maddvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4846 },
#else
    { 0, output_4846, 0 },
#endif
    { 0 },
    &operand_data[14085],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_msubvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4847 },
#else
    { 0, output_4847, 0 },
#endif
    { 0 },
    &operand_data[14085],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_maddvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4848 },
#else
    { 0, output_4848, 0 },
#endif
    { 0 },
    &operand_data[14094],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_msubvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4849 },
#else
    { 0, output_4849, 0 },
#endif
    { 0 },
    &operand_data[14094],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_maddvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4850 },
#else
    { 0, output_4850, 0 },
#endif
    { 0 },
    &operand_data[14103],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5646 */
  {
    "*pred_msubvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4851 },
#else
    { 0, output_4851, 0 },
#endif
    { 0 },
    &operand_data[14103],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_maccvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4852 },
#else
    { 0, output_4852, 0 },
#endif
    { 0 },
    &operand_data[14112],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_msacvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4853 },
#else
    { 0, output_4853, 0 },
#endif
    { 0 },
    &operand_data[14112],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_maccvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4854 },
#else
    { 0, output_4854, 0 },
#endif
    { 0 },
    &operand_data[14121],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_msacvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4855 },
#else
    { 0, output_4855, 0 },
#endif
    { 0 },
    &operand_data[14121],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_maccvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4856 },
#else
    { 0, output_4856, 0 },
#endif
    { 0 },
    &operand_data[14130],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_msacvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4857 },
#else
    { 0, output_4857, 0 },
#endif
    { 0 },
    &operand_data[14130],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_maccvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4858 },
#else
    { 0, output_4858, 0 },
#endif
    { 0 },
    &operand_data[14139],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_msacvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4859 },
#else
    { 0, output_4859, 0 },
#endif
    { 0 },
    &operand_data[14139],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_maccvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4860 },
#else
    { 0, output_4860, 0 },
#endif
    { 0 },
    &operand_data[14148],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_msacvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4861 },
#else
    { 0, output_4861, 0 },
#endif
    { 0 },
    &operand_data[14148],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_maccvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4862 },
#else
    { 0, output_4862, 0 },
#endif
    { 0 },
    &operand_data[14157],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_msacvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4863 },
#else
    { 0, output_4863, 0 },
#endif
    { 0 },
    &operand_data[14157],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_maccvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4864 },
#else
    { 0, output_4864, 0 },
#endif
    { 0 },
    &operand_data[14166],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_msacvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4865 },
#else
    { 0, output_4865, 0 },
#endif
    { 0 },
    &operand_data[14166],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_maccvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4866 },
#else
    { 0, output_4866, 0 },
#endif
    { 0 },
    &operand_data[14175],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_msacvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4867 },
#else
    { 0, output_4867, 0 },
#endif
    { 0 },
    &operand_data[14175],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_maccvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4868 },
#else
    { 0, output_4868, 0 },
#endif
    { 0 },
    &operand_data[14184],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5678 */
  {
    "*pred_msacvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4869 },
#else
    { 0, output_4869, 0 },
#endif
    { 0 },
    &operand_data[14184],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_addvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4870 },
#else
    { 0, output_4870, 0 },
#endif
    { 0 },
    &operand_data[14193],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_subvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4871 },
#else
    { 0, output_4871, 0 },
#endif
    { 0 },
    &operand_data[14193],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_addvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4872 },
#else
    { 0, output_4872, 0 },
#endif
    { 0 },
    &operand_data[14203],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_subvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4873 },
#else
    { 0, output_4873, 0 },
#endif
    { 0 },
    &operand_data[14203],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_addvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4874 },
#else
    { 0, output_4874, 0 },
#endif
    { 0 },
    &operand_data[14213],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_subvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4875 },
#else
    { 0, output_4875, 0 },
#endif
    { 0 },
    &operand_data[14213],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_addvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4876 },
#else
    { 0, output_4876, 0 },
#endif
    { 0 },
    &operand_data[14223],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_subvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4877 },
#else
    { 0, output_4877, 0 },
#endif
    { 0 },
    &operand_data[14223],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_addvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4878 },
#else
    { 0, output_4878, 0 },
#endif
    { 0 },
    &operand_data[14233],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_subvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4879 },
#else
    { 0, output_4879, 0 },
#endif
    { 0 },
    &operand_data[14233],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_addvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4880 },
#else
    { 0, output_4880, 0 },
#endif
    { 0 },
    &operand_data[14243],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_subvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4881 },
#else
    { 0, output_4881, 0 },
#endif
    { 0 },
    &operand_data[14243],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_addvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4882 },
#else
    { 0, output_4882, 0 },
#endif
    { 0 },
    &operand_data[14253],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_subvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4883 },
#else
    { 0, output_4883, 0 },
#endif
    { 0 },
    &operand_data[14253],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_addvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4884 },
#else
    { 0, output_4884, 0 },
#endif
    { 0 },
    &operand_data[14263],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_subvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4885 },
#else
    { 0, output_4885, 0 },
#endif
    { 0 },
    &operand_data[14263],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_addvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4886 },
#else
    { 0, output_4886, 0 },
#endif
    { 0 },
    &operand_data[14273],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5710 */
  {
    "*pred_mul_subvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4887 },
#else
    { 0, output_4887, 0 },
#endif
    { 0 },
    &operand_data[14273],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmsubvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4888 },
#else
    { 0, output_4888, 0 },
#endif
    { 0 },
    &operand_data[13779],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmaddvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4889 },
#else
    { 0, output_4889, 0 },
#endif
    { 0 },
    &operand_data[13779],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmsubvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4890 },
#else
    { 0, output_4890, 0 },
#endif
    { 0 },
    &operand_data[13788],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmaddvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4891 },
#else
    { 0, output_4891, 0 },
#endif
    { 0 },
    &operand_data[13788],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmsubvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4892 },
#else
    { 0, output_4892, 0 },
#endif
    { 0 },
    &operand_data[13797],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmaddvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4893 },
#else
    { 0, output_4893, 0 },
#endif
    { 0 },
    &operand_data[13797],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmsubvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4894 },
#else
    { 0, output_4894, 0 },
#endif
    { 0 },
    &operand_data[13806],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmaddvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4895 },
#else
    { 0, output_4895, 0 },
#endif
    { 0 },
    &operand_data[13806],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmsubvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4896 },
#else
    { 0, output_4896, 0 },
#endif
    { 0 },
    &operand_data[13815],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmaddvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4897 },
#else
    { 0, output_4897, 0 },
#endif
    { 0 },
    &operand_data[13815],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmsubvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4898 },
#else
    { 0, output_4898, 0 },
#endif
    { 0 },
    &operand_data[13824],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmaddvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4899 },
#else
    { 0, output_4899, 0 },
#endif
    { 0 },
    &operand_data[13824],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmsubvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4900 },
#else
    { 0, output_4900, 0 },
#endif
    { 0 },
    &operand_data[13833],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmaddvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4901 },
#else
    { 0, output_4901, 0 },
#endif
    { 0 },
    &operand_data[13833],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmsubvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4902 },
#else
    { 0, output_4902, 0 },
#endif
    { 0 },
    &operand_data[13842],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmaddvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4903 },
#else
    { 0, output_4903, 0 },
#endif
    { 0 },
    &operand_data[13842],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmsubvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4904 },
#else
    { 0, output_4904, 0 },
#endif
    { 0 },
    &operand_data[13851],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5771 */
  {
    "*pred_nmaddvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4905 },
#else
    { 0, output_4905, 0 },
#endif
    { 0 },
    &operand_data[13851],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmsacvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4906 },
#else
    { 0, output_4906, 0 },
#endif
    { 0 },
    &operand_data[13860],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmaccvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4907 },
#else
    { 0, output_4907, 0 },
#endif
    { 0 },
    &operand_data[13860],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmsacvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4908 },
#else
    { 0, output_4908, 0 },
#endif
    { 0 },
    &operand_data[13869],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmaccvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4909 },
#else
    { 0, output_4909, 0 },
#endif
    { 0 },
    &operand_data[13869],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmsacvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4910 },
#else
    { 0, output_4910, 0 },
#endif
    { 0 },
    &operand_data[13878],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmaccvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4911 },
#else
    { 0, output_4911, 0 },
#endif
    { 0 },
    &operand_data[13878],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmsacvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4912 },
#else
    { 0, output_4912, 0 },
#endif
    { 0 },
    &operand_data[13887],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmaccvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4913 },
#else
    { 0, output_4913, 0 },
#endif
    { 0 },
    &operand_data[13887],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmsacvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4914 },
#else
    { 0, output_4914, 0 },
#endif
    { 0 },
    &operand_data[13896],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmaccvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4915 },
#else
    { 0, output_4915, 0 },
#endif
    { 0 },
    &operand_data[13896],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmsacvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4916 },
#else
    { 0, output_4916, 0 },
#endif
    { 0 },
    &operand_data[13905],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmaccvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4917 },
#else
    { 0, output_4917, 0 },
#endif
    { 0 },
    &operand_data[13905],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmsacvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4918 },
#else
    { 0, output_4918, 0 },
#endif
    { 0 },
    &operand_data[13914],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmaccvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4919 },
#else
    { 0, output_4919, 0 },
#endif
    { 0 },
    &operand_data[13914],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmsacvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4920 },
#else
    { 0, output_4920, 0 },
#endif
    { 0 },
    &operand_data[13923],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmaccvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4921 },
#else
    { 0, output_4921, 0 },
#endif
    { 0 },
    &operand_data[13923],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmsacvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4922 },
#else
    { 0, output_4922, 0 },
#endif
    { 0 },
    &operand_data[13932],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5803 */
  {
    "*pred_nmaccvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4923 },
#else
    { 0, output_4923, 0 },
#endif
    { 0 },
    &operand_data[13932],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_addvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4924 },
#else
    { 0, output_4924, 0 },
#endif
    { 0 },
    &operand_data[13941],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_subvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4925 },
#else
    { 0, output_4925, 0 },
#endif
    { 0 },
    &operand_data[13941],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_addvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4926 },
#else
    { 0, output_4926, 0 },
#endif
    { 0 },
    &operand_data[13951],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_subvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4927 },
#else
    { 0, output_4927, 0 },
#endif
    { 0 },
    &operand_data[13951],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_addvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4928 },
#else
    { 0, output_4928, 0 },
#endif
    { 0 },
    &operand_data[13961],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_subvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4929 },
#else
    { 0, output_4929, 0 },
#endif
    { 0 },
    &operand_data[13961],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_addvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4930 },
#else
    { 0, output_4930, 0 },
#endif
    { 0 },
    &operand_data[13971],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_subvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4931 },
#else
    { 0, output_4931, 0 },
#endif
    { 0 },
    &operand_data[13971],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_addvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4932 },
#else
    { 0, output_4932, 0 },
#endif
    { 0 },
    &operand_data[13981],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_subvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4933 },
#else
    { 0, output_4933, 0 },
#endif
    { 0 },
    &operand_data[13981],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_addvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4934 },
#else
    { 0, output_4934, 0 },
#endif
    { 0 },
    &operand_data[13991],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_subvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4935 },
#else
    { 0, output_4935, 0 },
#endif
    { 0 },
    &operand_data[13991],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_addvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4936 },
#else
    { 0, output_4936, 0 },
#endif
    { 0 },
    &operand_data[14001],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_subvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4937 },
#else
    { 0, output_4937, 0 },
#endif
    { 0 },
    &operand_data[14001],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_addvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4938 },
#else
    { 0, output_4938, 0 },
#endif
    { 0 },
    &operand_data[14011],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_subvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4939 },
#else
    { 0, output_4939, 0 },
#endif
    { 0 },
    &operand_data[14011],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_addvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4940 },
#else
    { 0, output_4940, 0 },
#endif
    { 0 },
    &operand_data[14021],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5835 */
  {
    "*pred_mul_neg_subvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4941 },
#else
    { 0, output_4941, 0 },
#endif
    { 0 },
    &operand_data[14021],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmsubvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4942 },
#else
    { 0, output_4942, 0 },
#endif
    { 0 },
    &operand_data[14031],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmaddvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4943 },
#else
    { 0, output_4943, 0 },
#endif
    { 0 },
    &operand_data[14031],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmsubvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4944 },
#else
    { 0, output_4944, 0 },
#endif
    { 0 },
    &operand_data[14040],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmaddvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4945 },
#else
    { 0, output_4945, 0 },
#endif
    { 0 },
    &operand_data[14040],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmsubvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4946 },
#else
    { 0, output_4946, 0 },
#endif
    { 0 },
    &operand_data[14049],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmaddvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4947 },
#else
    { 0, output_4947, 0 },
#endif
    { 0 },
    &operand_data[14049],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmsubvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4948 },
#else
    { 0, output_4948, 0 },
#endif
    { 0 },
    &operand_data[14058],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmaddvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4949 },
#else
    { 0, output_4949, 0 },
#endif
    { 0 },
    &operand_data[14058],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmsubvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4950 },
#else
    { 0, output_4950, 0 },
#endif
    { 0 },
    &operand_data[14067],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmaddvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4951 },
#else
    { 0, output_4951, 0 },
#endif
    { 0 },
    &operand_data[14067],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmsubvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4952 },
#else
    { 0, output_4952, 0 },
#endif
    { 0 },
    &operand_data[14076],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmaddvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4953 },
#else
    { 0, output_4953, 0 },
#endif
    { 0 },
    &operand_data[14076],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmsubvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4954 },
#else
    { 0, output_4954, 0 },
#endif
    { 0 },
    &operand_data[14085],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmaddvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4955 },
#else
    { 0, output_4955, 0 },
#endif
    { 0 },
    &operand_data[14085],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmsubvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4956 },
#else
    { 0, output_4956, 0 },
#endif
    { 0 },
    &operand_data[14094],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmaddvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4957 },
#else
    { 0, output_4957, 0 },
#endif
    { 0 },
    &operand_data[14094],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmsubvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4958 },
#else
    { 0, output_4958, 0 },
#endif
    { 0 },
    &operand_data[14103],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5893 */
  {
    "*pred_nmaddvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4959 },
#else
    { 0, output_4959, 0 },
#endif
    { 0 },
    &operand_data[14103],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmsacvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4960 },
#else
    { 0, output_4960, 0 },
#endif
    { 0 },
    &operand_data[14112],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmaccvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4961 },
#else
    { 0, output_4961, 0 },
#endif
    { 0 },
    &operand_data[14112],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmsacvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4962 },
#else
    { 0, output_4962, 0 },
#endif
    { 0 },
    &operand_data[14121],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmaccvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4963 },
#else
    { 0, output_4963, 0 },
#endif
    { 0 },
    &operand_data[14121],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmsacvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4964 },
#else
    { 0, output_4964, 0 },
#endif
    { 0 },
    &operand_data[14130],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmaccvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4965 },
#else
    { 0, output_4965, 0 },
#endif
    { 0 },
    &operand_data[14130],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmsacvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4966 },
#else
    { 0, output_4966, 0 },
#endif
    { 0 },
    &operand_data[14139],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmaccvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4967 },
#else
    { 0, output_4967, 0 },
#endif
    { 0 },
    &operand_data[14139],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmsacvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4968 },
#else
    { 0, output_4968, 0 },
#endif
    { 0 },
    &operand_data[14148],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmaccvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4969 },
#else
    { 0, output_4969, 0 },
#endif
    { 0 },
    &operand_data[14148],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmsacvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4970 },
#else
    { 0, output_4970, 0 },
#endif
    { 0 },
    &operand_data[14157],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmaccvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4971 },
#else
    { 0, output_4971, 0 },
#endif
    { 0 },
    &operand_data[14157],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmsacvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4972 },
#else
    { 0, output_4972, 0 },
#endif
    { 0 },
    &operand_data[14166],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmaccvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4973 },
#else
    { 0, output_4973, 0 },
#endif
    { 0 },
    &operand_data[14166],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmsacvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4974 },
#else
    { 0, output_4974, 0 },
#endif
    { 0 },
    &operand_data[14175],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmaccvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4975 },
#else
    { 0, output_4975, 0 },
#endif
    { 0 },
    &operand_data[14175],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmsacvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4976 },
#else
    { 0, output_4976, 0 },
#endif
    { 0 },
    &operand_data[14184],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5926 */
  {
    "*pred_nmaccvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4977 },
#else
    { 0, output_4977, 0 },
#endif
    { 0 },
    &operand_data[14184],
    9,
    9,
    1,
    4,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_addvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4978 },
#else
    { 0, output_4978, 0 },
#endif
    { 0 },
    &operand_data[14193],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_subvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4979 },
#else
    { 0, output_4979, 0 },
#endif
    { 0 },
    &operand_data[14193],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_addvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4980 },
#else
    { 0, output_4980, 0 },
#endif
    { 0 },
    &operand_data[14203],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_subvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4981 },
#else
    { 0, output_4981, 0 },
#endif
    { 0 },
    &operand_data[14203],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_addvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4982 },
#else
    { 0, output_4982, 0 },
#endif
    { 0 },
    &operand_data[14213],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_subvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4983 },
#else
    { 0, output_4983, 0 },
#endif
    { 0 },
    &operand_data[14213],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_addvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4984 },
#else
    { 0, output_4984, 0 },
#endif
    { 0 },
    &operand_data[14223],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_subvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4985 },
#else
    { 0, output_4985, 0 },
#endif
    { 0 },
    &operand_data[14223],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_addvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4986 },
#else
    { 0, output_4986, 0 },
#endif
    { 0 },
    &operand_data[14233],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_subvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4987 },
#else
    { 0, output_4987, 0 },
#endif
    { 0 },
    &operand_data[14233],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_addvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4988 },
#else
    { 0, output_4988, 0 },
#endif
    { 0 },
    &operand_data[14243],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_subvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4989 },
#else
    { 0, output_4989, 0 },
#endif
    { 0 },
    &operand_data[14243],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_addvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4990 },
#else
    { 0, output_4990, 0 },
#endif
    { 0 },
    &operand_data[14253],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_subvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4991 },
#else
    { 0, output_4991, 0 },
#endif
    { 0 },
    &operand_data[14253],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_addvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4992 },
#else
    { 0, output_4992, 0 },
#endif
    { 0 },
    &operand_data[14263],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_subvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4993 },
#else
    { 0, output_4993, 0 },
#endif
    { 0 },
    &operand_data[14263],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_addvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4994 },
#else
    { 0, output_4994, 0 },
#endif
    { 0 },
    &operand_data[14273],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5959 */
  {
    "*pred_mul_neg_subvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .multi = output_4995 },
#else
    { 0, output_4995, 0 },
#endif
    { 0 },
    &operand_data[14273],
    10,
    10,
    0,
    2,
    2
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_negvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx1sf },
    &operand_data[14283],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_absvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfabs.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_absvnx1sf },
    &operand_data[14283],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_sqrtvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsqrt.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sqrtvnx1sf },
    &operand_data[14283],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_negvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx2sf },
    &operand_data[14291],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_absvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfabs.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_absvnx2sf },
    &operand_data[14291],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_sqrtvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsqrt.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sqrtvnx2sf },
    &operand_data[14291],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_negvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx4sf },
    &operand_data[14299],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_absvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfabs.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_absvnx4sf },
    &operand_data[14299],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_sqrtvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsqrt.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sqrtvnx4sf },
    &operand_data[14299],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_negvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx8sf },
    &operand_data[14307],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_absvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfabs.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_absvnx8sf },
    &operand_data[14307],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_sqrtvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsqrt.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sqrtvnx8sf },
    &operand_data[14307],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_negvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx16sf },
    &operand_data[14315],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_absvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfabs.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_absvnx16sf },
    &operand_data[14315],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_sqrtvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsqrt.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sqrtvnx16sf },
    &operand_data[14315],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_negvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx1df },
    &operand_data[14323],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_absvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfabs.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_absvnx1df },
    &operand_data[14323],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_sqrtvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsqrt.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sqrtvnx1df },
    &operand_data[14323],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_negvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx2df },
    &operand_data[14331],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_absvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfabs.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_absvnx2df },
    &operand_data[14331],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_sqrtvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsqrt.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sqrtvnx2df },
    &operand_data[14331],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_negvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx4df },
    &operand_data[14339],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_absvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfabs.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_absvnx4df },
    &operand_data[14339],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_sqrtvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsqrt.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sqrtvnx4df },
    &operand_data[14339],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_negvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfneg.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_negvnx8df },
    &operand_data[14347],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_absvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfabs.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_absvnx8df },
    &operand_data[14347],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6006 */
  {
    "pred_sqrtvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfsqrt.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sqrtvnx8df },
    &operand_data[14347],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rsqrt7vnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsqrt7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rsqrt7vnx1sf },
    &operand_data[14283],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rec7vnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrec7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rec7vnx1sf },
    &operand_data[14283],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rsqrt7vnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsqrt7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rsqrt7vnx2sf },
    &operand_data[14291],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rec7vnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrec7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rec7vnx2sf },
    &operand_data[14291],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rsqrt7vnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsqrt7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rsqrt7vnx4sf },
    &operand_data[14299],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rec7vnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrec7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rec7vnx4sf },
    &operand_data[14299],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rsqrt7vnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsqrt7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rsqrt7vnx8sf },
    &operand_data[14307],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rec7vnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrec7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rec7vnx8sf },
    &operand_data[14307],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rsqrt7vnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsqrt7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rsqrt7vnx16sf },
    &operand_data[14315],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rec7vnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrec7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rec7vnx16sf },
    &operand_data[14315],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rsqrt7vnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsqrt7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rsqrt7vnx1df },
    &operand_data[14323],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rec7vnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrec7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rec7vnx1df },
    &operand_data[14323],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rsqrt7vnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsqrt7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rsqrt7vnx2df },
    &operand_data[14331],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rec7vnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrec7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rec7vnx2df },
    &operand_data[14331],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rsqrt7vnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsqrt7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rsqrt7vnx4df },
    &operand_data[14339],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rec7vnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrec7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rec7vnx4df },
    &operand_data[14339],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rsqrt7vnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrsqrt7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rsqrt7vnx8df },
    &operand_data[14347],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6029 */
  {
    "pred_rec7vnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfrec7.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rec7vnx8df },
    &operand_data[14347],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
  {
    "pred_classvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfclass.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_classvnx1sf },
    &operand_data[14355],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
  {
    "pred_classvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfclass.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_classvnx2sf },
    &operand_data[14363],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
  {
    "pred_classvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfclass.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_classvnx4sf },
    &operand_data[14371],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
  {
    "pred_classvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfclass.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_classvnx8sf },
    &operand_data[14379],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
  {
    "pred_classvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfclass.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_classvnx16sf },
    &operand_data[14387],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
  {
    "pred_classvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfclass.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_classvnx1df },
    &operand_data[14395],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
  {
    "pred_classvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfclass.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_classvnx2df },
    &operand_data[14403],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
  {
    "pred_classvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfclass.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_classvnx4df },
    &operand_data[14411],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6048 */
  {
    "pred_classvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfclass.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_classvnx8df },
    &operand_data[14419],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
  {
    "pred_dual_widen_addvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addvnx1df },
    &operand_data[14427],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
  {
    "pred_dual_widen_subvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subvnx1df },
    &operand_data[14427],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
  {
    "pred_dual_widen_mulvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulvnx1df },
    &operand_data[14427],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
  {
    "pred_dual_widen_addvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addvnx2df },
    &operand_data[14436],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
  {
    "pred_dual_widen_subvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subvnx2df },
    &operand_data[14436],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
  {
    "pred_dual_widen_mulvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulvnx2df },
    &operand_data[14436],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
  {
    "pred_dual_widen_addvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addvnx4df },
    &operand_data[14445],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
  {
    "pred_dual_widen_subvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subvnx4df },
    &operand_data[14445],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
  {
    "pred_dual_widen_mulvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulvnx4df },
    &operand_data[14445],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
  {
    "pred_dual_widen_addvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addvnx8df },
    &operand_data[14454],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
  {
    "pred_dual_widen_subvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subvnx8df },
    &operand_data[14454],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6076 */
  {
    "pred_dual_widen_mulvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmul.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulvnx8df },
    &operand_data[14454],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
  {
    "pred_dual_widen_addvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addvnx1df_scalar },
    &operand_data[14463],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
  {
    "pred_dual_widen_subvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subvnx1df_scalar },
    &operand_data[14463],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
  {
    "pred_dual_widen_mulvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulvnx1df_scalar },
    &operand_data[14463],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
  {
    "pred_dual_widen_addvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addvnx2df_scalar },
    &operand_data[14472],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
  {
    "pred_dual_widen_subvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subvnx2df_scalar },
    &operand_data[14472],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
  {
    "pred_dual_widen_mulvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulvnx2df_scalar },
    &operand_data[14472],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
  {
    "pred_dual_widen_addvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addvnx4df_scalar },
    &operand_data[14481],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
  {
    "pred_dual_widen_subvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subvnx4df_scalar },
    &operand_data[14481],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
  {
    "pred_dual_widen_mulvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulvnx4df_scalar },
    &operand_data[14481],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
  {
    "pred_dual_widen_addvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_addvnx8df_scalar },
    &operand_data[14490],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
  {
    "pred_dual_widen_subvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_subvnx8df_scalar },
    &operand_data[14490],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6098 */
  {
    "pred_dual_widen_mulvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmul.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_dual_widen_mulvnx8df_scalar },
    &operand_data[14490],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
  {
    "pred_single_widen_addvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addvnx1df },
    &operand_data[14499],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
  {
    "pred_single_widen_subvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subvnx1df },
    &operand_data[14499],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
  {
    "pred_single_widen_addvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addvnx2df },
    &operand_data[14508],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
  {
    "pred_single_widen_subvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subvnx2df },
    &operand_data[14508],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
  {
    "pred_single_widen_addvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addvnx4df },
    &operand_data[14517],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
  {
    "pred_single_widen_subvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subvnx4df },
    &operand_data[14517],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
  {
    "pred_single_widen_addvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addvnx8df },
    &operand_data[14526],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6121 */
  {
    "pred_single_widen_subvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.wv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subvnx8df },
    &operand_data[14526],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
  {
    "pred_single_widen_addvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.wf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addvnx1df_scalar },
    &operand_data[14535],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
  {
    "pred_single_widen_subvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.wf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subvnx1df_scalar },
    &operand_data[14535],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
  {
    "pred_single_widen_addvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.wf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addvnx2df_scalar },
    &operand_data[14544],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
  {
    "pred_single_widen_subvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.wf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subvnx2df_scalar },
    &operand_data[14544],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
  {
    "pred_single_widen_addvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.wf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addvnx4df_scalar },
    &operand_data[14553],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
  {
    "pred_single_widen_subvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.wf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subvnx4df_scalar },
    &operand_data[14553],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
  {
    "pred_single_widen_addvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwadd.wf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_addvnx8df_scalar },
    &operand_data[14562],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6142 */
  {
    "pred_single_widen_subvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwsub.wf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_single_widen_subvnx8df_scalar },
    &operand_data[14562],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
  {
    "pred_widen_mul_addvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_addvnx1df },
    &operand_data[14571],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
  {
    "pred_widen_mul_subvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmsac.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_subvnx1df },
    &operand_data[14571],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
  {
    "pred_widen_mul_addvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_addvnx2df },
    &operand_data[14580],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
  {
    "pred_widen_mul_subvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmsac.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_subvnx2df },
    &operand_data[14580],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
  {
    "pred_widen_mul_addvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_addvnx4df },
    &operand_data[14589],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
  {
    "pred_widen_mul_subvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmsac.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_subvnx4df },
    &operand_data[14589],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
  {
    "pred_widen_mul_addvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_addvnx8df },
    &operand_data[14598],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6171 */
  {
    "pred_widen_mul_subvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmsac.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_subvnx8df },
    &operand_data[14598],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
  {
    "pred_widen_mul_addvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmacc.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_addvnx1df_scalar },
    &operand_data[14607],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
  {
    "pred_widen_mul_subvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmsac.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_subvnx1df_scalar },
    &operand_data[14607],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
  {
    "pred_widen_mul_addvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmacc.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_addvnx2df_scalar },
    &operand_data[14616],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
  {
    "pred_widen_mul_subvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmsac.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_subvnx2df_scalar },
    &operand_data[14616],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
  {
    "pred_widen_mul_addvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmacc.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_addvnx4df_scalar },
    &operand_data[14625],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
  {
    "pred_widen_mul_subvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmsac.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_subvnx4df_scalar },
    &operand_data[14625],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
  {
    "pred_widen_mul_addvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmacc.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_addvnx8df_scalar },
    &operand_data[14634],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6195 */
  {
    "pred_widen_mul_subvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwmsac.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_subvnx8df_scalar },
    &operand_data[14634],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
  {
    "pred_widen_mul_neg_addvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmsac.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_addvnx1df },
    &operand_data[14571],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
  {
    "pred_widen_mul_neg_subvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_subvnx1df },
    &operand_data[14571],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
  {
    "pred_widen_mul_neg_addvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmsac.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_addvnx2df },
    &operand_data[14580],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
  {
    "pred_widen_mul_neg_subvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_subvnx2df },
    &operand_data[14580],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
  {
    "pred_widen_mul_neg_addvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmsac.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_addvnx4df },
    &operand_data[14589],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
  {
    "pred_widen_mul_neg_subvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_subvnx4df },
    &operand_data[14589],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
  {
    "pred_widen_mul_neg_addvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmsac.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_addvnx8df },
    &operand_data[14598],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6220 */
  {
    "pred_widen_mul_neg_subvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmacc.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_subvnx8df },
    &operand_data[14598],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
  {
    "pred_widen_mul_neg_addvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmsac.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_addvnx1df_scalar },
    &operand_data[14607],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
  {
    "pred_widen_mul_neg_subvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmacc.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_subvnx1df_scalar },
    &operand_data[14607],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
  {
    "pred_widen_mul_neg_addvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmsac.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_addvnx2df_scalar },
    &operand_data[14616],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
  {
    "pred_widen_mul_neg_subvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmacc.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_subvnx2df_scalar },
    &operand_data[14616],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
  {
    "pred_widen_mul_neg_addvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmsac.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_addvnx4df_scalar },
    &operand_data[14625],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
  {
    "pred_widen_mul_neg_subvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmacc.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_subvnx4df_scalar },
    &operand_data[14625],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
  {
    "pred_widen_mul_neg_addvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmsac.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_addvnx8df_scalar },
    &operand_data[14634],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6245 */
  {
    "pred_widen_mul_neg_subvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwnmacc.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_mul_neg_subvnx8df_scalar },
    &operand_data[14634],
    9,
    9,
    1,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6296 */
  {
    "*pred_cmpvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14643],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6296 */
  {
    "*pred_cmpvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14652],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6296 */
  {
    "*pred_cmpvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14661],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6296 */
  {
    "*pred_cmpvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14670],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6296 */
  {
    "*pred_cmpvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14679],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6296 */
  {
    "*pred_cmpvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14688],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6296 */
  {
    "*pred_cmpvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14697],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6296 */
  {
    "*pred_cmpvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14706],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6296 */
  {
    "*pred_cmpvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14715],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6316 */
  {
    "*pred_cmpvnx1sf_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14724],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6316 */
  {
    "*pred_cmpvnx2sf_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14733],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6316 */
  {
    "*pred_cmpvnx4sf_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14742],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6316 */
  {
    "*pred_cmpvnx8sf_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14751],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6316 */
  {
    "*pred_cmpvnx16sf_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14760],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6316 */
  {
    "*pred_cmpvnx1df_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14769],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6316 */
  {
    "*pred_cmpvnx2df_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14778],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6316 */
  {
    "*pred_cmpvnx4df_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14787],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6316 */
  {
    "*pred_cmpvnx8df_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vv\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14796],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6354 */
  {
    "*pred_cmpvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14805],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6354 */
  {
    "*pred_cmpvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14814],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6354 */
  {
    "*pred_cmpvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14823],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6354 */
  {
    "*pred_cmpvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14832],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6354 */
  {
    "*pred_cmpvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14841],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6354 */
  {
    "*pred_cmpvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14850],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6354 */
  {
    "*pred_cmpvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14859],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6354 */
  {
    "*pred_cmpvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14868],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6354 */
  {
    "*pred_cmpvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14877],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6375 */
  {
    "*pred_cmpvnx1sf_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14886],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6375 */
  {
    "*pred_cmpvnx2sf_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14895],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6375 */
  {
    "*pred_cmpvnx4sf_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14904],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6375 */
  {
    "*pred_cmpvnx8sf_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14913],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6375 */
  {
    "*pred_cmpvnx16sf_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14922],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6375 */
  {
    "*pred_cmpvnx1df_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14931],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6375 */
  {
    "*pred_cmpvnx2df_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14940],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6375 */
  {
    "*pred_cmpvnx4df_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14949],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6375 */
  {
    "*pred_cmpvnx8df_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14958],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6414 */
  {
    "*pred_eqnevnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14967],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6414 */
  {
    "*pred_eqnevnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14976],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6414 */
  {
    "*pred_eqnevnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14985],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6414 */
  {
    "*pred_eqnevnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[14994],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6414 */
  {
    "*pred_eqnevnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15003],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6414 */
  {
    "*pred_eqnevnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15012],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6414 */
  {
    "*pred_eqnevnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15021],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6414 */
  {
    "*pred_eqnevnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15030],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6414 */
  {
    "*pred_eqnevnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15039],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6435 */
  {
    "*pred_eqnevnx1sf_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15048],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6435 */
  {
    "*pred_eqnevnx2sf_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15057],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6435 */
  {
    "*pred_eqnevnx4sf_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15066],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6435 */
  {
    "*pred_eqnevnx8sf_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15075],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6435 */
  {
    "*pred_eqnevnx16sf_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15084],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6435 */
  {
    "*pred_eqnevnx1df_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15093],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6435 */
  {
    "*pred_eqnevnx2df_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15102],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6435 */
  {
    "*pred_eqnevnx4df_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15111],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6435 */
  {
    "*pred_eqnevnx8df_scalar_narrow",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmf%B3.vf\t%0,%4,%5%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[15120],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
  {
    "pred_mergevnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmerge.vfm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx1sf_scalar },
    &operand_data[15129],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
  {
    "pred_mergevnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmerge.vfm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx2sf_scalar },
    &operand_data[15137],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
  {
    "pred_mergevnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmerge.vfm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx4sf_scalar },
    &operand_data[15145],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
  {
    "pred_mergevnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmerge.vfm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx8sf_scalar },
    &operand_data[15153],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
  {
    "pred_mergevnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmerge.vfm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx16sf_scalar },
    &operand_data[15161],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
  {
    "pred_mergevnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmerge.vfm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx1df_scalar },
    &operand_data[15169],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
  {
    "pred_mergevnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmerge.vfm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx2df_scalar },
    &operand_data[15177],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
  {
    "pred_mergevnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmerge.vfm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx4df_scalar },
    &operand_data[15185],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6462 */
  {
    "pred_mergevnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmerge.vfm\t%0,%2,%3,%4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx8df_scalar },
    &operand_data[15193],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_x_fvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_x_fvnx1sf },
    &operand_data[14355],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_xu_fvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_xu_fvnx1sf },
    &operand_data[14355],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_x_fvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_x_fvnx2sf },
    &operand_data[14363],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_xu_fvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_xu_fvnx2sf },
    &operand_data[14363],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_x_fvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_x_fvnx4sf },
    &operand_data[14371],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_xu_fvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_xu_fvnx4sf },
    &operand_data[14371],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_x_fvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_x_fvnx8sf },
    &operand_data[14379],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_xu_fvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_xu_fvnx8sf },
    &operand_data[14379],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_x_fvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_x_fvnx16sf },
    &operand_data[14387],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_xu_fvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_xu_fvnx16sf },
    &operand_data[14387],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_x_fvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_x_fvnx1df },
    &operand_data[14395],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_xu_fvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_xu_fvnx1df },
    &operand_data[14395],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_x_fvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_x_fvnx2df },
    &operand_data[14403],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_xu_fvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_xu_fvnx2df },
    &operand_data[14403],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_x_fvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_x_fvnx4df },
    &operand_data[14411],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_xu_fvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_xu_fvnx4df },
    &operand_data[14411],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_x_fvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_x_fvnx8df },
    &operand_data[14419],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6489 */
  {
    "pred_fcvt_xu_fvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fcvt_xu_fvnx8df },
    &operand_data[14419],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fix_truncvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fix_truncvnx1sf },
    &operand_data[14355],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fixuns_truncvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fixuns_truncvnx1sf },
    &operand_data[14355],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fix_truncvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fix_truncvnx2sf },
    &operand_data[14363],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fixuns_truncvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fixuns_truncvnx2sf },
    &operand_data[14363],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fix_truncvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fix_truncvnx4sf },
    &operand_data[14371],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fixuns_truncvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fixuns_truncvnx4sf },
    &operand_data[14371],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fix_truncvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fix_truncvnx8sf },
    &operand_data[14379],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fixuns_truncvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fixuns_truncvnx8sf },
    &operand_data[14379],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fix_truncvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fix_truncvnx16sf },
    &operand_data[14387],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fixuns_truncvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fixuns_truncvnx16sf },
    &operand_data[14387],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fix_truncvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fix_truncvnx1df },
    &operand_data[14395],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fixuns_truncvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fixuns_truncvnx1df },
    &operand_data[14395],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fix_truncvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fix_truncvnx2df },
    &operand_data[14403],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fixuns_truncvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fixuns_truncvnx2df },
    &operand_data[14403],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fix_truncvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fix_truncvnx4df },
    &operand_data[14411],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fixuns_truncvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fixuns_truncvnx4df },
    &operand_data[14411],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fix_truncvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fix_truncvnx8df },
    &operand_data[14419],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6508 */
  {
    "pred_fixuns_truncvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fixuns_truncvnx8df },
    &operand_data[14419],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatvnx1sf },
    &operand_data[15201],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatunsvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatunsvnx1sf },
    &operand_data[15201],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatvnx2sf },
    &operand_data[15209],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatunsvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatunsvnx2sf },
    &operand_data[15209],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatvnx4sf },
    &operand_data[15217],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatunsvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatunsvnx4sf },
    &operand_data[15217],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatvnx8sf },
    &operand_data[15225],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatunsvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatunsvnx8sf },
    &operand_data[15225],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatvnx16sf },
    &operand_data[15233],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatunsvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatunsvnx16sf },
    &operand_data[15233],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatvnx1df },
    &operand_data[15241],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatunsvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatunsvnx1df },
    &operand_data[15241],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatvnx2df },
    &operand_data[15249],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatunsvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatunsvnx2df },
    &operand_data[15249],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatvnx4df },
    &operand_data[15257],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatunsvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatunsvnx4df },
    &operand_data[15257],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatvnx8df },
    &operand_data[15265],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6527 */
  {
    "pred_floatunsvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_floatunsvnx8df },
    &operand_data[15265],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
  {
    "pred_widen_fcvt_x_fvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fcvt_x_fvnx1di },
    &operand_data[15273],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
  {
    "pred_widen_fcvt_xu_fvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fcvt_xu_fvnx1di },
    &operand_data[15273],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
  {
    "pred_widen_fcvt_x_fvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fcvt_x_fvnx2di },
    &operand_data[15281],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
  {
    "pred_widen_fcvt_xu_fvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fcvt_xu_fvnx2di },
    &operand_data[15281],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
  {
    "pred_widen_fcvt_x_fvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fcvt_x_fvnx4di },
    &operand_data[15289],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
  {
    "pred_widen_fcvt_xu_fvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fcvt_xu_fvnx4di },
    &operand_data[15289],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
  {
    "pred_widen_fcvt_x_fvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fcvt_x_fvnx8di },
    &operand_data[15297],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6553 */
  {
    "pred_widen_fcvt_xu_fvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fcvt_xu_fvnx8di },
    &operand_data[15297],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
  {
    "pred_widen_fix_truncvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fix_truncvnx1di },
    &operand_data[15273],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
  {
    "pred_widen_fixuns_truncvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fixuns_truncvnx1di },
    &operand_data[15273],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
  {
    "pred_widen_fix_truncvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fix_truncvnx2di },
    &operand_data[15281],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
  {
    "pred_widen_fixuns_truncvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fixuns_truncvnx2di },
    &operand_data[15281],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
  {
    "pred_widen_fix_truncvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fix_truncvnx4di },
    &operand_data[15289],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
  {
    "pred_widen_fixuns_truncvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fixuns_truncvnx4di },
    &operand_data[15289],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
  {
    "pred_widen_fix_truncvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.rtz.x.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fix_truncvnx8di },
    &operand_data[15297],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6572 */
  {
    "pred_widen_fixuns_truncvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.rtz.xu.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_fixuns_truncvnx8di },
    &operand_data[15297],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatvnx1sf },
    &operand_data[15305],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatunsvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatunsvnx1sf },
    &operand_data[15305],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatvnx2sf },
    &operand_data[15313],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatunsvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatunsvnx2sf },
    &operand_data[15313],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatvnx4sf },
    &operand_data[15321],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatunsvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatunsvnx4sf },
    &operand_data[15321],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatvnx8sf },
    &operand_data[15329],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatunsvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatunsvnx8sf },
    &operand_data[15329],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatvnx16sf },
    &operand_data[15337],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatunsvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatunsvnx16sf },
    &operand_data[15337],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatvnx1df },
    &operand_data[15345],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatunsvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatunsvnx1df },
    &operand_data[15345],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatvnx2df },
    &operand_data[15353],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatunsvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatunsvnx2df },
    &operand_data[15353],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatvnx4df },
    &operand_data[15361],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatunsvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatunsvnx4df },
    &operand_data[15361],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.x.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatvnx8df },
    &operand_data[15369],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6591 */
  {
    "pred_widen_floatunsvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.xu.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_floatunsvnx8df },
    &operand_data[15369],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6610 */
  {
    "pred_extendvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx1df },
    &operand_data[15377],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6610 */
  {
    "pred_extendvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx2df },
    &operand_data[15385],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6610 */
  {
    "pred_extendvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx4df },
    &operand_data[15393],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6610 */
  {
    "pred_extendvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwcvt.f.f.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extendvnx8df },
    &operand_data[15401],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_x_fvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_x_fvnx1sf },
    &operand_data[15409],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_xu_fvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_xu_fvnx1sf },
    &operand_data[15409],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_x_fvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_x_fvnx2sf },
    &operand_data[15417],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_xu_fvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_xu_fvnx2sf },
    &operand_data[15417],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_x_fvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_x_fvnx4sf },
    &operand_data[15425],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_xu_fvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_xu_fvnx4sf },
    &operand_data[15425],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_x_fvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_x_fvnx8sf },
    &operand_data[15433],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_xu_fvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_xu_fvnx8sf },
    &operand_data[15433],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_x_fvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_x_fvnx16sf },
    &operand_data[15441],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_xu_fvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_xu_fvnx16sf },
    &operand_data[15441],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_x_fvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_x_fvnx1df },
    &operand_data[15449],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_xu_fvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_xu_fvnx1df },
    &operand_data[15449],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_x_fvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_x_fvnx2df },
    &operand_data[15457],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_xu_fvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_xu_fvnx2df },
    &operand_data[15457],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_x_fvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_x_fvnx4df },
    &operand_data[15465],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_xu_fvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_xu_fvnx4df },
    &operand_data[15465],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_x_fvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_x_fvnx8df },
    &operand_data[15473],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6636 */
  {
    "pred_narrow_fcvt_xu_fvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fcvt_xu_fvnx8df },
    &operand_data[15473],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fix_truncvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fix_truncvnx1sf },
    &operand_data[15409],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fixuns_truncvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fixuns_truncvnx1sf },
    &operand_data[15409],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fix_truncvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fix_truncvnx2sf },
    &operand_data[15417],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fixuns_truncvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fixuns_truncvnx2sf },
    &operand_data[15417],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fix_truncvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fix_truncvnx4sf },
    &operand_data[15425],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fixuns_truncvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fixuns_truncvnx4sf },
    &operand_data[15425],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fix_truncvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fix_truncvnx8sf },
    &operand_data[15433],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fixuns_truncvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fixuns_truncvnx8sf },
    &operand_data[15433],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fix_truncvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fix_truncvnx16sf },
    &operand_data[15441],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fixuns_truncvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fixuns_truncvnx16sf },
    &operand_data[15441],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fix_truncvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fix_truncvnx1df },
    &operand_data[15449],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fixuns_truncvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fixuns_truncvnx1df },
    &operand_data[15449],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fix_truncvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fix_truncvnx2df },
    &operand_data[15457],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fixuns_truncvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fixuns_truncvnx2df },
    &operand_data[15457],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fix_truncvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fix_truncvnx4df },
    &operand_data[15465],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fixuns_truncvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fixuns_truncvnx4df },
    &operand_data[15465],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fix_truncvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.x.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fix_truncvnx8df },
    &operand_data[15473],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6655 */
  {
    "pred_narrow_fixuns_truncvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rtz.xu.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_fixuns_truncvnx8df },
    &operand_data[15473],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
  {
    "pred_narrow_floatvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.f.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_floatvnx1di },
    &operand_data[15481],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
  {
    "pred_narrow_floatunsvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.f.xu.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_floatunsvnx1di },
    &operand_data[15481],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
  {
    "pred_narrow_floatvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.f.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_floatvnx2di },
    &operand_data[15489],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
  {
    "pred_narrow_floatunsvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.f.xu.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_floatunsvnx2di },
    &operand_data[15489],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
  {
    "pred_narrow_floatvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.f.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_floatvnx4di },
    &operand_data[15497],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
  {
    "pred_narrow_floatunsvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.f.xu.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_floatunsvnx4di },
    &operand_data[15497],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
  {
    "pred_narrow_floatvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.f.x.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_floatvnx8di },
    &operand_data[15505],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6674 */
  {
    "pred_narrow_floatunsvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.f.xu.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_narrow_floatunsvnx8di },
    &operand_data[15505],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6693 */
  {
    "pred_truncvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.f.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx1df },
    &operand_data[15513],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6693 */
  {
    "pred_truncvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.f.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx2df },
    &operand_data[15521],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6693 */
  {
    "pred_truncvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.f.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx4df },
    &operand_data[15529],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6693 */
  {
    "pred_truncvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.f.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_truncvnx8df },
    &operand_data[15537],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6712 */
  {
    "pred_rod_truncvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rod.f.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rod_truncvnx1df },
    &operand_data[15513],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6712 */
  {
    "pred_rod_truncvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rod.f.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rod_truncvnx2df },
    &operand_data[15521],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6712 */
  {
    "pred_rod_truncvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rod.f.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rod_truncvnx4df },
    &operand_data[15529],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6712 */
  {
    "pred_rod_truncvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfncvt.rod.f.f.w\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_rod_truncvnx8df },
    &operand_data[15537],
    8,
    8,
    0,
    6,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx1qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx1qivnx8qi },
    &operand_data[15545],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx1qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx1qivnx8qi },
    &operand_data[15545],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx1qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx1qivnx8qi },
    &operand_data[15545],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx1qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx1qivnx8qi },
    &operand_data[15545],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx1qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx1qivnx8qi },
    &operand_data[15545],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx1qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx1qivnx8qi },
    &operand_data[15545],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx1qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx1qivnx8qi },
    &operand_data[15545],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx1qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx1qivnx8qi },
    &operand_data[15545],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx2qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx2qivnx8qi },
    &operand_data[15553],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx2qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx2qivnx8qi },
    &operand_data[15553],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx2qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx2qivnx8qi },
    &operand_data[15553],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx2qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx2qivnx8qi },
    &operand_data[15553],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx2qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx2qivnx8qi },
    &operand_data[15553],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx2qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx2qivnx8qi },
    &operand_data[15553],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx2qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx2qivnx8qi },
    &operand_data[15553],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx2qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx2qivnx8qi },
    &operand_data[15553],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx4qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx4qivnx8qi },
    &operand_data[15561],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx4qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx4qivnx8qi },
    &operand_data[15561],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx4qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx4qivnx8qi },
    &operand_data[15561],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx4qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx4qivnx8qi },
    &operand_data[15561],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx4qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx4qivnx8qi },
    &operand_data[15561],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx4qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx4qivnx8qi },
    &operand_data[15561],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx4qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx4qivnx8qi },
    &operand_data[15561],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx4qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx4qivnx8qi },
    &operand_data[15561],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx8qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx8qivnx8qi },
    &operand_data[5712],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx8qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx8qivnx8qi },
    &operand_data[5712],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx8qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx8qivnx8qi },
    &operand_data[5712],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx8qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx8qivnx8qi },
    &operand_data[5712],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx8qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx8qivnx8qi },
    &operand_data[5712],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx8qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx8qivnx8qi },
    &operand_data[5712],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx8qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx8qivnx8qi },
    &operand_data[5712],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx8qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx8qivnx8qi },
    &operand_data[5712],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx16qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx16qivnx8qi },
    &operand_data[15569],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx16qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx16qivnx8qi },
    &operand_data[15569],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx16qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx16qivnx8qi },
    &operand_data[15569],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx16qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx16qivnx8qi },
    &operand_data[15569],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx16qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx16qivnx8qi },
    &operand_data[15569],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx16qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx16qivnx8qi },
    &operand_data[15569],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx16qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx16qivnx8qi },
    &operand_data[15569],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx16qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx16qivnx8qi },
    &operand_data[15569],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx32qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx32qivnx8qi },
    &operand_data[15577],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx32qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx32qivnx8qi },
    &operand_data[15577],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx32qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx32qivnx8qi },
    &operand_data[15577],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx32qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx32qivnx8qi },
    &operand_data[15577],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx32qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx32qivnx8qi },
    &operand_data[15577],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx32qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx32qivnx8qi },
    &operand_data[15577],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx32qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx32qivnx8qi },
    &operand_data[15577],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx32qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx32qivnx8qi },
    &operand_data[15577],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx64qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx64qivnx8qi },
    &operand_data[15585],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx64qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx64qivnx8qi },
    &operand_data[15585],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx64qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx64qivnx8qi },
    &operand_data[15585],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx64qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx64qivnx8qi },
    &operand_data[15585],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx64qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx64qivnx8qi },
    &operand_data[15585],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx64qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx64qivnx8qi },
    &operand_data[15585],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx64qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx64qivnx8qi },
    &operand_data[15585],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx64qivnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx64qivnx8qi },
    &operand_data[15585],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx1hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx1hivnx4hi },
    &operand_data[15593],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx1hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx1hivnx4hi },
    &operand_data[15593],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx1hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx1hivnx4hi },
    &operand_data[15593],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx1hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx1hivnx4hi },
    &operand_data[15593],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx1hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx1hivnx4hi },
    &operand_data[15593],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx1hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx1hivnx4hi },
    &operand_data[15593],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx1hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx1hivnx4hi },
    &operand_data[15593],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx1hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx1hivnx4hi },
    &operand_data[15593],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx2hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx2hivnx4hi },
    &operand_data[15601],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx2hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx2hivnx4hi },
    &operand_data[15601],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx2hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx2hivnx4hi },
    &operand_data[15601],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx2hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx2hivnx4hi },
    &operand_data[15601],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx2hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx2hivnx4hi },
    &operand_data[15601],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx2hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx2hivnx4hi },
    &operand_data[15601],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx2hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx2hivnx4hi },
    &operand_data[15601],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx2hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx2hivnx4hi },
    &operand_data[15601],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx4hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx4hivnx4hi },
    &operand_data[5766],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx4hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx4hivnx4hi },
    &operand_data[5766],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx4hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx4hivnx4hi },
    &operand_data[5766],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx4hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx4hivnx4hi },
    &operand_data[5766],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx4hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx4hivnx4hi },
    &operand_data[5766],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx4hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx4hivnx4hi },
    &operand_data[5766],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx4hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx4hivnx4hi },
    &operand_data[5766],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx4hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx4hivnx4hi },
    &operand_data[5766],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx8hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx8hivnx4hi },
    &operand_data[15609],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx8hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx8hivnx4hi },
    &operand_data[15609],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx8hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx8hivnx4hi },
    &operand_data[15609],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx8hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx8hivnx4hi },
    &operand_data[15609],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx8hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx8hivnx4hi },
    &operand_data[15609],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx8hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx8hivnx4hi },
    &operand_data[15609],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx8hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx8hivnx4hi },
    &operand_data[15609],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx8hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx8hivnx4hi },
    &operand_data[15609],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx16hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx16hivnx4hi },
    &operand_data[15617],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx16hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx16hivnx4hi },
    &operand_data[15617],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx16hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx16hivnx4hi },
    &operand_data[15617],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx16hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx16hivnx4hi },
    &operand_data[15617],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx16hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx16hivnx4hi },
    &operand_data[15617],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx16hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx16hivnx4hi },
    &operand_data[15617],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx16hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx16hivnx4hi },
    &operand_data[15617],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx16hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx16hivnx4hi },
    &operand_data[15617],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx32hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx32hivnx4hi },
    &operand_data[15625],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx32hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx32hivnx4hi },
    &operand_data[15625],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx32hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx32hivnx4hi },
    &operand_data[15625],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx32hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx32hivnx4hi },
    &operand_data[15625],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx32hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx32hivnx4hi },
    &operand_data[15625],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx32hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx32hivnx4hi },
    &operand_data[15625],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx32hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx32hivnx4hi },
    &operand_data[15625],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx32hivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx32hivnx4hi },
    &operand_data[15625],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx1sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx1sivnx2si },
    &operand_data[15633],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx1sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx1sivnx2si },
    &operand_data[15633],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx1sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx1sivnx2si },
    &operand_data[15633],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx1sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx1sivnx2si },
    &operand_data[15633],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx1sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx1sivnx2si },
    &operand_data[15633],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx1sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx1sivnx2si },
    &operand_data[15633],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx1sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx1sivnx2si },
    &operand_data[15633],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx1sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx1sivnx2si },
    &operand_data[15633],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx2sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx2sivnx2si },
    &operand_data[5811],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx2sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx2sivnx2si },
    &operand_data[5811],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx2sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx2sivnx2si },
    &operand_data[5811],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx2sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx2sivnx2si },
    &operand_data[5811],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx2sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx2sivnx2si },
    &operand_data[5811],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx2sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx2sivnx2si },
    &operand_data[5811],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx2sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx2sivnx2si },
    &operand_data[5811],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx2sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx2sivnx2si },
    &operand_data[5811],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx4sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx4sivnx2si },
    &operand_data[15641],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx4sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx4sivnx2si },
    &operand_data[15641],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx4sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx4sivnx2si },
    &operand_data[15641],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx4sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx4sivnx2si },
    &operand_data[15641],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx4sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx4sivnx2si },
    &operand_data[15641],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx4sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx4sivnx2si },
    &operand_data[15641],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx4sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx4sivnx2si },
    &operand_data[15641],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx4sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx4sivnx2si },
    &operand_data[15641],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx8sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx8sivnx2si },
    &operand_data[15649],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx8sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx8sivnx2si },
    &operand_data[15649],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx8sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx8sivnx2si },
    &operand_data[15649],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx8sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx8sivnx2si },
    &operand_data[15649],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx8sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx8sivnx2si },
    &operand_data[15649],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx8sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx8sivnx2si },
    &operand_data[15649],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx8sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx8sivnx2si },
    &operand_data[15649],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx8sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx8sivnx2si },
    &operand_data[15649],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx16sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx16sivnx2si },
    &operand_data[15657],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx16sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx16sivnx2si },
    &operand_data[15657],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx16sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx16sivnx2si },
    &operand_data[15657],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx16sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx16sivnx2si },
    &operand_data[15657],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx16sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx16sivnx2si },
    &operand_data[15657],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx16sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx16sivnx2si },
    &operand_data[15657],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx16sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx16sivnx2si },
    &operand_data[15657],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx16sivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx16sivnx2si },
    &operand_data[15657],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx1divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx1divnx1DI },
    &operand_data[5847],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx1divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx1divnx1DI },
    &operand_data[5847],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx1divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx1divnx1DI },
    &operand_data[5847],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx1divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx1divnx1DI },
    &operand_data[5847],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx1divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx1divnx1DI },
    &operand_data[5847],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx1divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx1divnx1DI },
    &operand_data[5847],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx1divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx1divnx1DI },
    &operand_data[5847],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx1divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx1divnx1DI },
    &operand_data[5847],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx2divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx2divnx1DI },
    &operand_data[15665],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx2divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx2divnx1DI },
    &operand_data[15665],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx2divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx2divnx1DI },
    &operand_data[15665],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx2divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx2divnx1DI },
    &operand_data[15665],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx2divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx2divnx1DI },
    &operand_data[15665],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx2divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx2divnx1DI },
    &operand_data[15665],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx2divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx2divnx1DI },
    &operand_data[15665],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx2divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx2divnx1DI },
    &operand_data[15665],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx4divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx4divnx1DI },
    &operand_data[15673],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx4divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx4divnx1DI },
    &operand_data[15673],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx4divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx4divnx1DI },
    &operand_data[15673],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx4divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx4divnx1DI },
    &operand_data[15673],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx4divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx4divnx1DI },
    &operand_data[15673],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx4divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx4divnx1DI },
    &operand_data[15673],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx4divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx4divnx1DI },
    &operand_data[15673],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx4divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx4divnx1DI },
    &operand_data[15673],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_sumvnx8divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx8divnx1DI },
    &operand_data[15681],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxuvnx8divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx8divnx1DI },
    &operand_data[15681],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_maxvnx8divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx8divnx1DI },
    &operand_data[15681],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minuvnx8divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx8divnx1DI },
    &operand_data[15681],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_minvnx8divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx8divnx1DI },
    &operand_data[15681],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_andvnx8divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx8divnx1DI },
    &operand_data[15681],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_orvnx8divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx8divnx1DI },
    &operand_data[15681],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6748 */
  {
    "pred_reduc_xorvnx8divnx1DI",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx8divnx1DI },
    &operand_data[15681],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx1qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx1qivnx4qi },
    &operand_data[15689],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx1qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx1qivnx4qi },
    &operand_data[15689],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx1qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx1qivnx4qi },
    &operand_data[15689],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx1qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx1qivnx4qi },
    &operand_data[15689],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx1qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx1qivnx4qi },
    &operand_data[15689],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx1qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx1qivnx4qi },
    &operand_data[15689],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx1qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx1qivnx4qi },
    &operand_data[15689],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx1qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx1qivnx4qi },
    &operand_data[15689],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx2qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx2qivnx4qi },
    &operand_data[15697],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx2qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx2qivnx4qi },
    &operand_data[15697],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx2qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx2qivnx4qi },
    &operand_data[15697],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx2qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx2qivnx4qi },
    &operand_data[15697],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx2qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx2qivnx4qi },
    &operand_data[15697],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx2qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx2qivnx4qi },
    &operand_data[15697],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx2qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx2qivnx4qi },
    &operand_data[15697],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx2qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx2qivnx4qi },
    &operand_data[15697],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx4qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx4qivnx4qi },
    &operand_data[5703],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx4qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx4qivnx4qi },
    &operand_data[5703],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx4qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx4qivnx4qi },
    &operand_data[5703],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx4qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx4qivnx4qi },
    &operand_data[5703],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx4qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx4qivnx4qi },
    &operand_data[5703],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx4qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx4qivnx4qi },
    &operand_data[5703],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx4qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx4qivnx4qi },
    &operand_data[5703],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx4qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx4qivnx4qi },
    &operand_data[5703],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx8qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx8qivnx4qi },
    &operand_data[15705],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx8qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx8qivnx4qi },
    &operand_data[15705],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx8qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx8qivnx4qi },
    &operand_data[15705],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx8qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx8qivnx4qi },
    &operand_data[15705],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx8qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx8qivnx4qi },
    &operand_data[15705],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx8qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx8qivnx4qi },
    &operand_data[15705],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx8qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx8qivnx4qi },
    &operand_data[15705],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx8qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx8qivnx4qi },
    &operand_data[15705],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx16qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx16qivnx4qi },
    &operand_data[15713],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx16qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx16qivnx4qi },
    &operand_data[15713],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx16qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx16qivnx4qi },
    &operand_data[15713],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx16qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx16qivnx4qi },
    &operand_data[15713],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx16qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx16qivnx4qi },
    &operand_data[15713],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx16qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx16qivnx4qi },
    &operand_data[15713],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx16qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx16qivnx4qi },
    &operand_data[15713],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx16qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx16qivnx4qi },
    &operand_data[15713],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx32qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx32qivnx4qi },
    &operand_data[15721],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx32qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx32qivnx4qi },
    &operand_data[15721],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx32qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx32qivnx4qi },
    &operand_data[15721],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx32qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx32qivnx4qi },
    &operand_data[15721],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx32qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx32qivnx4qi },
    &operand_data[15721],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx32qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx32qivnx4qi },
    &operand_data[15721],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx32qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx32qivnx4qi },
    &operand_data[15721],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx32qivnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx32qivnx4qi },
    &operand_data[15721],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx1hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx1hivnx2hi },
    &operand_data[15729],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx1hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx1hivnx2hi },
    &operand_data[15729],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx1hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx1hivnx2hi },
    &operand_data[15729],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx1hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx1hivnx2hi },
    &operand_data[15729],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx1hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx1hivnx2hi },
    &operand_data[15729],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx1hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx1hivnx2hi },
    &operand_data[15729],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx1hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx1hivnx2hi },
    &operand_data[15729],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx1hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx1hivnx2hi },
    &operand_data[15729],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx2hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx2hivnx2hi },
    &operand_data[5757],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx2hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx2hivnx2hi },
    &operand_data[5757],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx2hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx2hivnx2hi },
    &operand_data[5757],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx2hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx2hivnx2hi },
    &operand_data[5757],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx2hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx2hivnx2hi },
    &operand_data[5757],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx2hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx2hivnx2hi },
    &operand_data[5757],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx2hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx2hivnx2hi },
    &operand_data[5757],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx2hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx2hivnx2hi },
    &operand_data[5757],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx4hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx4hivnx2hi },
    &operand_data[15737],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx4hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx4hivnx2hi },
    &operand_data[15737],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx4hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx4hivnx2hi },
    &operand_data[15737],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx4hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx4hivnx2hi },
    &operand_data[15737],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx4hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx4hivnx2hi },
    &operand_data[15737],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx4hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx4hivnx2hi },
    &operand_data[15737],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx4hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx4hivnx2hi },
    &operand_data[15737],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx4hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx4hivnx2hi },
    &operand_data[15737],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx8hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx8hivnx2hi },
    &operand_data[15745],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx8hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx8hivnx2hi },
    &operand_data[15745],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx8hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx8hivnx2hi },
    &operand_data[15745],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx8hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx8hivnx2hi },
    &operand_data[15745],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx8hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx8hivnx2hi },
    &operand_data[15745],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx8hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx8hivnx2hi },
    &operand_data[15745],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx8hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx8hivnx2hi },
    &operand_data[15745],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx8hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx8hivnx2hi },
    &operand_data[15745],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx16hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx16hivnx2hi },
    &operand_data[15753],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx16hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx16hivnx2hi },
    &operand_data[15753],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx16hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx16hivnx2hi },
    &operand_data[15753],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx16hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx16hivnx2hi },
    &operand_data[15753],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx16hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx16hivnx2hi },
    &operand_data[15753],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx16hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx16hivnx2hi },
    &operand_data[15753],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx16hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx16hivnx2hi },
    &operand_data[15753],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx16hivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx16hivnx2hi },
    &operand_data[15753],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx1sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx1sivnx1si },
    &operand_data[5802],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx1sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx1sivnx1si },
    &operand_data[5802],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx1sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx1sivnx1si },
    &operand_data[5802],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx1sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx1sivnx1si },
    &operand_data[5802],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx1sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx1sivnx1si },
    &operand_data[5802],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx1sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx1sivnx1si },
    &operand_data[5802],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx1sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx1sivnx1si },
    &operand_data[5802],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx1sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx1sivnx1si },
    &operand_data[5802],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx2sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx2sivnx1si },
    &operand_data[15761],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx2sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx2sivnx1si },
    &operand_data[15761],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx2sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx2sivnx1si },
    &operand_data[15761],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx2sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx2sivnx1si },
    &operand_data[15761],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx2sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx2sivnx1si },
    &operand_data[15761],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx2sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx2sivnx1si },
    &operand_data[15761],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx2sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx2sivnx1si },
    &operand_data[15761],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx2sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx2sivnx1si },
    &operand_data[15761],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx4sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx4sivnx1si },
    &operand_data[15769],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx4sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx4sivnx1si },
    &operand_data[15769],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx4sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx4sivnx1si },
    &operand_data[15769],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx4sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx4sivnx1si },
    &operand_data[15769],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx4sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx4sivnx1si },
    &operand_data[15769],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx4sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx4sivnx1si },
    &operand_data[15769],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx4sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx4sivnx1si },
    &operand_data[15769],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx4sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx4sivnx1si },
    &operand_data[15769],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_sumvnx8sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_sumvnx8sivnx1si },
    &operand_data[15777],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxuvnx8sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmaxu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxuvnx8sivnx1si },
    &operand_data[15777],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_maxvnx8sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx8sivnx1si },
    &operand_data[15777],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minuvnx8sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredminu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minuvnx8sivnx1si },
    &operand_data[15777],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_minvnx8sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx8sivnx1si },
    &operand_data[15777],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_andvnx8sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredand.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_andvnx8sivnx1si },
    &operand_data[15777],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_orvnx8sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_orvnx8sivnx1si },
    &operand_data[15777],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6770 */
  {
    "pred_reduc_xorvnx8sivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vredxor.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_xorvnx8sivnx1si },
    &operand_data[15777],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx1qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx1qivnx4hi },
    &operand_data[15785],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx1qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx1qivnx4hi },
    &operand_data[15785],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx2qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx2qivnx4hi },
    &operand_data[15793],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx2qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx2qivnx4hi },
    &operand_data[15793],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx4qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx4qivnx4hi },
    &operand_data[15801],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx4qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx4qivnx4hi },
    &operand_data[15801],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx8qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx8qivnx4hi },
    &operand_data[15809],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx8qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx8qivnx4hi },
    &operand_data[15809],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx16qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx16qivnx4hi },
    &operand_data[15817],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx16qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx16qivnx4hi },
    &operand_data[15817],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx32qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx32qivnx4hi },
    &operand_data[15825],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx32qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx32qivnx4hi },
    &operand_data[15825],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx64qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx64qivnx4hi },
    &operand_data[15833],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx64qivnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx64qivnx4hi },
    &operand_data[15833],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx1hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx1hivnx2si },
    &operand_data[15841],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx1hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx1hivnx2si },
    &operand_data[15841],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx2hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx2hivnx2si },
    &operand_data[15849],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx2hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx2hivnx2si },
    &operand_data[15849],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx4hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx4hivnx2si },
    &operand_data[15857],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx4hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx4hivnx2si },
    &operand_data[15857],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx8hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx8hivnx2si },
    &operand_data[15865],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx8hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx8hivnx2si },
    &operand_data[15865],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx16hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx16hivnx2si },
    &operand_data[15873],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx16hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx16hivnx2si },
    &operand_data[15873],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx32hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx32hivnx2si },
    &operand_data[15881],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx32hivnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx32hivnx2si },
    &operand_data[15881],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx1sivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx1sivnx2di },
    &operand_data[15889],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx1sivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx1sivnx2di },
    &operand_data[15889],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx2sivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx2sivnx2di },
    &operand_data[15897],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx2sivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx2sivnx2di },
    &operand_data[15897],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx4sivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx4sivnx2di },
    &operand_data[15905],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx4sivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx4sivnx2di },
    &operand_data[15905],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx8sivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx8sivnx2di },
    &operand_data[15913],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx8sivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx8sivnx2di },
    &operand_data[15913],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusvnx16sivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx16sivnx2di },
    &operand_data[15921],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6792 */
  {
    "pred_widen_reduc_plusuvnx16sivnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx16sivnx2di },
    &operand_data[15921],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusvnx1qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx1qivnx2hi },
    &operand_data[15929],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusuvnx1qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx1qivnx2hi },
    &operand_data[15929],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusvnx2qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx2qivnx2hi },
    &operand_data[15937],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusuvnx2qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx2qivnx2hi },
    &operand_data[15937],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusvnx4qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx4qivnx2hi },
    &operand_data[15945],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusuvnx4qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx4qivnx2hi },
    &operand_data[15945],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusvnx8qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx8qivnx2hi },
    &operand_data[15953],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusuvnx8qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx8qivnx2hi },
    &operand_data[15953],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusvnx16qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx16qivnx2hi },
    &operand_data[15961],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusuvnx16qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx16qivnx2hi },
    &operand_data[15961],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusvnx32qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx32qivnx2hi },
    &operand_data[15969],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusuvnx32qivnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx32qivnx2hi },
    &operand_data[15969],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusvnx1hivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx1hivnx1si },
    &operand_data[15977],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusuvnx1hivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx1hivnx1si },
    &operand_data[15977],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusvnx2hivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx2hivnx1si },
    &operand_data[15985],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusuvnx2hivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx2hivnx1si },
    &operand_data[15985],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusvnx4hivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx4hivnx1si },
    &operand_data[15993],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusuvnx4hivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx4hivnx1si },
    &operand_data[15993],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusvnx8hivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx8hivnx1si },
    &operand_data[16001],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusuvnx8hivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx8hivnx1si },
    &operand_data[16001],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusvnx16hivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusvnx16hivnx1si },
    &operand_data[16009],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6810 */
  {
    "pred_widen_reduc_plusuvnx16hivnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vwredsumu.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx16hivnx1si },
    &operand_data[16009],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_maxvnx1sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx1sfvnx2sf },
    &operand_data[16017],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_minvnx1sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx1sfvnx2sf },
    &operand_data[16017],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_maxvnx2sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx2sfvnx2sf },
    &operand_data[13626],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_minvnx2sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx2sfvnx2sf },
    &operand_data[13626],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_maxvnx4sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx4sfvnx2sf },
    &operand_data[16025],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_minvnx4sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx4sfvnx2sf },
    &operand_data[16025],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_maxvnx8sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx8sfvnx2sf },
    &operand_data[16033],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_minvnx8sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx8sfvnx2sf },
    &operand_data[16033],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_maxvnx16sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx16sfvnx2sf },
    &operand_data[16041],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_minvnx16sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx16sfvnx2sf },
    &operand_data[16041],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_maxvnx1dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx1dfvnx1df },
    &operand_data[13662],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_minvnx1dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx1dfvnx1df },
    &operand_data[13662],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_maxvnx2dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx2dfvnx1df },
    &operand_data[16049],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_minvnx2dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx2dfvnx1df },
    &operand_data[16049],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_maxvnx4dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx4dfvnx1df },
    &operand_data[16057],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_minvnx4dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx4dfvnx1df },
    &operand_data[16057],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_maxvnx8dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx8dfvnx1df },
    &operand_data[16065],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6828 */
  {
    "pred_reduc_minvnx8dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx8dfvnx1df },
    &operand_data[16065],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
  {
    "pred_reduc_maxvnx1sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx1sfvnx1sf },
    &operand_data[16017],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
  {
    "pred_reduc_minvnx1sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx1sfvnx1sf },
    &operand_data[16017],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
  {
    "pred_reduc_maxvnx2sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx2sfvnx1sf },
    &operand_data[13626],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
  {
    "pred_reduc_minvnx2sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx2sfvnx1sf },
    &operand_data[13626],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
  {
    "pred_reduc_maxvnx4sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx4sfvnx1sf },
    &operand_data[16025],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
  {
    "pred_reduc_minvnx4sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx4sfvnx1sf },
    &operand_data[16025],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
  {
    "pred_reduc_maxvnx8sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmax.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_maxvnx8sfvnx1sf },
    &operand_data[16033],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6850 */
  {
    "pred_reduc_minvnx8sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredmin.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_minvnx8sfvnx1sf },
    &operand_data[16033],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusovnx1sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx1sfvnx2sf },
    &operand_data[16017],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusuvnx1sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx1sfvnx2sf },
    &operand_data[16017],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusovnx2sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx2sfvnx2sf },
    &operand_data[13626],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusuvnx2sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx2sfvnx2sf },
    &operand_data[13626],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusovnx4sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx4sfvnx2sf },
    &operand_data[16025],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusuvnx4sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx4sfvnx2sf },
    &operand_data[16025],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusovnx8sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx8sfvnx2sf },
    &operand_data[16033],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusuvnx8sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx8sfvnx2sf },
    &operand_data[16033],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusovnx16sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx16sfvnx2sf },
    &operand_data[16041],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusuvnx16sfvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx16sfvnx2sf },
    &operand_data[16041],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusovnx1dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx1dfvnx1df },
    &operand_data[13662],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusuvnx1dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx1dfvnx1df },
    &operand_data[13662],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusovnx2dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx2dfvnx1df },
    &operand_data[16049],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusuvnx2dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx2dfvnx1df },
    &operand_data[16049],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusovnx4dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx4dfvnx1df },
    &operand_data[16057],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusuvnx4dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx4dfvnx1df },
    &operand_data[16057],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusovnx8dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx8dfvnx1df },
    &operand_data[16065],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6872 */
  {
    "pred_reduc_plusuvnx8dfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx8dfvnx1df },
    &operand_data[16065],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
  {
    "pred_reduc_plusovnx1sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx1sfvnx1sf },
    &operand_data[16017],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
  {
    "pred_reduc_plusuvnx1sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx1sfvnx1sf },
    &operand_data[16017],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
  {
    "pred_reduc_plusovnx2sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx2sfvnx1sf },
    &operand_data[13626],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
  {
    "pred_reduc_plusuvnx2sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx2sfvnx1sf },
    &operand_data[13626],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
  {
    "pred_reduc_plusovnx4sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx4sfvnx1sf },
    &operand_data[16025],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
  {
    "pred_reduc_plusuvnx4sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx4sfvnx1sf },
    &operand_data[16025],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
  {
    "pred_reduc_plusovnx8sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusovnx8sfvnx1sf },
    &operand_data[16033],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6895 */
  {
    "pred_reduc_plusuvnx8sfvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_reduc_plusuvnx8sfvnx1sf },
    &operand_data[16033],
    8,
    8,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
  {
    "pred_widen_reduc_plusovnx1sfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusovnx1sfvnx1df },
    &operand_data[16073],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
  {
    "pred_widen_reduc_plusuvnx1sfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx1sfvnx1df },
    &operand_data[16073],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
  {
    "pred_widen_reduc_plusovnx2sfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusovnx2sfvnx1df },
    &operand_data[16081],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
  {
    "pred_widen_reduc_plusuvnx2sfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx2sfvnx1df },
    &operand_data[16081],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
  {
    "pred_widen_reduc_plusovnx4sfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusovnx4sfvnx1df },
    &operand_data[16089],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
  {
    "pred_widen_reduc_plusuvnx4sfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx4sfvnx1df },
    &operand_data[16089],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
  {
    "pred_widen_reduc_plusovnx8sfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusovnx8sfvnx1df },
    &operand_data[16097],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
  {
    "pred_widen_reduc_plusuvnx8sfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx8sfvnx1df },
    &operand_data[16097],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
  {
    "pred_widen_reduc_plusovnx16sfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwredosum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusovnx16sfvnx1df },
    &operand_data[16105],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6918 */
  {
    "pred_widen_reduc_plusuvnx16sfvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfwredusum.vs\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_widen_reduc_plusuvnx16sfvnx1df },
    &operand_data[16105],
    8,
    8,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16113],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16115],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16117],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16119],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16121],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16123],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16125],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16127],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16129],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16131],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16133],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16135],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16137],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16139],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16141],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16143],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16145],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16147],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16149],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16151],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16153],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6965 */
  {
    "*pred_extract_firstvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16155],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6998 */
  {
    "pred_extract_first_truncvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_first_truncvnx1di },
    &operand_data[16157],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6998 */
  {
    "pred_extract_first_truncvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_first_truncvnx2di },
    &operand_data[16159],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6998 */
  {
    "pred_extract_first_truncvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_first_truncvnx4di },
    &operand_data[16161],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6998 */
  {
    "pred_extract_first_truncvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vmv.x.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_first_truncvnx8di },
    &operand_data[16163],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7028 */
  {
    "*pred_extract_firstvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmv.f.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16165],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7028 */
  {
    "*pred_extract_firstvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmv.f.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16167],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7028 */
  {
    "*pred_extract_firstvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmv.f.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16169],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7028 */
  {
    "*pred_extract_firstvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmv.f.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16171],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7028 */
  {
    "*pred_extract_firstvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmv.f.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16173],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7028 */
  {
    "*pred_extract_firstvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmv.f.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16175],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7028 */
  {
    "*pred_extract_firstvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmv.f.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16177],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7028 */
  {
    "*pred_extract_firstvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmv.f.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16179],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7028 */
  {
    "*pred_extract_firstvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfmv.f.s\t%0,%1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16181],
    2,
    2,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx1qi },
    &operand_data[16183],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx1qi },
    &operand_data[16192],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx2qi },
    &operand_data[16201],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx2qi },
    &operand_data[16210],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx4qi },
    &operand_data[16219],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx4qi },
    &operand_data[16228],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx8qi },
    &operand_data[16237],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx8qi },
    &operand_data[16246],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx16qi },
    &operand_data[16255],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx16qi },
    &operand_data[16264],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx32qi },
    &operand_data[16273],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx32qi },
    &operand_data[16282],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx64qi },
    &operand_data[16291],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx64qi },
    &operand_data[16300],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx1hi },
    &operand_data[16309],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx1hi },
    &operand_data[16318],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx2hi },
    &operand_data[16327],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx2hi },
    &operand_data[16336],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx4hi },
    &operand_data[16345],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx4hi },
    &operand_data[16354],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx8hi },
    &operand_data[16363],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx8hi },
    &operand_data[16372],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx16hi },
    &operand_data[16381],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx16hi },
    &operand_data[16390],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx32hi },
    &operand_data[16399],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx32hi },
    &operand_data[16408],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx1si },
    &operand_data[16417],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx1si },
    &operand_data[16426],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx2si },
    &operand_data[16435],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx2si },
    &operand_data[16444],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx4si },
    &operand_data[16453],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx4si },
    &operand_data[16462],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx8si },
    &operand_data[16471],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx8si },
    &operand_data[16480],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx16si },
    &operand_data[16489],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx16si },
    &operand_data[16498],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx1di },
    &operand_data[16507],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx1di },
    &operand_data[16516],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx2di },
    &operand_data[16525],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx2di },
    &operand_data[16534],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx4di },
    &operand_data[16543],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx4di },
    &operand_data[16552],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx8di },
    &operand_data[16561],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx8di },
    &operand_data[16570],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx1sf },
    &operand_data[16579],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx1sf },
    &operand_data[16588],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx2sf },
    &operand_data[16597],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx2sf },
    &operand_data[16606],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx4sf },
    &operand_data[16615],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx4sf },
    &operand_data[16624],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx8sf },
    &operand_data[16633],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx8sf },
    &operand_data[16642],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx16sf },
    &operand_data[16651],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx16sf },
    &operand_data[16660],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx1df },
    &operand_data[16669],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx1df },
    &operand_data[16678],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx2df },
    &operand_data[16687],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx2df },
    &operand_data[16696],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx4df },
    &operand_data[16705],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx4df },
    &operand_data[16714],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slideupvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslideup.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slideupvnx8df },
    &operand_data[16723],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7041 */
  {
    "pred_slidedownvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslidedown.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slidedownvnx8df },
    &operand_data[16732],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx1qi },
    &operand_data[16741],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx1qi },
    &operand_data[5451],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx2qi },
    &operand_data[16750],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx2qi },
    &operand_data[5460],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx4qi },
    &operand_data[16759],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx4qi },
    &operand_data[5469],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx8qi },
    &operand_data[16768],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx8qi },
    &operand_data[5478],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx16qi },
    &operand_data[16777],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx16qi },
    &operand_data[5487],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx32qi },
    &operand_data[16786],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx32qi },
    &operand_data[5496],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx64qi },
    &operand_data[16795],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx64qi },
    &operand_data[5505],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx1hi },
    &operand_data[16804],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx1hi },
    &operand_data[5514],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx2hi },
    &operand_data[16813],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx2hi },
    &operand_data[5523],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx4hi },
    &operand_data[16822],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx4hi },
    &operand_data[5532],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx8hi },
    &operand_data[16831],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx8hi },
    &operand_data[5541],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx16hi },
    &operand_data[16840],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx16hi },
    &operand_data[5550],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx32hi },
    &operand_data[16849],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx32hi },
    &operand_data[5559],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx1si },
    &operand_data[16858],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx1si },
    &operand_data[5568],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx2si },
    &operand_data[16867],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx2si },
    &operand_data[5577],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx4si },
    &operand_data[16876],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx4si },
    &operand_data[5586],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx8si },
    &operand_data[16885],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx8si },
    &operand_data[5595],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1upvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx16si },
    &operand_data[16894],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7061 */
  {
    "pred_slide1downvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx16si },
    &operand_data[5604],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7102 */
  {
    "*pred_slide1upvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16903],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7102 */
  {
    "*pred_slide1downvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5613],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7102 */
  {
    "*pred_slide1upvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16912],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7102 */
  {
    "*pred_slide1downvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5622],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7102 */
  {
    "*pred_slide1upvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16921],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7102 */
  {
    "*pred_slide1downvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5631],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7102 */
  {
    "*pred_slide1upvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16930],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7102 */
  {
    "*pred_slide1downvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5640],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7121 */
  {
    "*pred_slide1upvnx1di_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16939],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7121 */
  {
    "*pred_slide1downvnx1di_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5649],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7121 */
  {
    "*pred_slide1upvnx2di_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16948],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7121 */
  {
    "*pred_slide1downvnx2di_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5658],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7121 */
  {
    "*pred_slide1upvnx4di_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16957],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7121 */
  {
    "*pred_slide1downvnx4di_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5667],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7121 */
  {
    "*pred_slide1upvnx8di_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1up.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[16966],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7121 */
  {
    "*pred_slide1downvnx8di_extended",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vslide1down.vx\t%0,%3,%z4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { 0 },
    &operand_data[5676],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1upvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1up.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx1sf },
    &operand_data[16975],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1downvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1down.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx1sf },
    &operand_data[13698],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1upvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1up.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx2sf },
    &operand_data[16984],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1downvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1down.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx2sf },
    &operand_data[13707],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1upvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1up.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx4sf },
    &operand_data[16993],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1downvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1down.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx4sf },
    &operand_data[13716],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1upvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1up.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx8sf },
    &operand_data[17002],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1downvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1down.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx8sf },
    &operand_data[13725],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1upvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1up.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx16sf },
    &operand_data[17011],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1downvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1down.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx16sf },
    &operand_data[13734],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1upvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1up.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx1df },
    &operand_data[17020],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1downvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1down.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx1df },
    &operand_data[13743],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1upvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1up.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx2df },
    &operand_data[17029],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1downvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1down.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx2df },
    &operand_data[13752],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1upvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1up.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx4df },
    &operand_data[17038],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1downvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1down.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx4df },
    &operand_data[13761],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1upvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1up.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx8df },
    &operand_data[17047],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7142 */
  {
    "pred_slide1downvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vfslide1down.vf\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx8df },
    &operand_data[13770],
    9,
    9,
    0,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx1qi },
    &operand_data[17056],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx2qi },
    &operand_data[17065],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx4qi },
    &operand_data[17074],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx8qi },
    &operand_data[17083],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx16qi },
    &operand_data[17092],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx32qi },
    &operand_data[17101],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx64qi },
    &operand_data[17110],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx1hi },
    &operand_data[17119],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx2hi },
    &operand_data[17128],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx4hi },
    &operand_data[17137],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx8hi },
    &operand_data[17146],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx16hi },
    &operand_data[17155],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx32hi },
    &operand_data[17164],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx1si },
    &operand_data[17173],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx2si },
    &operand_data[17182],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx4si },
    &operand_data[17191],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx8si },
    &operand_data[17200],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx16si },
    &operand_data[17209],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx1di },
    &operand_data[17218],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx2di },
    &operand_data[17227],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx4di },
    &operand_data[17236],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx8di },
    &operand_data[17245],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx1sf },
    &operand_data[17254],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx2sf },
    &operand_data[17263],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx4sf },
    &operand_data[17272],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx8sf },
    &operand_data[17281],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx16sf },
    &operand_data[17290],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx1df },
    &operand_data[17299],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx2df },
    &operand_data[17308],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx4df },
    &operand_data[17317],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7162 */
  {
    "pred_gathervnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx8df },
    &operand_data[17326],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx1qi_scalar },
    &operand_data[17335],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx2qi_scalar },
    &operand_data[17344],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx4qi_scalar },
    &operand_data[17353],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx8qi_scalar },
    &operand_data[17362],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx16qi_scalar },
    &operand_data[17371],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx32qi_scalar },
    &operand_data[17380],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx64qi_scalar },
    &operand_data[17389],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx1hi_scalar },
    &operand_data[17398],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx2hi_scalar },
    &operand_data[17407],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx4hi_scalar },
    &operand_data[17416],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx8hi_scalar },
    &operand_data[17425],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx16hi_scalar },
    &operand_data[17434],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx32hi_scalar },
    &operand_data[17443],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx1si_scalar },
    &operand_data[17452],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx2si_scalar },
    &operand_data[17461],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx4si_scalar },
    &operand_data[17470],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx8si_scalar },
    &operand_data[17479],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx16si_scalar },
    &operand_data[17488],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx1di_scalar },
    &operand_data[17497],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx2di_scalar },
    &operand_data[17506],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx4di_scalar },
    &operand_data[17515],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx8di_scalar },
    &operand_data[17524],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx1sf_scalar },
    &operand_data[17533],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx2sf_scalar },
    &operand_data[17542],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx4sf_scalar },
    &operand_data[17551],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx8sf_scalar },
    &operand_data[17560],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx16sf_scalar },
    &operand_data[17569],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx1df_scalar },
    &operand_data[17578],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx2df_scalar },
    &operand_data[17587],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx4df_scalar },
    &operand_data[17596],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7182 */
  {
    "pred_gathervnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgather.v%o4\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gathervnx8df_scalar },
    &operand_data[17605],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx1qi },
    &operand_data[17614],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx2qi },
    &operand_data[17623],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx4qi },
    &operand_data[17632],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx8qi },
    &operand_data[17641],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx16qi },
    &operand_data[17650],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx32qi },
    &operand_data[17659],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx1hi },
    &operand_data[17119],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx2hi },
    &operand_data[17128],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx4hi },
    &operand_data[17137],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx8hi },
    &operand_data[17146],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx16hi },
    &operand_data[17155],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx32hi },
    &operand_data[17164],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx1si },
    &operand_data[7869],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx2si },
    &operand_data[7878],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx4si },
    &operand_data[7887],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx8si },
    &operand_data[7896],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx16si },
    &operand_data[7905],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx1di },
    &operand_data[17668],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx2di },
    &operand_data[17677],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx4di },
    &operand_data[17686],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx8di },
    &operand_data[17695],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx1sf },
    &operand_data[17704],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx2sf },
    &operand_data[17713],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx4sf },
    &operand_data[17722],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx8sf },
    &operand_data[17731],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx16sf },
    &operand_data[17740],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx1df },
    &operand_data[17749],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx2df },
    &operand_data[17758],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx4df },
    &operand_data[17767],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7203 */
  {
    "pred_gatherei16vnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vrgatherei16.vv\t%0,%3,%4%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gatherei16vnx8df },
    &operand_data[17776],
    9,
    9,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx1qi },
    &operand_data[17785],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx2qi },
    &operand_data[17792],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx4qi },
    &operand_data[17799],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx8qi },
    &operand_data[17806],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx16qi },
    &operand_data[17813],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx32qi },
    &operand_data[17820],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx64qi },
    &operand_data[17827],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx1hi },
    &operand_data[17834],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx2hi },
    &operand_data[17841],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx4hi },
    &operand_data[17848],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx8hi },
    &operand_data[17855],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx16hi },
    &operand_data[17862],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx32hi },
    &operand_data[17869],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx1si },
    &operand_data[17876],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx2si },
    &operand_data[17883],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx4si },
    &operand_data[17890],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx8si },
    &operand_data[17897],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx16si },
    &operand_data[17904],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx1di },
    &operand_data[17911],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx2di },
    &operand_data[17918],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx4di },
    &operand_data[17925],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx8di },
    &operand_data[17932],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx1sf },
    &operand_data[17939],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx2sf },
    &operand_data[17946],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx4sf },
    &operand_data[17953],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx8sf },
    &operand_data[17960],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx16sf },
    &operand_data[17967],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx1df },
    &operand_data[17974],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx2df },
    &operand_data[17981],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx4df },
    &operand_data[17988],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7224 */
  {
    "pred_compressvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vcompress.vm\t%0,%2,%3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_compressvnx8df },
    &operand_data[17995],
    7,
    7,
    0,
    2,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7248 */
  {
    "read_vlsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "csrr\t%0,vl",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_read_vlsi },
    &operand_data[26],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7256 */
  {
    "read_vldi_zero_extend",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "csrr\t%0,vl",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_read_vldi_zero_extend },
    &operand_data[23],
    1,
    1,
    0,
    1,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle8ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx1qi },
    &operand_data[18002],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle8ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx2qi },
    &operand_data[18010],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle8ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx4qi },
    &operand_data[18018],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle8ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx8qi },
    &operand_data[18026],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle8ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx16qi },
    &operand_data[18034],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle8ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx32qi },
    &operand_data[18042],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle8ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx64qi },
    &operand_data[18050],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle16ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx1hi },
    &operand_data[18058],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle16ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx2hi },
    &operand_data[18066],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle16ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx4hi },
    &operand_data[18074],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle16ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx8hi },
    &operand_data[18082],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle16ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx16hi },
    &operand_data[18090],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle16ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx32hi },
    &operand_data[18098],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle32ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx1si },
    &operand_data[18106],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle32ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx2si },
    &operand_data[18114],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle32ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx4si },
    &operand_data[18122],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle32ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx8si },
    &operand_data[18130],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle32ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx16si },
    &operand_data[18138],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle64ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx1di },
    &operand_data[18146],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle64ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx2di },
    &operand_data[18154],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle64ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx4di },
    &operand_data[18162],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle64ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx8di },
    &operand_data[18170],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle32ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx1sf },
    &operand_data[18178],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle32ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx2sf },
    &operand_data[18186],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle32ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx4sf },
    &operand_data[18194],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle32ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx8sf },
    &operand_data[18202],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle32ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx16sf },
    &operand_data[18210],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle64ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx1df },
    &operand_data[18218],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle64ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx2df },
    &operand_data[18226],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle64ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx4df },
    &operand_data[18234],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7264 */
  {
    "pred_fault_loadvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { .single =
#else
    {
#endif
    "vle64ff.v\t%0,%3%p1",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    },
#else
    0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_fault_loadvnx8df },
    &operand_data[18242],
    8,
    8,
    1,
    4,
    1
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:488 */
  {
    "addvsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_addvsi4 },
    &operand_data[18250],
    4,
    4,
    0,
    2,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:488 */
  {
    "addvdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_addvdi4 },
    &operand_data[18254],
    4,
    4,
    0,
    2,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:532 */
  {
    "uaddvsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_uaddvsi4 },
    &operand_data[18250],
    4,
    4,
    0,
    2,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:532 */
  {
    "uaddvdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_uaddvdi4 },
    &operand_data[18254],
    4,
    4,
    0,
    2,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:619 */
  {
    "subvsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subvsi4 },
    &operand_data[18258],
    4,
    4,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:619 */
  {
    "subvdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_subvdi4 },
    &operand_data[18262],
    4,
    4,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:666 */
  {
    "usubvsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_usubvsi4 },
    &operand_data[18258],
    4,
    4,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:666 */
  {
    "usubvdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_usubvdi4 },
    &operand_data[18262],
    4,
    4,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:789 */
  {
    "mulvsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_mulvsi4 },
    &operand_data[18266],
    4,
    4,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:789 */
  {
    "mulvdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_mulvdi4 },
    &operand_data[18270],
    4,
    4,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:834 */
  {
    "umulvsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_umulvsi4 },
    &operand_data[18266],
    4,
    4,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:834 */
  {
    "umulvdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_umulvdi4 },
    &operand_data[18270],
    4,
    4,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:910 */
  {
    "mulditi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_mulditi3 },
    &operand_data[18274],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:910 */
  {
    "umulditi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_umulditi3 },
    &operand_data[18274],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:941 */
  {
    "usmulditi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_usmulditi3 },
    &operand_data[18274],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:972 */
  {
    "mulsidi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_mulsidi3 },
    &operand_data[51],
    3,
    3,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:972 */
  {
    "umulsidi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_umulsidi3 },
    &operand_data[51],
    3,
    3,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1003 */
  {
    "usmulsidi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_usmulsidi3 },
    &operand_data[51],
    3,
    3,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1362 */
  {
    "zero_extendsidi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_zero_extendsidi2 },
    &operand_data[18276],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1388 */
  {
    "zero_extendhisi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_zero_extendhisi2 },
    &operand_data[18278],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1388 */
  {
    "zero_extendhidi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_zero_extendhidi2 },
    &operand_data[18280],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1445 */
  {
    "extendqihi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extendqihi2 },
    &operand_data[18282],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1445 */
  {
    "extendqisi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extendqisi2 },
    &operand_data[18284],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1445 */
  {
    "extendqidi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extendqidi2 },
    &operand_data[18286],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1445 */
  {
    "extendhihi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extendhihi2 },
    &operand_data[18288],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1445 */
  {
    "extendhisi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extendhisi2 },
    &operand_data[18278],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1445 */
  {
    "extendhidi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extendhidi2 },
    &operand_data[18280],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1501 */
  {
    "movhf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movhf },
    &operand_data[18290],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1707 */
  {
    "movdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movdi },
    &operand_data[18292],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1740 */
  {
    "movsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movsi },
    &operand_data[18294],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1768 */
  {
    "movhi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movhi },
    &operand_data[18296],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1811 */
  {
    "movqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movqi },
    &operand_data[18298],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1832 */
  {
    "movsf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movsf },
    &operand_data[18300],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1863 */
  {
    "movdf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movdf },
    &operand_data[18302],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1916 */
  {
    "cpymemsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_cpymemsi },
    &operand_data[18304],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:1931 */
  {
    "clear_cache",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_clear_cache },
    &operand_data[18308],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2323 */
  {
    "movsicc",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movsicc },
    &operand_data[18310],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2323 */
  {
    "movdicc",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movdicc },
    &operand_data[18314],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2386 */
  {
    "condjump",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_condjump },
    &operand_data[18318],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2392 */
  {
    "cbranchqi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_cbranchqi4 },
    &operand_data[18320],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2392 */
  {
    "cbranchsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_cbranchsi4 },
    &operand_data[18324],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2392 */
  {
    "cbranchdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_cbranchdi4 },
    &operand_data[18328],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2406 */
  {
    "cbranchsf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_cbranchsf4 },
    &operand_data[18332],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2406 */
  {
    "cbranchdf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_cbranchdf4 },
    &operand_data[18336],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2406 */
  {
    "cbranchhf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_cbranchhf4 },
    &operand_data[18340],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2485 */
  {
    "cstoresi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_cstoresi4 },
    &operand_data[18344],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2485 */
  {
    "cstoredi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_cstoredi4 },
    &operand_data[18348],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2497 */
  {
    "cstoresf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_cstoresf4 },
    &operand_data[18352],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2497 */
  {
    "cstoredf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_cstoredf4 },
    &operand_data[18356],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2497 */
  {
    "cstorehf4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_cstorehf4 },
    &operand_data[18360],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
  {
    "flt_quietsfsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_flt_quietsfsi4 },
    &operand_data[18364],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
  {
    "fle_quietsfsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fle_quietsfsi4 },
    &operand_data[18364],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
  {
    "flt_quietsfdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_flt_quietsfdi4 },
    &operand_data[18367],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
  {
    "fle_quietsfdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fle_quietsfdi4 },
    &operand_data[18367],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
  {
    "flt_quietdfsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_flt_quietdfsi4 },
    &operand_data[18370],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
  {
    "fle_quietdfsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fle_quietdfsi4 },
    &operand_data[18370],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
  {
    "flt_quietdfdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_flt_quietdfdi4 },
    &operand_data[18373],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
  {
    "fle_quietdfdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fle_quietdfdi4 },
    &operand_data[18373],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
  {
    "flt_quiethfsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_flt_quiethfsi4 },
    &operand_data[18376],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
  {
    "fle_quiethfsi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fle_quiethfsi4 },
    &operand_data[18376],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
  {
    "flt_quiethfdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_flt_quiethfdi4 },
    &operand_data[18379],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2519 */
  {
    "fle_quiethfdi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_fle_quiethfdi4 },
    &operand_data[18379],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2620 */
  {
    "indirect_jump",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_indirect_jump },
    &operand_data[18382],
    1,
    1,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2639 */
  {
    "tablejump",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_tablejump },
    &operand_data[18382],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2672 */
  {
    "prologue",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_prologue },
    &operand_data[0],
    0,
    0,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2691 */
  {
    "epilogue",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_epilogue },
    &operand_data[0],
    0,
    0,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2699 */
  {
    "sibcall_epilogue",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_sibcall_epilogue },
    &operand_data[0],
    0,
    0,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2710 */
  {
    "return",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_return },
    &operand_data[0],
    0,
    0,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2735 */
  {
    "eh_return",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_eh_return },
    &operand_data[18384],
    1,
    1,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2791 */
  {
    "sibcall",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_sibcall },
    &operand_data[18385],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2813 */
  {
    "sibcall_value",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_sibcall_value },
    &operand_data[18385],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2836 */
  {
    "call",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_call },
    &operand_data[18385],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2859 */
  {
    "call_value",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_call_value },
    &operand_data[18385],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2885 */
  {
    "untyped_call",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_untyped_call },
    &operand_data[18385],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:2994 */
  {
    "restore_stack_nonlocal",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_restore_stack_nonlocal },
    &operand_data[18389],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3007 */
  {
    "get_thread_pointersi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_get_thread_pointersi },
    &operand_data[26],
    1,
    1,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3007 */
  {
    "get_thread_pointerdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_get_thread_pointerdi },
    &operand_data[23],
    1,
    1,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3015 */
  {
    "stack_protect_set",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_stack_protect_set },
    &operand_data[18390],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3046 */
  {
    "stack_protect_test",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_stack_protect_test },
    &operand_data[18390],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3135 */
  {
    "extvsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extvsi },
    &operand_data[760],
    4,
    4,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3135 */
  {
    "extvdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extvdi },
    &operand_data[226],
    4,
    4,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3143 */
  {
    "extzvsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extzvsi },
    &operand_data[760],
    4,
    4,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3143 */
  {
    "extzvdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_extzvdi },
    &operand_data[226],
    4,
    4,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3155 */
  {
    "maddhisi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_maddhisi4 },
    &operand_data[18393],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/riscv.md:3164 */
  {
    "msubhisi4",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_msubhisi4 },
    &operand_data[18393],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:190 */
  {
    "clzdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_clzdi2 },
    &operand_data[18275],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:195 */
  {
    "clzsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_clzsi2 },
    &operand_data[18396],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:200 */
  {
    "ctzsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_ctzsi2 },
    &operand_data[18396],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:200 */
  {
    "ctzdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_ctzdi2 },
    &operand_data[18275],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:205 */
  {
    "popcountsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_popcountsi2 },
    &operand_data[18396],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:205 */
  {
    "popcountdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_popcountdi2 },
    &operand_data[18275],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:298 */
  {
    "rotrsi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_rotrsi3 },
    &operand_data[18396],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:298 */
  {
    "rotrdi3",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_rotrdi3 },
    &operand_data[18399],
    3,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:364 */
  {
    "bswapdi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_bswapdi2 },
    &operand_data[18275],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:369 */
  {
    "bswapsi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_bswapsi2 },
    &operand_data[18396],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/bitmanip.md:385 */
  {
    "bswaphi2",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_bswaphi2 },
    &operand_data[18402],
    2,
    2,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:36 */
  {
    "mem_thread_fence",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_mem_thread_fence },
    &operand_data[144],
    1,
    1,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:174 */
  {
    "atomic_fetch_nandqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_nandqi },
    &operand_data[18404],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:174 */
  {
    "atomic_fetch_nandhi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_nandhi },
    &operand_data[18408],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
  {
    "atomic_fetch_addqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_addqi },
    &operand_data[18404],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
  {
    "atomic_fetch_orqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_orqi },
    &operand_data[18404],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
  {
    "atomic_fetch_xorqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_xorqi },
    &operand_data[18404],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
  {
    "atomic_fetch_andqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_andqi },
    &operand_data[18404],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
  {
    "atomic_fetch_addhi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_addhi },
    &operand_data[18408],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
  {
    "atomic_fetch_orhi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_orhi },
    &operand_data[18408],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
  {
    "atomic_fetch_xorhi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_xorhi },
    &operand_data[18408],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:241 */
  {
    "atomic_fetch_andhi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_fetch_andhi },
    &operand_data[18408],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:295 */
  {
    "atomic_exchangeqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_exchangeqi },
    &operand_data[18412],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:295 */
  {
    "atomic_exchangehi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_exchangehi },
    &operand_data[18416],
    4,
    4,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:375 */
  {
    "atomic_compare_and_swapsi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_compare_and_swapsi },
    &operand_data[18420],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:375 */
  {
    "atomic_compare_and_swapdi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_compare_and_swapdi },
    &operand_data[18428],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:418 */
  {
    "atomic_compare_and_swapqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_compare_and_swapqi },
    &operand_data[18436],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:418 */
  {
    "atomic_compare_and_swaphi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_compare_and_swaphi },
    &operand_data[18444],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:464 */
  {
    "atomic_cas_value_strongqi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_cas_value_strongqi },
    &operand_data[18452],
    6,
    7,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:464 */
  {
    "atomic_cas_value_stronghi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_cas_value_stronghi },
    &operand_data[18459],
    6,
    7,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/sync.md:544 */
  {
    "atomic_test_and_set",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_atomic_test_and_set },
    &operand_data[18466],
    3,
    3,
    0,
    1,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx1qi },
    &operand_data[18469],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx2qi },
    &operand_data[18471],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx4qi },
    &operand_data[18473],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx8qi },
    &operand_data[18475],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx16qi },
    &operand_data[18477],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx32qi },
    &operand_data[18479],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx64qi },
    &operand_data[18481],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx1hi },
    &operand_data[18483],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx2hi },
    &operand_data[18485],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx4hi },
    &operand_data[18487],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx8hi },
    &operand_data[18489],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx16hi },
    &operand_data[18491],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx32hi },
    &operand_data[18493],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx1si },
    &operand_data[18495],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx2si },
    &operand_data[18497],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx4si },
    &operand_data[18499],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx8si },
    &operand_data[18501],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx16si },
    &operand_data[18503],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx1di },
    &operand_data[18505],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx2di },
    &operand_data[18507],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx4di },
    &operand_data[18509],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx8di },
    &operand_data[18511],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx1sf },
    &operand_data[18513],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx2sf },
    &operand_data[18515],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx4sf },
    &operand_data[18517],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx8sf },
    &operand_data[18519],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx16sf },
    &operand_data[18521],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx1df },
    &operand_data[18523],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx2df },
    &operand_data[18525],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx4df },
    &operand_data[18527],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:370 */
  {
    "vreinterpretvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vreinterpretvnx8df },
    &operand_data[18529],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx1qi },
    &operand_data[18531],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx2qi },
    &operand_data[18533],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx4qi },
    &operand_data[18535],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx8qi },
    &operand_data[18537],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx16qi },
    &operand_data[18539],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx32qi },
    &operand_data[18541],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx1hi },
    &operand_data[18543],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx2hi },
    &operand_data[18545],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx4hi },
    &operand_data[18547],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx8hi },
    &operand_data[18549],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx16hi },
    &operand_data[18551],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx1si },
    &operand_data[18553],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx2si },
    &operand_data[18555],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx4si },
    &operand_data[18557],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx8si },
    &operand_data[18559],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx1di },
    &operand_data[18561],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx2di },
    &operand_data[18563],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx4di },
    &operand_data[18565],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx1sf },
    &operand_data[18567],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx2sf },
    &operand_data[18569],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx4sf },
    &operand_data[18571],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx8sf },
    &operand_data[18573],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx1df },
    &operand_data[18575],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx2df },
    &operand_data[18577],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:380 */
  {
    "vlmul_extx2vnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx2vnx4df },
    &operand_data[18579],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx1qi },
    &operand_data[18581],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx2qi },
    &operand_data[18583],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx4qi },
    &operand_data[18585],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx8qi },
    &operand_data[18587],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx16qi },
    &operand_data[18589],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx1hi },
    &operand_data[18591],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx2hi },
    &operand_data[18593],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx4hi },
    &operand_data[18595],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx8hi },
    &operand_data[18597],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx1si },
    &operand_data[18599],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx2si },
    &operand_data[18601],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx4si },
    &operand_data[18603],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx1di },
    &operand_data[18605],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx2di },
    &operand_data[18607],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx1sf },
    &operand_data[18609],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx2sf },
    &operand_data[18611],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx4sf },
    &operand_data[18613],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx1df },
    &operand_data[18615],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:387 */
  {
    "vlmul_extx4vnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx4vnx2df },
    &operand_data[18617],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx1qi },
    &operand_data[18619],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx2qi },
    &operand_data[18621],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx4qi },
    &operand_data[18623],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx8qi },
    &operand_data[18625],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx1hi },
    &operand_data[18627],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx2hi },
    &operand_data[18629],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx4hi },
    &operand_data[18631],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx1si },
    &operand_data[18633],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx2si },
    &operand_data[18635],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx1di },
    &operand_data[18637],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx1sf },
    &operand_data[18639],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx2sf },
    &operand_data[18641],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:394 */
  {
    "vlmul_extx8vnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx8vnx1df },
    &operand_data[18643],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
  {
    "vlmul_extx16vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx16vnx1qi },
    &operand_data[18645],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
  {
    "vlmul_extx16vnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx16vnx2qi },
    &operand_data[18647],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
  {
    "vlmul_extx16vnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx16vnx4qi },
    &operand_data[18649],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
  {
    "vlmul_extx16vnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx16vnx1hi },
    &operand_data[18651],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
  {
    "vlmul_extx16vnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx16vnx2hi },
    &operand_data[18653],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
  {
    "vlmul_extx16vnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx16vnx1si },
    &operand_data[18655],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:401 */
  {
    "vlmul_extx16vnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx16vnx1sf },
    &operand_data[18657],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:408 */
  {
    "vlmul_extx32vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx32vnx1qi },
    &operand_data[18659],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:408 */
  {
    "vlmul_extx32vnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx32vnx2qi },
    &operand_data[18661],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:408 */
  {
    "vlmul_extx32vnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx32vnx1hi },
    &operand_data[18663],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:415 */
  {
    "vlmul_extx64vnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vlmul_extx64vnx1qi },
    &operand_data[18665],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1qi },
    &operand_data[18667],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2qi },
    &operand_data[18669],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx4qi },
    &operand_data[18671],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx8qi },
    &operand_data[18673],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx16qi },
    &operand_data[18675],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx32qi },
    &operand_data[18677],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx64qi },
    &operand_data[18679],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1hi },
    &operand_data[18681],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2hi },
    &operand_data[18683],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx4hi },
    &operand_data[18685],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx8hi },
    &operand_data[18687],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx16hi },
    &operand_data[18689],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx32hi },
    &operand_data[18691],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1si },
    &operand_data[18693],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2si },
    &operand_data[18695],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx4si },
    &operand_data[18697],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx8si },
    &operand_data[18699],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx16si },
    &operand_data[18701],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1di },
    &operand_data[18703],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2di },
    &operand_data[18705],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx4di },
    &operand_data[18707],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx8di },
    &operand_data[18709],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1sf },
    &operand_data[18711],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2sf },
    &operand_data[18713],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx4sf },
    &operand_data[18715],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx8sf },
    &operand_data[18717],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx16sf },
    &operand_data[18719],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1df },
    &operand_data[18721],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2df },
    &operand_data[18723],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx4df },
    &operand_data[18725],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:535 */
  {
    "movvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx8df },
    &operand_data[18727],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
  {
    "movvnx1bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1bi },
    &operand_data[18729],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
  {
    "movvnx2bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2bi },
    &operand_data[18731],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
  {
    "movvnx4bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx4bi },
    &operand_data[18733],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
  {
    "movvnx8bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx8bi },
    &operand_data[18735],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
  {
    "movvnx16bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx16bi },
    &operand_data[18737],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
  {
    "movvnx32bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx32bi },
    &operand_data[18739],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:621 */
  {
    "movvnx64bi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx64bi },
    &operand_data[18741],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx1qisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1qisi_lra },
    &operand_data[18743],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx1qidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1qidi_lra },
    &operand_data[18746],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx2qisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2qisi_lra },
    &operand_data[18749],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx2qidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2qidi_lra },
    &operand_data[18752],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx4qisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx4qisi_lra },
    &operand_data[18755],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx4qidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx4qidi_lra },
    &operand_data[18758],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx1hisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1hisi_lra },
    &operand_data[18761],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx1hidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1hidi_lra },
    &operand_data[18764],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx2hisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2hisi_lra },
    &operand_data[18767],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx2hidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2hidi_lra },
    &operand_data[18770],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx1sisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1sisi_lra },
    &operand_data[18773],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx1sidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1sidi_lra },
    &operand_data[18776],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx1sfsi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1sfsi_lra },
    &operand_data[18779],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:638 */
  {
    "movvnx1sfdi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1sfdi_lra },
    &operand_data[18782],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx1bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1bisi_lra },
    &operand_data[18785],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx2bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2bisi_lra },
    &operand_data[18788],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx4bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx4bisi_lra },
    &operand_data[18791],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx8bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx8bisi_lra },
    &operand_data[18794],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx16bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx16bisi_lra },
    &operand_data[18797],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx32bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx32bisi_lra },
    &operand_data[18800],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx64bisi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx64bisi_lra },
    &operand_data[18803],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx1bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx1bidi_lra },
    &operand_data[18806],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx2bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx2bidi_lra },
    &operand_data[18809],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx4bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx4bidi_lra },
    &operand_data[18812],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx8bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx8bidi_lra },
    &operand_data[18815],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx16bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx16bidi_lra },
    &operand_data[18818],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx32bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx32bidi_lra },
    &operand_data[18821],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:646 */
  {
    "movvnx64bidi_lra",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_movvnx64bidi_lra },
    &operand_data[18824],
    2,
    3,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx1qi },
    &operand_data[18827],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx2qi },
    &operand_data[18829],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx4qi },
    &operand_data[18831],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx8qi },
    &operand_data[18833],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx16qi },
    &operand_data[18835],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx32qi },
    &operand_data[18837],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx64qi },
    &operand_data[18839],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx1hi },
    &operand_data[18841],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx2hi },
    &operand_data[18843],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx4hi },
    &operand_data[18845],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx8hi },
    &operand_data[18847],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx16hi },
    &operand_data[18849],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx32hi },
    &operand_data[18851],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx1si },
    &operand_data[18853],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx2si },
    &operand_data[18855],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx4si },
    &operand_data[18857],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx8si },
    &operand_data[18859],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx16si },
    &operand_data[18861],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx1di },
    &operand_data[18863],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx2di },
    &operand_data[18865],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx4di },
    &operand_data[18867],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx8di },
    &operand_data[18869],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx1sf },
    &operand_data[18871],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx2sf },
    &operand_data[18873],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx4sf },
    &operand_data[18875],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx8sf },
    &operand_data[18877],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx16sf },
    &operand_data[18879],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx1df },
    &operand_data[18881],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx2df },
    &operand_data[18883],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx4df },
    &operand_data[18885],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:702 */
  {
    "vec_duplicatevnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_vec_duplicatevnx8df },
    &operand_data[18887],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1112 */
  {
    "pred_mergevnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx1di_scalar },
    &operand_data[18889],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1112 */
  {
    "pred_mergevnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx2di_scalar },
    &operand_data[18897],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1112 */
  {
    "pred_mergevnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx4di_scalar },
    &operand_data[18905],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1112 */
  {
    "pred_mergevnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mergevnx8di_scalar },
    &operand_data[18913],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx1qi },
    &operand_data[18921],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx2qi },
    &operand_data[18929],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx4qi },
    &operand_data[18937],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx8qi },
    &operand_data[18945],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx16qi },
    &operand_data[18953],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx32qi },
    &operand_data[18961],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx64qi },
    &operand_data[18969],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx1hi },
    &operand_data[18977],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx2hi },
    &operand_data[18985],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx4hi },
    &operand_data[18993],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx8hi },
    &operand_data[19001],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx16hi },
    &operand_data[19009],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx32hi },
    &operand_data[19017],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx1si },
    &operand_data[19025],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx2si },
    &operand_data[19033],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx4si },
    &operand_data[19041],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx8si },
    &operand_data[19049],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx16si },
    &operand_data[19057],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx1di },
    &operand_data[19065],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx2di },
    &operand_data[19073],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx4di },
    &operand_data[19081],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx8di },
    &operand_data[19089],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx1sf },
    &operand_data[19097],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx2sf },
    &operand_data[19105],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx4sf },
    &operand_data[19113],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx8sf },
    &operand_data[19121],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx16sf },
    &operand_data[19129],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx1df },
    &operand_data[19137],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx2df },
    &operand_data[19145],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx4df },
    &operand_data[19153],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1204 */
  {
    "pred_broadcastvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_broadcastvnx8df },
    &operand_data[19161],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_addvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_andvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_iorvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_xorvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_smaxvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_umaxvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_sminvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_uminvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_mulvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_addvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_andvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_iorvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_xorvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_smaxvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_umaxvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_sminvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_uminvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_mulvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_addvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_andvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_iorvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_xorvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_smaxvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_umaxvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_sminvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_uminvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_mulvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_addvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_addvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_andvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_andvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_iorvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_iorvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_xorvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_xorvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_smaxvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smaxvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_umaxvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umaxvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_sminvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sminvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_uminvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_uminvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1805 */
  {
    "pred_mulvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_subvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_divvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_udivvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_modvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_umodvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_subvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_divvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_udivvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_modvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_umodvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_subvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_divvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_udivvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_modvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_umodvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_subvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_divvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_divvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_udivvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_udivvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_modvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_modvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1881 */
  {
    "pred_umodvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_umodvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1957 */
  {
    "pred_subvnx1di_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx1di_reverse_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1957 */
  {
    "pred_subvnx2di_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx2di_reverse_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1957 */
  {
    "pred_subvnx4di_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx4di_reverse_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:1957 */
  {
    "pred_subvnx8di_reverse_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_subvnx8di_reverse_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
  {
    "pred_mulhvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
  {
    "pred_mulhuvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
  {
    "pred_mulhsuvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
  {
    "pred_mulhvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
  {
    "pred_mulhuvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
  {
    "pred_mulhsuvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
  {
    "pred_mulhvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
  {
    "pred_mulhuvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
  {
    "pred_mulhsuvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
  {
    "pred_mulhvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
  {
    "pred_mulhuvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhuvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2075 */
  {
    "pred_mulhsuvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mulhsuvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2250 */
  {
    "pred_adcvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx1di_scalar },
    &operand_data[18889],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2250 */
  {
    "pred_adcvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx2di_scalar },
    &operand_data[18897],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2250 */
  {
    "pred_adcvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx4di_scalar },
    &operand_data[18905],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2250 */
  {
    "pred_adcvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_adcvnx8di_scalar },
    &operand_data[18913],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2334 */
  {
    "pred_sbcvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx1di_scalar },
    &operand_data[18889],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2334 */
  {
    "pred_sbcvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx2di_scalar },
    &operand_data[18897],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2334 */
  {
    "pred_sbcvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx4di_scalar },
    &operand_data[18905],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2334 */
  {
    "pred_sbcvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sbcvnx8di_scalar },
    &operand_data[18913],
    8,
    8,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2496 */
  {
    "pred_madcvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1di_scalar },
    &operand_data[19205],
    6,
    6,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2496 */
  {
    "pred_madcvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2di_scalar },
    &operand_data[19211],
    6,
    6,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2496 */
  {
    "pred_madcvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4di_scalar },
    &operand_data[19217],
    6,
    6,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2496 */
  {
    "pred_madcvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8di_scalar },
    &operand_data[19223],
    6,
    6,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2566 */
  {
    "pred_msbcvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1di_scalar },
    &operand_data[19205],
    6,
    6,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2566 */
  {
    "pred_msbcvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2di_scalar },
    &operand_data[19211],
    6,
    6,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2566 */
  {
    "pred_msbcvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4di_scalar },
    &operand_data[19217],
    6,
    6,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2566 */
  {
    "pred_msbcvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8di_scalar },
    &operand_data[19223],
    6,
    6,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2710 */
  {
    "pred_madcvnx1di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx1di_overflow_scalar },
    &operand_data[19229],
    5,
    5,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2710 */
  {
    "pred_madcvnx2di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx2di_overflow_scalar },
    &operand_data[19234],
    5,
    5,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2710 */
  {
    "pred_madcvnx4di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx4di_overflow_scalar },
    &operand_data[19239],
    5,
    5,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2710 */
  {
    "pred_madcvnx8di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_madcvnx8di_overflow_scalar },
    &operand_data[19244],
    5,
    5,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2777 */
  {
    "pred_msbcvnx1di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx1di_overflow_scalar },
    &operand_data[19229],
    5,
    5,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2777 */
  {
    "pred_msbcvnx2di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx2di_overflow_scalar },
    &operand_data[19234],
    5,
    5,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2777 */
  {
    "pred_msbcvnx4di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx4di_overflow_scalar },
    &operand_data[19239],
    5,
    5,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:2777 */
  {
    "pred_msbcvnx8di_overflow_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_msbcvnx8di_overflow_scalar },
    &operand_data[19244],
    5,
    5,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
  {
    "pred_ssaddvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
  {
    "pred_usaddvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
  {
    "pred_ssaddvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
  {
    "pred_usaddvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
  {
    "pred_ssaddvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
  {
    "pred_usaddvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
  {
    "pred_ssaddvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ssaddvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3263 */
  {
    "pred_usaddvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_usaddvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
  {
    "pred_sssubvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
  {
    "pred_ussubvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
  {
    "pred_sssubvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
  {
    "pred_ussubvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
  {
    "pred_sssubvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
  {
    "pred_ussubvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
  {
    "pred_sssubvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_sssubvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3339 */
  {
    "pred_ussubvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ussubvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_aadduvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_aaddvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_asubuvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_asubvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_smulvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx1di_scalar },
    &operand_data[19169],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_aadduvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_aaddvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_asubuvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_asubvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_smulvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx2di_scalar },
    &operand_data[19178],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_aadduvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_aaddvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_asubuvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_asubvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_smulvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx4di_scalar },
    &operand_data[19187],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_aadduvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aadduvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_aaddvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_aaddvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_asubuvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubuvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_asubvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_asubvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3478 */
  {
    "pred_smulvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_smulvnx8di_scalar },
    &operand_data[19196],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx1qi },
    &operand_data[19249],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx2qi },
    &operand_data[19258],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx4qi },
    &operand_data[19267],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx8qi },
    &operand_data[19276],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx16qi },
    &operand_data[19285],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx32qi },
    &operand_data[19294],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx64qi },
    &operand_data[19303],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx1hi },
    &operand_data[19312],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx2hi },
    &operand_data[19321],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx4hi },
    &operand_data[19330],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx8hi },
    &operand_data[19339],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx16hi },
    &operand_data[19348],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx32hi },
    &operand_data[19357],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx1si },
    &operand_data[19366],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx2si },
    &operand_data[19375],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx4si },
    &operand_data[19384],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx8si },
    &operand_data[19393],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx16si },
    &operand_data[19402],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx1di },
    &operand_data[19411],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx2di },
    &operand_data[19420],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx4di },
    &operand_data[19429],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3599 */
  {
    "pred_cmpvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx8di },
    &operand_data[19438],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx1qi },
    &operand_data[19447],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx2qi },
    &operand_data[19456],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx4qi },
    &operand_data[19465],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx8qi },
    &operand_data[19474],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx16qi },
    &operand_data[19483],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx32qi },
    &operand_data[19492],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx64qi },
    &operand_data[19501],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx1hi },
    &operand_data[19510],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx2hi },
    &operand_data[19519],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx4hi },
    &operand_data[19528],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx8hi },
    &operand_data[19537],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx16hi },
    &operand_data[19546],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx32hi },
    &operand_data[19555],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx1si },
    &operand_data[19564],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx2si },
    &operand_data[19573],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx4si },
    &operand_data[19582],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx8si },
    &operand_data[19591],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx16si },
    &operand_data[19600],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx1di },
    &operand_data[19609],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx2di },
    &operand_data[19618],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx4di },
    &operand_data[19627],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3656 */
  {
    "pred_ltgevnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_ltgevnx8di },
    &operand_data[19636],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx1qi_scalar },
    &operand_data[19645],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx2qi_scalar },
    &operand_data[19654],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx4qi_scalar },
    &operand_data[19663],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx8qi_scalar },
    &operand_data[19672],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx16qi_scalar },
    &operand_data[19681],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx32qi_scalar },
    &operand_data[19690],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx64qi_scalar },
    &operand_data[19699],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx1hi_scalar },
    &operand_data[19708],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx2hi_scalar },
    &operand_data[19717],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx4hi_scalar },
    &operand_data[19726],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx8hi_scalar },
    &operand_data[19735],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx16hi_scalar },
    &operand_data[19744],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx32hi_scalar },
    &operand_data[19753],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx1si_scalar },
    &operand_data[19762],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx2si_scalar },
    &operand_data[19771],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx4si_scalar },
    &operand_data[19780],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx8si_scalar },
    &operand_data[19789],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3713 */
  {
    "pred_cmpvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx16si_scalar },
    &operand_data[19798],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx1qi_scalar },
    &operand_data[19807],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx2qi_scalar },
    &operand_data[19816],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx4qi_scalar },
    &operand_data[19825],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx8qi_scalar },
    &operand_data[19834],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx16qi_scalar },
    &operand_data[19843],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx32qi_scalar },
    &operand_data[19852],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx64qi_scalar },
    &operand_data[19861],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx1hi_scalar },
    &operand_data[19870],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx2hi_scalar },
    &operand_data[19879],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx4hi_scalar },
    &operand_data[19888],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx8hi_scalar },
    &operand_data[19897],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx16hi_scalar },
    &operand_data[19906],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx32hi_scalar },
    &operand_data[19915],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx1si_scalar },
    &operand_data[19924],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx2si_scalar },
    &operand_data[19933],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx4si_scalar },
    &operand_data[19942],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx8si_scalar },
    &operand_data[19951],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3773 */
  {
    "pred_eqnevnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx16si_scalar },
    &operand_data[19960],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3835 */
  {
    "pred_cmpvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx1di_scalar },
    &operand_data[19969],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3835 */
  {
    "pred_cmpvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx2di_scalar },
    &operand_data[19978],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3835 */
  {
    "pred_cmpvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx4di_scalar },
    &operand_data[19987],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3835 */
  {
    "pred_cmpvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx8di_scalar },
    &operand_data[19996],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3875 */
  {
    "pred_eqnevnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx1di_scalar },
    &operand_data[20005],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3875 */
  {
    "pred_eqnevnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx2di_scalar },
    &operand_data[20014],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3875 */
  {
    "pred_eqnevnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx4di_scalar },
    &operand_data[20023],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:3875 */
  {
    "pred_eqnevnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx8di_scalar },
    &operand_data[20032],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx1qi_scalar },
    &operand_data[20041],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx2qi_scalar },
    &operand_data[20050],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx4qi_scalar },
    &operand_data[20059],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx8qi_scalar },
    &operand_data[20068],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx16qi_scalar },
    &operand_data[20077],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx32qi_scalar },
    &operand_data[20086],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx64qi_scalar },
    &operand_data[20095],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx1hi_scalar },
    &operand_data[20104],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx2hi_scalar },
    &operand_data[20113],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx4hi_scalar },
    &operand_data[20122],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx8hi_scalar },
    &operand_data[20131],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx16hi_scalar },
    &operand_data[20140],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx32hi_scalar },
    &operand_data[20149],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx1si_scalar },
    &operand_data[20158],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx2si_scalar },
    &operand_data[20167],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx4si_scalar },
    &operand_data[20176],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx8si_scalar },
    &operand_data[20185],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx16si_scalar },
    &operand_data[20194],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx1di_scalar },
    &operand_data[20203],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx2di_scalar },
    &operand_data[20212],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx4di_scalar },
    &operand_data[20221],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4091 */
  {
    "pred_gevnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_gevnx8di_scalar },
    &operand_data[20230],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx1qi },
    &operand_data[20239],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx2qi },
    &operand_data[20249],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx4qi },
    &operand_data[20259],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx8qi },
    &operand_data[20269],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx16qi },
    &operand_data[20279],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx32qi },
    &operand_data[20289],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx64qi },
    &operand_data[20299],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx1hi },
    &operand_data[20309],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx2hi },
    &operand_data[20319],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx4hi },
    &operand_data[20329],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx8hi },
    &operand_data[20339],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx16hi },
    &operand_data[20349],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx32hi },
    &operand_data[20359],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx1si },
    &operand_data[20369],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx2si },
    &operand_data[20379],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx4si },
    &operand_data[20389],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx8si },
    &operand_data[20399],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx16si },
    &operand_data[20409],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx1di },
    &operand_data[20419],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx2di },
    &operand_data[20429],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx4di },
    &operand_data[20439],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4203 */
  {
    "pred_mul_plusvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx8di },
    &operand_data[20449],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx1qi_scalar },
    &operand_data[20459],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx2qi_scalar },
    &operand_data[20469],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx4qi_scalar },
    &operand_data[20479],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx8qi_scalar },
    &operand_data[20489],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx16qi_scalar },
    &operand_data[20499],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx32qi_scalar },
    &operand_data[20509],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx64qi_scalar },
    &operand_data[20519],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx1hi_scalar },
    &operand_data[20529],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx2hi_scalar },
    &operand_data[20539],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx4hi_scalar },
    &operand_data[20549],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx8hi_scalar },
    &operand_data[20559],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx16hi_scalar },
    &operand_data[20569],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx32hi_scalar },
    &operand_data[20579],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx1si_scalar },
    &operand_data[20589],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx2si_scalar },
    &operand_data[20599],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx4si_scalar },
    &operand_data[20609],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx8si_scalar },
    &operand_data[20619],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4341 */
  {
    "pred_mul_plusvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx16si_scalar },
    &operand_data[20629],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4475 */
  {
    "pred_mul_plusvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx1di_scalar },
    &operand_data[20639],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4475 */
  {
    "pred_mul_plusvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx2di_scalar },
    &operand_data[20649],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4475 */
  {
    "pred_mul_plusvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx4di_scalar },
    &operand_data[20659],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4475 */
  {
    "pred_mul_plusvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_plusvnx8di_scalar },
    &operand_data[20669],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx1qi },
    &operand_data[20239],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx2qi },
    &operand_data[20249],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx4qi },
    &operand_data[20259],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx8qi },
    &operand_data[20269],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx16qi },
    &operand_data[20279],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx32qi },
    &operand_data[20289],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx64qi },
    &operand_data[20299],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx1hi },
    &operand_data[20309],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx2hi },
    &operand_data[20319],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx4hi },
    &operand_data[20329],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx8hi },
    &operand_data[20339],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx16hi },
    &operand_data[20349],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx32hi },
    &operand_data[20359],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx1si },
    &operand_data[20369],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx2si },
    &operand_data[20379],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx4si },
    &operand_data[20389],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx8si },
    &operand_data[20399],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx16si },
    &operand_data[20409],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx1di },
    &operand_data[20419],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx2di },
    &operand_data[20429],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx4di },
    &operand_data[20439],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4624 */
  {
    "pred_minus_mulvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx8di },
    &operand_data[20449],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx1qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx1qi_scalar },
    &operand_data[20459],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx2qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx2qi_scalar },
    &operand_data[20469],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx4qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx4qi_scalar },
    &operand_data[20479],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx8qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx8qi_scalar },
    &operand_data[20489],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx16qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx16qi_scalar },
    &operand_data[20499],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx32qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx32qi_scalar },
    &operand_data[20509],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx64qi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx64qi_scalar },
    &operand_data[20519],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx1hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx1hi_scalar },
    &operand_data[20529],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx2hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx2hi_scalar },
    &operand_data[20539],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx4hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx4hi_scalar },
    &operand_data[20549],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx8hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx8hi_scalar },
    &operand_data[20559],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx16hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx16hi_scalar },
    &operand_data[20569],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx32hi_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx32hi_scalar },
    &operand_data[20579],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx1si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx1si_scalar },
    &operand_data[20589],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx2si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx2si_scalar },
    &operand_data[20599],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx4si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx4si_scalar },
    &operand_data[20609],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx8si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx8si_scalar },
    &operand_data[20619],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4762 */
  {
    "pred_minus_mulvnx16si_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx16si_scalar },
    &operand_data[20629],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4896 */
  {
    "pred_minus_mulvnx1di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx1di_scalar },
    &operand_data[20639],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4896 */
  {
    "pred_minus_mulvnx2di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx2di_scalar },
    &operand_data[20649],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4896 */
  {
    "pred_minus_mulvnx4di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx4di_scalar },
    &operand_data[20659],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:4896 */
  {
    "pred_minus_mulvnx8di_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_minus_mulvnx8di_scalar },
    &operand_data[20669],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_addvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx1sf },
    &operand_data[20679],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_subvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx1sf },
    &operand_data[20679],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_addvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx2sf },
    &operand_data[20689],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_subvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx2sf },
    &operand_data[20689],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_addvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx4sf },
    &operand_data[20699],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_subvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx4sf },
    &operand_data[20699],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_addvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx8sf },
    &operand_data[20709],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_subvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx8sf },
    &operand_data[20709],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_addvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx16sf },
    &operand_data[20719],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_subvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx16sf },
    &operand_data[20719],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_addvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx1df },
    &operand_data[20729],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_subvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx1df },
    &operand_data[20729],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_addvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx2df },
    &operand_data[20739],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_subvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx2df },
    &operand_data[20739],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_addvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx4df },
    &operand_data[20749],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_subvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx4df },
    &operand_data[20749],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_addvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx8df },
    &operand_data[20759],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5503 */
  {
    "pred_mul_subvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx8df },
    &operand_data[20759],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_addvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx1sf_scalar },
    &operand_data[20769],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_subvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx1sf_scalar },
    &operand_data[20769],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_addvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx2sf_scalar },
    &operand_data[20779],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_subvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx2sf_scalar },
    &operand_data[20779],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_addvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx4sf_scalar },
    &operand_data[20789],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_subvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx4sf_scalar },
    &operand_data[20789],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_addvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx8sf_scalar },
    &operand_data[20799],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_subvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx8sf_scalar },
    &operand_data[20799],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_addvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx16sf_scalar },
    &operand_data[20809],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_subvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx16sf_scalar },
    &operand_data[20809],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_addvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx1df_scalar },
    &operand_data[20819],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_subvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx1df_scalar },
    &operand_data[20819],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_addvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx2df_scalar },
    &operand_data[20829],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_subvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx2df_scalar },
    &operand_data[20829],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_addvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx4df_scalar },
    &operand_data[20839],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_subvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx4df_scalar },
    &operand_data[20839],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_addvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_addvnx8df_scalar },
    &operand_data[20849],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5625 */
  {
    "pred_mul_subvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_subvnx8df_scalar },
    &operand_data[20849],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_addvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx1sf },
    &operand_data[20679],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_subvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx1sf },
    &operand_data[20679],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_addvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx2sf },
    &operand_data[20689],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_subvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx2sf },
    &operand_data[20689],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_addvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx4sf },
    &operand_data[20699],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_subvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx4sf },
    &operand_data[20699],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_addvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx8sf },
    &operand_data[20709],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_subvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx8sf },
    &operand_data[20709],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_addvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx16sf },
    &operand_data[20719],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_subvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx16sf },
    &operand_data[20719],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_addvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx1df },
    &operand_data[20729],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_subvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx1df },
    &operand_data[20729],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_addvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx2df },
    &operand_data[20739],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_subvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx2df },
    &operand_data[20739],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_addvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx4df },
    &operand_data[20749],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_subvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx4df },
    &operand_data[20749],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_addvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx8df },
    &operand_data[20759],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5745 */
  {
    "pred_mul_neg_subvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx8df },
    &operand_data[20759],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_addvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx1sf_scalar },
    &operand_data[20769],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_subvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx1sf_scalar },
    &operand_data[20769],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_addvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx2sf_scalar },
    &operand_data[20779],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_subvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx2sf_scalar },
    &operand_data[20779],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_addvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx4sf_scalar },
    &operand_data[20789],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_subvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx4sf_scalar },
    &operand_data[20789],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_addvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx8sf_scalar },
    &operand_data[20799],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_subvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx8sf_scalar },
    &operand_data[20799],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_addvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx16sf_scalar },
    &operand_data[20809],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_subvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx16sf_scalar },
    &operand_data[20809],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_addvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx1df_scalar },
    &operand_data[20819],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_subvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx1df_scalar },
    &operand_data[20819],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_addvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx2df_scalar },
    &operand_data[20829],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_subvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx2df_scalar },
    &operand_data[20829],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_addvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx4df_scalar },
    &operand_data[20839],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_subvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx4df_scalar },
    &operand_data[20839],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_addvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_addvnx8df_scalar },
    &operand_data[20849],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:5871 */
  {
    "pred_mul_neg_subvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_mul_neg_subvnx8df_scalar },
    &operand_data[20849],
    10,
    10,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
  {
    "pred_cmpvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx1sf },
    &operand_data[20859],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
  {
    "pred_cmpvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx2sf },
    &operand_data[20868],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
  {
    "pred_cmpvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx4sf },
    &operand_data[20877],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
  {
    "pred_cmpvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx8sf },
    &operand_data[20886],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
  {
    "pred_cmpvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx16sf },
    &operand_data[20895],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
  {
    "pred_cmpvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx1df },
    &operand_data[20904],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
  {
    "pred_cmpvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx2df },
    &operand_data[20913],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
  {
    "pred_cmpvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx4df },
    &operand_data[20922],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6278 */
  {
    "pred_cmpvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx8df },
    &operand_data[20931],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
  {
    "pred_cmpvnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx1sf_scalar },
    &operand_data[20940],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
  {
    "pred_cmpvnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx2sf_scalar },
    &operand_data[20949],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
  {
    "pred_cmpvnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx4sf_scalar },
    &operand_data[20958],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
  {
    "pred_cmpvnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx8sf_scalar },
    &operand_data[20967],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
  {
    "pred_cmpvnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx16sf_scalar },
    &operand_data[20976],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
  {
    "pred_cmpvnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx1df_scalar },
    &operand_data[20985],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
  {
    "pred_cmpvnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx2df_scalar },
    &operand_data[20994],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
  {
    "pred_cmpvnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx4df_scalar },
    &operand_data[21003],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6335 */
  {
    "pred_cmpvnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_cmpvnx8df_scalar },
    &operand_data[21012],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
  {
    "pred_eqnevnx1sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx1sf_scalar },
    &operand_data[21021],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
  {
    "pred_eqnevnx2sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx2sf_scalar },
    &operand_data[21030],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
  {
    "pred_eqnevnx4sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx4sf_scalar },
    &operand_data[21039],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
  {
    "pred_eqnevnx8sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx8sf_scalar },
    &operand_data[21048],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
  {
    "pred_eqnevnx16sf_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx16sf_scalar },
    &operand_data[21057],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
  {
    "pred_eqnevnx1df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx1df_scalar },
    &operand_data[21066],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
  {
    "pred_eqnevnx2df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx2df_scalar },
    &operand_data[21075],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
  {
    "pred_eqnevnx4df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx4df_scalar },
    &operand_data[21084],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6395 */
  {
    "pred_eqnevnx8df_scalar",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_eqnevnx8df_scalar },
    &operand_data[21093],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx1qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx1qi },
    &operand_data[21102],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx2qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx2qi },
    &operand_data[21104],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx4qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx4qi },
    &operand_data[21106],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx8qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx8qi },
    &operand_data[21108],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx16qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx16qi },
    &operand_data[21110],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx32qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx32qi },
    &operand_data[21112],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx64qi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx64qi },
    &operand_data[21114],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx1hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx1hi },
    &operand_data[21116],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx2hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx2hi },
    &operand_data[21118],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx4hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx4hi },
    &operand_data[21120],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx8hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx8hi },
    &operand_data[21122],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx16hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx16hi },
    &operand_data[21124],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx32hi",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx32hi },
    &operand_data[21126],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx1si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx1si },
    &operand_data[21128],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx2si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx2si },
    &operand_data[21130],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx4si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx4si },
    &operand_data[21132],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx8si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx8si },
    &operand_data[21134],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx16si",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx16si },
    &operand_data[21136],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx1di },
    &operand_data[21138],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx2di },
    &operand_data[21140],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx4di },
    &operand_data[21142],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:6948 */
  {
    "pred_extract_firstvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx8di },
    &operand_data[21144],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
  {
    "pred_extract_firstvnx1sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx1sf },
    &operand_data[21146],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
  {
    "pred_extract_firstvnx2sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx2sf },
    &operand_data[21148],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
  {
    "pred_extract_firstvnx4sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx4sf },
    &operand_data[21150],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
  {
    "pred_extract_firstvnx8sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx8sf },
    &operand_data[21152],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
  {
    "pred_extract_firstvnx16sf",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx16sf },
    &operand_data[21154],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
  {
    "pred_extract_firstvnx1df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx1df },
    &operand_data[21156],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
  {
    "pred_extract_firstvnx2df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx2df },
    &operand_data[21158],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
  {
    "pred_extract_firstvnx4df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx4df },
    &operand_data[21160],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7011 */
  {
    "pred_extract_firstvnx8df",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_extract_firstvnx8df },
    &operand_data[21162],
    2,
    2,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
  {
    "pred_slide1upvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx1di },
    &operand_data[21164],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
  {
    "pred_slide1downvnx1di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx1di },
    &operand_data[21164],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
  {
    "pred_slide1upvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx2di },
    &operand_data[21173],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
  {
    "pred_slide1downvnx2di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx2di },
    &operand_data[21173],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
  {
    "pred_slide1upvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx4di },
    &operand_data[21182],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
  {
    "pred_slide1downvnx4di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx4di },
    &operand_data[21182],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
  {
    "pred_slide1upvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1upvnx8di },
    &operand_data[21191],
    9,
    9,
    0,
    0,
    0
  },
  /* ../../../../../../../work-shared/gcc-13.4.0-r0/gcc-13.4.0/gcc/config/riscv/vector.md:7080 */
  {
    "pred_slide1downvnx8di",
#if HAVE_DESIGNATED_UNION_INITIALIZERS
    { 0 },
#else
    { 0, 0, 0 },
#endif
    { (insn_gen_fn::stored_funcptr) gen_pred_slide1downvnx8di },
    &operand_data[21191],
    9,
    9,
    0,
    0,
    0
  },
};


const char *
get_insn_name (int code)
{
  if (code == NOOP_MOVE_INSN_CODE)
    return "NOOP_MOVE";
  else
    return insn_data[code].name;
}
